setup-bus.c revision 6faf17f6f1ffc586d16efc2f9fa2083a7785ee74
11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * drivers/pci/setup-bus.c 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Extruded from code written by 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Dave Rusling (david.rusling@reo.mts.dec.com) 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * David Mosberger (davidm@cs.arizona.edu) 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * David Miller (davem@redhat.com) 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Support routines for initializing a PCI subsystem. 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PCI-PCI bridges cleanup, sorted resource allocation. 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Converted to allocation in 3 passes, which gives 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * tighter packing. Prefetchable range support. 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/init.h> 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/kernel.h> 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/module.h> 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/pci.h> 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/errno.h> 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/ioport.h> 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/cache.h> 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/slab.h> 286faf17f6f1ffc586d16efc2f9fa2083a7785ee74Chris Wright#include "pci.h" 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 30ea7415512a07add2b09c070c9a5d1950833cf9b3Andrew Mortonstatic void pbus_assign_resources_sorted(const struct pci_bus *bus) 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_dev *dev; 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct resource *res; 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct resource_list head, *list, *tmp; 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int idx; 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds head.next = NULL; 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds list_for_each_entry(dev, &bus->devices, bus_list) { 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u16 class = dev->class >> 8; 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 419bded00bf62090ebc9d6e8be640cdb69e8497db6Kenji Kaneshige /* Don't touch classless devices or host bridges or ioapics. */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (class == PCI_CLASS_NOT_DEFINED || 4323186279658cea6d42a050400d3e79c56cb459b4Satoru Takeuchi class == PCI_CLASS_BRIDGE_HOST) 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds continue; 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 469bded00bf62090ebc9d6e8be640cdb69e8497db6Kenji Kaneshige /* Don't touch ioapic devices already enabled by firmware */ 4723186279658cea6d42a050400d3e79c56cb459b4Satoru Takeuchi if (class == PCI_CLASS_SYSTEM_PIC) { 489bded00bf62090ebc9d6e8be640cdb69e8497db6Kenji Kaneshige u16 command; 499bded00bf62090ebc9d6e8be640cdb69e8497db6Kenji Kaneshige pci_read_config_word(dev, PCI_COMMAND, &command); 509bded00bf62090ebc9d6e8be640cdb69e8497db6Kenji Kaneshige if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) 5123186279658cea6d42a050400d3e79c56cb459b4Satoru Takeuchi continue; 5223186279658cea6d42a050400d3e79c56cb459b4Satoru Takeuchi } 5323186279658cea6d42a050400d3e79c56cb459b4Satoru Takeuchi 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pdev_sort_resources(dev, &head); 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds for (list = head.next; list;) { 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds res = list->res; 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds idx = res - &list->dev->resource[0]; 60542df5de56a23bf2d94b75e2b304ab0e5a5508a8Rajesh Shah if (pci_assign_resource(list->dev, idx)) { 61542df5de56a23bf2d94b75e2b304ab0e5a5508a8Rajesh Shah res->start = 0; 62960b8466548c9bc6f718b5f470c1a58000fab09dIvan Kokshaysky res->end = 0; 63542df5de56a23bf2d94b75e2b304ab0e5a5508a8Rajesh Shah res->flags = 0; 64542df5de56a23bf2d94b75e2b304ab0e5a5508a8Rajesh Shah } 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = list; 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds list = list->next; 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds kfree(tmp); 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 71b3743fa4442fc172e950ff0eaf6aa96e7d5ce9beDominik Brodowskivoid pci_setup_cardbus(struct pci_bus *bus) 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_dev *bridge = bus->self; 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_bus_region region; 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7680ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n", 7780ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas pci_domain_nr(bus), bus->number); 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (bus->resource[0]->flags & IORESOURCE_IO) { 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The IO resource is allocated a range twice as large as it 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * would normally need. This allows us to set both IO regs. 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 8580ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n", 86c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.start, 87c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.end); 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds region.start); 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds region.end); 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (bus->resource[1]->flags & IORESOURCE_IO) { 9680ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n", 97c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.start, 98c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.end); 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds region.start); 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds region.end); 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (bus->resource[2]->flags & IORESOURCE_MEM) { 10780ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&bridge->dev, " PREFETCH window: %#08lx-%#08lx\n", 108c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.start, 109c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.end); 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds region.start); 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds region.end); 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]); 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (bus->resource[3]->flags & IORESOURCE_MEM) { 11880ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n", 119c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.start, 120c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.end); 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds region.start); 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds region.end); 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 127b3743fa4442fc172e950ff0eaf6aa96e7d5ce9beDominik BrodowskiEXPORT_SYMBOL(pci_setup_cardbus); 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Initialize bridges with base/limit values we have collected. 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds requires that if there is no I/O ports or memory behind the 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bridge, corresponding range must be turned off by writing base 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds value greater than limit to the bridge's base/limit registers. 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds Note: care must be taken when updating I/O base/limit registers 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds of bridges which support 32-bit I/O. This update requires two 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds config space writes, so it's quite possible that an I/O window of 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds the bridge will have some undesirable address (e.g. 0) after the 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds first write. Ditto 64-bit prefetchable MMIO. */ 140a391f19717984a8f70756b29074298f379fcfdbcAdrian Bunkstatic void pci_setup_bridge(struct pci_bus *bus) 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_dev *bridge = bus->self; 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_bus_region region; 144c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt u32 l, bu, lu, io_upper16; 1451f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu int pref_mem64; 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 147296ccb086dfb89b5b8d73ef08c795ffdff12a597Yuji Shimada if (pci_is_enabled(bridge)) 148b73e97d95c168cbc19bd1208c894077f25931ba1Alex Chiang return; 149b73e97d95c168cbc19bd1208c894077f25931ba1Alex Chiang 15080ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&bridge->dev, "PCI bridge, secondary bus %04x:%02x\n", 15180ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas pci_domain_nr(bus), bus->number); 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Set up the top and bottom of the PCI I/O segment for this bus. */ 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (bus->resource[0]->flags & IORESOURCE_IO) { 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_read_config_dword(bridge, PCI_IO_BASE, &l); 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds l &= 0xffff0000; 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds l |= (region.start >> 8) & 0x00f0; 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds l |= region.end & 0xf000; 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Set up upper 16 bits of I/O base/limit. */ 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 16280ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&bridge->dev, " IO window: %#04lx-%#04lx\n", 163c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.start, 164c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.end); 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else { 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Clear upper 16 bits of I/O base/limit. */ 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds io_upper16 = 0; 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds l = 0x00f0; 17080ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&bridge->dev, " IO window: disabled\n"); 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Update lower 16 bits of I/O base/limit. */ 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_IO_BASE, l); 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Update upper 16 bits of I/O base/limit. */ 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Set up the top and bottom of the PCI Memory segment 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds for this bus. */ 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (bus->resource[1]->flags & IORESOURCE_MEM) { 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds l = (region.start >> 16) & 0xfff0; 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds l |= region.end & 0xfff00000; 18580ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n", 186c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.start, 187c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt (unsigned long)region.end); 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else { 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds l = 0x0000fff0; 19180ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&bridge->dev, " MEM window: disabled\n"); 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Clear out the upper 32 bits of PREF limit. 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds disables PREF range, which is ok. */ 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Set up PREF base/limit. */ 2011f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu pref_mem64 = 0; 202c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt bu = lu = 0; 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { 2051f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu int width = 8; 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds l = (region.start >> 16) & 0xfff0; 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds l |= region.end & 0xfff00000; 2081f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu if (bus->resource[2]->flags & IORESOURCE_MEM_64) { 2091f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu pref_mem64 = 1; 2101f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu bu = upper_32_bits(region.start); 2111f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu lu = upper_32_bits(region.end); 2121f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu width = 16; 2131f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu } 2141f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu dev_info(&bridge->dev, " PREFETCH window: %#0*llx-%#0*llx\n", 2151f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu width, (unsigned long long)region.start, 2161f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu width, (unsigned long long)region.end); 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else { 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds l = 0x0000fff0; 22080ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&bridge->dev, " PREFETCH window: disabled\n"); 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2241f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu if (pref_mem64) { 2251f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu /* Set the upper 32 bits of PREF base & limit. */ 2261f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); 2271f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); 2281f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu } 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Check whether the bridge supports optional I/O and 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds prefetchable memory ranges. If not, the respective 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds base/limit registers must be read-only and read as 0. */ 23696bde06a2df1b363206d3cdef53134b84ff37813Sam Ravnborgstatic void pci_bridge_check_ranges(struct pci_bus *bus) 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u16 io; 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 pmem; 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_dev *bridge = bus->self; 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct resource *b_res; 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b_res[1].flags |= IORESOURCE_MEM; 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_read_config_word(bridge, PCI_IO_BASE, &io); 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!io) { 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_read_config_word(bridge, PCI_IO_BASE, &io); 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (io) 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b_res[0].flags |= IORESOURCE_IO; 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* DECchip 21050 pass 2 errata: the bridge may miss an address 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds disconnect boundary by one PCI data phase. 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds Workaround: do not use prefetching on this device. */ 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!pmem) { 2611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 2621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 0xfff0fff0); 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2661f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu if (pmem) { 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 2681f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) 2691f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu b_res[2].flags |= IORESOURCE_MEM_64; 2701f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu } 2711f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu 2721f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu /* double check if bridge does support 64 bit pref */ 2731f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu if (b_res[2].flags & IORESOURCE_MEM_64) { 2741f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu u32 mem_base_hi, tmp; 2751f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, 2761f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu &mem_base_hi); 2771f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 2781f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu 0xffffffff); 2791f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 2801f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu if (!tmp) 2811f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu b_res[2].flags &= ~IORESOURCE_MEM_64; 2821f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 2831f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu mem_base_hi); 2841f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu } 2851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Helper function for sizing routines: find first available 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bus resource of a given type. Note: we intentionally skip 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds the bus resources which have already been assigned (that is, 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds have non-NULL parent resource). */ 29196bde06a2df1b363206d3cdef53134b84ff37813Sam Ravnborgstatic struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) 2921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int i; 2941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct resource *r; 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds IORESOURCE_PREFETCH; 2971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds r = bus->resource[i]; 300299de0343c7d18448a69c635378342e9214b14afIvan Kokshaysky if (r == &ioport_resource || r == &iomem_resource) 301299de0343c7d18448a69c635378342e9214b14afIvan Kokshaysky continue; 3021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (r && (r->flags & type_mask) == type && !r->parent) 3031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return r; 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 3051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return NULL; 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Sizing the IO windows of the PCI-PCI bridge is trivial, 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds since these windows have 4K granularity and the IO ranges 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds of non-bridge PCI devices are limited to 256 bytes. 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds We must be careful with the ISA aliasing though. */ 31296bde06a2df1b363206d3cdef53134b84ff37813Sam Ravnborgstatic void pbus_size_io(struct pci_bus *bus) 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_dev *dev; 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long size = 0, size1 = 0; 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!b_res) 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds list_for_each_entry(dev, &bus->devices, bus_list) { 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int i; 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds for (i = 0; i < PCI_NUM_RESOURCES; i++) { 3251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct resource *r = &dev->resource[i]; 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long r_size; 3271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (r->parent || !(r->flags & IORESOURCE_IO)) 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds continue; 330022edd86d7c864bc8fadc3c8ac4e6a464472ab05Zhao, Yu r_size = resource_size(r); 3311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (r_size < 0x400) 3331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Might be re-aligned for ISA */ 3341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds size += r_size; 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds size1 += r_size; 3371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 3381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* To be fixed in 2.5: we should have sort of HAVE_ISA 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds flag in the struct pci_bus. */ 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if defined(CONFIG_ISA) || defined(CONFIG_EISA) 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds size = (size & 0xff) + ((size & ~0xffUL) << 2); 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 3446f6f8c2f4b59711857d14ada8e70309d52e8fae4Milind Arun Choudhary size = ALIGN(size + size1, 4096); 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!size) { 3461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b_res->flags = 0; 3471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 3481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 3491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Alignment of the IO window is always 4K */ 3501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b_res->start = 4096; 3511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b_res->end = b_res->start + size - 1; 352884525655d07fdee9245716b998ecdc45cdd8007Ivan Kokshaysky b_res->flags |= IORESOURCE_STARTALIGN; 3531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Calculate the size of the bus and minimal alignment which 3561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds guarantees that all child resources fit in this size. */ 35796bde06a2df1b363206d3cdef53134b84ff37813Sam Ravnborgstatic int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type) 3581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 3591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_dev *dev; 360c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt resource_size_t min_align, align, size; 361c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ 3621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int order, max_order; 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct resource *b_res = find_free_bus_resource(bus, type); 3641f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu unsigned int mem64_mask = 0; 3651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!b_res) 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds memset(aligns, 0, sizeof(aligns)); 3701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds max_order = 0; 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds size = 0; 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3731f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu mem64_mask = b_res->flags & IORESOURCE_MEM_64; 3741f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu b_res->flags &= ~IORESOURCE_MEM_64; 3751f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu 3761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds list_for_each_entry(dev, &bus->devices, bus_list) { 3771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int i; 3781f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu 3791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds for (i = 0; i < PCI_NUM_RESOURCES; i++) { 3801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct resource *r = &dev->resource[i]; 381c40a22e0ce5eb400f27449e59e43d021bee58b8dBenjamin Herrenschmidt resource_size_t r_size; 3821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (r->parent || (r->flags & mask) != type) 3841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds continue; 385022edd86d7c864bc8fadc3c8ac4e6a464472ab05Zhao, Yu r_size = resource_size(r); 3861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* For bridges size != alignment */ 3876faf17f6f1ffc586d16efc2f9fa2083a7785ee74Chris Wright align = pci_resource_alignment(dev, r); 3881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds order = __ffs(align) - 20; 3891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (order > 11) { 3905f17cfce5776c566d64430f543a289e5cfa4538bLinus Torvalds dev_warn(&dev->dev, "BAR %d bad alignment %llx: " 391096e6f673dc02a6394dc9a7d8f8735c6978f5b91Benjamin Herrenschmidt "%pR\n", i, (unsigned long long)align, r); 3921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds r->flags = 0; 3931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds continue; 3941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 3951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds size += r_size; 3961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (order < 0) 3971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds order = 0; 3981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Exclude ranges with size > align from 3991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds calculation of the alignment. */ 4001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (r_size == align) 4011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds aligns[order] += align; 4021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (order > max_order) 4031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds max_order = order; 4041f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu mem64_mask &= r->flags & IORESOURCE_MEM_64; 4051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 4061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 4071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds align = 0; 4091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds min_align = 0; 4101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds for (order = 0; order <= max_order; order++) { 4118308c54d7e312f7a03e2ce2057d0837e6fe3843fJeremy Fitzhardinge resource_size_t align1 = 1; 4128308c54d7e312f7a03e2ce2057d0837e6fe3843fJeremy Fitzhardinge 4138308c54d7e312f7a03e2ce2057d0837e6fe3843fJeremy Fitzhardinge align1 <<= (order + 20); 4148308c54d7e312f7a03e2ce2057d0837e6fe3843fJeremy Fitzhardinge 4151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!align) 4161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds min_align = align1; 4176f6f8c2f4b59711857d14ada8e70309d52e8fae4Milind Arun Choudhary else if (ALIGN(align + min_align, min_align) < align1) 4181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds min_align = align1 >> 1; 4191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds align += aligns[order]; 4201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 4216f6f8c2f4b59711857d14ada8e70309d52e8fae4Milind Arun Choudhary size = ALIGN(size, min_align); 4221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!size) { 4231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b_res->flags = 0; 4241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 1; 4251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 4261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b_res->start = min_align; 4271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b_res->end = size + min_align - 1; 428884525655d07fdee9245716b998ecdc45cdd8007Ivan Kokshaysky b_res->flags |= IORESOURCE_STARTALIGN; 4291f82de10d6b1d845155363c895c552e61b36b51aYinghai Lu b_res->flags |= mem64_mask; 4301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 1; 4311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 4321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4335468ae617035f06ae1e07c264d6cdfcd721b539fAdrian Bunkstatic void pci_bus_size_cardbus(struct pci_bus *bus) 4341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 4351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_dev *bridge = bus->self; 4361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 4371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u16 ctrl; 4381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 4401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Reserve some resources for CardBus. We reserve 4411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * a fixed amount of bus space for CardBus bridges. 4421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 443934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[0].start = 0; 444934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[0].end = pci_cardbus_io_size - 1; 445934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; 4461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 447934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[1].start = 0; 448934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[1].end = pci_cardbus_io_size - 1; 449934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; 4501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 4521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Check whether prefetchable memory is supported 4531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * by this bridge. 4541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 4561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 4571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 4581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 4591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 4601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 4611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 4631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * If we have prefetchable memory support, allocate 4641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * two regions. Otherwise, allocate one region of 4651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * twice the size. 4661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 468934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[2].start = 0; 469934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[2].end = pci_cardbus_mem_size - 1; 470934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; 4711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 472934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[3].start = 0; 473934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[3].end = pci_cardbus_mem_size - 1; 474934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; 4751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } else { 476934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[3].start = 0; 477934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[3].end = pci_cardbus_mem_size * 2 - 1; 478934b7024f0ed29003c95cef447d92737ab86dc4fLinus Torvalds b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; 4791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 4801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 4811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 482451124a7cc6c89fcb83d48082c7290f16f652f1cSam Ravnborgvoid __ref pci_bus_size_bridges(struct pci_bus *bus) 4831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 4841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_dev *dev; 4851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long mask, prefmask; 4861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds list_for_each_entry(dev, &bus->devices, bus_list) { 4881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_bus *b = dev->subordinate; 4891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!b) 4901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds continue; 4911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (dev->class >> 8) { 4931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case PCI_CLASS_BRIDGE_CARDBUS: 4941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_bus_size_cardbus(b); 4951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 4961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case PCI_CLASS_BRIDGE_PCI: 4981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 4991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_bus_size_bridges(b); 5001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* The root bus? */ 5051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!bus->self) 5061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 5071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (bus->self->class >> 8) { 5091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case PCI_CLASS_BRIDGE_CARDBUS: 5101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* don't size cardbuses yet. */ 5111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case PCI_CLASS_BRIDGE_PCI: 5141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_bridge_check_ranges(bus); 5151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 5161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pbus_size_io(bus); 5171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* If the bridge supports prefetchable range, size it 5181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds separately. If it doesn't, or its prefetchable window 5191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds has already been allocated by arch code, try 5201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds non-prefetchable range for both types of PCI memory 5211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds resources. */ 5221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mask = IORESOURCE_MEM; 5231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; 5241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (pbus_size_mem(bus, prefmask, prefmask)) 5251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mask = prefmask; /* Success, size non-prefetch only. */ 5261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pbus_size_mem(bus, mask, IORESOURCE_MEM); 5271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 5301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsEXPORT_SYMBOL(pci_bus_size_bridges); 5311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 532ea7415512a07add2b09c070c9a5d1950833cf9b3Andrew Mortonvoid __ref pci_bus_assign_resources(const struct pci_bus *bus) 5331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 5341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_bus *b; 5351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_dev *dev; 5361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pbus_assign_resources_sorted(bus); 5381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds list_for_each_entry(dev, &bus->devices, bus_list) { 5401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b = dev->subordinate; 5411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!b) 5421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds continue; 5431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_bus_assign_resources(b); 5451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (dev->class >> 8) { 5471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case PCI_CLASS_BRIDGE_PCI: 5481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_setup_bridge(b); 5491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case PCI_CLASS_BRIDGE_CARDBUS: 5521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_setup_cardbus(b); 5531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 55680ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas dev_info(&dev->dev, "not setting up bridge for bus " 55780ccba1186d48fa728dc4b1456cc07ffb07da501Bjorn Helgaas "%04x:%02x\n", pci_domain_nr(b), b->number); 5581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 5621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsEXPORT_SYMBOL(pci_bus_assign_resources); 5631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 56476fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lustatic void pci_bus_dump_res(struct pci_bus *bus) 56576fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu{ 56676fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu int i; 56776fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu 56876fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 56976fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu struct resource *res = bus->resource[i]; 570681bf597215c62bd6f5ae1180a58a38997122b5bYinghai Lu if (!res || !res->end) 57176fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu continue; 57276fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu 573a19f5df7d9696b9e53ba7c865816597057d5f76eBjorn Helgaas dev_printk(KERN_DEBUG, &bus->dev, "resource %d %s %pR\n", i, 574681bf597215c62bd6f5ae1180a58a38997122b5bYinghai Lu (res->flags & IORESOURCE_IO) ? "io: " : 575681bf597215c62bd6f5ae1180a58a38997122b5bYinghai Lu ((res->flags & IORESOURCE_PREFETCH)? "pref mem":"mem:"), 576681bf597215c62bd6f5ae1180a58a38997122b5bYinghai Lu res); 57776fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu } 57876fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu} 57976fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu 58076fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lustatic void pci_bus_dump_resources(struct pci_bus *bus) 58176fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu{ 58276fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu struct pci_bus *b; 58376fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu struct pci_dev *dev; 58476fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu 58576fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu 58676fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu pci_bus_dump_res(bus); 58776fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu 58876fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu list_for_each_entry(dev, &bus->devices, bus_list) { 58976fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu b = dev->subordinate; 59076fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu if (!b) 59176fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu continue; 59276fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu 59376fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu pci_bus_dump_resources(b); 59476fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu } 59576fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu} 59676fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu 5971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid __init 5981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldspci_assign_unassigned_resources(void) 5991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 6001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_bus *bus; 6011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Depth first, calculate sizes and alignments of all 6031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds subordinate buses. */ 6041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds list_for_each_entry(bus, &pci_root_buses, node) { 6051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_bus_size_bridges(bus); 6061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 6071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Depth last, allocate resources and update the hardware. */ 6081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds list_for_each_entry(bus, &pci_root_buses, node) { 6091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_bus_assign_resources(bus); 6101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_enable_bridges(bus); 6111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 61276fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu 61376fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu /* dump the resource on buses */ 61476fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu list_for_each_entry(bus, &pci_root_buses, node) { 61576fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu pci_bus_dump_resources(bus); 61676fbc263ff7e42ce8b21b8aee176e3c74b45f81aYinghai Lu } 6171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 618