ti113x.h revision 78187865efa5aec5a28a200a39153f98d8f38d4d
1/* 2 * ti113x.h 1.16 1999/10/25 20:03:34 3 * 4 * The contents of this file are subject to the Mozilla Public License 5 * Version 1.1 (the "License"); you may not use this file except in 6 * compliance with the License. You may obtain a copy of the License 7 * at http://www.mozilla.org/MPL/ 8 * 9 * Software distributed under the License is distributed on an "AS IS" 10 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See 11 * the License for the specific language governing rights and 12 * limitations under the License. 13 * 14 * The initial developer of the original code is David A. Hinds 15 * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds 16 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. 17 * 18 * Alternatively, the contents of this file may be used under the 19 * terms of the GNU General Public License version 2 (the "GPL"), in which 20 * case the provisions of the GPL are applicable instead of the 21 * above. If you wish to allow the use of your version of this file 22 * only under the terms of the GPL and not to allow others to use 23 * your version of this file under the MPL, indicate your decision by 24 * deleting the provisions above and replace them with the notice and 25 * other provisions required by the GPL. If you do not delete the 26 * provisions above, a recipient may use your version of this file 27 * under either the MPL or the GPL. 28 */ 29 30#ifndef _LINUX_TI113X_H 31#define _LINUX_TI113X_H 32 33 34/* Register definitions for TI 113X PCI-to-CardBus bridges */ 35 36/* System Control Register */ 37#define TI113X_SYSTEM_CONTROL 0x0080 /* 32 bit */ 38#define TI113X_SCR_SMIROUTE 0x04000000 39#define TI113X_SCR_SMISTATUS 0x02000000 40#define TI113X_SCR_SMIENB 0x01000000 41#define TI113X_SCR_VCCPROT 0x00200000 42#define TI113X_SCR_REDUCEZV 0x00100000 43#define TI113X_SCR_CDREQEN 0x00080000 44#define TI113X_SCR_CDMACHAN 0x00070000 45#define TI113X_SCR_SOCACTIVE 0x00002000 46#define TI113X_SCR_PWRSTREAM 0x00000800 47#define TI113X_SCR_DELAYUP 0x00000400 48#define TI113X_SCR_DELAYDOWN 0x00000200 49#define TI113X_SCR_INTERROGATE 0x00000100 50#define TI113X_SCR_CLKRUN_SEL 0x00000080 51#define TI113X_SCR_PWRSAVINGS 0x00000040 52#define TI113X_SCR_SUBSYSRW 0x00000020 53#define TI113X_SCR_CB_DPAR 0x00000010 54#define TI113X_SCR_CDMA_EN 0x00000008 55#define TI113X_SCR_ASYNC_IRQ 0x00000004 56#define TI113X_SCR_KEEPCLK 0x00000002 57#define TI113X_SCR_CLKRUN_ENA 0x00000001 58 59#define TI122X_SCR_SER_STEP 0xc0000000 60#define TI122X_SCR_INTRTIE 0x20000000 61#define TIXX21_SCR_TIEALL 0x10000000 62#define TI122X_SCR_CBRSVD 0x00400000 63#define TI122X_SCR_MRBURSTDN 0x00008000 64#define TI122X_SCR_MRBURSTUP 0x00004000 65#define TI122X_SCR_RIMUX 0x00000001 66 67/* Multimedia Control Register */ 68#define TI1250_MULTIMEDIA_CTL 0x0084 /* 8 bit */ 69#define TI1250_MMC_ZVOUTEN 0x80 70#define TI1250_MMC_PORTSEL 0x40 71#define TI1250_MMC_ZVEN1 0x02 72#define TI1250_MMC_ZVEN0 0x01 73 74#define TI1250_GENERAL_STATUS 0x0085 /* 8 bit */ 75#define TI1250_GPIO0_CONTROL 0x0088 /* 8 bit */ 76#define TI1250_GPIO1_CONTROL 0x0089 /* 8 bit */ 77#define TI1250_GPIO2_CONTROL 0x008a /* 8 bit */ 78#define TI1250_GPIO3_CONTROL 0x008b /* 8 bit */ 79#define TI1250_GPIO_MODE_MASK 0xc0 80 81/* IRQMUX/MFUNC Register */ 82#define TI122X_MFUNC 0x008c /* 32 bit */ 83#define TI122X_MFUNC0_MASK 0x0000000f 84#define TI122X_MFUNC1_MASK 0x000000f0 85#define TI122X_MFUNC2_MASK 0x00000f00 86#define TI122X_MFUNC3_MASK 0x0000f000 87#define TI122X_MFUNC4_MASK 0x000f0000 88#define TI122X_MFUNC5_MASK 0x00f00000 89#define TI122X_MFUNC6_MASK 0x0f000000 90 91#define TI122X_MFUNC0_INTA 0x00000002 92#define TI125X_MFUNC0_INTB 0x00000001 93#define TI122X_MFUNC1_INTB 0x00000020 94#define TI122X_MFUNC3_IRQSER 0x00001000 95 96 97/* Retry Status Register */ 98#define TI113X_RETRY_STATUS 0x0090 /* 8 bit */ 99#define TI113X_RSR_PCIRETRY 0x80 100#define TI113X_RSR_CBRETRY 0x40 101#define TI113X_RSR_TEXP_CBB 0x20 102#define TI113X_RSR_MEXP_CBB 0x10 103#define TI113X_RSR_TEXP_CBA 0x08 104#define TI113X_RSR_MEXP_CBA 0x04 105#define TI113X_RSR_TEXP_PCI 0x02 106#define TI113X_RSR_MEXP_PCI 0x01 107 108/* Card Control Register */ 109#define TI113X_CARD_CONTROL 0x0091 /* 8 bit */ 110#define TI113X_CCR_RIENB 0x80 111#define TI113X_CCR_ZVENABLE 0x40 112#define TI113X_CCR_PCI_IRQ_ENA 0x20 113#define TI113X_CCR_PCI_IREQ 0x10 114#define TI113X_CCR_PCI_CSC 0x08 115#define TI113X_CCR_SPKROUTEN 0x02 116#define TI113X_CCR_IFG 0x01 117 118#define TI1220_CCR_PORT_SEL 0x20 119#define TI122X_CCR_AUD2MUX 0x04 120 121/* Device Control Register */ 122#define TI113X_DEVICE_CONTROL 0x0092 /* 8 bit */ 123#define TI113X_DCR_5V_FORCE 0x40 124#define TI113X_DCR_3V_FORCE 0x20 125#define TI113X_DCR_IMODE_MASK 0x06 126#define TI113X_DCR_IMODE_ISA 0x02 127#define TI113X_DCR_IMODE_SERIAL 0x04 128 129#define TI12XX_DCR_IMODE_PCI_ONLY 0x00 130#define TI12XX_DCR_IMODE_ALL_SERIAL 0x06 131 132/* Buffer Control Register */ 133#define TI113X_BUFFER_CONTROL 0x0093 /* 8 bit */ 134#define TI113X_BCR_CB_READ_DEPTH 0x08 135#define TI113X_BCR_CB_WRITE_DEPTH 0x04 136#define TI113X_BCR_PCI_READ_DEPTH 0x02 137#define TI113X_BCR_PCI_WRITE_DEPTH 0x01 138 139/* Diagnostic Register */ 140#define TI1250_DIAGNOSTIC 0x0093 /* 8 bit */ 141#define TI1250_DIAG_TRUE_VALUE 0x80 142#define TI1250_DIAG_PCI_IREQ 0x40 143#define TI1250_DIAG_PCI_CSC 0x20 144#define TI1250_DIAG_ASYNC_CSC 0x01 145 146/* DMA Registers */ 147#define TI113X_DMA_0 0x0094 /* 32 bit */ 148#define TI113X_DMA_1 0x0098 /* 32 bit */ 149 150/* ExCA IO offset registers */ 151#define TI113X_IO_OFFSET(map) (0x36+((map)<<1)) 152 153/* EnE test register */ 154#define ENE_TEST_C9 0xc9 /* 8bit */ 155#define ENE_TEST_C9_TLTENABLE 0x02 156#define ENE_TEST_C9_PFENABLE_F0 0x04 157#define ENE_TEST_C9_PFENABLE_F1 0x08 158#define ENE_TEST_C9_PFENABLE (ENE_TEST_C9_PFENABLE_F0 | ENE_TEST_C9_PFENABLE_F0) 159#define ENE_TEST_C9_WPDISALBLE_F0 0x40 160#define ENE_TEST_C9_WPDISALBLE_F1 0x80 161#define ENE_TEST_C9_WPDISALBLE (ENE_TEST_C9_WPDISALBLE_F0 | ENE_TEST_C9_WPDISALBLE_F1) 162 163/* 164 * Texas Instruments CardBus controller overrides. 165 */ 166#define ti_sysctl(socket) ((socket)->private[0]) 167#define ti_cardctl(socket) ((socket)->private[1]) 168#define ti_devctl(socket) ((socket)->private[2]) 169#define ti_diag(socket) ((socket)->private[3]) 170#define ti_mfunc(socket) ((socket)->private[4]) 171#define ene_test_c9(socket) ((socket)->private[5]) 172 173/* 174 * These are the TI specific power management handlers. 175 */ 176static void ti_save_state(struct yenta_socket *socket) 177{ 178 ti_sysctl(socket) = config_readl(socket, TI113X_SYSTEM_CONTROL); 179 ti_mfunc(socket) = config_readl(socket, TI122X_MFUNC); 180 ti_cardctl(socket) = config_readb(socket, TI113X_CARD_CONTROL); 181 ti_devctl(socket) = config_readb(socket, TI113X_DEVICE_CONTROL); 182 ti_diag(socket) = config_readb(socket, TI1250_DIAGNOSTIC); 183 184 if (socket->dev->vendor == PCI_VENDOR_ID_ENE) 185 ene_test_c9(socket) = config_readb(socket, ENE_TEST_C9); 186} 187 188static void ti_restore_state(struct yenta_socket *socket) 189{ 190 config_writel(socket, TI113X_SYSTEM_CONTROL, ti_sysctl(socket)); 191 config_writel(socket, TI122X_MFUNC, ti_mfunc(socket)); 192 config_writeb(socket, TI113X_CARD_CONTROL, ti_cardctl(socket)); 193 config_writeb(socket, TI113X_DEVICE_CONTROL, ti_devctl(socket)); 194 config_writeb(socket, TI1250_DIAGNOSTIC, ti_diag(socket)); 195 196 if (socket->dev->vendor == PCI_VENDOR_ID_ENE) 197 config_writeb(socket, ENE_TEST_C9, ene_test_c9(socket)); 198} 199 200/* 201 * Zoom video control for TI122x/113x chips 202 */ 203 204static void ti_zoom_video(struct pcmcia_socket *sock, int onoff) 205{ 206 u8 reg; 207 struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket); 208 209 /* If we don't have a Zoom Video switch this is harmless, 210 we just tristate the unused (ZV) lines */ 211 reg = config_readb(socket, TI113X_CARD_CONTROL); 212 if (onoff) 213 /* Zoom zoom, we will all go together, zoom zoom, zoom zoom */ 214 reg |= TI113X_CCR_ZVENABLE; 215 else 216 reg &= ~TI113X_CCR_ZVENABLE; 217 config_writeb(socket, TI113X_CARD_CONTROL, reg); 218} 219 220/* 221 * The 145x series can also use this. They have an additional 222 * ZV autodetect mode we don't use but don't actually need. 223 * FIXME: manual says its in func0 and func1 but disagrees with 224 * itself about this - do we need to force func0, if so we need 225 * to know a lot more about socket pairings in pcmcia_socket than 226 * we do now.. uggh. 227 */ 228 229static void ti1250_zoom_video(struct pcmcia_socket *sock, int onoff) 230{ 231 struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket); 232 int shift = 0; 233 u8 reg; 234 235 ti_zoom_video(sock, onoff); 236 237 reg = config_readb(socket, TI1250_MULTIMEDIA_CTL); 238 reg |= TI1250_MMC_ZVOUTEN; /* ZV bus enable */ 239 240 if(PCI_FUNC(socket->dev->devfn)==1) 241 shift = 1; 242 243 if(onoff) 244 { 245 reg &= ~(1<<6); /* Clear select bit */ 246 reg |= shift<<6; /* Favour our socket */ 247 reg |= 1<<shift; /* Socket zoom video on */ 248 } 249 else 250 { 251 reg &= ~(1<<6); /* Clear select bit */ 252 reg |= (1^shift)<<6; /* Favour other socket */ 253 reg &= ~(1<<shift); /* Socket zoon video off */ 254 } 255 256 config_writeb(socket, TI1250_MULTIMEDIA_CTL, reg); 257} 258 259static void ti_set_zv(struct yenta_socket *socket) 260{ 261 if(socket->dev->vendor == PCI_VENDOR_ID_TI) 262 { 263 switch(socket->dev->device) 264 { 265 /* There may be more .. */ 266 case PCI_DEVICE_ID_TI_1220: 267 case PCI_DEVICE_ID_TI_1221: 268 case PCI_DEVICE_ID_TI_1225: 269 case PCI_DEVICE_ID_TI_4510: 270 socket->socket.zoom_video = ti_zoom_video; 271 break; 272 case PCI_DEVICE_ID_TI_1250: 273 case PCI_DEVICE_ID_TI_1251A: 274 case PCI_DEVICE_ID_TI_1251B: 275 case PCI_DEVICE_ID_TI_1450: 276 socket->socket.zoom_video = ti1250_zoom_video; 277 } 278 } 279} 280 281 282/* 283 * Generic TI init - TI has an extension for the 284 * INTCTL register that sets the PCI CSC interrupt. 285 * Make sure we set it correctly at open and init 286 * time 287 * - override: disable the PCI CSC interrupt. This makes 288 * it possible to use the CSC interrupt to probe the 289 * ISA interrupts. 290 * - init: set the interrupt to match our PCI state. 291 * This makes us correctly get PCI CSC interrupt 292 * events. 293 */ 294static int ti_init(struct yenta_socket *socket) 295{ 296 u8 new, reg = exca_readb(socket, I365_INTCTL); 297 298 new = reg & ~I365_INTR_ENA; 299 if (socket->cb_irq) 300 new |= I365_INTR_ENA; 301 if (new != reg) 302 exca_writeb(socket, I365_INTCTL, new); 303 return 0; 304} 305 306static int ti_override(struct yenta_socket *socket) 307{ 308 u8 new, reg = exca_readb(socket, I365_INTCTL); 309 310 new = reg & ~I365_INTR_ENA; 311 if (new != reg) 312 exca_writeb(socket, I365_INTCTL, new); 313 314 ti_set_zv(socket); 315 316 return 0; 317} 318 319static int ti113x_override(struct yenta_socket *socket) 320{ 321 u8 cardctl; 322 323 cardctl = config_readb(socket, TI113X_CARD_CONTROL); 324 cardctl &= ~(TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_IREQ | TI113X_CCR_PCI_CSC); 325 if (socket->cb_irq) 326 cardctl |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_CSC | TI113X_CCR_PCI_IREQ; 327 config_writeb(socket, TI113X_CARD_CONTROL, cardctl); 328 329 return ti_override(socket); 330} 331 332 333/* irqrouting for func0, probes PCI interrupt and ISA interrupts */ 334static void ti12xx_irqroute_func0(struct yenta_socket *socket) 335{ 336 u32 mfunc, mfunc_old, devctl; 337 u8 gpio3, gpio3_old; 338 int pci_irq_status; 339 340 mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC); 341 devctl = config_readb(socket, TI113X_DEVICE_CONTROL); 342 printk(KERN_INFO "Yenta TI: socket %s, mfunc 0x%08x, devctl 0x%02x\n", 343 pci_name(socket->dev), mfunc, devctl); 344 345 /* make sure PCI interrupts are enabled before probing */ 346 ti_init(socket); 347 348 /* test PCI interrupts first. only try fixing if return value is 0! */ 349 pci_irq_status = yenta_probe_cb_irq(socket); 350 if (pci_irq_status) 351 goto out; 352 353 /* 354 * We're here which means PCI interrupts are _not_ delivered. try to 355 * find the right setting (all serial or parallel) 356 */ 357 printk(KERN_INFO "Yenta TI: socket %s probing PCI interrupt failed, trying to fix\n", 358 pci_name(socket->dev)); 359 360 /* for serial PCI make sure MFUNC3 is set to IRQSER */ 361 if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) { 362 switch (socket->dev->device) { 363 case PCI_DEVICE_ID_TI_1250: 364 case PCI_DEVICE_ID_TI_1251A: 365 case PCI_DEVICE_ID_TI_1251B: 366 case PCI_DEVICE_ID_TI_1450: 367 case PCI_DEVICE_ID_TI_1451A: 368 case PCI_DEVICE_ID_TI_4450: 369 case PCI_DEVICE_ID_TI_4451: 370 /* these chips have no IRQSER setting in MFUNC3 */ 371 break; 372 373 default: 374 mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER; 375 376 /* write down if changed, probe */ 377 if (mfunc != mfunc_old) { 378 config_writel(socket, TI122X_MFUNC, mfunc); 379 380 pci_irq_status = yenta_probe_cb_irq(socket); 381 if (pci_irq_status == 1) { 382 printk(KERN_INFO "Yenta TI: socket %s all-serial interrupts ok\n", 383 pci_name(socket->dev)); 384 mfunc_old = mfunc; 385 goto out; 386 } 387 388 /* not working, back to old value */ 389 mfunc = mfunc_old; 390 config_writel(socket, TI122X_MFUNC, mfunc); 391 392 if (pci_irq_status == -1) 393 goto out; 394 } 395 } 396 397 /* serial PCI interrupts not working fall back to parallel */ 398 printk(KERN_INFO "Yenta TI: socket %s falling back to parallel PCI interrupts\n", 399 pci_name(socket->dev)); 400 devctl &= ~TI113X_DCR_IMODE_MASK; 401 devctl |= TI113X_DCR_IMODE_SERIAL; /* serial ISA could be right */ 402 config_writeb(socket, TI113X_DEVICE_CONTROL, devctl); 403 } 404 405 /* parallel PCI interrupts: route INTA */ 406 switch (socket->dev->device) { 407 case PCI_DEVICE_ID_TI_1250: 408 case PCI_DEVICE_ID_TI_1251A: 409 case PCI_DEVICE_ID_TI_1251B: 410 case PCI_DEVICE_ID_TI_1450: 411 /* make sure GPIO3 is set to INTA */ 412 gpio3 = gpio3_old = config_readb(socket, TI1250_GPIO3_CONTROL); 413 gpio3 &= ~TI1250_GPIO_MODE_MASK; 414 if (gpio3 != gpio3_old) 415 config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3); 416 break; 417 418 default: 419 gpio3 = gpio3_old = 0; 420 421 mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI122X_MFUNC0_INTA; 422 if (mfunc != mfunc_old) 423 config_writel(socket, TI122X_MFUNC, mfunc); 424 } 425 426 /* time to probe again */ 427 pci_irq_status = yenta_probe_cb_irq(socket); 428 if (pci_irq_status == 1) { 429 mfunc_old = mfunc; 430 printk(KERN_INFO "Yenta TI: socket %s parallel PCI interrupts ok\n", 431 pci_name(socket->dev)); 432 } else { 433 /* not working, back to old value */ 434 mfunc = mfunc_old; 435 config_writel(socket, TI122X_MFUNC, mfunc); 436 if (gpio3 != gpio3_old) 437 config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3_old); 438 } 439 440out: 441 if (pci_irq_status < 1) { 442 socket->cb_irq = 0; 443 printk(KERN_INFO "Yenta TI: socket %s no PCI interrupts. Fish. Please report.\n", 444 pci_name(socket->dev)); 445 } 446} 447 448 449/* changes the irq of func1 to match that of func0 */ 450static int ti12xx_align_irqs(struct yenta_socket *socket, int *old_irq) 451{ 452 struct pci_dev *func0; 453 454 /* find func0 device */ 455 func0 = pci_get_slot(socket->dev->bus, socket->dev->devfn & ~0x07); 456 if (!func0) 457 return 0; 458 459 if (old_irq) 460 *old_irq = socket->cb_irq; 461 socket->cb_irq = socket->dev->irq = func0->irq; 462 463 pci_dev_put(func0); 464 465 return 1; 466} 467 468/* 469 * ties INTA and INTB together. also changes the devices irq to that of 470 * the function 0 device. call from func1 only. 471 * returns 1 if INTRTIE changed, 0 otherwise. 472 */ 473static int ti12xx_tie_interrupts(struct yenta_socket *socket, int *old_irq) 474{ 475 u32 sysctl; 476 int ret; 477 478 sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL); 479 if (sysctl & TI122X_SCR_INTRTIE) 480 return 0; 481 482 /* align */ 483 ret = ti12xx_align_irqs(socket, old_irq); 484 if (!ret) 485 return 0; 486 487 /* tie */ 488 sysctl |= TI122X_SCR_INTRTIE; 489 config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl); 490 491 return 1; 492} 493 494/* undo what ti12xx_tie_interrupts() did */ 495static void ti12xx_untie_interrupts(struct yenta_socket *socket, int old_irq) 496{ 497 u32 sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL); 498 sysctl &= ~TI122X_SCR_INTRTIE; 499 config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl); 500 501 socket->cb_irq = socket->dev->irq = old_irq; 502} 503 504/* 505 * irqrouting for func1, plays with INTB routing 506 * only touches MFUNC for INTB routing. all other bits are taken 507 * care of in func0 already. 508 */ 509static void ti12xx_irqroute_func1(struct yenta_socket *socket) 510{ 511 u32 mfunc, mfunc_old, devctl, sysctl; 512 int pci_irq_status; 513 514 mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC); 515 devctl = config_readb(socket, TI113X_DEVICE_CONTROL); 516 printk(KERN_INFO "Yenta TI: socket %s, mfunc 0x%08x, devctl 0x%02x\n", 517 pci_name(socket->dev), mfunc, devctl); 518 519 /* if IRQs are configured as tied, align irq of func1 with func0 */ 520 sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL); 521 if (sysctl & TI122X_SCR_INTRTIE) 522 ti12xx_align_irqs(socket, NULL); 523 524 /* make sure PCI interrupts are enabled before probing */ 525 ti_init(socket); 526 527 /* test PCI interrupts first. only try fixing if return value is 0! */ 528 pci_irq_status = yenta_probe_cb_irq(socket); 529 if (pci_irq_status) 530 goto out; 531 532 /* 533 * We're here which means PCI interrupts are _not_ delivered. try to 534 * find the right setting 535 */ 536 printk(KERN_INFO "Yenta TI: socket %s probing PCI interrupt failed, trying to fix\n", 537 pci_name(socket->dev)); 538 539 540 /* if all serial: set INTRTIE, probe again */ 541 if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) { 542 int old_irq; 543 544 if (ti12xx_tie_interrupts(socket, &old_irq)) { 545 pci_irq_status = yenta_probe_cb_irq(socket); 546 if (pci_irq_status == 1) { 547 printk(KERN_INFO "Yenta TI: socket %s all-serial interrupts, tied ok\n", 548 pci_name(socket->dev)); 549 goto out; 550 } 551 552 ti12xx_untie_interrupts(socket, old_irq); 553 } 554 } 555 /* parallel PCI: route INTB, probe again */ 556 else { 557 int old_irq; 558 559 switch (socket->dev->device) { 560 case PCI_DEVICE_ID_TI_1250: 561 /* the 1250 has one pin for IRQSER/INTB depending on devctl */ 562 break; 563 564 case PCI_DEVICE_ID_TI_1251A: 565 case PCI_DEVICE_ID_TI_1251B: 566 case PCI_DEVICE_ID_TI_1450: 567 /* 568 * those have a pin for IRQSER/INTB plus INTB in MFUNC0 569 * we alread probed the shared pin, now go for MFUNC0 570 */ 571 mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI125X_MFUNC0_INTB; 572 break; 573 574 default: 575 mfunc = (mfunc & ~TI122X_MFUNC1_MASK) | TI122X_MFUNC1_INTB; 576 break; 577 } 578 579 /* write, probe */ 580 if (mfunc != mfunc_old) { 581 config_writel(socket, TI122X_MFUNC, mfunc); 582 583 pci_irq_status = yenta_probe_cb_irq(socket); 584 if (pci_irq_status == 1) { 585 printk(KERN_INFO "Yenta TI: socket %s parallel PCI interrupts ok\n", 586 pci_name(socket->dev)); 587 goto out; 588 } 589 590 mfunc = mfunc_old; 591 config_writel(socket, TI122X_MFUNC, mfunc); 592 593 if (pci_irq_status == -1) 594 goto out; 595 } 596 597 /* still nothing: set INTRTIE */ 598 if (ti12xx_tie_interrupts(socket, &old_irq)) { 599 pci_irq_status = yenta_probe_cb_irq(socket); 600 if (pci_irq_status == 1) { 601 printk(KERN_INFO "Yenta TI: socket %s parallel PCI interrupts, tied ok\n", 602 pci_name(socket->dev)); 603 goto out; 604 } 605 606 ti12xx_untie_interrupts(socket, old_irq); 607 } 608 } 609 610out: 611 if (pci_irq_status < 1) { 612 socket->cb_irq = 0; 613 printk(KERN_INFO "Yenta TI: socket %s no PCI interrupts. Fish. Please report.\n", 614 pci_name(socket->dev)); 615 } 616} 617 618 619/* Returns true value if the second slot of a two-slot controller is empty */ 620static int ti12xx_2nd_slot_empty(struct yenta_socket *socket) 621{ 622 struct pci_dev *func; 623 struct yenta_socket *slot2; 624 int devfn; 625 unsigned int state; 626 int ret = 1; 627 u32 sysctl; 628 629 /* catch the two-slot controllers */ 630 switch (socket->dev->device) { 631 case PCI_DEVICE_ID_TI_1220: 632 case PCI_DEVICE_ID_TI_1221: 633 case PCI_DEVICE_ID_TI_1225: 634 case PCI_DEVICE_ID_TI_1251A: 635 case PCI_DEVICE_ID_TI_1251B: 636 case PCI_DEVICE_ID_TI_1420: 637 case PCI_DEVICE_ID_TI_1450: 638 case PCI_DEVICE_ID_TI_1451A: 639 case PCI_DEVICE_ID_TI_1520: 640 case PCI_DEVICE_ID_TI_1620: 641 case PCI_DEVICE_ID_TI_4520: 642 case PCI_DEVICE_ID_TI_4450: 643 case PCI_DEVICE_ID_TI_4451: 644 /* 645 * there are way more, but they need to be added in yenta_socket.c 646 * and pci_ids.h first anyway. 647 */ 648 break; 649 650 case PCI_DEVICE_ID_TI_XX12: 651 case PCI_DEVICE_ID_TI_X515: 652 case PCI_DEVICE_ID_TI_X420: 653 case PCI_DEVICE_ID_TI_X620: 654 case PCI_DEVICE_ID_TI_XX21_XX11: 655 case PCI_DEVICE_ID_TI_7410: 656 case PCI_DEVICE_ID_TI_7610: 657 /* 658 * those are either single or dual slot CB with additional functions 659 * like 1394, smartcard reader, etc. check the TIEALL flag for them 660 * the TIEALL flag binds the IRQ of all functions toghether. 661 * we catch the single slot variants later. 662 */ 663 sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL); 664 if (sysctl & TIXX21_SCR_TIEALL) 665 return 0; 666 667 break; 668 669 /* single-slot controllers have the 2nd slot empty always :) */ 670 default: 671 return 1; 672 } 673 674 /* get other slot */ 675 devfn = socket->dev->devfn & ~0x07; 676 func = pci_get_slot(socket->dev->bus, 677 (socket->dev->devfn & 0x07) ? devfn : devfn | 0x01); 678 if (!func) 679 return 1; 680 681 /* 682 * check that the device id of both slots match. this is needed for the 683 * XX21 and the XX11 controller that share the same device id for single 684 * and dual slot controllers. return '2nd slot empty'. we already checked 685 * if the interrupt is tied to another function. 686 */ 687 if (socket->dev->device != func->device) 688 goto out; 689 690 slot2 = pci_get_drvdata(func); 691 if (!slot2) 692 goto out; 693 694 /* check state */ 695 yenta_get_status(&socket->socket, &state); 696 if (state & SS_DETECT) { 697 ret = 0; 698 goto out; 699 } 700 701out: 702 pci_dev_put(func); 703 return ret; 704} 705 706/* 707 * TI specifiy parts for the power hook. 708 * 709 * some TI's with some CB's produces interrupt storm on power on. it has been 710 * seen with atheros wlan cards on TI1225 and TI1410. solution is simply to 711 * disable any CB interrupts during this time. 712 */ 713static int ti12xx_power_hook(struct pcmcia_socket *sock, int operation) 714{ 715 struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket); 716 u32 mfunc, devctl, sysctl; 717 u8 gpio3; 718 719 /* only POWER_PRE and POWER_POST are interesting */ 720 if ((operation != HOOK_POWER_PRE) && (operation != HOOK_POWER_POST)) 721 return 0; 722 723 devctl = config_readb(socket, TI113X_DEVICE_CONTROL); 724 sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL); 725 mfunc = config_readl(socket, TI122X_MFUNC); 726 727 /* 728 * all serial/tied: only disable when modparm set. always doing it 729 * would mean a regression for working setups 'cos it disables the 730 * interrupts for both both slots on 2-slot controllers 731 * (and users of single slot controllers where it's save have to 732 * live with setting the modparm, most don't have to anyway) 733 */ 734 if (((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) && 735 (pwr_irqs_off || ti12xx_2nd_slot_empty(socket))) { 736 switch (socket->dev->device) { 737 case PCI_DEVICE_ID_TI_1250: 738 case PCI_DEVICE_ID_TI_1251A: 739 case PCI_DEVICE_ID_TI_1251B: 740 case PCI_DEVICE_ID_TI_1450: 741 case PCI_DEVICE_ID_TI_1451A: 742 case PCI_DEVICE_ID_TI_4450: 743 case PCI_DEVICE_ID_TI_4451: 744 /* these chips have no IRQSER setting in MFUNC3 */ 745 break; 746 747 default: 748 if (operation == HOOK_POWER_PRE) 749 mfunc = (mfunc & ~TI122X_MFUNC3_MASK); 750 else 751 mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER; 752 } 753 754 return 0; 755 } 756 757 /* do the job differently for func0/1 */ 758 if ((PCI_FUNC(socket->dev->devfn) == 0) || 759 ((sysctl & TI122X_SCR_INTRTIE) && 760 (pwr_irqs_off || ti12xx_2nd_slot_empty(socket)))) { 761 /* some bridges are different */ 762 switch (socket->dev->device) { 763 case PCI_DEVICE_ID_TI_1250: 764 case PCI_DEVICE_ID_TI_1251A: 765 case PCI_DEVICE_ID_TI_1251B: 766 case PCI_DEVICE_ID_TI_1450: 767 /* those oldies use gpio3 for INTA */ 768 gpio3 = config_readb(socket, TI1250_GPIO3_CONTROL); 769 if (operation == HOOK_POWER_PRE) 770 gpio3 = (gpio3 & ~TI1250_GPIO_MODE_MASK) | 0x40; 771 else 772 gpio3 &= ~TI1250_GPIO_MODE_MASK; 773 config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3); 774 break; 775 776 default: 777 /* all new bridges are the same */ 778 if (operation == HOOK_POWER_PRE) 779 mfunc &= ~TI122X_MFUNC0_MASK; 780 else 781 mfunc |= TI122X_MFUNC0_INTA; 782 config_writel(socket, TI122X_MFUNC, mfunc); 783 } 784 } else { 785 switch (socket->dev->device) { 786 case PCI_DEVICE_ID_TI_1251A: 787 case PCI_DEVICE_ID_TI_1251B: 788 case PCI_DEVICE_ID_TI_1450: 789 /* those have INTA elsewhere and INTB in MFUNC0 */ 790 if (operation == HOOK_POWER_PRE) 791 mfunc &= ~TI122X_MFUNC0_MASK; 792 else 793 mfunc |= TI125X_MFUNC0_INTB; 794 config_writel(socket, TI122X_MFUNC, mfunc); 795 796 break; 797 798 default: 799 /* all new bridges are the same */ 800 if (operation == HOOK_POWER_PRE) 801 mfunc &= ~TI122X_MFUNC1_MASK; 802 else 803 mfunc |= TI122X_MFUNC1_INTB; 804 config_writel(socket, TI122X_MFUNC, mfunc); 805 } 806 } 807 808 return 0; 809} 810 811static int ti12xx_override(struct yenta_socket *socket) 812{ 813 u32 val, val_orig; 814 815 /* make sure that memory burst is active */ 816 val_orig = val = config_readl(socket, TI113X_SYSTEM_CONTROL); 817 if (disable_clkrun && PCI_FUNC(socket->dev->devfn) == 0) { 818 printk(KERN_INFO "Yenta: Disabling CLKRUN feature\n"); 819 val |= TI113X_SCR_KEEPCLK; 820 } 821 if (!(val & TI122X_SCR_MRBURSTUP)) { 822 printk(KERN_INFO "Yenta: Enabling burst memory read transactions\n"); 823 val |= TI122X_SCR_MRBURSTUP; 824 } 825 if (val_orig != val) 826 config_writel(socket, TI113X_SYSTEM_CONTROL, val); 827 828 /* 829 * Yenta expects controllers to use CSCINT to route 830 * CSC interrupts to PCI rather than INTVAL. 831 */ 832 val = config_readb(socket, TI1250_DIAGNOSTIC); 833 printk(KERN_INFO "Yenta: Using %s to route CSC interrupts to PCI\n", 834 (val & TI1250_DIAG_PCI_CSC) ? "CSCINT" : "INTVAL"); 835 printk(KERN_INFO "Yenta: Routing CardBus interrupts to %s\n", 836 (val & TI1250_DIAG_PCI_IREQ) ? "PCI" : "ISA"); 837 838 /* do irqrouting, depending on function */ 839 if (PCI_FUNC(socket->dev->devfn) == 0) 840 ti12xx_irqroute_func0(socket); 841 else 842 ti12xx_irqroute_func1(socket); 843 844 /* install power hook */ 845 socket->socket.power_hook = ti12xx_power_hook; 846 847 return ti_override(socket); 848} 849 850 851static int ti1250_override(struct yenta_socket *socket) 852{ 853 u8 old, diag; 854 855 old = config_readb(socket, TI1250_DIAGNOSTIC); 856 diag = old & ~(TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ); 857 if (socket->cb_irq) 858 diag |= TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ; 859 860 if (diag != old) { 861 printk(KERN_INFO "Yenta: adjusting diagnostic: %02x -> %02x\n", 862 old, diag); 863 config_writeb(socket, TI1250_DIAGNOSTIC, diag); 864 } 865 866 return ti12xx_override(socket); 867} 868 869 870/** 871 * EnE specific part. EnE bridges are register compatible with TI bridges but 872 * have their own test registers and more important their own little problems. 873 * Some fixup code to make everybody happy (TM). 874 */ 875 876#ifdef CONFIG_YENTA_ENE_TUNE 877/* 878 * set/clear various test bits: 879 * Defaults to clear the bit. 880 * - mask (u8) defines what bits to change 881 * - bits (u8) is the values to change them to 882 * -> it's 883 * current = (current & ~mask) | bits 884 */ 885/* pci ids of devices that wants to have the bit set */ 886#define DEVID(_vend,_dev,_subvend,_subdev,mask,bits) { \ 887 .vendor = _vend, \ 888 .device = _dev, \ 889 .subvendor = _subvend, \ 890 .subdevice = _subdev, \ 891 .driver_data = ((mask) << 8 | (bits)), \ 892 } 893static struct pci_device_id ene_tune_tbl[] = { 894 /* Echo Audio products based on motorola DSP56301 and DSP56361 */ 895 DEVID(PCI_VENDOR_ID_MOTOROLA, 0x1801, 0xECC0, PCI_ANY_ID, 896 ENE_TEST_C9_TLTENABLE | ENE_TEST_C9_PFENABLE, ENE_TEST_C9_TLTENABLE), 897 DEVID(PCI_VENDOR_ID_MOTOROLA, 0x3410, 0xECC0, PCI_ANY_ID, 898 ENE_TEST_C9_TLTENABLE | ENE_TEST_C9_PFENABLE, ENE_TEST_C9_TLTENABLE), 899 900 {} 901}; 902 903static void ene_tune_bridge(struct pcmcia_socket *sock, struct pci_bus *bus) 904{ 905 struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket); 906 struct pci_dev *dev; 907 struct pci_device_id *id = NULL; 908 u8 test_c9, old_c9, mask, bits; 909 910 list_for_each_entry(dev, &bus->devices, bus_list) { 911 id = (struct pci_device_id *) pci_match_id(ene_tune_tbl, dev); 912 if (id) 913 break; 914 } 915 916 test_c9 = old_c9 = config_readb(socket, ENE_TEST_C9); 917 if (id) { 918 mask = (id->driver_data >> 8) & 0xFF; 919 bits = id->driver_data & 0xFF; 920 921 test_c9 = (test_c9 & ~mask) | bits; 922 } 923 else 924 /* default to clear TLTEnable bit, old behaviour */ 925 test_c9 &= ~ENE_TEST_C9_TLTENABLE; 926 927 printk(KERN_INFO "yenta EnE: chaning testregister 0xC9, %02x -> %02x\n", old_c9, test_c9); 928 config_writeb(socket, ENE_TEST_C9, test_c9); 929} 930 931static int ene_override(struct yenta_socket *socket) 932{ 933 /* install tune_bridge() function */ 934 socket->socket.tune_bridge = ene_tune_bridge; 935 936 return ti1250_override(socket); 937} 938#else 939# define ene_override ti1250_override 940#endif /* !CONFIG_YENTA_ENE_TUNE */ 941 942#endif /* _LINUX_TI113X_H */ 943 944