1/*
2 * Pinctrl data for the NVIDIA Tegra30 pinmux
3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19
20#include "pinctrl-tegra.h"
21
22/*
23 * Most pins affected by the pinmux can also be GPIOs. Define these first.
24 * These must match how the GPIO driver names/numbers its pins.
25 */
26#define _GPIO(offset)				(offset)
27
28#define TEGRA_PIN_CLK_32K_OUT_PA0	_GPIO(0)
29#define TEGRA_PIN_UART3_CTS_N_PA1	_GPIO(1)
30#define TEGRA_PIN_DAP2_FS_PA2		_GPIO(2)
31#define TEGRA_PIN_DAP2_SCLK_PA3		_GPIO(3)
32#define TEGRA_PIN_DAP2_DIN_PA4		_GPIO(4)
33#define TEGRA_PIN_DAP2_DOUT_PA5		_GPIO(5)
34#define TEGRA_PIN_SDMMC3_CLK_PA6	_GPIO(6)
35#define TEGRA_PIN_SDMMC3_CMD_PA7	_GPIO(7)
36#define TEGRA_PIN_GMI_A17_PB0		_GPIO(8)
37#define TEGRA_PIN_GMI_A18_PB1		_GPIO(9)
38#define TEGRA_PIN_LCD_PWR0_PB2		_GPIO(10)
39#define TEGRA_PIN_LCD_PCLK_PB3		_GPIO(11)
40#define TEGRA_PIN_SDMMC3_DAT3_PB4	_GPIO(12)
41#define TEGRA_PIN_SDMMC3_DAT2_PB5	_GPIO(13)
42#define TEGRA_PIN_SDMMC3_DAT1_PB6	_GPIO(14)
43#define TEGRA_PIN_SDMMC3_DAT0_PB7	_GPIO(15)
44#define TEGRA_PIN_UART3_RTS_N_PC0	_GPIO(16)
45#define TEGRA_PIN_LCD_PWR1_PC1		_GPIO(17)
46#define TEGRA_PIN_UART2_TXD_PC2		_GPIO(18)
47#define TEGRA_PIN_UART2_RXD_PC3		_GPIO(19)
48#define TEGRA_PIN_GEN1_I2C_SCL_PC4	_GPIO(20)
49#define TEGRA_PIN_GEN1_I2C_SDA_PC5	_GPIO(21)
50#define TEGRA_PIN_LCD_PWR2_PC6		_GPIO(22)
51#define TEGRA_PIN_GMI_WP_N_PC7		_GPIO(23)
52#define TEGRA_PIN_SDMMC3_DAT5_PD0	_GPIO(24)
53#define TEGRA_PIN_SDMMC3_DAT4_PD1	_GPIO(25)
54#define TEGRA_PIN_LCD_DC1_PD2		_GPIO(26)
55#define TEGRA_PIN_SDMMC3_DAT6_PD3	_GPIO(27)
56#define TEGRA_PIN_SDMMC3_DAT7_PD4	_GPIO(28)
57#define TEGRA_PIN_VI_D1_PD5		_GPIO(29)
58#define TEGRA_PIN_VI_VSYNC_PD6		_GPIO(30)
59#define TEGRA_PIN_VI_HSYNC_PD7		_GPIO(31)
60#define TEGRA_PIN_LCD_D0_PE0		_GPIO(32)
61#define TEGRA_PIN_LCD_D1_PE1		_GPIO(33)
62#define TEGRA_PIN_LCD_D2_PE2		_GPIO(34)
63#define TEGRA_PIN_LCD_D3_PE3		_GPIO(35)
64#define TEGRA_PIN_LCD_D4_PE4		_GPIO(36)
65#define TEGRA_PIN_LCD_D5_PE5		_GPIO(37)
66#define TEGRA_PIN_LCD_D6_PE6		_GPIO(38)
67#define TEGRA_PIN_LCD_D7_PE7		_GPIO(39)
68#define TEGRA_PIN_LCD_D8_PF0		_GPIO(40)
69#define TEGRA_PIN_LCD_D9_PF1		_GPIO(41)
70#define TEGRA_PIN_LCD_D10_PF2		_GPIO(42)
71#define TEGRA_PIN_LCD_D11_PF3		_GPIO(43)
72#define TEGRA_PIN_LCD_D12_PF4		_GPIO(44)
73#define TEGRA_PIN_LCD_D13_PF5		_GPIO(45)
74#define TEGRA_PIN_LCD_D14_PF6		_GPIO(46)
75#define TEGRA_PIN_LCD_D15_PF7		_GPIO(47)
76#define TEGRA_PIN_GMI_AD0_PG0		_GPIO(48)
77#define TEGRA_PIN_GMI_AD1_PG1		_GPIO(49)
78#define TEGRA_PIN_GMI_AD2_PG2		_GPIO(50)
79#define TEGRA_PIN_GMI_AD3_PG3		_GPIO(51)
80#define TEGRA_PIN_GMI_AD4_PG4		_GPIO(52)
81#define TEGRA_PIN_GMI_AD5_PG5		_GPIO(53)
82#define TEGRA_PIN_GMI_AD6_PG6		_GPIO(54)
83#define TEGRA_PIN_GMI_AD7_PG7		_GPIO(55)
84#define TEGRA_PIN_GMI_AD8_PH0		_GPIO(56)
85#define TEGRA_PIN_GMI_AD9_PH1		_GPIO(57)
86#define TEGRA_PIN_GMI_AD10_PH2		_GPIO(58)
87#define TEGRA_PIN_GMI_AD11_PH3		_GPIO(59)
88#define TEGRA_PIN_GMI_AD12_PH4		_GPIO(60)
89#define TEGRA_PIN_GMI_AD13_PH5		_GPIO(61)
90#define TEGRA_PIN_GMI_AD14_PH6		_GPIO(62)
91#define TEGRA_PIN_GMI_AD15_PH7		_GPIO(63)
92#define TEGRA_PIN_GMI_WR_N_PI0		_GPIO(64)
93#define TEGRA_PIN_GMI_OE_N_PI1		_GPIO(65)
94#define TEGRA_PIN_GMI_DQS_PI2		_GPIO(66)
95#define TEGRA_PIN_GMI_CS6_N_PI3		_GPIO(67)
96#define TEGRA_PIN_GMI_RST_N_PI4		_GPIO(68)
97#define TEGRA_PIN_GMI_IORDY_PI5		_GPIO(69)
98#define TEGRA_PIN_GMI_CS7_N_PI6		_GPIO(70)
99#define TEGRA_PIN_GMI_WAIT_PI7		_GPIO(71)
100#define TEGRA_PIN_GMI_CS0_N_PJ0		_GPIO(72)
101#define TEGRA_PIN_LCD_DE_PJ1		_GPIO(73)
102#define TEGRA_PIN_GMI_CS1_N_PJ2		_GPIO(74)
103#define TEGRA_PIN_LCD_HSYNC_PJ3		_GPIO(75)
104#define TEGRA_PIN_LCD_VSYNC_PJ4		_GPIO(76)
105#define TEGRA_PIN_UART2_CTS_N_PJ5	_GPIO(77)
106#define TEGRA_PIN_UART2_RTS_N_PJ6	_GPIO(78)
107#define TEGRA_PIN_GMI_A16_PJ7		_GPIO(79)
108#define TEGRA_PIN_GMI_ADV_N_PK0		_GPIO(80)
109#define TEGRA_PIN_GMI_CLK_PK1		_GPIO(81)
110#define TEGRA_PIN_GMI_CS4_N_PK2		_GPIO(82)
111#define TEGRA_PIN_GMI_CS2_N_PK3		_GPIO(83)
112#define TEGRA_PIN_GMI_CS3_N_PK4		_GPIO(84)
113#define TEGRA_PIN_SPDIF_OUT_PK5		_GPIO(85)
114#define TEGRA_PIN_SPDIF_IN_PK6		_GPIO(86)
115#define TEGRA_PIN_GMI_A19_PK7		_GPIO(87)
116#define TEGRA_PIN_VI_D2_PL0		_GPIO(88)
117#define TEGRA_PIN_VI_D3_PL1		_GPIO(89)
118#define TEGRA_PIN_VI_D4_PL2		_GPIO(90)
119#define TEGRA_PIN_VI_D5_PL3		_GPIO(91)
120#define TEGRA_PIN_VI_D6_PL4		_GPIO(92)
121#define TEGRA_PIN_VI_D7_PL5		_GPIO(93)
122#define TEGRA_PIN_VI_D8_PL6		_GPIO(94)
123#define TEGRA_PIN_VI_D9_PL7		_GPIO(95)
124#define TEGRA_PIN_LCD_D16_PM0		_GPIO(96)
125#define TEGRA_PIN_LCD_D17_PM1		_GPIO(97)
126#define TEGRA_PIN_LCD_D18_PM2		_GPIO(98)
127#define TEGRA_PIN_LCD_D19_PM3		_GPIO(99)
128#define TEGRA_PIN_LCD_D20_PM4		_GPIO(100)
129#define TEGRA_PIN_LCD_D21_PM5		_GPIO(101)
130#define TEGRA_PIN_LCD_D22_PM6		_GPIO(102)
131#define TEGRA_PIN_LCD_D23_PM7		_GPIO(103)
132#define TEGRA_PIN_DAP1_FS_PN0		_GPIO(104)
133#define TEGRA_PIN_DAP1_DIN_PN1		_GPIO(105)
134#define TEGRA_PIN_DAP1_DOUT_PN2		_GPIO(106)
135#define TEGRA_PIN_DAP1_SCLK_PN3		_GPIO(107)
136#define TEGRA_PIN_LCD_CS0_N_PN4		_GPIO(108)
137#define TEGRA_PIN_LCD_SDOUT_PN5		_GPIO(109)
138#define TEGRA_PIN_LCD_DC0_PN6		_GPIO(110)
139#define TEGRA_PIN_HDMI_INT_PN7		_GPIO(111)
140#define TEGRA_PIN_ULPI_DATA7_PO0	_GPIO(112)
141#define TEGRA_PIN_ULPI_DATA0_PO1	_GPIO(113)
142#define TEGRA_PIN_ULPI_DATA1_PO2	_GPIO(114)
143#define TEGRA_PIN_ULPI_DATA2_PO3	_GPIO(115)
144#define TEGRA_PIN_ULPI_DATA3_PO4	_GPIO(116)
145#define TEGRA_PIN_ULPI_DATA4_PO5	_GPIO(117)
146#define TEGRA_PIN_ULPI_DATA5_PO6	_GPIO(118)
147#define TEGRA_PIN_ULPI_DATA6_PO7	_GPIO(119)
148#define TEGRA_PIN_DAP3_FS_PP0		_GPIO(120)
149#define TEGRA_PIN_DAP3_DIN_PP1		_GPIO(121)
150#define TEGRA_PIN_DAP3_DOUT_PP2		_GPIO(122)
151#define TEGRA_PIN_DAP3_SCLK_PP3		_GPIO(123)
152#define TEGRA_PIN_DAP4_FS_PP4		_GPIO(124)
153#define TEGRA_PIN_DAP4_DIN_PP5		_GPIO(125)
154#define TEGRA_PIN_DAP4_DOUT_PP6		_GPIO(126)
155#define TEGRA_PIN_DAP4_SCLK_PP7		_GPIO(127)
156#define TEGRA_PIN_KB_COL0_PQ0		_GPIO(128)
157#define TEGRA_PIN_KB_COL1_PQ1		_GPIO(129)
158#define TEGRA_PIN_KB_COL2_PQ2		_GPIO(130)
159#define TEGRA_PIN_KB_COL3_PQ3		_GPIO(131)
160#define TEGRA_PIN_KB_COL4_PQ4		_GPIO(132)
161#define TEGRA_PIN_KB_COL5_PQ5		_GPIO(133)
162#define TEGRA_PIN_KB_COL6_PQ6		_GPIO(134)
163#define TEGRA_PIN_KB_COL7_PQ7		_GPIO(135)
164#define TEGRA_PIN_KB_ROW0_PR0		_GPIO(136)
165#define TEGRA_PIN_KB_ROW1_PR1		_GPIO(137)
166#define TEGRA_PIN_KB_ROW2_PR2		_GPIO(138)
167#define TEGRA_PIN_KB_ROW3_PR3		_GPIO(139)
168#define TEGRA_PIN_KB_ROW4_PR4		_GPIO(140)
169#define TEGRA_PIN_KB_ROW5_PR5		_GPIO(141)
170#define TEGRA_PIN_KB_ROW6_PR6		_GPIO(142)
171#define TEGRA_PIN_KB_ROW7_PR7		_GPIO(143)
172#define TEGRA_PIN_KB_ROW8_PS0		_GPIO(144)
173#define TEGRA_PIN_KB_ROW9_PS1		_GPIO(145)
174#define TEGRA_PIN_KB_ROW10_PS2		_GPIO(146)
175#define TEGRA_PIN_KB_ROW11_PS3		_GPIO(147)
176#define TEGRA_PIN_KB_ROW12_PS4		_GPIO(148)
177#define TEGRA_PIN_KB_ROW13_PS5		_GPIO(149)
178#define TEGRA_PIN_KB_ROW14_PS6		_GPIO(150)
179#define TEGRA_PIN_KB_ROW15_PS7		_GPIO(151)
180#define TEGRA_PIN_VI_PCLK_PT0		_GPIO(152)
181#define TEGRA_PIN_VI_MCLK_PT1		_GPIO(153)
182#define TEGRA_PIN_VI_D10_PT2		_GPIO(154)
183#define TEGRA_PIN_VI_D11_PT3		_GPIO(155)
184#define TEGRA_PIN_VI_D0_PT4		_GPIO(156)
185#define TEGRA_PIN_GEN2_I2C_SCL_PT5	_GPIO(157)
186#define TEGRA_PIN_GEN2_I2C_SDA_PT6	_GPIO(158)
187#define TEGRA_PIN_SDMMC4_CMD_PT7	_GPIO(159)
188#define TEGRA_PIN_PU0			_GPIO(160)
189#define TEGRA_PIN_PU1			_GPIO(161)
190#define TEGRA_PIN_PU2			_GPIO(162)
191#define TEGRA_PIN_PU3			_GPIO(163)
192#define TEGRA_PIN_PU4			_GPIO(164)
193#define TEGRA_PIN_PU5			_GPIO(165)
194#define TEGRA_PIN_PU6			_GPIO(166)
195#define TEGRA_PIN_JTAG_RTCK_PU7		_GPIO(167)
196#define TEGRA_PIN_PV0			_GPIO(168)
197#define TEGRA_PIN_PV1			_GPIO(169)
198#define TEGRA_PIN_PV2			_GPIO(170)
199#define TEGRA_PIN_PV3			_GPIO(171)
200#define TEGRA_PIN_DDC_SCL_PV4		_GPIO(172)
201#define TEGRA_PIN_DDC_SDA_PV5		_GPIO(173)
202#define TEGRA_PIN_CRT_HSYNC_PV6		_GPIO(174)
203#define TEGRA_PIN_CRT_VSYNC_PV7		_GPIO(175)
204#define TEGRA_PIN_LCD_CS1_N_PW0		_GPIO(176)
205#define TEGRA_PIN_LCD_M1_PW1		_GPIO(177)
206#define TEGRA_PIN_SPI2_CS1_N_PW2	_GPIO(178)
207#define TEGRA_PIN_SPI2_CS2_N_PW3	_GPIO(179)
208#define TEGRA_PIN_CLK1_OUT_PW4		_GPIO(180)
209#define TEGRA_PIN_CLK2_OUT_PW5		_GPIO(181)
210#define TEGRA_PIN_UART3_TXD_PW6		_GPIO(182)
211#define TEGRA_PIN_UART3_RXD_PW7		_GPIO(183)
212#define TEGRA_PIN_SPI2_MOSI_PX0		_GPIO(184)
213#define TEGRA_PIN_SPI2_MISO_PX1		_GPIO(185)
214#define TEGRA_PIN_SPI2_SCK_PX2		_GPIO(186)
215#define TEGRA_PIN_SPI2_CS0_N_PX3	_GPIO(187)
216#define TEGRA_PIN_SPI1_MOSI_PX4		_GPIO(188)
217#define TEGRA_PIN_SPI1_SCK_PX5		_GPIO(189)
218#define TEGRA_PIN_SPI1_CS0_N_PX6	_GPIO(190)
219#define TEGRA_PIN_SPI1_MISO_PX7		_GPIO(191)
220#define TEGRA_PIN_ULPI_CLK_PY0		_GPIO(192)
221#define TEGRA_PIN_ULPI_DIR_PY1		_GPIO(193)
222#define TEGRA_PIN_ULPI_NXT_PY2		_GPIO(194)
223#define TEGRA_PIN_ULPI_STP_PY3		_GPIO(195)
224#define TEGRA_PIN_SDMMC1_DAT3_PY4	_GPIO(196)
225#define TEGRA_PIN_SDMMC1_DAT2_PY5	_GPIO(197)
226#define TEGRA_PIN_SDMMC1_DAT1_PY6	_GPIO(198)
227#define TEGRA_PIN_SDMMC1_DAT0_PY7	_GPIO(199)
228#define TEGRA_PIN_SDMMC1_CLK_PZ0	_GPIO(200)
229#define TEGRA_PIN_SDMMC1_CMD_PZ1	_GPIO(201)
230#define TEGRA_PIN_LCD_SDIN_PZ2		_GPIO(202)
231#define TEGRA_PIN_LCD_WR_N_PZ3		_GPIO(203)
232#define TEGRA_PIN_LCD_SCK_PZ4		_GPIO(204)
233#define TEGRA_PIN_SYS_CLK_REQ_PZ5	_GPIO(205)
234#define TEGRA_PIN_PWR_I2C_SCL_PZ6	_GPIO(206)
235#define TEGRA_PIN_PWR_I2C_SDA_PZ7	_GPIO(207)
236#define TEGRA_PIN_SDMMC4_DAT0_PAA0	_GPIO(208)
237#define TEGRA_PIN_SDMMC4_DAT1_PAA1	_GPIO(209)
238#define TEGRA_PIN_SDMMC4_DAT2_PAA2	_GPIO(210)
239#define TEGRA_PIN_SDMMC4_DAT3_PAA3	_GPIO(211)
240#define TEGRA_PIN_SDMMC4_DAT4_PAA4	_GPIO(212)
241#define TEGRA_PIN_SDMMC4_DAT5_PAA5	_GPIO(213)
242#define TEGRA_PIN_SDMMC4_DAT6_PAA6	_GPIO(214)
243#define TEGRA_PIN_SDMMC4_DAT7_PAA7	_GPIO(215)
244#define TEGRA_PIN_PBB0			_GPIO(216)
245#define TEGRA_PIN_CAM_I2C_SCL_PBB1	_GPIO(217)
246#define TEGRA_PIN_CAM_I2C_SDA_PBB2	_GPIO(218)
247#define TEGRA_PIN_PBB3			_GPIO(219)
248#define TEGRA_PIN_PBB4			_GPIO(220)
249#define TEGRA_PIN_PBB5			_GPIO(221)
250#define TEGRA_PIN_PBB6			_GPIO(222)
251#define TEGRA_PIN_PBB7			_GPIO(223)
252#define TEGRA_PIN_CAM_MCLK_PCC0		_GPIO(224)
253#define TEGRA_PIN_PCC1			_GPIO(225)
254#define TEGRA_PIN_PCC2			_GPIO(226)
255#define TEGRA_PIN_SDMMC4_RST_N_PCC3	_GPIO(227)
256#define TEGRA_PIN_SDMMC4_CLK_PCC4	_GPIO(228)
257#define TEGRA_PIN_CLK2_REQ_PCC5		_GPIO(229)
258#define TEGRA_PIN_PEX_L2_RST_N_PCC6	_GPIO(230)
259#define TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7	_GPIO(231)
260#define TEGRA_PIN_PEX_L0_PRSNT_N_PDD0	_GPIO(232)
261#define TEGRA_PIN_PEX_L0_RST_N_PDD1	_GPIO(233)
262#define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2	_GPIO(234)
263#define TEGRA_PIN_PEX_WAKE_N_PDD3	_GPIO(235)
264#define TEGRA_PIN_PEX_L1_PRSNT_N_PDD4	_GPIO(236)
265#define TEGRA_PIN_PEX_L1_RST_N_PDD5	_GPIO(237)
266#define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6	_GPIO(238)
267#define TEGRA_PIN_PEX_L2_PRSNT_N_PDD7	_GPIO(239)
268#define TEGRA_PIN_CLK3_OUT_PEE0		_GPIO(240)
269#define TEGRA_PIN_CLK3_REQ_PEE1		_GPIO(241)
270#define TEGRA_PIN_CLK1_REQ_PEE2		_GPIO(242)
271#define TEGRA_PIN_HDMI_CEC_PEE3		_GPIO(243)
272#define TEGRA_PIN_PEE4			_GPIO(244)
273#define TEGRA_PIN_PEE5			_GPIO(245)
274#define TEGRA_PIN_PEE6			_GPIO(246)
275#define TEGRA_PIN_PEE7			_GPIO(247)
276
277/* All non-GPIO pins follow */
278#define NUM_GPIOS				(TEGRA_PIN_PEE7 + 1)
279#define _PIN(offset)				(NUM_GPIOS + (offset))
280
281/* Non-GPIO pins */
282#define TEGRA_PIN_CLK_32K_IN		_PIN(0)
283#define TEGRA_PIN_CORE_PWR_REQ		_PIN(1)
284#define TEGRA_PIN_CPU_PWR_REQ		_PIN(2)
285#define TEGRA_PIN_JTAG_TCK		_PIN(3)
286#define TEGRA_PIN_JTAG_TDI		_PIN(4)
287#define TEGRA_PIN_JTAG_TDO		_PIN(5)
288#define TEGRA_PIN_JTAG_TMS		_PIN(6)
289#define TEGRA_PIN_JTAG_TRST_N		_PIN(7)
290#define TEGRA_PIN_OWR			_PIN(8)
291#define TEGRA_PIN_PWR_INT_N		_PIN(9)
292#define TEGRA_PIN_SYS_RESET_N		_PIN(10)
293#define TEGRA_PIN_TEST_MODE_EN		_PIN(11)
294
295static const struct pinctrl_pin_desc tegra30_pins[] = {
296	PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
297	PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
298	PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
299	PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
300	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
301	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
302	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
303	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
304	PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
305	PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
306	PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
307	PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
308	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
309	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
310	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
311	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
312	PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
313	PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
314	PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
315	PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
316	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
317	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
318	PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
319	PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
320	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT5_PD0, "SDMMC3_DAT5 PD0"),
321	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "SDMMC3_DAT4 PD1"),
322	PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, "LCD_DC1 PD2"),
323	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "SDMMC3_DAT6 PD3"),
324	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, "SDMMC3_DAT7 PD4"),
325	PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
326	PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
327	PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
328	PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
329	PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
330	PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
331	PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
332	PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
333	PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
334	PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
335	PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
336	PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
337	PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
338	PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
339	PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
340	PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
341	PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
342	PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
343	PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
344	PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
345	PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
346	PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
347	PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
348	PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
349	PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
350	PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
351	PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
352	PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
353	PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
354	PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
355	PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
356	PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
357	PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
358	PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
359	PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
360	PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
361	PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
362	PINCTRL_PIN(TEGRA_PIN_GMI_DQS_PI2, "GMI_DQS PI2"),
363	PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
364	PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
365	PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
366	PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
367	PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
368	PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
369	PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
370	PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
371	PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
372	PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
373	PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
374	PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
375	PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
376	PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
377	PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
378	PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
379	PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
380	PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
381	PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
382	PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
383	PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
384	PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
385	PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
386	PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
387	PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
388	PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
389	PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
390	PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
391	PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
392	PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
393	PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
394	PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
395	PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
396	PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
397	PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
398	PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
399	PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
400	PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
401	PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
402	PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
403	PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
404	PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
405	PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
406	PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
407	PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
408	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
409	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
410	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
411	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
412	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
413	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
414	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
415	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
416	PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
417	PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
418	PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
419	PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
420	PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
421	PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
422	PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
423	PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
424	PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
425	PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
426	PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
427	PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
428	PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
429	PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
430	PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
431	PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
432	PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
433	PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
434	PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
435	PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
436	PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
437	PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
438	PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
439	PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
440	PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
441	PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
442	PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
443	PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
444	PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
445	PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
446	PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
447	PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
448	PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
449	PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
450	PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VI_D10 PT2"),
451	PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
452	PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
453	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
454	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
455	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
456	PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
457	PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
458	PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
459	PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
460	PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
461	PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
462	PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
463	PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
464	PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
465	PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
466	PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
467	PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
468	PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
469	PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
470	PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC_PV6, "CRT_HSYNC PV6"),
471	PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC_PV7, "CRT_VSYNC PV7"),
472	PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
473	PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
474	PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
475	PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
476	PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
477	PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
478	PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
479	PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
480	PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
481	PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
482	PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
483	PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
484	PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
485	PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
486	PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
487	PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
488	PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
489	PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
490	PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
491	PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
492	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
493	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
494	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
495	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
496	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
497	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
498	PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
499	PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
500	PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
501	PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
502	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
503	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
504	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
505	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
506	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
507	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
508	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
509	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
510	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
511	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
512	PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
513	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
514	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
515	PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
516	PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
517	PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
518	PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
519	PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
520	PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
521	PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
522	PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
523	PINCTRL_PIN(TEGRA_PIN_SDMMC4_RST_N_PCC3, "SDMMC4_RST_N PCC3"),
524	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
525	PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
526	PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PCC6, "PEX_L2_RST_N PCC6"),
527	PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7, "PEX_L2_CLKREQ_N PCC7"),
528	PINCTRL_PIN(TEGRA_PIN_PEX_L0_PRSNT_N_PDD0, "PEX_L0_PRSNT_N PDD0"),
529	PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
530	PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
531	PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
532	PINCTRL_PIN(TEGRA_PIN_PEX_L1_PRSNT_N_PDD4, "PEX_L1_PRSNT_N PDD4"),
533	PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
534	PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
535	PINCTRL_PIN(TEGRA_PIN_PEX_L2_PRSNT_N_PDD7, "PEX_L2_PRSNT_N PDD7"),
536	PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
537	PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
538	PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
539	PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
540	PINCTRL_PIN(TEGRA_PIN_PEE4, "PEE4"),
541	PINCTRL_PIN(TEGRA_PIN_PEE5, "PEE5"),
542	PINCTRL_PIN(TEGRA_PIN_PEE6, "PEE6"),
543	PINCTRL_PIN(TEGRA_PIN_PEE7, "PEE7"),
544	PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
545	PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
546	PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
547	PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
548	PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
549	PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
550	PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
551	PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
552	PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
553	PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
554	PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
555	PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
556};
557
558static const unsigned clk_32k_out_pa0_pins[] = {
559	TEGRA_PIN_CLK_32K_OUT_PA0,
560};
561
562static const unsigned uart3_cts_n_pa1_pins[] = {
563	TEGRA_PIN_UART3_CTS_N_PA1,
564};
565
566static const unsigned dap2_fs_pa2_pins[] = {
567	TEGRA_PIN_DAP2_FS_PA2,
568};
569
570static const unsigned dap2_sclk_pa3_pins[] = {
571	TEGRA_PIN_DAP2_SCLK_PA3,
572};
573
574static const unsigned dap2_din_pa4_pins[] = {
575	TEGRA_PIN_DAP2_DIN_PA4,
576};
577
578static const unsigned dap2_dout_pa5_pins[] = {
579	TEGRA_PIN_DAP2_DOUT_PA5,
580};
581
582static const unsigned sdmmc3_clk_pa6_pins[] = {
583	TEGRA_PIN_SDMMC3_CLK_PA6,
584};
585
586static const unsigned sdmmc3_cmd_pa7_pins[] = {
587	TEGRA_PIN_SDMMC3_CMD_PA7,
588};
589
590static const unsigned gmi_a17_pb0_pins[] = {
591	TEGRA_PIN_GMI_A17_PB0,
592};
593
594static const unsigned gmi_a18_pb1_pins[] = {
595	TEGRA_PIN_GMI_A18_PB1,
596};
597
598static const unsigned lcd_pwr0_pb2_pins[] = {
599	TEGRA_PIN_LCD_PWR0_PB2,
600};
601
602static const unsigned lcd_pclk_pb3_pins[] = {
603	TEGRA_PIN_LCD_PCLK_PB3,
604};
605
606static const unsigned sdmmc3_dat3_pb4_pins[] = {
607	TEGRA_PIN_SDMMC3_DAT3_PB4,
608};
609
610static const unsigned sdmmc3_dat2_pb5_pins[] = {
611	TEGRA_PIN_SDMMC3_DAT2_PB5,
612};
613
614static const unsigned sdmmc3_dat1_pb6_pins[] = {
615	TEGRA_PIN_SDMMC3_DAT1_PB6,
616};
617
618static const unsigned sdmmc3_dat0_pb7_pins[] = {
619	TEGRA_PIN_SDMMC3_DAT0_PB7,
620};
621
622static const unsigned uart3_rts_n_pc0_pins[] = {
623	TEGRA_PIN_UART3_RTS_N_PC0,
624};
625
626static const unsigned lcd_pwr1_pc1_pins[] = {
627	TEGRA_PIN_LCD_PWR1_PC1,
628};
629
630static const unsigned uart2_txd_pc2_pins[] = {
631	TEGRA_PIN_UART2_TXD_PC2,
632};
633
634static const unsigned uart2_rxd_pc3_pins[] = {
635	TEGRA_PIN_UART2_RXD_PC3,
636};
637
638static const unsigned gen1_i2c_scl_pc4_pins[] = {
639	TEGRA_PIN_GEN1_I2C_SCL_PC4,
640};
641
642static const unsigned gen1_i2c_sda_pc5_pins[] = {
643	TEGRA_PIN_GEN1_I2C_SDA_PC5,
644};
645
646static const unsigned lcd_pwr2_pc6_pins[] = {
647	TEGRA_PIN_LCD_PWR2_PC6,
648};
649
650static const unsigned gmi_wp_n_pc7_pins[] = {
651	TEGRA_PIN_GMI_WP_N_PC7,
652};
653
654static const unsigned sdmmc3_dat5_pd0_pins[] = {
655	TEGRA_PIN_SDMMC3_DAT5_PD0,
656};
657
658static const unsigned sdmmc3_dat4_pd1_pins[] = {
659	TEGRA_PIN_SDMMC3_DAT4_PD1,
660};
661
662static const unsigned lcd_dc1_pd2_pins[] = {
663	TEGRA_PIN_LCD_DC1_PD2,
664};
665
666static const unsigned sdmmc3_dat6_pd3_pins[] = {
667	TEGRA_PIN_SDMMC3_DAT6_PD3,
668};
669
670static const unsigned sdmmc3_dat7_pd4_pins[] = {
671	TEGRA_PIN_SDMMC3_DAT7_PD4,
672};
673
674static const unsigned vi_d1_pd5_pins[] = {
675	TEGRA_PIN_VI_D1_PD5,
676};
677
678static const unsigned vi_vsync_pd6_pins[] = {
679	TEGRA_PIN_VI_VSYNC_PD6,
680};
681
682static const unsigned vi_hsync_pd7_pins[] = {
683	TEGRA_PIN_VI_HSYNC_PD7,
684};
685
686static const unsigned lcd_d0_pe0_pins[] = {
687	TEGRA_PIN_LCD_D0_PE0,
688};
689
690static const unsigned lcd_d1_pe1_pins[] = {
691	TEGRA_PIN_LCD_D1_PE1,
692};
693
694static const unsigned lcd_d2_pe2_pins[] = {
695	TEGRA_PIN_LCD_D2_PE2,
696};
697
698static const unsigned lcd_d3_pe3_pins[] = {
699	TEGRA_PIN_LCD_D3_PE3,
700};
701
702static const unsigned lcd_d4_pe4_pins[] = {
703	TEGRA_PIN_LCD_D4_PE4,
704};
705
706static const unsigned lcd_d5_pe5_pins[] = {
707	TEGRA_PIN_LCD_D5_PE5,
708};
709
710static const unsigned lcd_d6_pe6_pins[] = {
711	TEGRA_PIN_LCD_D6_PE6,
712};
713
714static const unsigned lcd_d7_pe7_pins[] = {
715	TEGRA_PIN_LCD_D7_PE7,
716};
717
718static const unsigned lcd_d8_pf0_pins[] = {
719	TEGRA_PIN_LCD_D8_PF0,
720};
721
722static const unsigned lcd_d9_pf1_pins[] = {
723	TEGRA_PIN_LCD_D9_PF1,
724};
725
726static const unsigned lcd_d10_pf2_pins[] = {
727	TEGRA_PIN_LCD_D10_PF2,
728};
729
730static const unsigned lcd_d11_pf3_pins[] = {
731	TEGRA_PIN_LCD_D11_PF3,
732};
733
734static const unsigned lcd_d12_pf4_pins[] = {
735	TEGRA_PIN_LCD_D12_PF4,
736};
737
738static const unsigned lcd_d13_pf5_pins[] = {
739	TEGRA_PIN_LCD_D13_PF5,
740};
741
742static const unsigned lcd_d14_pf6_pins[] = {
743	TEGRA_PIN_LCD_D14_PF6,
744};
745
746static const unsigned lcd_d15_pf7_pins[] = {
747	TEGRA_PIN_LCD_D15_PF7,
748};
749
750static const unsigned gmi_ad0_pg0_pins[] = {
751	TEGRA_PIN_GMI_AD0_PG0,
752};
753
754static const unsigned gmi_ad1_pg1_pins[] = {
755	TEGRA_PIN_GMI_AD1_PG1,
756};
757
758static const unsigned gmi_ad2_pg2_pins[] = {
759	TEGRA_PIN_GMI_AD2_PG2,
760};
761
762static const unsigned gmi_ad3_pg3_pins[] = {
763	TEGRA_PIN_GMI_AD3_PG3,
764};
765
766static const unsigned gmi_ad4_pg4_pins[] = {
767	TEGRA_PIN_GMI_AD4_PG4,
768};
769
770static const unsigned gmi_ad5_pg5_pins[] = {
771	TEGRA_PIN_GMI_AD5_PG5,
772};
773
774static const unsigned gmi_ad6_pg6_pins[] = {
775	TEGRA_PIN_GMI_AD6_PG6,
776};
777
778static const unsigned gmi_ad7_pg7_pins[] = {
779	TEGRA_PIN_GMI_AD7_PG7,
780};
781
782static const unsigned gmi_ad8_ph0_pins[] = {
783	TEGRA_PIN_GMI_AD8_PH0,
784};
785
786static const unsigned gmi_ad9_ph1_pins[] = {
787	TEGRA_PIN_GMI_AD9_PH1,
788};
789
790static const unsigned gmi_ad10_ph2_pins[] = {
791	TEGRA_PIN_GMI_AD10_PH2,
792};
793
794static const unsigned gmi_ad11_ph3_pins[] = {
795	TEGRA_PIN_GMI_AD11_PH3,
796};
797
798static const unsigned gmi_ad12_ph4_pins[] = {
799	TEGRA_PIN_GMI_AD12_PH4,
800};
801
802static const unsigned gmi_ad13_ph5_pins[] = {
803	TEGRA_PIN_GMI_AD13_PH5,
804};
805
806static const unsigned gmi_ad14_ph6_pins[] = {
807	TEGRA_PIN_GMI_AD14_PH6,
808};
809
810static const unsigned gmi_ad15_ph7_pins[] = {
811	TEGRA_PIN_GMI_AD15_PH7,
812};
813
814static const unsigned gmi_wr_n_pi0_pins[] = {
815	TEGRA_PIN_GMI_WR_N_PI0,
816};
817
818static const unsigned gmi_oe_n_pi1_pins[] = {
819	TEGRA_PIN_GMI_OE_N_PI1,
820};
821
822static const unsigned gmi_dqs_pi2_pins[] = {
823	TEGRA_PIN_GMI_DQS_PI2,
824};
825
826static const unsigned gmi_cs6_n_pi3_pins[] = {
827	TEGRA_PIN_GMI_CS6_N_PI3,
828};
829
830static const unsigned gmi_rst_n_pi4_pins[] = {
831	TEGRA_PIN_GMI_RST_N_PI4,
832};
833
834static const unsigned gmi_iordy_pi5_pins[] = {
835	TEGRA_PIN_GMI_IORDY_PI5,
836};
837
838static const unsigned gmi_cs7_n_pi6_pins[] = {
839	TEGRA_PIN_GMI_CS7_N_PI6,
840};
841
842static const unsigned gmi_wait_pi7_pins[] = {
843	TEGRA_PIN_GMI_WAIT_PI7,
844};
845
846static const unsigned gmi_cs0_n_pj0_pins[] = {
847	TEGRA_PIN_GMI_CS0_N_PJ0,
848};
849
850static const unsigned lcd_de_pj1_pins[] = {
851	TEGRA_PIN_LCD_DE_PJ1,
852};
853
854static const unsigned gmi_cs1_n_pj2_pins[] = {
855	TEGRA_PIN_GMI_CS1_N_PJ2,
856};
857
858static const unsigned lcd_hsync_pj3_pins[] = {
859	TEGRA_PIN_LCD_HSYNC_PJ3,
860};
861
862static const unsigned lcd_vsync_pj4_pins[] = {
863	TEGRA_PIN_LCD_VSYNC_PJ4,
864};
865
866static const unsigned uart2_cts_n_pj5_pins[] = {
867	TEGRA_PIN_UART2_CTS_N_PJ5,
868};
869
870static const unsigned uart2_rts_n_pj6_pins[] = {
871	TEGRA_PIN_UART2_RTS_N_PJ6,
872};
873
874static const unsigned gmi_a16_pj7_pins[] = {
875	TEGRA_PIN_GMI_A16_PJ7,
876};
877
878static const unsigned gmi_adv_n_pk0_pins[] = {
879	TEGRA_PIN_GMI_ADV_N_PK0,
880};
881
882static const unsigned gmi_clk_pk1_pins[] = {
883	TEGRA_PIN_GMI_CLK_PK1,
884};
885
886static const unsigned gmi_cs4_n_pk2_pins[] = {
887	TEGRA_PIN_GMI_CS4_N_PK2,
888};
889
890static const unsigned gmi_cs2_n_pk3_pins[] = {
891	TEGRA_PIN_GMI_CS2_N_PK3,
892};
893
894static const unsigned gmi_cs3_n_pk4_pins[] = {
895	TEGRA_PIN_GMI_CS3_N_PK4,
896};
897
898static const unsigned spdif_out_pk5_pins[] = {
899	TEGRA_PIN_SPDIF_OUT_PK5,
900};
901
902static const unsigned spdif_in_pk6_pins[] = {
903	TEGRA_PIN_SPDIF_IN_PK6,
904};
905
906static const unsigned gmi_a19_pk7_pins[] = {
907	TEGRA_PIN_GMI_A19_PK7,
908};
909
910static const unsigned vi_d2_pl0_pins[] = {
911	TEGRA_PIN_VI_D2_PL0,
912};
913
914static const unsigned vi_d3_pl1_pins[] = {
915	TEGRA_PIN_VI_D3_PL1,
916};
917
918static const unsigned vi_d4_pl2_pins[] = {
919	TEGRA_PIN_VI_D4_PL2,
920};
921
922static const unsigned vi_d5_pl3_pins[] = {
923	TEGRA_PIN_VI_D5_PL3,
924};
925
926static const unsigned vi_d6_pl4_pins[] = {
927	TEGRA_PIN_VI_D6_PL4,
928};
929
930static const unsigned vi_d7_pl5_pins[] = {
931	TEGRA_PIN_VI_D7_PL5,
932};
933
934static const unsigned vi_d8_pl6_pins[] = {
935	TEGRA_PIN_VI_D8_PL6,
936};
937
938static const unsigned vi_d9_pl7_pins[] = {
939	TEGRA_PIN_VI_D9_PL7,
940};
941
942static const unsigned lcd_d16_pm0_pins[] = {
943	TEGRA_PIN_LCD_D16_PM0,
944};
945
946static const unsigned lcd_d17_pm1_pins[] = {
947	TEGRA_PIN_LCD_D17_PM1,
948};
949
950static const unsigned lcd_d18_pm2_pins[] = {
951	TEGRA_PIN_LCD_D18_PM2,
952};
953
954static const unsigned lcd_d19_pm3_pins[] = {
955	TEGRA_PIN_LCD_D19_PM3,
956};
957
958static const unsigned lcd_d20_pm4_pins[] = {
959	TEGRA_PIN_LCD_D20_PM4,
960};
961
962static const unsigned lcd_d21_pm5_pins[] = {
963	TEGRA_PIN_LCD_D21_PM5,
964};
965
966static const unsigned lcd_d22_pm6_pins[] = {
967	TEGRA_PIN_LCD_D22_PM6,
968};
969
970static const unsigned lcd_d23_pm7_pins[] = {
971	TEGRA_PIN_LCD_D23_PM7,
972};
973
974static const unsigned dap1_fs_pn0_pins[] = {
975	TEGRA_PIN_DAP1_FS_PN0,
976};
977
978static const unsigned dap1_din_pn1_pins[] = {
979	TEGRA_PIN_DAP1_DIN_PN1,
980};
981
982static const unsigned dap1_dout_pn2_pins[] = {
983	TEGRA_PIN_DAP1_DOUT_PN2,
984};
985
986static const unsigned dap1_sclk_pn3_pins[] = {
987	TEGRA_PIN_DAP1_SCLK_PN3,
988};
989
990static const unsigned lcd_cs0_n_pn4_pins[] = {
991	TEGRA_PIN_LCD_CS0_N_PN4,
992};
993
994static const unsigned lcd_sdout_pn5_pins[] = {
995	TEGRA_PIN_LCD_SDOUT_PN5,
996};
997
998static const unsigned lcd_dc0_pn6_pins[] = {
999	TEGRA_PIN_LCD_DC0_PN6,
1000};
1001
1002static const unsigned hdmi_int_pn7_pins[] = {
1003	TEGRA_PIN_HDMI_INT_PN7,
1004};
1005
1006static const unsigned ulpi_data7_po0_pins[] = {
1007	TEGRA_PIN_ULPI_DATA7_PO0,
1008};
1009
1010static const unsigned ulpi_data0_po1_pins[] = {
1011	TEGRA_PIN_ULPI_DATA0_PO1,
1012};
1013
1014static const unsigned ulpi_data1_po2_pins[] = {
1015	TEGRA_PIN_ULPI_DATA1_PO2,
1016};
1017
1018static const unsigned ulpi_data2_po3_pins[] = {
1019	TEGRA_PIN_ULPI_DATA2_PO3,
1020};
1021
1022static const unsigned ulpi_data3_po4_pins[] = {
1023	TEGRA_PIN_ULPI_DATA3_PO4,
1024};
1025
1026static const unsigned ulpi_data4_po5_pins[] = {
1027	TEGRA_PIN_ULPI_DATA4_PO5,
1028};
1029
1030static const unsigned ulpi_data5_po6_pins[] = {
1031	TEGRA_PIN_ULPI_DATA5_PO6,
1032};
1033
1034static const unsigned ulpi_data6_po7_pins[] = {
1035	TEGRA_PIN_ULPI_DATA6_PO7,
1036};
1037
1038static const unsigned dap3_fs_pp0_pins[] = {
1039	TEGRA_PIN_DAP3_FS_PP0,
1040};
1041
1042static const unsigned dap3_din_pp1_pins[] = {
1043	TEGRA_PIN_DAP3_DIN_PP1,
1044};
1045
1046static const unsigned dap3_dout_pp2_pins[] = {
1047	TEGRA_PIN_DAP3_DOUT_PP2,
1048};
1049
1050static const unsigned dap3_sclk_pp3_pins[] = {
1051	TEGRA_PIN_DAP3_SCLK_PP3,
1052};
1053
1054static const unsigned dap4_fs_pp4_pins[] = {
1055	TEGRA_PIN_DAP4_FS_PP4,
1056};
1057
1058static const unsigned dap4_din_pp5_pins[] = {
1059	TEGRA_PIN_DAP4_DIN_PP5,
1060};
1061
1062static const unsigned dap4_dout_pp6_pins[] = {
1063	TEGRA_PIN_DAP4_DOUT_PP6,
1064};
1065
1066static const unsigned dap4_sclk_pp7_pins[] = {
1067	TEGRA_PIN_DAP4_SCLK_PP7,
1068};
1069
1070static const unsigned kb_col0_pq0_pins[] = {
1071	TEGRA_PIN_KB_COL0_PQ0,
1072};
1073
1074static const unsigned kb_col1_pq1_pins[] = {
1075	TEGRA_PIN_KB_COL1_PQ1,
1076};
1077
1078static const unsigned kb_col2_pq2_pins[] = {
1079	TEGRA_PIN_KB_COL2_PQ2,
1080};
1081
1082static const unsigned kb_col3_pq3_pins[] = {
1083	TEGRA_PIN_KB_COL3_PQ3,
1084};
1085
1086static const unsigned kb_col4_pq4_pins[] = {
1087	TEGRA_PIN_KB_COL4_PQ4,
1088};
1089
1090static const unsigned kb_col5_pq5_pins[] = {
1091	TEGRA_PIN_KB_COL5_PQ5,
1092};
1093
1094static const unsigned kb_col6_pq6_pins[] = {
1095	TEGRA_PIN_KB_COL6_PQ6,
1096};
1097
1098static const unsigned kb_col7_pq7_pins[] = {
1099	TEGRA_PIN_KB_COL7_PQ7,
1100};
1101
1102static const unsigned kb_row0_pr0_pins[] = {
1103	TEGRA_PIN_KB_ROW0_PR0,
1104};
1105
1106static const unsigned kb_row1_pr1_pins[] = {
1107	TEGRA_PIN_KB_ROW1_PR1,
1108};
1109
1110static const unsigned kb_row2_pr2_pins[] = {
1111	TEGRA_PIN_KB_ROW2_PR2,
1112};
1113
1114static const unsigned kb_row3_pr3_pins[] = {
1115	TEGRA_PIN_KB_ROW3_PR3,
1116};
1117
1118static const unsigned kb_row4_pr4_pins[] = {
1119	TEGRA_PIN_KB_ROW4_PR4,
1120};
1121
1122static const unsigned kb_row5_pr5_pins[] = {
1123	TEGRA_PIN_KB_ROW5_PR5,
1124};
1125
1126static const unsigned kb_row6_pr6_pins[] = {
1127	TEGRA_PIN_KB_ROW6_PR6,
1128};
1129
1130static const unsigned kb_row7_pr7_pins[] = {
1131	TEGRA_PIN_KB_ROW7_PR7,
1132};
1133
1134static const unsigned kb_row8_ps0_pins[] = {
1135	TEGRA_PIN_KB_ROW8_PS0,
1136};
1137
1138static const unsigned kb_row9_ps1_pins[] = {
1139	TEGRA_PIN_KB_ROW9_PS1,
1140};
1141
1142static const unsigned kb_row10_ps2_pins[] = {
1143	TEGRA_PIN_KB_ROW10_PS2,
1144};
1145
1146static const unsigned kb_row11_ps3_pins[] = {
1147	TEGRA_PIN_KB_ROW11_PS3,
1148};
1149
1150static const unsigned kb_row12_ps4_pins[] = {
1151	TEGRA_PIN_KB_ROW12_PS4,
1152};
1153
1154static const unsigned kb_row13_ps5_pins[] = {
1155	TEGRA_PIN_KB_ROW13_PS5,
1156};
1157
1158static const unsigned kb_row14_ps6_pins[] = {
1159	TEGRA_PIN_KB_ROW14_PS6,
1160};
1161
1162static const unsigned kb_row15_ps7_pins[] = {
1163	TEGRA_PIN_KB_ROW15_PS7,
1164};
1165
1166static const unsigned vi_pclk_pt0_pins[] = {
1167	TEGRA_PIN_VI_PCLK_PT0,
1168};
1169
1170static const unsigned vi_mclk_pt1_pins[] = {
1171	TEGRA_PIN_VI_MCLK_PT1,
1172};
1173
1174static const unsigned vi_d10_pt2_pins[] = {
1175	TEGRA_PIN_VI_D10_PT2,
1176};
1177
1178static const unsigned vi_d11_pt3_pins[] = {
1179	TEGRA_PIN_VI_D11_PT3,
1180};
1181
1182static const unsigned vi_d0_pt4_pins[] = {
1183	TEGRA_PIN_VI_D0_PT4,
1184};
1185
1186static const unsigned gen2_i2c_scl_pt5_pins[] = {
1187	TEGRA_PIN_GEN2_I2C_SCL_PT5,
1188};
1189
1190static const unsigned gen2_i2c_sda_pt6_pins[] = {
1191	TEGRA_PIN_GEN2_I2C_SDA_PT6,
1192};
1193
1194static const unsigned sdmmc4_cmd_pt7_pins[] = {
1195	TEGRA_PIN_SDMMC4_CMD_PT7,
1196};
1197
1198static const unsigned pu0_pins[] = {
1199	TEGRA_PIN_PU0,
1200};
1201
1202static const unsigned pu1_pins[] = {
1203	TEGRA_PIN_PU1,
1204};
1205
1206static const unsigned pu2_pins[] = {
1207	TEGRA_PIN_PU2,
1208};
1209
1210static const unsigned pu3_pins[] = {
1211	TEGRA_PIN_PU3,
1212};
1213
1214static const unsigned pu4_pins[] = {
1215	TEGRA_PIN_PU4,
1216};
1217
1218static const unsigned pu5_pins[] = {
1219	TEGRA_PIN_PU5,
1220};
1221
1222static const unsigned pu6_pins[] = {
1223	TEGRA_PIN_PU6,
1224};
1225
1226static const unsigned jtag_rtck_pu7_pins[] = {
1227	TEGRA_PIN_JTAG_RTCK_PU7,
1228};
1229
1230static const unsigned pv0_pins[] = {
1231	TEGRA_PIN_PV0,
1232};
1233
1234static const unsigned pv1_pins[] = {
1235	TEGRA_PIN_PV1,
1236};
1237
1238static const unsigned pv2_pins[] = {
1239	TEGRA_PIN_PV2,
1240};
1241
1242static const unsigned pv3_pins[] = {
1243	TEGRA_PIN_PV3,
1244};
1245
1246static const unsigned ddc_scl_pv4_pins[] = {
1247	TEGRA_PIN_DDC_SCL_PV4,
1248};
1249
1250static const unsigned ddc_sda_pv5_pins[] = {
1251	TEGRA_PIN_DDC_SDA_PV5,
1252};
1253
1254static const unsigned crt_hsync_pv6_pins[] = {
1255	TEGRA_PIN_CRT_HSYNC_PV6,
1256};
1257
1258static const unsigned crt_vsync_pv7_pins[] = {
1259	TEGRA_PIN_CRT_VSYNC_PV7,
1260};
1261
1262static const unsigned lcd_cs1_n_pw0_pins[] = {
1263	TEGRA_PIN_LCD_CS1_N_PW0,
1264};
1265
1266static const unsigned lcd_m1_pw1_pins[] = {
1267	TEGRA_PIN_LCD_M1_PW1,
1268};
1269
1270static const unsigned spi2_cs1_n_pw2_pins[] = {
1271	TEGRA_PIN_SPI2_CS1_N_PW2,
1272};
1273
1274static const unsigned spi2_cs2_n_pw3_pins[] = {
1275	TEGRA_PIN_SPI2_CS2_N_PW3,
1276};
1277
1278static const unsigned clk1_out_pw4_pins[] = {
1279	TEGRA_PIN_CLK1_OUT_PW4,
1280};
1281
1282static const unsigned clk2_out_pw5_pins[] = {
1283	TEGRA_PIN_CLK2_OUT_PW5,
1284};
1285
1286static const unsigned uart3_txd_pw6_pins[] = {
1287	TEGRA_PIN_UART3_TXD_PW6,
1288};
1289
1290static const unsigned uart3_rxd_pw7_pins[] = {
1291	TEGRA_PIN_UART3_RXD_PW7,
1292};
1293
1294static const unsigned spi2_mosi_px0_pins[] = {
1295	TEGRA_PIN_SPI2_MOSI_PX0,
1296};
1297
1298static const unsigned spi2_miso_px1_pins[] = {
1299	TEGRA_PIN_SPI2_MISO_PX1,
1300};
1301
1302static const unsigned spi2_sck_px2_pins[] = {
1303	TEGRA_PIN_SPI2_SCK_PX2,
1304};
1305
1306static const unsigned spi2_cs0_n_px3_pins[] = {
1307	TEGRA_PIN_SPI2_CS0_N_PX3,
1308};
1309
1310static const unsigned spi1_mosi_px4_pins[] = {
1311	TEGRA_PIN_SPI1_MOSI_PX4,
1312};
1313
1314static const unsigned spi1_sck_px5_pins[] = {
1315	TEGRA_PIN_SPI1_SCK_PX5,
1316};
1317
1318static const unsigned spi1_cs0_n_px6_pins[] = {
1319	TEGRA_PIN_SPI1_CS0_N_PX6,
1320};
1321
1322static const unsigned spi1_miso_px7_pins[] = {
1323	TEGRA_PIN_SPI1_MISO_PX7,
1324};
1325
1326static const unsigned ulpi_clk_py0_pins[] = {
1327	TEGRA_PIN_ULPI_CLK_PY0,
1328};
1329
1330static const unsigned ulpi_dir_py1_pins[] = {
1331	TEGRA_PIN_ULPI_DIR_PY1,
1332};
1333
1334static const unsigned ulpi_nxt_py2_pins[] = {
1335	TEGRA_PIN_ULPI_NXT_PY2,
1336};
1337
1338static const unsigned ulpi_stp_py3_pins[] = {
1339	TEGRA_PIN_ULPI_STP_PY3,
1340};
1341
1342static const unsigned sdmmc1_dat3_py4_pins[] = {
1343	TEGRA_PIN_SDMMC1_DAT3_PY4,
1344};
1345
1346static const unsigned sdmmc1_dat2_py5_pins[] = {
1347	TEGRA_PIN_SDMMC1_DAT2_PY5,
1348};
1349
1350static const unsigned sdmmc1_dat1_py6_pins[] = {
1351	TEGRA_PIN_SDMMC1_DAT1_PY6,
1352};
1353
1354static const unsigned sdmmc1_dat0_py7_pins[] = {
1355	TEGRA_PIN_SDMMC1_DAT0_PY7,
1356};
1357
1358static const unsigned sdmmc1_clk_pz0_pins[] = {
1359	TEGRA_PIN_SDMMC1_CLK_PZ0,
1360};
1361
1362static const unsigned sdmmc1_cmd_pz1_pins[] = {
1363	TEGRA_PIN_SDMMC1_CMD_PZ1,
1364};
1365
1366static const unsigned lcd_sdin_pz2_pins[] = {
1367	TEGRA_PIN_LCD_SDIN_PZ2,
1368};
1369
1370static const unsigned lcd_wr_n_pz3_pins[] = {
1371	TEGRA_PIN_LCD_WR_N_PZ3,
1372};
1373
1374static const unsigned lcd_sck_pz4_pins[] = {
1375	TEGRA_PIN_LCD_SCK_PZ4,
1376};
1377
1378static const unsigned sys_clk_req_pz5_pins[] = {
1379	TEGRA_PIN_SYS_CLK_REQ_PZ5,
1380};
1381
1382static const unsigned pwr_i2c_scl_pz6_pins[] = {
1383	TEGRA_PIN_PWR_I2C_SCL_PZ6,
1384};
1385
1386static const unsigned pwr_i2c_sda_pz7_pins[] = {
1387	TEGRA_PIN_PWR_I2C_SDA_PZ7,
1388};
1389
1390static const unsigned sdmmc4_dat0_paa0_pins[] = {
1391	TEGRA_PIN_SDMMC4_DAT0_PAA0,
1392};
1393
1394static const unsigned sdmmc4_dat1_paa1_pins[] = {
1395	TEGRA_PIN_SDMMC4_DAT1_PAA1,
1396};
1397
1398static const unsigned sdmmc4_dat2_paa2_pins[] = {
1399	TEGRA_PIN_SDMMC4_DAT2_PAA2,
1400};
1401
1402static const unsigned sdmmc4_dat3_paa3_pins[] = {
1403	TEGRA_PIN_SDMMC4_DAT3_PAA3,
1404};
1405
1406static const unsigned sdmmc4_dat4_paa4_pins[] = {
1407	TEGRA_PIN_SDMMC4_DAT4_PAA4,
1408};
1409
1410static const unsigned sdmmc4_dat5_paa5_pins[] = {
1411	TEGRA_PIN_SDMMC4_DAT5_PAA5,
1412};
1413
1414static const unsigned sdmmc4_dat6_paa6_pins[] = {
1415	TEGRA_PIN_SDMMC4_DAT6_PAA6,
1416};
1417
1418static const unsigned sdmmc4_dat7_paa7_pins[] = {
1419	TEGRA_PIN_SDMMC4_DAT7_PAA7,
1420};
1421
1422static const unsigned pbb0_pins[] = {
1423	TEGRA_PIN_PBB0,
1424};
1425
1426static const unsigned cam_i2c_scl_pbb1_pins[] = {
1427	TEGRA_PIN_CAM_I2C_SCL_PBB1,
1428};
1429
1430static const unsigned cam_i2c_sda_pbb2_pins[] = {
1431	TEGRA_PIN_CAM_I2C_SDA_PBB2,
1432};
1433
1434static const unsigned pbb3_pins[] = {
1435	TEGRA_PIN_PBB3,
1436};
1437
1438static const unsigned pbb4_pins[] = {
1439	TEGRA_PIN_PBB4,
1440};
1441
1442static const unsigned pbb5_pins[] = {
1443	TEGRA_PIN_PBB5,
1444};
1445
1446static const unsigned pbb6_pins[] = {
1447	TEGRA_PIN_PBB6,
1448};
1449
1450static const unsigned pbb7_pins[] = {
1451	TEGRA_PIN_PBB7,
1452};
1453
1454static const unsigned cam_mclk_pcc0_pins[] = {
1455	TEGRA_PIN_CAM_MCLK_PCC0,
1456};
1457
1458static const unsigned pcc1_pins[] = {
1459	TEGRA_PIN_PCC1,
1460};
1461
1462static const unsigned pcc2_pins[] = {
1463	TEGRA_PIN_PCC2,
1464};
1465
1466static const unsigned sdmmc4_rst_n_pcc3_pins[] = {
1467	TEGRA_PIN_SDMMC4_RST_N_PCC3,
1468};
1469
1470static const unsigned sdmmc4_clk_pcc4_pins[] = {
1471	TEGRA_PIN_SDMMC4_CLK_PCC4,
1472};
1473
1474static const unsigned clk2_req_pcc5_pins[] = {
1475	TEGRA_PIN_CLK2_REQ_PCC5,
1476};
1477
1478static const unsigned pex_l2_rst_n_pcc6_pins[] = {
1479	TEGRA_PIN_PEX_L2_RST_N_PCC6,
1480};
1481
1482static const unsigned pex_l2_clkreq_n_pcc7_pins[] = {
1483	TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
1484};
1485
1486static const unsigned pex_l0_prsnt_n_pdd0_pins[] = {
1487	TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
1488};
1489
1490static const unsigned pex_l0_rst_n_pdd1_pins[] = {
1491	TEGRA_PIN_PEX_L0_RST_N_PDD1,
1492};
1493
1494static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
1495	TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1496};
1497
1498static const unsigned pex_wake_n_pdd3_pins[] = {
1499	TEGRA_PIN_PEX_WAKE_N_PDD3,
1500};
1501
1502static const unsigned pex_l1_prsnt_n_pdd4_pins[] = {
1503	TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
1504};
1505
1506static const unsigned pex_l1_rst_n_pdd5_pins[] = {
1507	TEGRA_PIN_PEX_L1_RST_N_PDD5,
1508};
1509
1510static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
1511	TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1512};
1513
1514static const unsigned pex_l2_prsnt_n_pdd7_pins[] = {
1515	TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
1516};
1517
1518static const unsigned clk3_out_pee0_pins[] = {
1519	TEGRA_PIN_CLK3_OUT_PEE0,
1520};
1521
1522static const unsigned clk3_req_pee1_pins[] = {
1523	TEGRA_PIN_CLK3_REQ_PEE1,
1524};
1525
1526static const unsigned clk1_req_pee2_pins[] = {
1527	TEGRA_PIN_CLK1_REQ_PEE2,
1528};
1529
1530static const unsigned hdmi_cec_pee3_pins[] = {
1531	TEGRA_PIN_HDMI_CEC_PEE3,
1532};
1533
1534static const unsigned clk_32k_in_pins[] = {
1535	TEGRA_PIN_CLK_32K_IN,
1536};
1537
1538static const unsigned core_pwr_req_pins[] = {
1539	TEGRA_PIN_CORE_PWR_REQ,
1540};
1541
1542static const unsigned cpu_pwr_req_pins[] = {
1543	TEGRA_PIN_CPU_PWR_REQ,
1544};
1545
1546static const unsigned owr_pins[] = {
1547	TEGRA_PIN_OWR,
1548};
1549
1550static const unsigned pwr_int_n_pins[] = {
1551	TEGRA_PIN_PWR_INT_N,
1552};
1553
1554static const unsigned drive_ao1_pins[] = {
1555	TEGRA_PIN_KB_ROW0_PR0,
1556	TEGRA_PIN_KB_ROW1_PR1,
1557	TEGRA_PIN_KB_ROW2_PR2,
1558	TEGRA_PIN_KB_ROW3_PR3,
1559	TEGRA_PIN_KB_ROW4_PR4,
1560	TEGRA_PIN_KB_ROW5_PR5,
1561	TEGRA_PIN_KB_ROW6_PR6,
1562	TEGRA_PIN_KB_ROW7_PR7,
1563	TEGRA_PIN_PWR_I2C_SCL_PZ6,
1564	TEGRA_PIN_PWR_I2C_SDA_PZ7,
1565	TEGRA_PIN_SYS_RESET_N,
1566};
1567
1568static const unsigned drive_ao2_pins[] = {
1569	TEGRA_PIN_CLK_32K_OUT_PA0,
1570	TEGRA_PIN_KB_COL0_PQ0,
1571	TEGRA_PIN_KB_COL1_PQ1,
1572	TEGRA_PIN_KB_COL2_PQ2,
1573	TEGRA_PIN_KB_COL3_PQ3,
1574	TEGRA_PIN_KB_COL4_PQ4,
1575	TEGRA_PIN_KB_COL5_PQ5,
1576	TEGRA_PIN_KB_COL6_PQ6,
1577	TEGRA_PIN_KB_COL7_PQ7,
1578	TEGRA_PIN_KB_ROW8_PS0,
1579	TEGRA_PIN_KB_ROW9_PS1,
1580	TEGRA_PIN_KB_ROW10_PS2,
1581	TEGRA_PIN_KB_ROW11_PS3,
1582	TEGRA_PIN_KB_ROW12_PS4,
1583	TEGRA_PIN_KB_ROW13_PS5,
1584	TEGRA_PIN_KB_ROW14_PS6,
1585	TEGRA_PIN_KB_ROW15_PS7,
1586	TEGRA_PIN_SYS_CLK_REQ_PZ5,
1587	TEGRA_PIN_CLK_32K_IN,
1588	TEGRA_PIN_CORE_PWR_REQ,
1589	TEGRA_PIN_CPU_PWR_REQ,
1590	TEGRA_PIN_PWR_INT_N,
1591};
1592
1593static const unsigned drive_at1_pins[] = {
1594	TEGRA_PIN_GMI_AD8_PH0,
1595	TEGRA_PIN_GMI_AD9_PH1,
1596	TEGRA_PIN_GMI_AD10_PH2,
1597	TEGRA_PIN_GMI_AD11_PH3,
1598	TEGRA_PIN_GMI_AD12_PH4,
1599	TEGRA_PIN_GMI_AD13_PH5,
1600	TEGRA_PIN_GMI_AD14_PH6,
1601	TEGRA_PIN_GMI_AD15_PH7,
1602	TEGRA_PIN_GMI_IORDY_PI5,
1603	TEGRA_PIN_GMI_CS7_N_PI6,
1604};
1605
1606static const unsigned drive_at2_pins[] = {
1607	TEGRA_PIN_GMI_AD0_PG0,
1608	TEGRA_PIN_GMI_AD1_PG1,
1609	TEGRA_PIN_GMI_AD2_PG2,
1610	TEGRA_PIN_GMI_AD3_PG3,
1611	TEGRA_PIN_GMI_AD4_PG4,
1612	TEGRA_PIN_GMI_AD5_PG5,
1613	TEGRA_PIN_GMI_AD6_PG6,
1614	TEGRA_PIN_GMI_AD7_PG7,
1615	TEGRA_PIN_GMI_WR_N_PI0,
1616	TEGRA_PIN_GMI_OE_N_PI1,
1617	TEGRA_PIN_GMI_DQS_PI2,
1618	TEGRA_PIN_GMI_CS6_N_PI3,
1619	TEGRA_PIN_GMI_RST_N_PI4,
1620	TEGRA_PIN_GMI_WAIT_PI7,
1621	TEGRA_PIN_GMI_ADV_N_PK0,
1622	TEGRA_PIN_GMI_CLK_PK1,
1623	TEGRA_PIN_GMI_CS4_N_PK2,
1624	TEGRA_PIN_GMI_CS2_N_PK3,
1625	TEGRA_PIN_GMI_CS3_N_PK4,
1626};
1627
1628static const unsigned drive_at3_pins[] = {
1629	TEGRA_PIN_GMI_WP_N_PC7,
1630	TEGRA_PIN_GMI_CS0_N_PJ0,
1631};
1632
1633static const unsigned drive_at4_pins[] = {
1634	TEGRA_PIN_GMI_A17_PB0,
1635	TEGRA_PIN_GMI_A18_PB1,
1636	TEGRA_PIN_GMI_CS1_N_PJ2,
1637	TEGRA_PIN_GMI_A16_PJ7,
1638	TEGRA_PIN_GMI_A19_PK7,
1639};
1640
1641static const unsigned drive_at5_pins[] = {
1642	TEGRA_PIN_GEN2_I2C_SCL_PT5,
1643	TEGRA_PIN_GEN2_I2C_SDA_PT6,
1644};
1645
1646static const unsigned drive_cdev1_pins[] = {
1647	TEGRA_PIN_CLK1_OUT_PW4,
1648	TEGRA_PIN_CLK1_REQ_PEE2,
1649};
1650
1651static const unsigned drive_cdev2_pins[] = {
1652	TEGRA_PIN_CLK2_OUT_PW5,
1653	TEGRA_PIN_CLK2_REQ_PCC5,
1654};
1655
1656static const unsigned drive_cec_pins[] = {
1657	TEGRA_PIN_HDMI_CEC_PEE3,
1658};
1659
1660static const unsigned drive_crt_pins[] = {
1661	TEGRA_PIN_CRT_HSYNC_PV6,
1662	TEGRA_PIN_CRT_VSYNC_PV7,
1663};
1664
1665static const unsigned drive_csus_pins[] = {
1666	TEGRA_PIN_VI_MCLK_PT1,
1667};
1668
1669static const unsigned drive_dap1_pins[] = {
1670	TEGRA_PIN_SPDIF_OUT_PK5,
1671	TEGRA_PIN_SPDIF_IN_PK6,
1672	TEGRA_PIN_DAP1_FS_PN0,
1673	TEGRA_PIN_DAP1_DIN_PN1,
1674	TEGRA_PIN_DAP1_DOUT_PN2,
1675	TEGRA_PIN_DAP1_SCLK_PN3,
1676};
1677
1678static const unsigned drive_dap2_pins[] = {
1679	TEGRA_PIN_DAP2_FS_PA2,
1680	TEGRA_PIN_DAP2_SCLK_PA3,
1681	TEGRA_PIN_DAP2_DIN_PA4,
1682	TEGRA_PIN_DAP2_DOUT_PA5,
1683};
1684
1685static const unsigned drive_dap3_pins[] = {
1686	TEGRA_PIN_DAP3_FS_PP0,
1687	TEGRA_PIN_DAP3_DIN_PP1,
1688	TEGRA_PIN_DAP3_DOUT_PP2,
1689	TEGRA_PIN_DAP3_SCLK_PP3,
1690};
1691
1692static const unsigned drive_dap4_pins[] = {
1693	TEGRA_PIN_DAP4_FS_PP4,
1694	TEGRA_PIN_DAP4_DIN_PP5,
1695	TEGRA_PIN_DAP4_DOUT_PP6,
1696	TEGRA_PIN_DAP4_SCLK_PP7,
1697};
1698
1699static const unsigned drive_dbg_pins[] = {
1700	TEGRA_PIN_GEN1_I2C_SCL_PC4,
1701	TEGRA_PIN_GEN1_I2C_SDA_PC5,
1702	TEGRA_PIN_PU0,
1703	TEGRA_PIN_PU1,
1704	TEGRA_PIN_PU2,
1705	TEGRA_PIN_PU3,
1706	TEGRA_PIN_PU4,
1707	TEGRA_PIN_PU5,
1708	TEGRA_PIN_PU6,
1709	TEGRA_PIN_JTAG_RTCK_PU7,
1710	TEGRA_PIN_JTAG_TCK,
1711	TEGRA_PIN_JTAG_TDI,
1712	TEGRA_PIN_JTAG_TDO,
1713	TEGRA_PIN_JTAG_TMS,
1714	TEGRA_PIN_JTAG_TRST_N,
1715	TEGRA_PIN_TEST_MODE_EN,
1716};
1717
1718static const unsigned drive_ddc_pins[] = {
1719	TEGRA_PIN_DDC_SCL_PV4,
1720	TEGRA_PIN_DDC_SDA_PV5,
1721};
1722
1723static const unsigned drive_dev3_pins[] = {
1724	TEGRA_PIN_CLK3_OUT_PEE0,
1725	TEGRA_PIN_CLK3_REQ_PEE1,
1726};
1727
1728static const unsigned drive_gma_pins[] = {
1729	TEGRA_PIN_SDMMC4_DAT0_PAA0,
1730	TEGRA_PIN_SDMMC4_DAT1_PAA1,
1731	TEGRA_PIN_SDMMC4_DAT2_PAA2,
1732	TEGRA_PIN_SDMMC4_DAT3_PAA3,
1733	TEGRA_PIN_SDMMC4_RST_N_PCC3,
1734};
1735
1736static const unsigned drive_gmb_pins[] = {
1737	TEGRA_PIN_SDMMC4_DAT4_PAA4,
1738	TEGRA_PIN_SDMMC4_DAT5_PAA5,
1739	TEGRA_PIN_SDMMC4_DAT6_PAA6,
1740	TEGRA_PIN_SDMMC4_DAT7_PAA7,
1741};
1742
1743static const unsigned drive_gmc_pins[] = {
1744	TEGRA_PIN_SDMMC4_CLK_PCC4,
1745};
1746
1747static const unsigned drive_gmd_pins[] = {
1748	TEGRA_PIN_SDMMC4_CMD_PT7,
1749};
1750
1751static const unsigned drive_gme_pins[] = {
1752	TEGRA_PIN_PBB0,
1753	TEGRA_PIN_CAM_I2C_SCL_PBB1,
1754	TEGRA_PIN_CAM_I2C_SDA_PBB2,
1755	TEGRA_PIN_PBB3,
1756	TEGRA_PIN_PCC2,
1757};
1758
1759static const unsigned drive_gmf_pins[] = {
1760	TEGRA_PIN_PBB4,
1761	TEGRA_PIN_PBB5,
1762	TEGRA_PIN_PBB6,
1763	TEGRA_PIN_PBB7,
1764};
1765
1766static const unsigned drive_gmg_pins[] = {
1767	TEGRA_PIN_CAM_MCLK_PCC0,
1768};
1769
1770static const unsigned drive_gmh_pins[] = {
1771	TEGRA_PIN_PCC1,
1772};
1773
1774static const unsigned drive_gpv_pins[] = {
1775	TEGRA_PIN_PEX_L2_RST_N_PCC6,
1776	TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
1777	TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
1778	TEGRA_PIN_PEX_L0_RST_N_PDD1,
1779	TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1780	TEGRA_PIN_PEX_WAKE_N_PDD3,
1781	TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
1782	TEGRA_PIN_PEX_L1_RST_N_PDD5,
1783	TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1784	TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
1785};
1786
1787static const unsigned drive_lcd1_pins[] = {
1788	TEGRA_PIN_LCD_PWR1_PC1,
1789	TEGRA_PIN_LCD_PWR2_PC6,
1790	TEGRA_PIN_LCD_CS0_N_PN4,
1791	TEGRA_PIN_LCD_SDOUT_PN5,
1792	TEGRA_PIN_LCD_DC0_PN6,
1793	TEGRA_PIN_LCD_SDIN_PZ2,
1794	TEGRA_PIN_LCD_WR_N_PZ3,
1795	TEGRA_PIN_LCD_SCK_PZ4,
1796};
1797
1798static const unsigned drive_lcd2_pins[] = {
1799	TEGRA_PIN_LCD_PWR0_PB2,
1800	TEGRA_PIN_LCD_PCLK_PB3,
1801	TEGRA_PIN_LCD_DC1_PD2,
1802	TEGRA_PIN_LCD_D0_PE0,
1803	TEGRA_PIN_LCD_D1_PE1,
1804	TEGRA_PIN_LCD_D2_PE2,
1805	TEGRA_PIN_LCD_D3_PE3,
1806	TEGRA_PIN_LCD_D4_PE4,
1807	TEGRA_PIN_LCD_D5_PE5,
1808	TEGRA_PIN_LCD_D6_PE6,
1809	TEGRA_PIN_LCD_D7_PE7,
1810	TEGRA_PIN_LCD_D8_PF0,
1811	TEGRA_PIN_LCD_D9_PF1,
1812	TEGRA_PIN_LCD_D10_PF2,
1813	TEGRA_PIN_LCD_D11_PF3,
1814	TEGRA_PIN_LCD_D12_PF4,
1815	TEGRA_PIN_LCD_D13_PF5,
1816	TEGRA_PIN_LCD_D14_PF6,
1817	TEGRA_PIN_LCD_D15_PF7,
1818	TEGRA_PIN_LCD_DE_PJ1,
1819	TEGRA_PIN_LCD_HSYNC_PJ3,
1820	TEGRA_PIN_LCD_VSYNC_PJ4,
1821	TEGRA_PIN_LCD_D16_PM0,
1822	TEGRA_PIN_LCD_D17_PM1,
1823	TEGRA_PIN_LCD_D18_PM2,
1824	TEGRA_PIN_LCD_D19_PM3,
1825	TEGRA_PIN_LCD_D20_PM4,
1826	TEGRA_PIN_LCD_D21_PM5,
1827	TEGRA_PIN_LCD_D22_PM6,
1828	TEGRA_PIN_LCD_D23_PM7,
1829	TEGRA_PIN_HDMI_INT_PN7,
1830	TEGRA_PIN_LCD_CS1_N_PW0,
1831	TEGRA_PIN_LCD_M1_PW1,
1832};
1833
1834static const unsigned drive_owr_pins[] = {
1835	TEGRA_PIN_OWR,
1836};
1837
1838static const unsigned drive_sdio1_pins[] = {
1839	TEGRA_PIN_SDMMC1_DAT3_PY4,
1840	TEGRA_PIN_SDMMC1_DAT2_PY5,
1841	TEGRA_PIN_SDMMC1_DAT1_PY6,
1842	TEGRA_PIN_SDMMC1_DAT0_PY7,
1843	TEGRA_PIN_SDMMC1_CLK_PZ0,
1844	TEGRA_PIN_SDMMC1_CMD_PZ1,
1845};
1846
1847static const unsigned drive_sdio2_pins[] = {
1848	TEGRA_PIN_SDMMC3_DAT5_PD0,
1849	TEGRA_PIN_SDMMC3_DAT4_PD1,
1850	TEGRA_PIN_SDMMC3_DAT6_PD3,
1851	TEGRA_PIN_SDMMC3_DAT7_PD4,
1852};
1853
1854static const unsigned drive_sdio3_pins[] = {
1855	TEGRA_PIN_SDMMC3_CLK_PA6,
1856	TEGRA_PIN_SDMMC3_CMD_PA7,
1857	TEGRA_PIN_SDMMC3_DAT3_PB4,
1858	TEGRA_PIN_SDMMC3_DAT2_PB5,
1859	TEGRA_PIN_SDMMC3_DAT1_PB6,
1860	TEGRA_PIN_SDMMC3_DAT0_PB7,
1861};
1862
1863static const unsigned drive_spi_pins[] = {
1864	TEGRA_PIN_SPI2_CS1_N_PW2,
1865	TEGRA_PIN_SPI2_CS2_N_PW3,
1866	TEGRA_PIN_SPI2_MOSI_PX0,
1867	TEGRA_PIN_SPI2_MISO_PX1,
1868	TEGRA_PIN_SPI2_SCK_PX2,
1869	TEGRA_PIN_SPI2_CS0_N_PX3,
1870	TEGRA_PIN_SPI1_MOSI_PX4,
1871	TEGRA_PIN_SPI1_SCK_PX5,
1872	TEGRA_PIN_SPI1_CS0_N_PX6,
1873	TEGRA_PIN_SPI1_MISO_PX7,
1874};
1875
1876static const unsigned drive_uaa_pins[] = {
1877	TEGRA_PIN_ULPI_DATA0_PO1,
1878	TEGRA_PIN_ULPI_DATA1_PO2,
1879	TEGRA_PIN_ULPI_DATA2_PO3,
1880	TEGRA_PIN_ULPI_DATA3_PO4,
1881};
1882
1883static const unsigned drive_uab_pins[] = {
1884	TEGRA_PIN_ULPI_DATA7_PO0,
1885	TEGRA_PIN_ULPI_DATA4_PO5,
1886	TEGRA_PIN_ULPI_DATA5_PO6,
1887	TEGRA_PIN_ULPI_DATA6_PO7,
1888	TEGRA_PIN_PV0,
1889	TEGRA_PIN_PV1,
1890	TEGRA_PIN_PV2,
1891	TEGRA_PIN_PV3,
1892};
1893
1894static const unsigned drive_uart2_pins[] = {
1895	TEGRA_PIN_UART2_TXD_PC2,
1896	TEGRA_PIN_UART2_RXD_PC3,
1897	TEGRA_PIN_UART2_CTS_N_PJ5,
1898	TEGRA_PIN_UART2_RTS_N_PJ6,
1899};
1900
1901static const unsigned drive_uart3_pins[] = {
1902	TEGRA_PIN_UART3_CTS_N_PA1,
1903	TEGRA_PIN_UART3_RTS_N_PC0,
1904	TEGRA_PIN_UART3_TXD_PW6,
1905	TEGRA_PIN_UART3_RXD_PW7,
1906};
1907
1908static const unsigned drive_uda_pins[] = {
1909	TEGRA_PIN_ULPI_CLK_PY0,
1910	TEGRA_PIN_ULPI_DIR_PY1,
1911	TEGRA_PIN_ULPI_NXT_PY2,
1912	TEGRA_PIN_ULPI_STP_PY3,
1913};
1914
1915static const unsigned drive_vi1_pins[] = {
1916	TEGRA_PIN_VI_D1_PD5,
1917	TEGRA_PIN_VI_VSYNC_PD6,
1918	TEGRA_PIN_VI_HSYNC_PD7,
1919	TEGRA_PIN_VI_D2_PL0,
1920	TEGRA_PIN_VI_D3_PL1,
1921	TEGRA_PIN_VI_D4_PL2,
1922	TEGRA_PIN_VI_D5_PL3,
1923	TEGRA_PIN_VI_D6_PL4,
1924	TEGRA_PIN_VI_D7_PL5,
1925	TEGRA_PIN_VI_D8_PL6,
1926	TEGRA_PIN_VI_D9_PL7,
1927	TEGRA_PIN_VI_PCLK_PT0,
1928	TEGRA_PIN_VI_D10_PT2,
1929	TEGRA_PIN_VI_D11_PT3,
1930	TEGRA_PIN_VI_D0_PT4,
1931};
1932
1933enum tegra_mux {
1934	TEGRA_MUX_BLINK,
1935	TEGRA_MUX_CEC,
1936	TEGRA_MUX_CLK_12M_OUT,
1937	TEGRA_MUX_CLK_32K_IN,
1938	TEGRA_MUX_CORE_PWR_REQ,
1939	TEGRA_MUX_CPU_PWR_REQ,
1940	TEGRA_MUX_CRT,
1941	TEGRA_MUX_DAP,
1942	TEGRA_MUX_DDR,
1943	TEGRA_MUX_DEV3,
1944	TEGRA_MUX_DISPLAYA,
1945	TEGRA_MUX_DISPLAYB,
1946	TEGRA_MUX_DTV,
1947	TEGRA_MUX_EXTPERIPH1,
1948	TEGRA_MUX_EXTPERIPH2,
1949	TEGRA_MUX_EXTPERIPH3,
1950	TEGRA_MUX_GMI,
1951	TEGRA_MUX_GMI_ALT,
1952	TEGRA_MUX_HDA,
1953	TEGRA_MUX_HDCP,
1954	TEGRA_MUX_HDMI,
1955	TEGRA_MUX_HSI,
1956	TEGRA_MUX_I2C1,
1957	TEGRA_MUX_I2C2,
1958	TEGRA_MUX_I2C3,
1959	TEGRA_MUX_I2C4,
1960	TEGRA_MUX_I2CPWR,
1961	TEGRA_MUX_I2S0,
1962	TEGRA_MUX_I2S1,
1963	TEGRA_MUX_I2S2,
1964	TEGRA_MUX_I2S3,
1965	TEGRA_MUX_I2S4,
1966	TEGRA_MUX_INVALID,
1967	TEGRA_MUX_KBC,
1968	TEGRA_MUX_MIO,
1969	TEGRA_MUX_NAND,
1970	TEGRA_MUX_NAND_ALT,
1971	TEGRA_MUX_OWR,
1972	TEGRA_MUX_PCIE,
1973	TEGRA_MUX_PWM0,
1974	TEGRA_MUX_PWM1,
1975	TEGRA_MUX_PWM2,
1976	TEGRA_MUX_PWM3,
1977	TEGRA_MUX_PWR_INT_N,
1978	TEGRA_MUX_RSVD1,
1979	TEGRA_MUX_RSVD2,
1980	TEGRA_MUX_RSVD3,
1981	TEGRA_MUX_RSVD4,
1982	TEGRA_MUX_RTCK,
1983	TEGRA_MUX_SATA,
1984	TEGRA_MUX_SDMMC1,
1985	TEGRA_MUX_SDMMC2,
1986	TEGRA_MUX_SDMMC3,
1987	TEGRA_MUX_SDMMC4,
1988	TEGRA_MUX_SPDIF,
1989	TEGRA_MUX_SPI1,
1990	TEGRA_MUX_SPI2,
1991	TEGRA_MUX_SPI2_ALT,
1992	TEGRA_MUX_SPI3,
1993	TEGRA_MUX_SPI4,
1994	TEGRA_MUX_SPI5,
1995	TEGRA_MUX_SPI6,
1996	TEGRA_MUX_SYSCLK,
1997	TEGRA_MUX_TEST,
1998	TEGRA_MUX_TRACE,
1999	TEGRA_MUX_UARTA,
2000	TEGRA_MUX_UARTB,
2001	TEGRA_MUX_UARTC,
2002	TEGRA_MUX_UARTD,
2003	TEGRA_MUX_UARTE,
2004	TEGRA_MUX_ULPI,
2005	TEGRA_MUX_VGP1,
2006	TEGRA_MUX_VGP2,
2007	TEGRA_MUX_VGP3,
2008	TEGRA_MUX_VGP4,
2009	TEGRA_MUX_VGP5,
2010	TEGRA_MUX_VGP6,
2011	TEGRA_MUX_VI,
2012	TEGRA_MUX_VI_ALT1,
2013	TEGRA_MUX_VI_ALT2,
2014	TEGRA_MUX_VI_ALT3,
2015};
2016static const char * const blink_groups[] = {
2017	"clk_32k_out_pa0",
2018};
2019
2020static const char * const cec_groups[] = {
2021	"hdmi_cec_pee3",
2022	"owr",
2023};
2024
2025static const char * const clk_12m_out_groups[] = {
2026	"pv3",
2027};
2028
2029static const char * const clk_32k_in_groups[] = {
2030	"clk_32k_in",
2031};
2032
2033static const char * const core_pwr_req_groups[] = {
2034	"core_pwr_req",
2035};
2036
2037static const char * const cpu_pwr_req_groups[] = {
2038	"cpu_pwr_req",
2039};
2040
2041static const char * const crt_groups[] = {
2042	"crt_hsync_pv6",
2043	"crt_vsync_pv7",
2044};
2045
2046static const char * const dap_groups[] = {
2047	"clk1_req_pee2",
2048	"clk2_req_pcc5",
2049};
2050
2051static const char * const ddr_groups[] = {
2052	"vi_d0_pt4",
2053	"vi_d1_pd5",
2054	"vi_d10_pt2",
2055	"vi_d11_pt3",
2056	"vi_d2_pl0",
2057	"vi_d3_pl1",
2058	"vi_d4_pl2",
2059	"vi_d5_pl3",
2060	"vi_d6_pl4",
2061	"vi_d7_pl5",
2062	"vi_d8_pl6",
2063	"vi_d9_pl7",
2064	"vi_hsync_pd7",
2065	"vi_vsync_pd6",
2066};
2067
2068static const char * const dev3_groups[] = {
2069	"clk3_req_pee1",
2070};
2071
2072static const char * const displaya_groups[] = {
2073	"dap3_din_pp1",
2074	"dap3_dout_pp2",
2075	"dap3_fs_pp0",
2076	"dap3_sclk_pp3",
2077	"pbb3",
2078	"pbb4",
2079	"pbb5",
2080	"pbb6",
2081	"lcd_cs0_n_pn4",
2082	"lcd_cs1_n_pw0",
2083	"lcd_d0_pe0",
2084	"lcd_d1_pe1",
2085	"lcd_d10_pf2",
2086	"lcd_d11_pf3",
2087	"lcd_d12_pf4",
2088	"lcd_d13_pf5",
2089	"lcd_d14_pf6",
2090	"lcd_d15_pf7",
2091	"lcd_d16_pm0",
2092	"lcd_d17_pm1",
2093	"lcd_d18_pm2",
2094	"lcd_d19_pm3",
2095	"lcd_d2_pe2",
2096	"lcd_d20_pm4",
2097	"lcd_d21_pm5",
2098	"lcd_d22_pm6",
2099	"lcd_d23_pm7",
2100	"lcd_d3_pe3",
2101	"lcd_d4_pe4",
2102	"lcd_d5_pe5",
2103	"lcd_d6_pe6",
2104	"lcd_d7_pe7",
2105	"lcd_d8_pf0",
2106	"lcd_d9_pf1",
2107	"lcd_dc0_pn6",
2108	"lcd_dc1_pd2",
2109	"lcd_de_pj1",
2110	"lcd_hsync_pj3",
2111	"lcd_m1_pw1",
2112	"lcd_pclk_pb3",
2113	"lcd_pwr0_pb2",
2114	"lcd_pwr1_pc1",
2115	"lcd_pwr2_pc6",
2116	"lcd_sck_pz4",
2117	"lcd_sdin_pz2",
2118	"lcd_sdout_pn5",
2119	"lcd_vsync_pj4",
2120	"lcd_wr_n_pz3",
2121};
2122
2123static const char * const displayb_groups[] = {
2124	"dap3_din_pp1",
2125	"dap3_dout_pp2",
2126	"dap3_fs_pp0",
2127	"dap3_sclk_pp3",
2128	"pbb3",
2129	"pbb4",
2130	"pbb5",
2131	"pbb6",
2132	"lcd_cs0_n_pn4",
2133	"lcd_cs1_n_pw0",
2134	"lcd_d0_pe0",
2135	"lcd_d1_pe1",
2136	"lcd_d10_pf2",
2137	"lcd_d11_pf3",
2138	"lcd_d12_pf4",
2139	"lcd_d13_pf5",
2140	"lcd_d14_pf6",
2141	"lcd_d15_pf7",
2142	"lcd_d16_pm0",
2143	"lcd_d17_pm1",
2144	"lcd_d18_pm2",
2145	"lcd_d19_pm3",
2146	"lcd_d2_pe2",
2147	"lcd_d20_pm4",
2148	"lcd_d21_pm5",
2149	"lcd_d22_pm6",
2150	"lcd_d23_pm7",
2151	"lcd_d3_pe3",
2152	"lcd_d4_pe4",
2153	"lcd_d5_pe5",
2154	"lcd_d6_pe6",
2155	"lcd_d7_pe7",
2156	"lcd_d8_pf0",
2157	"lcd_d9_pf1",
2158	"lcd_dc0_pn6",
2159	"lcd_dc1_pd2",
2160	"lcd_de_pj1",
2161	"lcd_hsync_pj3",
2162	"lcd_m1_pw1",
2163	"lcd_pclk_pb3",
2164	"lcd_pwr0_pb2",
2165	"lcd_pwr1_pc1",
2166	"lcd_pwr2_pc6",
2167	"lcd_sck_pz4",
2168	"lcd_sdin_pz2",
2169	"lcd_sdout_pn5",
2170	"lcd_vsync_pj4",
2171	"lcd_wr_n_pz3",
2172};
2173
2174static const char * const dtv_groups[] = {
2175	"gmi_a17_pb0",
2176	"gmi_a18_pb1",
2177	"gmi_cs0_n_pj0",
2178	"gmi_cs1_n_pj2",
2179};
2180
2181static const char * const extperiph1_groups[] = {
2182	"clk1_out_pw4",
2183};
2184
2185static const char * const extperiph2_groups[] = {
2186	"clk2_out_pw5",
2187};
2188
2189static const char * const extperiph3_groups[] = {
2190	"clk3_out_pee0",
2191};
2192
2193static const char * const gmi_groups[] = {
2194	"dap1_din_pn1",
2195	"dap1_dout_pn2",
2196	"dap1_fs_pn0",
2197	"dap1_sclk_pn3",
2198	"dap2_din_pa4",
2199	"dap2_dout_pa5",
2200	"dap2_fs_pa2",
2201	"dap2_sclk_pa3",
2202	"dap4_din_pp5",
2203	"dap4_dout_pp6",
2204	"dap4_fs_pp4",
2205	"dap4_sclk_pp7",
2206	"gen2_i2c_scl_pt5",
2207	"gen2_i2c_sda_pt6",
2208	"gmi_a16_pj7",
2209	"gmi_a17_pb0",
2210	"gmi_a18_pb1",
2211	"gmi_a19_pk7",
2212	"gmi_ad0_pg0",
2213	"gmi_ad1_pg1",
2214	"gmi_ad10_ph2",
2215	"gmi_ad11_ph3",
2216	"gmi_ad12_ph4",
2217	"gmi_ad13_ph5",
2218	"gmi_ad14_ph6",
2219	"gmi_ad15_ph7",
2220	"gmi_ad2_pg2",
2221	"gmi_ad3_pg3",
2222	"gmi_ad4_pg4",
2223	"gmi_ad5_pg5",
2224	"gmi_ad6_pg6",
2225	"gmi_ad7_pg7",
2226	"gmi_ad8_ph0",
2227	"gmi_ad9_ph1",
2228	"gmi_adv_n_pk0",
2229	"gmi_clk_pk1",
2230	"gmi_cs0_n_pj0",
2231	"gmi_cs1_n_pj2",
2232	"gmi_cs2_n_pk3",
2233	"gmi_cs3_n_pk4",
2234	"gmi_cs4_n_pk2",
2235	"gmi_cs6_n_pi3",
2236	"gmi_cs7_n_pi6",
2237	"gmi_dqs_pi2",
2238	"gmi_iordy_pi5",
2239	"gmi_oe_n_pi1",
2240	"gmi_rst_n_pi4",
2241	"gmi_wait_pi7",
2242	"gmi_wp_n_pc7",
2243	"gmi_wr_n_pi0",
2244	"pu0",
2245	"pu1",
2246	"pu2",
2247	"pu3",
2248	"pu4",
2249	"pu5",
2250	"pu6",
2251	"sdmmc4_clk_pcc4",
2252	"sdmmc4_cmd_pt7",
2253	"sdmmc4_dat0_paa0",
2254	"sdmmc4_dat1_paa1",
2255	"sdmmc4_dat2_paa2",
2256	"sdmmc4_dat3_paa3",
2257	"sdmmc4_dat4_paa4",
2258	"sdmmc4_dat5_paa5",
2259	"sdmmc4_dat6_paa6",
2260	"sdmmc4_dat7_paa7",
2261	"spi1_cs0_n_px6",
2262	"spi1_mosi_px4",
2263	"spi1_sck_px5",
2264	"spi2_cs0_n_px3",
2265	"spi2_miso_px1",
2266	"spi2_mosi_px0",
2267	"spi2_sck_px2",
2268	"uart2_cts_n_pj5",
2269	"uart2_rts_n_pj6",
2270	"uart3_cts_n_pa1",
2271	"uart3_rts_n_pc0",
2272	"uart3_rxd_pw7",
2273	"uart3_txd_pw6",
2274};
2275
2276static const char * const gmi_alt_groups[] = {
2277	"gmi_a16_pj7",
2278	"gmi_cs3_n_pk4",
2279	"gmi_cs7_n_pi6",
2280	"gmi_wp_n_pc7",
2281};
2282
2283static const char * const hda_groups[] = {
2284	"clk1_req_pee2",
2285	"dap1_din_pn1",
2286	"dap1_dout_pn2",
2287	"dap1_fs_pn0",
2288	"dap1_sclk_pn3",
2289	"dap2_din_pa4",
2290	"dap2_dout_pa5",
2291	"dap2_fs_pa2",
2292	"dap2_sclk_pa3",
2293	"pex_l0_clkreq_n_pdd2",
2294	"pex_l0_prsnt_n_pdd0",
2295	"pex_l0_rst_n_pdd1",
2296	"pex_l1_clkreq_n_pdd6",
2297	"pex_l1_prsnt_n_pdd4",
2298	"pex_l1_rst_n_pdd5",
2299	"pex_l2_clkreq_n_pcc7",
2300	"pex_l2_prsnt_n_pdd7",
2301	"pex_l2_rst_n_pcc6",
2302	"pex_wake_n_pdd3",
2303	"spdif_in_pk6",
2304};
2305
2306static const char * const hdcp_groups[] = {
2307	"gen2_i2c_scl_pt5",
2308	"gen2_i2c_sda_pt6",
2309	"lcd_pwr0_pb2",
2310	"lcd_pwr2_pc6",
2311	"lcd_sck_pz4",
2312	"lcd_sdout_pn5",
2313	"lcd_wr_n_pz3",
2314};
2315
2316static const char * const hdmi_groups[] = {
2317	"hdmi_int_pn7",
2318};
2319
2320static const char * const hsi_groups[] = {
2321	"ulpi_data0_po1",
2322	"ulpi_data1_po2",
2323	"ulpi_data2_po3",
2324	"ulpi_data3_po4",
2325	"ulpi_data4_po5",
2326	"ulpi_data5_po6",
2327	"ulpi_data6_po7",
2328	"ulpi_data7_po0",
2329};
2330
2331static const char * const i2c1_groups[] = {
2332	"gen1_i2c_scl_pc4",
2333	"gen1_i2c_sda_pc5",
2334	"spdif_in_pk6",
2335	"spdif_out_pk5",
2336	"spi2_cs1_n_pw2",
2337	"spi2_cs2_n_pw3",
2338};
2339
2340static const char * const i2c2_groups[] = {
2341	"gen2_i2c_scl_pt5",
2342	"gen2_i2c_sda_pt6",
2343};
2344
2345static const char * const i2c3_groups[] = {
2346	"cam_i2c_scl_pbb1",
2347	"cam_i2c_sda_pbb2",
2348	"sdmmc4_cmd_pt7",
2349	"sdmmc4_dat4_paa4",
2350};
2351
2352static const char * const i2c4_groups[] = {
2353	"ddc_scl_pv4",
2354	"ddc_sda_pv5",
2355};
2356
2357static const char * const i2cpwr_groups[] = {
2358	"pwr_i2c_scl_pz6",
2359	"pwr_i2c_sda_pz7",
2360};
2361
2362static const char * const i2s0_groups[] = {
2363	"dap1_din_pn1",
2364	"dap1_dout_pn2",
2365	"dap1_fs_pn0",
2366	"dap1_sclk_pn3",
2367};
2368
2369static const char * const i2s1_groups[] = {
2370	"dap2_din_pa4",
2371	"dap2_dout_pa5",
2372	"dap2_fs_pa2",
2373	"dap2_sclk_pa3",
2374};
2375
2376static const char * const i2s2_groups[] = {
2377	"dap3_din_pp1",
2378	"dap3_dout_pp2",
2379	"dap3_fs_pp0",
2380	"dap3_sclk_pp3",
2381};
2382
2383static const char * const i2s3_groups[] = {
2384	"dap4_din_pp5",
2385	"dap4_dout_pp6",
2386	"dap4_fs_pp4",
2387	"dap4_sclk_pp7",
2388};
2389
2390static const char * const i2s4_groups[] = {
2391	"pbb0",
2392	"pbb7",
2393	"pcc1",
2394	"pcc2",
2395	"sdmmc4_dat4_paa4",
2396	"sdmmc4_dat5_paa5",
2397	"sdmmc4_dat6_paa6",
2398	"sdmmc4_dat7_paa7",
2399};
2400
2401static const char * const invalid_groups[] = {
2402	"kb_row3_pr3",
2403	"sdmmc4_clk_pcc4",
2404};
2405
2406static const char * const kbc_groups[] = {
2407	"kb_col0_pq0",
2408	"kb_col1_pq1",
2409	"kb_col2_pq2",
2410	"kb_col3_pq3",
2411	"kb_col4_pq4",
2412	"kb_col5_pq5",
2413	"kb_col6_pq6",
2414	"kb_col7_pq7",
2415	"kb_row0_pr0",
2416	"kb_row1_pr1",
2417	"kb_row10_ps2",
2418	"kb_row11_ps3",
2419	"kb_row12_ps4",
2420	"kb_row13_ps5",
2421	"kb_row14_ps6",
2422	"kb_row15_ps7",
2423	"kb_row2_pr2",
2424	"kb_row3_pr3",
2425	"kb_row4_pr4",
2426	"kb_row5_pr5",
2427	"kb_row6_pr6",
2428	"kb_row7_pr7",
2429	"kb_row8_ps0",
2430	"kb_row9_ps1",
2431};
2432
2433static const char * const mio_groups[] = {
2434	"kb_col6_pq6",
2435	"kb_col7_pq7",
2436	"kb_row10_ps2",
2437	"kb_row11_ps3",
2438	"kb_row12_ps4",
2439	"kb_row13_ps5",
2440	"kb_row14_ps6",
2441	"kb_row15_ps7",
2442	"kb_row6_pr6",
2443	"kb_row7_pr7",
2444	"kb_row8_ps0",
2445	"kb_row9_ps1",
2446};
2447
2448static const char * const nand_groups[] = {
2449	"gmi_ad0_pg0",
2450	"gmi_ad1_pg1",
2451	"gmi_ad10_ph2",
2452	"gmi_ad11_ph3",
2453	"gmi_ad12_ph4",
2454	"gmi_ad13_ph5",
2455	"gmi_ad14_ph6",
2456	"gmi_ad15_ph7",
2457	"gmi_ad2_pg2",
2458	"gmi_ad3_pg3",
2459	"gmi_ad4_pg4",
2460	"gmi_ad5_pg5",
2461	"gmi_ad6_pg6",
2462	"gmi_ad7_pg7",
2463	"gmi_ad8_ph0",
2464	"gmi_ad9_ph1",
2465	"gmi_adv_n_pk0",
2466	"gmi_clk_pk1",
2467	"gmi_cs0_n_pj0",
2468	"gmi_cs1_n_pj2",
2469	"gmi_cs2_n_pk3",
2470	"gmi_cs3_n_pk4",
2471	"gmi_cs4_n_pk2",
2472	"gmi_cs6_n_pi3",
2473	"gmi_cs7_n_pi6",
2474	"gmi_dqs_pi2",
2475	"gmi_iordy_pi5",
2476	"gmi_oe_n_pi1",
2477	"gmi_rst_n_pi4",
2478	"gmi_wait_pi7",
2479	"gmi_wp_n_pc7",
2480	"gmi_wr_n_pi0",
2481	"kb_col0_pq0",
2482	"kb_col1_pq1",
2483	"kb_col2_pq2",
2484	"kb_col3_pq3",
2485	"kb_col4_pq4",
2486	"kb_col5_pq5",
2487	"kb_col6_pq6",
2488	"kb_col7_pq7",
2489	"kb_row0_pr0",
2490	"kb_row1_pr1",
2491	"kb_row10_ps2",
2492	"kb_row11_ps3",
2493	"kb_row12_ps4",
2494	"kb_row13_ps5",
2495	"kb_row14_ps6",
2496	"kb_row15_ps7",
2497	"kb_row2_pr2",
2498	"kb_row3_pr3",
2499	"kb_row4_pr4",
2500	"kb_row5_pr5",
2501	"kb_row6_pr6",
2502	"kb_row7_pr7",
2503	"kb_row8_ps0",
2504	"kb_row9_ps1",
2505	"sdmmc4_clk_pcc4",
2506	"sdmmc4_cmd_pt7",
2507};
2508
2509static const char * const nand_alt_groups[] = {
2510	"gmi_cs6_n_pi3",
2511	"gmi_cs7_n_pi6",
2512	"gmi_rst_n_pi4",
2513};
2514
2515static const char * const owr_groups[] = {
2516	"pu0",
2517	"pv2",
2518	"kb_row5_pr5",
2519	"owr",
2520};
2521
2522static const char * const pcie_groups[] = {
2523	"pex_l0_clkreq_n_pdd2",
2524	"pex_l0_prsnt_n_pdd0",
2525	"pex_l0_rst_n_pdd1",
2526	"pex_l1_clkreq_n_pdd6",
2527	"pex_l1_prsnt_n_pdd4",
2528	"pex_l1_rst_n_pdd5",
2529	"pex_l2_clkreq_n_pcc7",
2530	"pex_l2_prsnt_n_pdd7",
2531	"pex_l2_rst_n_pcc6",
2532	"pex_wake_n_pdd3",
2533};
2534
2535static const char * const pwm0_groups[] = {
2536	"gmi_ad8_ph0",
2537	"pu3",
2538	"sdmmc3_dat3_pb4",
2539	"sdmmc3_dat5_pd0",
2540	"uart3_rts_n_pc0",
2541};
2542
2543static const char * const pwm1_groups[] = {
2544	"gmi_ad9_ph1",
2545	"pu4",
2546	"sdmmc3_dat2_pb5",
2547	"sdmmc3_dat4_pd1",
2548};
2549
2550static const char * const pwm2_groups[] = {
2551	"gmi_ad10_ph2",
2552	"pu5",
2553	"sdmmc3_clk_pa6",
2554};
2555
2556static const char * const pwm3_groups[] = {
2557	"gmi_ad11_ph3",
2558	"pu6",
2559	"sdmmc3_cmd_pa7",
2560};
2561
2562static const char * const pwr_int_n_groups[] = {
2563	"pwr_int_n",
2564};
2565
2566static const char * const rsvd1_groups[] = {
2567	"gmi_ad0_pg0",
2568	"gmi_ad1_pg1",
2569	"gmi_ad12_ph4",
2570	"gmi_ad13_ph5",
2571	"gmi_ad14_ph6",
2572	"gmi_ad15_ph7",
2573	"gmi_ad2_pg2",
2574	"gmi_ad3_pg3",
2575	"gmi_ad4_pg4",
2576	"gmi_ad5_pg5",
2577	"gmi_ad6_pg6",
2578	"gmi_ad7_pg7",
2579	"gmi_adv_n_pk0",
2580	"gmi_clk_pk1",
2581	"gmi_cs0_n_pj0",
2582	"gmi_cs1_n_pj2",
2583	"gmi_cs2_n_pk3",
2584	"gmi_cs3_n_pk4",
2585	"gmi_cs4_n_pk2",
2586	"gmi_dqs_pi2",
2587	"gmi_iordy_pi5",
2588	"gmi_oe_n_pi1",
2589	"gmi_wait_pi7",
2590	"gmi_wp_n_pc7",
2591	"gmi_wr_n_pi0",
2592	"pu1",
2593	"pu2",
2594	"pv0",
2595	"pv1",
2596	"sdmmc3_dat0_pb7",
2597	"sdmmc3_dat1_pb6",
2598	"sdmmc3_dat2_pb5",
2599	"sdmmc3_dat3_pb4",
2600	"vi_pclk_pt0",
2601};
2602
2603static const char * const rsvd2_groups[] = {
2604	"clk1_out_pw4",
2605	"clk2_out_pw5",
2606	"clk2_req_pcc5",
2607	"clk3_out_pee0",
2608	"clk3_req_pee1",
2609	"clk_32k_in",
2610	"clk_32k_out_pa0",
2611	"core_pwr_req",
2612	"cpu_pwr_req",
2613	"crt_hsync_pv6",
2614	"crt_vsync_pv7",
2615	"dap3_din_pp1",
2616	"dap3_dout_pp2",
2617	"dap3_fs_pp0",
2618	"dap3_sclk_pp3",
2619	"dap4_din_pp5",
2620	"dap4_dout_pp6",
2621	"dap4_fs_pp4",
2622	"dap4_sclk_pp7",
2623	"ddc_scl_pv4",
2624	"ddc_sda_pv5",
2625	"gen1_i2c_scl_pc4",
2626	"gen1_i2c_sda_pc5",
2627	"pbb0",
2628	"pbb7",
2629	"pcc1",
2630	"pcc2",
2631	"pv0",
2632	"pv1",
2633	"pv2",
2634	"pv3",
2635	"hdmi_cec_pee3",
2636	"hdmi_int_pn7",
2637	"jtag_rtck_pu7",
2638	"pwr_i2c_scl_pz6",
2639	"pwr_i2c_sda_pz7",
2640	"pwr_int_n",
2641	"sdmmc1_clk_pz0",
2642	"sdmmc1_cmd_pz1",
2643	"sdmmc1_dat0_py7",
2644	"sdmmc1_dat1_py6",
2645	"sdmmc1_dat2_py5",
2646	"sdmmc1_dat3_py4",
2647	"sdmmc3_dat0_pb7",
2648	"sdmmc3_dat1_pb6",
2649	"sdmmc4_rst_n_pcc3",
2650	"spdif_out_pk5",
2651	"sys_clk_req_pz5",
2652	"uart3_cts_n_pa1",
2653	"uart3_rxd_pw7",
2654	"uart3_txd_pw6",
2655	"ulpi_clk_py0",
2656	"ulpi_dir_py1",
2657	"ulpi_nxt_py2",
2658	"ulpi_stp_py3",
2659	"vi_d0_pt4",
2660	"vi_d10_pt2",
2661	"vi_d11_pt3",
2662	"vi_hsync_pd7",
2663	"vi_vsync_pd6",
2664};
2665
2666static const char * const rsvd3_groups[] = {
2667	"cam_i2c_scl_pbb1",
2668	"cam_i2c_sda_pbb2",
2669	"clk1_out_pw4",
2670	"clk1_req_pee2",
2671	"clk2_out_pw5",
2672	"clk2_req_pcc5",
2673	"clk3_out_pee0",
2674	"clk3_req_pee1",
2675	"clk_32k_in",
2676	"clk_32k_out_pa0",
2677	"core_pwr_req",
2678	"cpu_pwr_req",
2679	"crt_hsync_pv6",
2680	"crt_vsync_pv7",
2681	"dap2_din_pa4",
2682	"dap2_dout_pa5",
2683	"dap2_fs_pa2",
2684	"dap2_sclk_pa3",
2685	"ddc_scl_pv4",
2686	"ddc_sda_pv5",
2687	"gen1_i2c_scl_pc4",
2688	"gen1_i2c_sda_pc5",
2689	"pbb0",
2690	"pbb7",
2691	"pcc1",
2692	"pcc2",
2693	"pv0",
2694	"pv1",
2695	"pv2",
2696	"pv3",
2697	"hdmi_cec_pee3",
2698	"hdmi_int_pn7",
2699	"jtag_rtck_pu7",
2700	"kb_row0_pr0",
2701	"kb_row1_pr1",
2702	"kb_row2_pr2",
2703	"kb_row3_pr3",
2704	"lcd_d0_pe0",
2705	"lcd_d1_pe1",
2706	"lcd_d10_pf2",
2707	"lcd_d11_pf3",
2708	"lcd_d12_pf4",
2709	"lcd_d13_pf5",
2710	"lcd_d14_pf6",
2711	"lcd_d15_pf7",
2712	"lcd_d16_pm0",
2713	"lcd_d17_pm1",
2714	"lcd_d18_pm2",
2715	"lcd_d19_pm3",
2716	"lcd_d2_pe2",
2717	"lcd_d20_pm4",
2718	"lcd_d21_pm5",
2719	"lcd_d22_pm6",
2720	"lcd_d23_pm7",
2721	"lcd_d3_pe3",
2722	"lcd_d4_pe4",
2723	"lcd_d5_pe5",
2724	"lcd_d6_pe6",
2725	"lcd_d7_pe7",
2726	"lcd_d8_pf0",
2727	"lcd_d9_pf1",
2728	"lcd_dc0_pn6",
2729	"lcd_dc1_pd2",
2730	"lcd_de_pj1",
2731	"lcd_hsync_pj3",
2732	"lcd_m1_pw1",
2733	"lcd_pclk_pb3",
2734	"lcd_pwr1_pc1",
2735	"lcd_vsync_pj4",
2736	"owr",
2737	"pex_l0_clkreq_n_pdd2",
2738	"pex_l0_prsnt_n_pdd0",
2739	"pex_l0_rst_n_pdd1",
2740	"pex_l1_clkreq_n_pdd6",
2741	"pex_l1_prsnt_n_pdd4",
2742	"pex_l1_rst_n_pdd5",
2743	"pex_l2_clkreq_n_pcc7",
2744	"pex_l2_prsnt_n_pdd7",
2745	"pex_l2_rst_n_pcc6",
2746	"pex_wake_n_pdd3",
2747	"pwr_i2c_scl_pz6",
2748	"pwr_i2c_sda_pz7",
2749	"pwr_int_n",
2750	"sdmmc1_clk_pz0",
2751	"sdmmc1_cmd_pz1",
2752	"sdmmc4_rst_n_pcc3",
2753	"sys_clk_req_pz5",
2754};
2755
2756static const char * const rsvd4_groups[] = {
2757	"clk1_out_pw4",
2758	"clk1_req_pee2",
2759	"clk2_out_pw5",
2760	"clk2_req_pcc5",
2761	"clk3_out_pee0",
2762	"clk3_req_pee1",
2763	"clk_32k_in",
2764	"clk_32k_out_pa0",
2765	"core_pwr_req",
2766	"cpu_pwr_req",
2767	"crt_hsync_pv6",
2768	"crt_vsync_pv7",
2769	"dap4_din_pp5",
2770	"dap4_dout_pp6",
2771	"dap4_fs_pp4",
2772	"dap4_sclk_pp7",
2773	"ddc_scl_pv4",
2774	"ddc_sda_pv5",
2775	"gen1_i2c_scl_pc4",
2776	"gen1_i2c_sda_pc5",
2777	"gen2_i2c_scl_pt5",
2778	"gen2_i2c_sda_pt6",
2779	"gmi_a19_pk7",
2780	"gmi_ad0_pg0",
2781	"gmi_ad1_pg1",
2782	"gmi_ad10_ph2",
2783	"gmi_ad11_ph3",
2784	"gmi_ad12_ph4",
2785	"gmi_ad13_ph5",
2786	"gmi_ad14_ph6",
2787	"gmi_ad15_ph7",
2788	"gmi_ad2_pg2",
2789	"gmi_ad3_pg3",
2790	"gmi_ad4_pg4",
2791	"gmi_ad5_pg5",
2792	"gmi_ad6_pg6",
2793	"gmi_ad7_pg7",
2794	"gmi_ad8_ph0",
2795	"gmi_ad9_ph1",
2796	"gmi_adv_n_pk0",
2797	"gmi_clk_pk1",
2798	"gmi_cs2_n_pk3",
2799	"gmi_cs4_n_pk2",
2800	"gmi_dqs_pi2",
2801	"gmi_iordy_pi5",
2802	"gmi_oe_n_pi1",
2803	"gmi_rst_n_pi4",
2804	"gmi_wait_pi7",
2805	"gmi_wr_n_pi0",
2806	"pcc2",
2807	"pu0",
2808	"pu1",
2809	"pu2",
2810	"pu3",
2811	"pu4",
2812	"pu5",
2813	"pu6",
2814	"pv0",
2815	"pv1",
2816	"pv2",
2817	"pv3",
2818	"hdmi_cec_pee3",
2819	"hdmi_int_pn7",
2820	"jtag_rtck_pu7",
2821	"kb_col2_pq2",
2822	"kb_col3_pq3",
2823	"kb_col4_pq4",
2824	"kb_col5_pq5",
2825	"kb_row0_pr0",
2826	"kb_row1_pr1",
2827	"kb_row2_pr2",
2828	"kb_row4_pr4",
2829	"lcd_cs0_n_pn4",
2830	"lcd_cs1_n_pw0",
2831	"lcd_d0_pe0",
2832	"lcd_d1_pe1",
2833	"lcd_d10_pf2",
2834	"lcd_d11_pf3",
2835	"lcd_d12_pf4",
2836	"lcd_d13_pf5",
2837	"lcd_d14_pf6",
2838	"lcd_d15_pf7",
2839	"lcd_d16_pm0",
2840	"lcd_d17_pm1",
2841	"lcd_d18_pm2",
2842	"lcd_d19_pm3",
2843	"lcd_d2_pe2",
2844	"lcd_d20_pm4",
2845	"lcd_d21_pm5",
2846	"lcd_d22_pm6",
2847	"lcd_d23_pm7",
2848	"lcd_d3_pe3",
2849	"lcd_d4_pe4",
2850	"lcd_d5_pe5",
2851	"lcd_d6_pe6",
2852	"lcd_d7_pe7",
2853	"lcd_d8_pf0",
2854	"lcd_d9_pf1",
2855	"lcd_dc0_pn6",
2856	"lcd_dc1_pd2",
2857	"lcd_de_pj1",
2858	"lcd_hsync_pj3",
2859	"lcd_m1_pw1",
2860	"lcd_pclk_pb3",
2861	"lcd_pwr1_pc1",
2862	"lcd_sdin_pz2",
2863	"lcd_vsync_pj4",
2864	"owr",
2865	"pex_l0_clkreq_n_pdd2",
2866	"pex_l0_prsnt_n_pdd0",
2867	"pex_l0_rst_n_pdd1",
2868	"pex_l1_clkreq_n_pdd6",
2869	"pex_l1_prsnt_n_pdd4",
2870	"pex_l1_rst_n_pdd5",
2871	"pex_l2_clkreq_n_pcc7",
2872	"pex_l2_prsnt_n_pdd7",
2873	"pex_l2_rst_n_pcc6",
2874	"pex_wake_n_pdd3",
2875	"pwr_i2c_scl_pz6",
2876	"pwr_i2c_sda_pz7",
2877	"pwr_int_n",
2878	"spi1_miso_px7",
2879	"sys_clk_req_pz5",
2880	"uart3_cts_n_pa1",
2881	"uart3_rts_n_pc0",
2882	"uart3_rxd_pw7",
2883	"uart3_txd_pw6",
2884	"vi_d0_pt4",
2885	"vi_d1_pd5",
2886	"vi_d10_pt2",
2887	"vi_d11_pt3",
2888	"vi_d2_pl0",
2889	"vi_d3_pl1",
2890	"vi_d4_pl2",
2891	"vi_d5_pl3",
2892	"vi_d6_pl4",
2893	"vi_d7_pl5",
2894	"vi_d8_pl6",
2895	"vi_d9_pl7",
2896	"vi_hsync_pd7",
2897	"vi_pclk_pt0",
2898	"vi_vsync_pd6",
2899};
2900
2901static const char * const rtck_groups[] = {
2902	"jtag_rtck_pu7",
2903};
2904
2905static const char * const sata_groups[] = {
2906	"gmi_cs6_n_pi3",
2907};
2908
2909static const char * const sdmmc1_groups[] = {
2910	"sdmmc1_clk_pz0",
2911	"sdmmc1_cmd_pz1",
2912	"sdmmc1_dat0_py7",
2913	"sdmmc1_dat1_py6",
2914	"sdmmc1_dat2_py5",
2915	"sdmmc1_dat3_py4",
2916};
2917
2918static const char * const sdmmc2_groups[] = {
2919	"dap1_din_pn1",
2920	"dap1_dout_pn2",
2921	"dap1_fs_pn0",
2922	"dap1_sclk_pn3",
2923	"kb_row10_ps2",
2924	"kb_row11_ps3",
2925	"kb_row12_ps4",
2926	"kb_row13_ps5",
2927	"kb_row14_ps6",
2928	"kb_row15_ps7",
2929	"kb_row6_pr6",
2930	"kb_row7_pr7",
2931	"kb_row8_ps0",
2932	"kb_row9_ps1",
2933	"spdif_in_pk6",
2934	"spdif_out_pk5",
2935	"vi_d1_pd5",
2936	"vi_d2_pl0",
2937	"vi_d3_pl1",
2938	"vi_d4_pl2",
2939	"vi_d5_pl3",
2940	"vi_d6_pl4",
2941	"vi_d7_pl5",
2942	"vi_d8_pl6",
2943	"vi_d9_pl7",
2944	"vi_pclk_pt0",
2945};
2946
2947static const char * const sdmmc3_groups[] = {
2948	"sdmmc3_clk_pa6",
2949	"sdmmc3_cmd_pa7",
2950	"sdmmc3_dat0_pb7",
2951	"sdmmc3_dat1_pb6",
2952	"sdmmc3_dat2_pb5",
2953	"sdmmc3_dat3_pb4",
2954	"sdmmc3_dat4_pd1",
2955	"sdmmc3_dat5_pd0",
2956	"sdmmc3_dat6_pd3",
2957	"sdmmc3_dat7_pd4",
2958};
2959
2960static const char * const sdmmc4_groups[] = {
2961	"cam_i2c_scl_pbb1",
2962	"cam_i2c_sda_pbb2",
2963	"cam_mclk_pcc0",
2964	"pbb0",
2965	"pbb3",
2966	"pbb4",
2967	"pbb5",
2968	"pbb6",
2969	"pbb7",
2970	"pcc1",
2971	"sdmmc4_clk_pcc4",
2972	"sdmmc4_cmd_pt7",
2973	"sdmmc4_dat0_paa0",
2974	"sdmmc4_dat1_paa1",
2975	"sdmmc4_dat2_paa2",
2976	"sdmmc4_dat3_paa3",
2977	"sdmmc4_dat4_paa4",
2978	"sdmmc4_dat5_paa5",
2979	"sdmmc4_dat6_paa6",
2980	"sdmmc4_dat7_paa7",
2981	"sdmmc4_rst_n_pcc3",
2982};
2983
2984static const char * const spdif_groups[] = {
2985	"sdmmc3_dat6_pd3",
2986	"sdmmc3_dat7_pd4",
2987	"spdif_in_pk6",
2988	"spdif_out_pk5",
2989	"uart2_rxd_pc3",
2990	"uart2_txd_pc2",
2991};
2992
2993static const char * const spi1_groups[] = {
2994	"spi1_cs0_n_px6",
2995	"spi1_miso_px7",
2996	"spi1_mosi_px4",
2997	"spi1_sck_px5",
2998	"ulpi_clk_py0",
2999	"ulpi_dir_py1",
3000	"ulpi_nxt_py2",
3001	"ulpi_stp_py3",
3002};
3003
3004static const char * const spi2_groups[] = {
3005	"sdmmc3_cmd_pa7",
3006	"sdmmc3_dat4_pd1",
3007	"sdmmc3_dat5_pd0",
3008	"sdmmc3_dat6_pd3",
3009	"sdmmc3_dat7_pd4",
3010	"spi1_cs0_n_px6",
3011	"spi1_mosi_px4",
3012	"spi1_sck_px5",
3013	"spi2_cs0_n_px3",
3014	"spi2_cs1_n_pw2",
3015	"spi2_cs2_n_pw3",
3016	"spi2_miso_px1",
3017	"spi2_mosi_px0",
3018	"spi2_sck_px2",
3019	"ulpi_data4_po5",
3020	"ulpi_data5_po6",
3021	"ulpi_data6_po7",
3022	"ulpi_data7_po0",
3023};
3024
3025static const char * const spi2_alt_groups[] = {
3026	"spi1_cs0_n_px6",
3027	"spi1_miso_px7",
3028	"spi1_mosi_px4",
3029	"spi1_sck_px5",
3030	"spi2_cs1_n_pw2",
3031	"spi2_cs2_n_pw3",
3032};
3033
3034static const char * const spi3_groups[] = {
3035	"sdmmc3_clk_pa6",
3036	"sdmmc3_dat0_pb7",
3037	"sdmmc3_dat1_pb6",
3038	"sdmmc3_dat2_pb5",
3039	"sdmmc3_dat3_pb4",
3040	"sdmmc4_dat0_paa0",
3041	"sdmmc4_dat1_paa1",
3042	"sdmmc4_dat2_paa2",
3043	"sdmmc4_dat3_paa3",
3044	"spi1_miso_px7",
3045	"spi2_cs0_n_px3",
3046	"spi2_cs1_n_pw2",
3047	"spi2_cs2_n_pw3",
3048	"spi2_miso_px1",
3049	"spi2_mosi_px0",
3050	"spi2_sck_px2",
3051	"ulpi_data0_po1",
3052	"ulpi_data1_po2",
3053	"ulpi_data2_po3",
3054	"ulpi_data3_po4",
3055};
3056
3057static const char * const spi4_groups[] = {
3058	"gmi_a16_pj7",
3059	"gmi_a17_pb0",
3060	"gmi_a18_pb1",
3061	"gmi_a19_pk7",
3062	"sdmmc3_dat4_pd1",
3063	"sdmmc3_dat5_pd0",
3064	"sdmmc3_dat6_pd3",
3065	"sdmmc3_dat7_pd4",
3066	"uart2_cts_n_pj5",
3067	"uart2_rts_n_pj6",
3068	"uart2_rxd_pc3",
3069	"uart2_txd_pc2",
3070};
3071
3072static const char * const spi5_groups[] = {
3073	"lcd_cs0_n_pn4",
3074	"lcd_cs1_n_pw0",
3075	"lcd_pwr0_pb2",
3076	"lcd_pwr2_pc6",
3077	"lcd_sck_pz4",
3078	"lcd_sdin_pz2",
3079	"lcd_sdout_pn5",
3080	"lcd_wr_n_pz3",
3081};
3082
3083static const char * const spi6_groups[] = {
3084	"spi2_cs0_n_px3",
3085	"spi2_miso_px1",
3086	"spi2_mosi_px0",
3087	"spi2_sck_px2",
3088};
3089
3090static const char * const sysclk_groups[] = {
3091	"sys_clk_req_pz5",
3092};
3093
3094static const char * const test_groups[] = {
3095	"kb_col0_pq0",
3096	"kb_col1_pq1",
3097};
3098
3099static const char * const trace_groups[] = {
3100	"kb_col0_pq0",
3101	"kb_col1_pq1",
3102	"kb_col2_pq2",
3103	"kb_col3_pq3",
3104	"kb_col4_pq4",
3105	"kb_col5_pq5",
3106	"kb_col6_pq6",
3107	"kb_col7_pq7",
3108	"kb_row4_pr4",
3109	"kb_row5_pr5",
3110};
3111
3112static const char * const uarta_groups[] = {
3113	"pu0",
3114	"pu1",
3115	"pu2",
3116	"pu3",
3117	"pu4",
3118	"pu5",
3119	"pu6",
3120	"sdmmc1_clk_pz0",
3121	"sdmmc1_cmd_pz1",
3122	"sdmmc1_dat0_py7",
3123	"sdmmc1_dat1_py6",
3124	"sdmmc1_dat2_py5",
3125	"sdmmc1_dat3_py4",
3126	"sdmmc3_clk_pa6",
3127	"sdmmc3_cmd_pa7",
3128	"uart2_cts_n_pj5",
3129	"uart2_rts_n_pj6",
3130	"uart2_rxd_pc3",
3131	"uart2_txd_pc2",
3132	"ulpi_data0_po1",
3133	"ulpi_data1_po2",
3134	"ulpi_data2_po3",
3135	"ulpi_data3_po4",
3136	"ulpi_data4_po5",
3137	"ulpi_data5_po6",
3138	"ulpi_data6_po7",
3139	"ulpi_data7_po0",
3140};
3141
3142static const char * const uartb_groups[] = {
3143	"uart2_cts_n_pj5",
3144	"uart2_rts_n_pj6",
3145	"uart2_rxd_pc3",
3146	"uart2_txd_pc2",
3147};
3148
3149static const char * const uartc_groups[] = {
3150	"uart3_cts_n_pa1",
3151	"uart3_rts_n_pc0",
3152	"uart3_rxd_pw7",
3153	"uart3_txd_pw6",
3154};
3155
3156static const char * const uartd_groups[] = {
3157	"gmi_a16_pj7",
3158	"gmi_a17_pb0",
3159	"gmi_a18_pb1",
3160	"gmi_a19_pk7",
3161	"ulpi_clk_py0",
3162	"ulpi_dir_py1",
3163	"ulpi_nxt_py2",
3164	"ulpi_stp_py3",
3165};
3166
3167static const char * const uarte_groups[] = {
3168	"sdmmc1_dat0_py7",
3169	"sdmmc1_dat1_py6",
3170	"sdmmc1_dat2_py5",
3171	"sdmmc1_dat3_py4",
3172	"sdmmc4_dat0_paa0",
3173	"sdmmc4_dat1_paa1",
3174	"sdmmc4_dat2_paa2",
3175	"sdmmc4_dat3_paa3",
3176};
3177
3178static const char * const ulpi_groups[] = {
3179	"ulpi_clk_py0",
3180	"ulpi_data0_po1",
3181	"ulpi_data1_po2",
3182	"ulpi_data2_po3",
3183	"ulpi_data3_po4",
3184	"ulpi_data4_po5",
3185	"ulpi_data5_po6",
3186	"ulpi_data6_po7",
3187	"ulpi_data7_po0",
3188	"ulpi_dir_py1",
3189	"ulpi_nxt_py2",
3190	"ulpi_stp_py3",
3191};
3192
3193static const char * const vgp1_groups[] = {
3194	"cam_i2c_scl_pbb1",
3195};
3196
3197static const char * const vgp2_groups[] = {
3198	"cam_i2c_sda_pbb2",
3199};
3200
3201static const char * const vgp3_groups[] = {
3202	"pbb3",
3203	"sdmmc4_dat5_paa5",
3204};
3205
3206static const char * const vgp4_groups[] = {
3207	"pbb4",
3208	"sdmmc4_dat6_paa6",
3209};
3210
3211static const char * const vgp5_groups[] = {
3212	"pbb5",
3213	"sdmmc4_dat7_paa7",
3214};
3215
3216static const char * const vgp6_groups[] = {
3217	"pbb6",
3218	"sdmmc4_rst_n_pcc3",
3219};
3220
3221static const char * const vi_groups[] = {
3222	"cam_mclk_pcc0",
3223	"vi_d0_pt4",
3224	"vi_d1_pd5",
3225	"vi_d10_pt2",
3226	"vi_d11_pt3",
3227	"vi_d2_pl0",
3228	"vi_d3_pl1",
3229	"vi_d4_pl2",
3230	"vi_d5_pl3",
3231	"vi_d6_pl4",
3232	"vi_d7_pl5",
3233	"vi_d8_pl6",
3234	"vi_d9_pl7",
3235	"vi_hsync_pd7",
3236	"vi_mclk_pt1",
3237	"vi_pclk_pt0",
3238	"vi_vsync_pd6",
3239};
3240
3241static const char * const vi_alt1_groups[] = {
3242	"cam_mclk_pcc0",
3243	"vi_mclk_pt1",
3244};
3245
3246static const char * const vi_alt2_groups[] = {
3247	"vi_mclk_pt1",
3248};
3249
3250static const char * const vi_alt3_groups[] = {
3251	"cam_mclk_pcc0",
3252	"vi_mclk_pt1",
3253};
3254
3255#define FUNCTION(fname)					\
3256	{						\
3257		.name = #fname,				\
3258		.groups = fname##_groups,		\
3259		.ngroups = ARRAY_SIZE(fname##_groups),	\
3260	}
3261
3262static const struct tegra_function tegra30_functions[] = {
3263	FUNCTION(blink),
3264	FUNCTION(cec),
3265	FUNCTION(clk_12m_out),
3266	FUNCTION(clk_32k_in),
3267	FUNCTION(core_pwr_req),
3268	FUNCTION(cpu_pwr_req),
3269	FUNCTION(crt),
3270	FUNCTION(dap),
3271	FUNCTION(ddr),
3272	FUNCTION(dev3),
3273	FUNCTION(displaya),
3274	FUNCTION(displayb),
3275	FUNCTION(dtv),
3276	FUNCTION(extperiph1),
3277	FUNCTION(extperiph2),
3278	FUNCTION(extperiph3),
3279	FUNCTION(gmi),
3280	FUNCTION(gmi_alt),
3281	FUNCTION(hda),
3282	FUNCTION(hdcp),
3283	FUNCTION(hdmi),
3284	FUNCTION(hsi),
3285	FUNCTION(i2c1),
3286	FUNCTION(i2c2),
3287	FUNCTION(i2c3),
3288	FUNCTION(i2c4),
3289	FUNCTION(i2cpwr),
3290	FUNCTION(i2s0),
3291	FUNCTION(i2s1),
3292	FUNCTION(i2s2),
3293	FUNCTION(i2s3),
3294	FUNCTION(i2s4),
3295	FUNCTION(invalid),
3296	FUNCTION(kbc),
3297	FUNCTION(mio),
3298	FUNCTION(nand),
3299	FUNCTION(nand_alt),
3300	FUNCTION(owr),
3301	FUNCTION(pcie),
3302	FUNCTION(pwm0),
3303	FUNCTION(pwm1),
3304	FUNCTION(pwm2),
3305	FUNCTION(pwm3),
3306	FUNCTION(pwr_int_n),
3307	FUNCTION(rsvd1),
3308	FUNCTION(rsvd2),
3309	FUNCTION(rsvd3),
3310	FUNCTION(rsvd4),
3311	FUNCTION(rtck),
3312	FUNCTION(sata),
3313	FUNCTION(sdmmc1),
3314	FUNCTION(sdmmc2),
3315	FUNCTION(sdmmc3),
3316	FUNCTION(sdmmc4),
3317	FUNCTION(spdif),
3318	FUNCTION(spi1),
3319	FUNCTION(spi2),
3320	FUNCTION(spi2_alt),
3321	FUNCTION(spi3),
3322	FUNCTION(spi4),
3323	FUNCTION(spi5),
3324	FUNCTION(spi6),
3325	FUNCTION(sysclk),
3326	FUNCTION(test),
3327	FUNCTION(trace),
3328	FUNCTION(uarta),
3329	FUNCTION(uartb),
3330	FUNCTION(uartc),
3331	FUNCTION(uartd),
3332	FUNCTION(uarte),
3333	FUNCTION(ulpi),
3334	FUNCTION(vgp1),
3335	FUNCTION(vgp2),
3336	FUNCTION(vgp3),
3337	FUNCTION(vgp4),
3338	FUNCTION(vgp5),
3339	FUNCTION(vgp6),
3340	FUNCTION(vi),
3341	FUNCTION(vi_alt1),
3342	FUNCTION(vi_alt2),
3343	FUNCTION(vi_alt3),
3344};
3345
3346#define MUXCTL_REG_A	0x3000
3347#define PINGROUP_REG_A	0x868
3348
3349#define PINGROUP_REG_Y(r) ((r) - MUXCTL_REG_A)
3350#define PINGROUP_REG_N(r) -1
3351
3352#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior)	\
3353	{							\
3354		.name = #pg_name,				\
3355		.pins = pg_name##_pins,				\
3356		.npins = ARRAY_SIZE(pg_name##_pins),		\
3357		.funcs = {					\
3358			TEGRA_MUX_ ## f0,			\
3359			TEGRA_MUX_ ## f1,			\
3360			TEGRA_MUX_ ## f2,			\
3361			TEGRA_MUX_ ## f3,			\
3362		},						\
3363		.func_safe = TEGRA_MUX_ ## f_safe,		\
3364		.mux_reg = PINGROUP_REG_Y(r),			\
3365		.mux_bank = 0,					\
3366		.mux_bit = 0,					\
3367		.pupd_reg = PINGROUP_REG_Y(r),			\
3368		.pupd_bank = 0,					\
3369		.pupd_bit = 2,					\
3370		.tri_reg = PINGROUP_REG_Y(r),			\
3371		.tri_bank = 0,					\
3372		.tri_bit = 4,					\
3373		.einput_reg = PINGROUP_REG_Y(r),		\
3374		.einput_bank = 0,				\
3375		.einput_bit = 5,				\
3376		.odrain_reg = PINGROUP_REG_##od(r),		\
3377		.odrain_bank = 0,				\
3378		.odrain_bit = 6,				\
3379		.lock_reg = PINGROUP_REG_Y(r),			\
3380		.lock_bank = 0,					\
3381		.lock_bit = 7,					\
3382		.ioreset_reg = PINGROUP_REG_##ior(r),		\
3383		.ioreset_bank = 0,				\
3384		.ioreset_bit = 8,				\
3385		.drv_reg = -1,					\
3386	}
3387
3388#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b,	\
3389		     drvdn_b, drvdn_w, drvup_b, drvup_w,	\
3390		     slwr_b, slwr_w, slwf_b, slwf_w)		\
3391	{							\
3392		.name = "drive_" #pg_name,			\
3393		.pins = drive_##pg_name##_pins,			\
3394		.npins = ARRAY_SIZE(drive_##pg_name##_pins),	\
3395		.mux_reg = -1,					\
3396		.pupd_reg = -1,					\
3397		.tri_reg = -1,					\
3398		.einput_reg = -1,				\
3399		.odrain_reg = -1,				\
3400		.lock_reg = -1,					\
3401		.ioreset_reg = -1,				\
3402		.drv_reg = ((r) - PINGROUP_REG_A),		\
3403		.drv_bank = 1,					\
3404		.hsm_bit = hsm_b,				\
3405		.schmitt_bit = schmitt_b,			\
3406		.lpmd_bit = lpmd_b,				\
3407		.drvdn_bit = drvdn_b,				\
3408		.drvdn_width = drvdn_w,				\
3409		.drvup_bit = drvup_b,				\
3410		.drvup_width = drvup_w,				\
3411		.slwr_bit = slwr_b,				\
3412		.slwr_width = slwr_w,				\
3413		.slwf_bit = slwf_b,				\
3414		.slwf_width = slwf_w,				\
3415	}
3416
3417static const struct tegra_pingroup tegra30_groups[] = {
3418	/*       pg_name,              f0,           f1,           f2,           f3,           safe,         r,      od, ior */
3419	/* FIXME: Fill in correct data in safe column */
3420	PINGROUP(clk_32k_out_pa0,      BLINK,        RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x331c, N, N),
3421	PINGROUP(uart3_cts_n_pa1,      UARTC,        RSVD2,        GMI,          RSVD4,        RSVD4,        0x317c, N, N),
3422	PINGROUP(dap2_fs_pa2,          I2S1,         HDA,          RSVD3,        GMI,          RSVD3,        0x3358, N, N),
3423	PINGROUP(dap2_sclk_pa3,        I2S1,         HDA,          RSVD3,        GMI,          RSVD3,        0x3364, N, N),
3424	PINGROUP(dap2_din_pa4,         I2S1,         HDA,          RSVD3,        GMI,          RSVD3,        0x335c, N, N),
3425	PINGROUP(dap2_dout_pa5,        I2S1,         HDA,          RSVD3,        GMI,          RSVD3,        0x3360, N, N),
3426	PINGROUP(sdmmc3_clk_pa6,       UARTA,        PWM2,         SDMMC3,       SPI3,         SPI3,         0x3390, N, N),
3427	PINGROUP(sdmmc3_cmd_pa7,       UARTA,        PWM3,         SDMMC3,       SPI2,         SPI2,         0x3394, N, N),
3428	PINGROUP(gmi_a17_pb0,          UARTD,        SPI4,         GMI,          DTV,          DTV,          0x3234, N, N),
3429	PINGROUP(gmi_a18_pb1,          UARTD,        SPI4,         GMI,          DTV,          DTV,          0x3238, N, N),
3430	PINGROUP(lcd_pwr0_pb2,         DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         HDCP,         0x3090, N, N),
3431	PINGROUP(lcd_pclk_pb3,         DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3094, N, N),
3432	PINGROUP(sdmmc3_dat3_pb4,      RSVD1,        PWM0,         SDMMC3,       SPI3,         RSVD1,        0x33a4, N, N),
3433	PINGROUP(sdmmc3_dat2_pb5,      RSVD1,        PWM1,         SDMMC3,       SPI3,         RSVD1,        0x33a0, N, N),
3434	PINGROUP(sdmmc3_dat1_pb6,      RSVD1,        RSVD2,        SDMMC3,       SPI3,         RSVD2,        0x339c, N, N),
3435	PINGROUP(sdmmc3_dat0_pb7,      RSVD1,        RSVD2,        SDMMC3,       SPI3,         RSVD2,        0x3398, N, N),
3436	PINGROUP(uart3_rts_n_pc0,      UARTC,        PWM0,         GMI,          RSVD4,        RSVD4,        0x3180, N, N),
3437	PINGROUP(lcd_pwr1_pc1,         DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3070, N, N),
3438	PINGROUP(uart2_txd_pc2,        UARTB,        SPDIF,        UARTA,        SPI4,         SPI4,         0x3168, N, N),
3439	PINGROUP(uart2_rxd_pc3,        UARTB,        SPDIF,        UARTA,        SPI4,         SPI4,         0x3164, N, N),
3440	PINGROUP(gen1_i2c_scl_pc4,     I2C1,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x31a4, Y, N),
3441	PINGROUP(gen1_i2c_sda_pc5,     I2C1,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x31a0, Y, N),
3442	PINGROUP(lcd_pwr2_pc6,         DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         HDCP,         0x3074, N, N),
3443	PINGROUP(gmi_wp_n_pc7,         RSVD1,        NAND,         GMI,          GMI_ALT,      RSVD1,        0x31c0, N, N),
3444	PINGROUP(sdmmc3_dat5_pd0,      PWM0,         SPI4,         SDMMC3,       SPI2,         SPI2,         0x33ac, N, N),
3445	PINGROUP(sdmmc3_dat4_pd1,      PWM1,         SPI4,         SDMMC3,       SPI2,         SPI2,         0x33a8, N, N),
3446	PINGROUP(lcd_dc1_pd2,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x310c, N, N),
3447	PINGROUP(sdmmc3_dat6_pd3,      SPDIF,        SPI4,         SDMMC3,       SPI2,         SPI2,         0x33b0, N, N),
3448	PINGROUP(sdmmc3_dat7_pd4,      SPDIF,        SPI4,         SDMMC3,       SPI2,         SPI2,         0x33b4, N, N),
3449	PINGROUP(vi_d1_pd5,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3128, N, Y),
3450	PINGROUP(vi_vsync_pd6,         DDR,          RSVD2,        VI,           RSVD4,        RSVD4,        0x315c, N, Y),
3451	PINGROUP(vi_hsync_pd7,         DDR,          RSVD2,        VI,           RSVD4,        RSVD4,        0x3160, N, Y),
3452	PINGROUP(lcd_d0_pe0,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30a4, N, N),
3453	PINGROUP(lcd_d1_pe1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30a8, N, N),
3454	PINGROUP(lcd_d2_pe2,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30ac, N, N),
3455	PINGROUP(lcd_d3_pe3,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30b0, N, N),
3456	PINGROUP(lcd_d4_pe4,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30b4, N, N),
3457	PINGROUP(lcd_d5_pe5,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30b8, N, N),
3458	PINGROUP(lcd_d6_pe6,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30bc, N, N),
3459	PINGROUP(lcd_d7_pe7,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30c0, N, N),
3460	PINGROUP(lcd_d8_pf0,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30c4, N, N),
3461	PINGROUP(lcd_d9_pf1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30c8, N, N),
3462	PINGROUP(lcd_d10_pf2,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30cc, N, N),
3463	PINGROUP(lcd_d11_pf3,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30d0, N, N),
3464	PINGROUP(lcd_d12_pf4,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30d4, N, N),
3465	PINGROUP(lcd_d13_pf5,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30d8, N, N),
3466	PINGROUP(lcd_d14_pf6,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30dc, N, N),
3467	PINGROUP(lcd_d15_pf7,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30e0, N, N),
3468	PINGROUP(gmi_ad0_pg0,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31f0, N, N),
3469	PINGROUP(gmi_ad1_pg1,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31f4, N, N),
3470	PINGROUP(gmi_ad2_pg2,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31f8, N, N),
3471	PINGROUP(gmi_ad3_pg3,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31fc, N, N),
3472	PINGROUP(gmi_ad4_pg4,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3200, N, N),
3473	PINGROUP(gmi_ad5_pg5,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3204, N, N),
3474	PINGROUP(gmi_ad6_pg6,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3208, N, N),
3475	PINGROUP(gmi_ad7_pg7,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x320c, N, N),
3476	PINGROUP(gmi_ad8_ph0,          PWM0,         NAND,         GMI,          RSVD4,        RSVD4,        0x3210, N, N),
3477	PINGROUP(gmi_ad9_ph1,          PWM1,         NAND,         GMI,          RSVD4,        RSVD4,        0x3214, N, N),
3478	PINGROUP(gmi_ad10_ph2,         PWM2,         NAND,         GMI,          RSVD4,        RSVD4,        0x3218, N, N),
3479	PINGROUP(gmi_ad11_ph3,         PWM3,         NAND,         GMI,          RSVD4,        RSVD4,        0x321c, N, N),
3480	PINGROUP(gmi_ad12_ph4,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3220, N, N),
3481	PINGROUP(gmi_ad13_ph5,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3224, N, N),
3482	PINGROUP(gmi_ad14_ph6,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3228, N, N),
3483	PINGROUP(gmi_ad15_ph7,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x322c, N, N),
3484	PINGROUP(gmi_wr_n_pi0,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3240, N, N),
3485	PINGROUP(gmi_oe_n_pi1,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3244, N, N),
3486	PINGROUP(gmi_dqs_pi2,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3248, N, N),
3487	PINGROUP(gmi_cs6_n_pi3,        NAND,         NAND_ALT,     GMI,          SATA,         SATA,         0x31e8, N, N),
3488	PINGROUP(gmi_rst_n_pi4,        NAND,         NAND_ALT,     GMI,          RSVD4,        RSVD4,        0x324c, N, N),
3489	PINGROUP(gmi_iordy_pi5,        RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31c4, N, N),
3490	PINGROUP(gmi_cs7_n_pi6,        NAND,         NAND_ALT,     GMI,          GMI_ALT,      GMI_ALT,      0x31ec, N, N),
3491	PINGROUP(gmi_wait_pi7,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31c8, N, N),
3492	PINGROUP(gmi_cs0_n_pj0,        RSVD1,        NAND,         GMI,          DTV,          RSVD1,        0x31d4, N, N),
3493	PINGROUP(lcd_de_pj1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3098, N, N),
3494	PINGROUP(gmi_cs1_n_pj2,        RSVD1,        NAND,         GMI,          DTV,          RSVD1,        0x31d8, N, N),
3495	PINGROUP(lcd_hsync_pj3,        DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x309c, N, N),
3496	PINGROUP(lcd_vsync_pj4,        DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30a0, N, N),
3497	PINGROUP(uart2_cts_n_pj5,      UARTA,        UARTB,        GMI,          SPI4,         SPI4,         0x3170, N, N),
3498	PINGROUP(uart2_rts_n_pj6,      UARTA,        UARTB,        GMI,          SPI4,         SPI4,         0x316c, N, N),
3499	PINGROUP(gmi_a16_pj7,          UARTD,        SPI4,         GMI,          GMI_ALT,      GMI_ALT,      0x3230, N, N),
3500	PINGROUP(gmi_adv_n_pk0,        RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31cc, N, N),
3501	PINGROUP(gmi_clk_pk1,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31d0, N, N),
3502	PINGROUP(gmi_cs4_n_pk2,        RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31e4, N, N),
3503	PINGROUP(gmi_cs2_n_pk3,        RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31dc, N, N),
3504	PINGROUP(gmi_cs3_n_pk4,        RSVD1,        NAND,         GMI,          GMI_ALT,      RSVD1,        0x31e0, N, N),
3505	PINGROUP(spdif_out_pk5,        SPDIF,        RSVD2,        I2C1,         SDMMC2,       RSVD2,        0x3354, N, N),
3506	PINGROUP(spdif_in_pk6,         SPDIF,        HDA,          I2C1,         SDMMC2,       SDMMC2,       0x3350, N, N),
3507	PINGROUP(gmi_a19_pk7,          UARTD,        SPI4,         GMI,          RSVD4,        RSVD4,        0x323c, N, N),
3508	PINGROUP(vi_d2_pl0,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x312c, N, Y),
3509	PINGROUP(vi_d3_pl1,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3130, N, Y),
3510	PINGROUP(vi_d4_pl2,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3134, N, Y),
3511	PINGROUP(vi_d5_pl3,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3138, N, Y),
3512	PINGROUP(vi_d6_pl4,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x313c, N, Y),
3513	PINGROUP(vi_d7_pl5,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3140, N, Y),
3514	PINGROUP(vi_d8_pl6,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3144, N, Y),
3515	PINGROUP(vi_d9_pl7,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3148, N, Y),
3516	PINGROUP(lcd_d16_pm0,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30e4, N, N),
3517	PINGROUP(lcd_d17_pm1,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30e8, N, N),
3518	PINGROUP(lcd_d18_pm2,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30ec, N, N),
3519	PINGROUP(lcd_d19_pm3,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30f0, N, N),
3520	PINGROUP(lcd_d20_pm4,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30f4, N, N),
3521	PINGROUP(lcd_d21_pm5,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30f8, N, N),
3522	PINGROUP(lcd_d22_pm6,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30fc, N, N),
3523	PINGROUP(lcd_d23_pm7,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3100, N, N),
3524	PINGROUP(dap1_fs_pn0,          I2S0,         HDA,          GMI,          SDMMC2,       SDMMC2,       0x3338, N, N),
3525	PINGROUP(dap1_din_pn1,         I2S0,         HDA,          GMI,          SDMMC2,       SDMMC2,       0x333c, N, N),
3526	PINGROUP(dap1_dout_pn2,        I2S0,         HDA,          GMI,          SDMMC2,       SDMMC2,       0x3340, N, N),
3527	PINGROUP(dap1_sclk_pn3,        I2S0,         HDA,          GMI,          SDMMC2,       SDMMC2,       0x3344, N, N),
3528	PINGROUP(lcd_cs0_n_pn4,        DISPLAYA,     DISPLAYB,     SPI5,         RSVD4,        RSVD4,        0x3084, N, N),
3529	PINGROUP(lcd_sdout_pn5,        DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         HDCP,         0x307c, N, N),
3530	PINGROUP(lcd_dc0_pn6,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3088, N, N),
3531	PINGROUP(hdmi_int_pn7,         HDMI,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3110, N, N),
3532	PINGROUP(ulpi_data7_po0,       SPI2,         HSI,          UARTA,        ULPI,         ULPI,         0x301c, N, N),
3533	PINGROUP(ulpi_data0_po1,       SPI3,         HSI,          UARTA,        ULPI,         ULPI,         0x3000, N, N),
3534	PINGROUP(ulpi_data1_po2,       SPI3,         HSI,          UARTA,        ULPI,         ULPI,         0x3004, N, N),
3535	PINGROUP(ulpi_data2_po3,       SPI3,         HSI,          UARTA,        ULPI,         ULPI,         0x3008, N, N),
3536	PINGROUP(ulpi_data3_po4,       SPI3,         HSI,          UARTA,        ULPI,         ULPI,         0x300c, N, N),
3537	PINGROUP(ulpi_data4_po5,       SPI2,         HSI,          UARTA,        ULPI,         ULPI,         0x3010, N, N),
3538	PINGROUP(ulpi_data5_po6,       SPI2,         HSI,          UARTA,        ULPI,         ULPI,         0x3014, N, N),
3539	PINGROUP(ulpi_data6_po7,       SPI2,         HSI,          UARTA,        ULPI,         ULPI,         0x3018, N, N),
3540	PINGROUP(dap3_fs_pp0,          I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     RSVD2,        0x3030, N, N),
3541	PINGROUP(dap3_din_pp1,         I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     RSVD2,        0x3034, N, N),
3542	PINGROUP(dap3_dout_pp2,        I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     RSVD2,        0x3038, N, N),
3543	PINGROUP(dap3_sclk_pp3,        I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     RSVD2,        0x303c, N, N),
3544	PINGROUP(dap4_fs_pp4,          I2S3,         RSVD2,        GMI,          RSVD4,        RSVD4,        0x31a8, N, N),
3545	PINGROUP(dap4_din_pp5,         I2S3,         RSVD2,        GMI,          RSVD4,        RSVD4,        0x31ac, N, N),
3546	PINGROUP(dap4_dout_pp6,        I2S3,         RSVD2,        GMI,          RSVD4,        RSVD4,        0x31b0, N, N),
3547	PINGROUP(dap4_sclk_pp7,        I2S3,         RSVD2,        GMI,          RSVD4,        RSVD4,        0x31b4, N, N),
3548	PINGROUP(kb_col0_pq0,          KBC,          NAND,         TRACE,        TEST,         TEST,         0x32fc, N, N),
3549	PINGROUP(kb_col1_pq1,          KBC,          NAND,         TRACE,        TEST,         TEST,         0x3300, N, N),
3550	PINGROUP(kb_col2_pq2,          KBC,          NAND,         TRACE,        RSVD4,        RSVD4,        0x3304, N, N),
3551	PINGROUP(kb_col3_pq3,          KBC,          NAND,         TRACE,        RSVD4,        RSVD4,        0x3308, N, N),
3552	PINGROUP(kb_col4_pq4,          KBC,          NAND,         TRACE,        RSVD4,        RSVD4,        0x330c, N, N),
3553	PINGROUP(kb_col5_pq5,          KBC,          NAND,         TRACE,        RSVD4,        RSVD4,        0x3310, N, N),
3554	PINGROUP(kb_col6_pq6,          KBC,          NAND,         TRACE,        MIO,          MIO,          0x3314, N, N),
3555	PINGROUP(kb_col7_pq7,          KBC,          NAND,         TRACE,        MIO,          MIO,          0x3318, N, N),
3556	PINGROUP(kb_row0_pr0,          KBC,          NAND,         RSVD3,        RSVD4,        RSVD4,        0x32bc, N, N),
3557	PINGROUP(kb_row1_pr1,          KBC,          NAND,         RSVD3,        RSVD4,        RSVD4,        0x32c0, N, N),
3558	PINGROUP(kb_row2_pr2,          KBC,          NAND,         RSVD3,        RSVD4,        RSVD4,        0x32c4, N, N),
3559	PINGROUP(kb_row3_pr3,          KBC,          NAND,         RSVD3,        INVALID,      RSVD3,        0x32c8, N, N),
3560	PINGROUP(kb_row4_pr4,          KBC,          NAND,         TRACE,        RSVD4,        RSVD4,        0x32cc, N, N),
3561	PINGROUP(kb_row5_pr5,          KBC,          NAND,         TRACE,        OWR,          OWR,          0x32d0, N, N),
3562	PINGROUP(kb_row6_pr6,          KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32d4, N, N),
3563	PINGROUP(kb_row7_pr7,          KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32d8, N, N),
3564	PINGROUP(kb_row8_ps0,          KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32dc, N, N),
3565	PINGROUP(kb_row9_ps1,          KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32e0, N, N),
3566	PINGROUP(kb_row10_ps2,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32e4, N, N),
3567	PINGROUP(kb_row11_ps3,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32e8, N, N),
3568	PINGROUP(kb_row12_ps4,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32ec, N, N),
3569	PINGROUP(kb_row13_ps5,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32f0, N, N),
3570	PINGROUP(kb_row14_ps6,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32f4, N, N),
3571	PINGROUP(kb_row15_ps7,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32f8, N, N),
3572	PINGROUP(vi_pclk_pt0,          RSVD1,        SDMMC2,       VI,           RSVD4,        RSVD4,        0x3154, N, Y),
3573	PINGROUP(vi_mclk_pt1,          VI,           VI_ALT1,      VI_ALT2,      VI_ALT3,      VI_ALT3,      0x3158, N, Y),
3574	PINGROUP(vi_d10_pt2,           DDR,          RSVD2,        VI,           RSVD4,        RSVD4,        0x314c, N, Y),
3575	PINGROUP(vi_d11_pt3,           DDR,          RSVD2,        VI,           RSVD4,        RSVD4,        0x3150, N, Y),
3576	PINGROUP(vi_d0_pt4,            DDR,          RSVD2,        VI,           RSVD4,        RSVD4,        0x3124, N, Y),
3577	PINGROUP(gen2_i2c_scl_pt5,     I2C2,         HDCP,         GMI,          RSVD4,        RSVD4,        0x3250, Y, N),
3578	PINGROUP(gen2_i2c_sda_pt6,     I2C2,         HDCP,         GMI,          RSVD4,        RSVD4,        0x3254, Y, N),
3579	PINGROUP(sdmmc4_cmd_pt7,       I2C3,         NAND,         GMI,          SDMMC4,       SDMMC4,       0x325c, N, Y),
3580	PINGROUP(pu0,                  OWR,          UARTA,        GMI,          RSVD4,        RSVD4,        0x3184, N, N),
3581	PINGROUP(pu1,                  RSVD1,        UARTA,        GMI,          RSVD4,        RSVD4,        0x3188, N, N),
3582	PINGROUP(pu2,                  RSVD1,        UARTA,        GMI,          RSVD4,        RSVD4,        0x318c, N, N),
3583	PINGROUP(pu3,                  PWM0,         UARTA,        GMI,          RSVD4,        RSVD4,        0x3190, N, N),
3584	PINGROUP(pu4,                  PWM1,         UARTA,        GMI,          RSVD4,        RSVD4,        0x3194, N, N),
3585	PINGROUP(pu5,                  PWM2,         UARTA,        GMI,          RSVD4,        RSVD4,        0x3198, N, N),
3586	PINGROUP(pu6,                  PWM3,         UARTA,        GMI,          RSVD4,        RSVD4,        0x319c, N, N),
3587	PINGROUP(jtag_rtck_pu7,        RTCK,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x32b0, N, N),
3588	PINGROUP(pv0,                  RSVD1,        RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3040, N, N),
3589	PINGROUP(pv1,                  RSVD1,        RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3044, N, N),
3590	PINGROUP(pv2,                  OWR,          RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3060, N, N),
3591	PINGROUP(pv3,                  CLK_12M_OUT,  RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3064, N, N),
3592	PINGROUP(ddc_scl_pv4,          I2C4,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3114, N, N),
3593	PINGROUP(ddc_sda_pv5,          I2C4,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3118, N, N),
3594	PINGROUP(crt_hsync_pv6,        CRT,          RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x311c, N, N),
3595	PINGROUP(crt_vsync_pv7,        CRT,          RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3120, N, N),
3596	PINGROUP(lcd_cs1_n_pw0,        DISPLAYA,     DISPLAYB,     SPI5,         RSVD4,        RSVD4,        0x3104, N, N),
3597	PINGROUP(lcd_m1_pw1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3108, N, N),
3598	PINGROUP(spi2_cs1_n_pw2,       SPI3,         SPI2,         SPI2_ALT,     I2C1,         I2C1,         0x3388, N, N),
3599	PINGROUP(spi2_cs2_n_pw3,       SPI3,         SPI2,         SPI2_ALT,     I2C1,         I2C1,         0x338c, N, N),
3600	PINGROUP(clk1_out_pw4,         EXTPERIPH1,   RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x334c, N, N),
3601	PINGROUP(clk2_out_pw5,         EXTPERIPH2,   RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3068, N, N),
3602	PINGROUP(uart3_txd_pw6,        UARTC,        RSVD2,        GMI,          RSVD4,        RSVD4,        0x3174, N, N),
3603	PINGROUP(uart3_rxd_pw7,        UARTC,        RSVD2,        GMI,          RSVD4,        RSVD4,        0x3178, N, N),
3604	PINGROUP(spi2_mosi_px0,        SPI6,         SPI2,         SPI3,         GMI,          GMI,          0x3368, N, N),
3605	PINGROUP(spi2_miso_px1,        SPI6,         SPI2,         SPI3,         GMI,          GMI,          0x336c, N, N),
3606	PINGROUP(spi2_sck_px2,         SPI6,         SPI2,         SPI3,         GMI,          GMI,          0x3374, N, N),
3607	PINGROUP(spi2_cs0_n_px3,       SPI6,         SPI2,         SPI3,         GMI,          GMI,          0x3370, N, N),
3608	PINGROUP(spi1_mosi_px4,        SPI2,         SPI1,         SPI2_ALT,     GMI,          GMI,          0x3378, N, N),
3609	PINGROUP(spi1_sck_px5,         SPI2,         SPI1,         SPI2_ALT,     GMI,          GMI,          0x337c, N, N),
3610	PINGROUP(spi1_cs0_n_px6,       SPI2,         SPI1,         SPI2_ALT,     GMI,          GMI,          0x3380, N, N),
3611	PINGROUP(spi1_miso_px7,        SPI3,         SPI1,         SPI2_ALT,     RSVD4,        RSVD4,        0x3384, N, N),
3612	PINGROUP(ulpi_clk_py0,         SPI1,         RSVD2,        UARTD,        ULPI,         RSVD2,        0x3020, N, N),
3613	PINGROUP(ulpi_dir_py1,         SPI1,         RSVD2,        UARTD,        ULPI,         RSVD2,        0x3024, N, N),
3614	PINGROUP(ulpi_nxt_py2,         SPI1,         RSVD2,        UARTD,        ULPI,         RSVD2,        0x3028, N, N),
3615	PINGROUP(ulpi_stp_py3,         SPI1,         RSVD2,        UARTD,        ULPI,         RSVD2,        0x302c, N, N),
3616	PINGROUP(sdmmc1_dat3_py4,      SDMMC1,       RSVD2,        UARTE,        UARTA,        RSVD2,        0x3050, N, N),
3617	PINGROUP(sdmmc1_dat2_py5,      SDMMC1,       RSVD2,        UARTE,        UARTA,        RSVD2,        0x3054, N, N),
3618	PINGROUP(sdmmc1_dat1_py6,      SDMMC1,       RSVD2,        UARTE,        UARTA,        RSVD2,        0x3058, N, N),
3619	PINGROUP(sdmmc1_dat0_py7,      SDMMC1,       RSVD2,        UARTE,        UARTA,        RSVD2,        0x305c, N, N),
3620	PINGROUP(sdmmc1_clk_pz0,       SDMMC1,       RSVD2,        RSVD3,        UARTA,        RSVD3,        0x3048, N, N),
3621	PINGROUP(sdmmc1_cmd_pz1,       SDMMC1,       RSVD2,        RSVD3,        UARTA,        RSVD3,        0x304c, N, N),
3622	PINGROUP(lcd_sdin_pz2,         DISPLAYA,     DISPLAYB,     SPI5,         RSVD4,        RSVD4,        0x3078, N, N),
3623	PINGROUP(lcd_wr_n_pz3,         DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         HDCP,         0x3080, N, N),
3624	PINGROUP(lcd_sck_pz4,          DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         HDCP,         0x308c, N, N),
3625	PINGROUP(sys_clk_req_pz5,      SYSCLK,       RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3320, N, N),
3626	PINGROUP(pwr_i2c_scl_pz6,      I2CPWR,       RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x32b4, Y, N),
3627	PINGROUP(pwr_i2c_sda_pz7,      I2CPWR,       RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x32b8, Y, N),
3628	PINGROUP(sdmmc4_dat0_paa0,     UARTE,        SPI3,         GMI,          SDMMC4,       SDMMC4,       0x3260, N, Y),
3629	PINGROUP(sdmmc4_dat1_paa1,     UARTE,        SPI3,         GMI,          SDMMC4,       SDMMC4,       0x3264, N, Y),
3630	PINGROUP(sdmmc4_dat2_paa2,     UARTE,        SPI3,         GMI,          SDMMC4,       SDMMC4,       0x3268, N, Y),
3631	PINGROUP(sdmmc4_dat3_paa3,     UARTE,        SPI3,         GMI,          SDMMC4,       SDMMC4,       0x326c, N, Y),
3632	PINGROUP(sdmmc4_dat4_paa4,     I2C3,         I2S4,         GMI,          SDMMC4,       SDMMC4,       0x3270, N, Y),
3633	PINGROUP(sdmmc4_dat5_paa5,     VGP3,         I2S4,         GMI,          SDMMC4,       SDMMC4,       0x3274, N, Y),
3634	PINGROUP(sdmmc4_dat6_paa6,     VGP4,         I2S4,         GMI,          SDMMC4,       SDMMC4,       0x3278, N, Y),
3635	PINGROUP(sdmmc4_dat7_paa7,     VGP5,         I2S4,         GMI,          SDMMC4,       SDMMC4,       0x327c, N, Y),
3636	PINGROUP(pbb0,                 I2S4,         RSVD2,        RSVD3,        SDMMC4,       RSVD3,        0x328c, N, N),
3637	PINGROUP(cam_i2c_scl_pbb1,     VGP1,         I2C3,         RSVD3,        SDMMC4,       RSVD3,        0x3290, Y, N),
3638	PINGROUP(cam_i2c_sda_pbb2,     VGP2,         I2C3,         RSVD3,        SDMMC4,       RSVD3,        0x3294, Y, N),
3639	PINGROUP(pbb3,                 VGP3,         DISPLAYA,     DISPLAYB,     SDMMC4,       SDMMC4,       0x3298, N, N),
3640	PINGROUP(pbb4,                 VGP4,         DISPLAYA,     DISPLAYB,     SDMMC4,       SDMMC4,       0x329c, N, N),
3641	PINGROUP(pbb5,                 VGP5,         DISPLAYA,     DISPLAYB,     SDMMC4,       SDMMC4,       0x32a0, N, N),
3642	PINGROUP(pbb6,                 VGP6,         DISPLAYA,     DISPLAYB,     SDMMC4,       SDMMC4,       0x32a4, N, N),
3643	PINGROUP(pbb7,                 I2S4,         RSVD2,        RSVD3,        SDMMC4,       RSVD3,        0x32a8, N, N),
3644	PINGROUP(cam_mclk_pcc0,        VI,           VI_ALT1,      VI_ALT3,      SDMMC4,       SDMMC4,       0x3284, N, N),
3645	PINGROUP(pcc1,                 I2S4,         RSVD2,        RSVD3,        SDMMC4,       RSVD3,        0x3288, N, N),
3646	PINGROUP(pcc2,                 I2S4,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x32ac, N, N),
3647	PINGROUP(sdmmc4_rst_n_pcc3,    VGP6,         RSVD2,        RSVD3,        SDMMC4,       RSVD3,        0x3280, N, Y),
3648	PINGROUP(sdmmc4_clk_pcc4,      INVALID,      NAND,         GMI,          SDMMC4,       SDMMC4,       0x3258, N, Y),
3649	PINGROUP(clk2_req_pcc5,        DAP,          RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x306c, N, N),
3650	PINGROUP(pex_l2_rst_n_pcc6,    PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33d8, N, N),
3651	PINGROUP(pex_l2_clkreq_n_pcc7, PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33dc, N, N),
3652	PINGROUP(pex_l0_prsnt_n_pdd0,  PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33b8, N, N),
3653	PINGROUP(pex_l0_rst_n_pdd1,    PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33bc, N, N),
3654	PINGROUP(pex_l0_clkreq_n_pdd2, PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33c0, N, N),
3655	PINGROUP(pex_wake_n_pdd3,      PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33c4, N, N),
3656	PINGROUP(pex_l1_prsnt_n_pdd4,  PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33c8, N, N),
3657	PINGROUP(pex_l1_rst_n_pdd5,    PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33cc, N, N),
3658	PINGROUP(pex_l1_clkreq_n_pdd6, PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33d0, N, N),
3659	PINGROUP(pex_l2_prsnt_n_pdd7,  PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33d4, N, N),
3660	PINGROUP(clk3_out_pee0,        EXTPERIPH3,   RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x31b8, N, N),
3661	PINGROUP(clk3_req_pee1,        DEV3,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x31bc, N, N),
3662	PINGROUP(clk1_req_pee2,        DAP,          HDA,          RSVD3,        RSVD4,        RSVD4,        0x3348, N, N),
3663	PINGROUP(hdmi_cec_pee3,        CEC,          RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x33e0, Y, N),
3664	PINGROUP(clk_32k_in,           CLK_32K_IN,   RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3330, N, N),
3665	PINGROUP(core_pwr_req,         CORE_PWR_REQ, RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3324, N, N),
3666	PINGROUP(cpu_pwr_req,          CPU_PWR_REQ,  RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3328, N, N),
3667	PINGROUP(owr,                  OWR,          CEC,          RSVD3,        RSVD4,        RSVD4,        0x3334, N, N),
3668	PINGROUP(pwr_int_n,            PWR_INT_N,    RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x332c, N, N),
3669	/* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
3670	DRV_PINGROUP(ao1,   0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3671	DRV_PINGROUP(ao2,   0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3672	DRV_PINGROUP(at1,   0x870,  2,  3,  4,  14,  5,  19,  5,  24,  2,  28,  2),
3673	DRV_PINGROUP(at2,   0x874,  2,  3,  4,  14,  5,  19,  5,  24,  2,  28,  2),
3674	DRV_PINGROUP(at3,   0x878,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3675	DRV_PINGROUP(at4,   0x87c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3676	DRV_PINGROUP(at5,   0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3677	DRV_PINGROUP(cdev1, 0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3678	DRV_PINGROUP(cdev2, 0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3679	DRV_PINGROUP(cec,   0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3680	DRV_PINGROUP(crt,   0x8f8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3681	DRV_PINGROUP(csus,  0x88c, -1, -1, -1,  12,  5,  19,  5,  24,  4,  28,  4),
3682	DRV_PINGROUP(dap1,  0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3683	DRV_PINGROUP(dap2,  0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3684	DRV_PINGROUP(dap3,  0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3685	DRV_PINGROUP(dap4,  0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3686	DRV_PINGROUP(dbg,   0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3687	DRV_PINGROUP(ddc,   0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3688	DRV_PINGROUP(dev3,  0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3689	DRV_PINGROUP(gma,   0x900, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
3690	DRV_PINGROUP(gmb,   0x904, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
3691	DRV_PINGROUP(gmc,   0x908, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
3692	DRV_PINGROUP(gmd,   0x90c, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
3693	DRV_PINGROUP(gme,   0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3694	DRV_PINGROUP(gmf,   0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3695	DRV_PINGROUP(gmg,   0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3696	DRV_PINGROUP(gmh,   0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3697	DRV_PINGROUP(gpv,   0x928,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3698	DRV_PINGROUP(lcd1,  0x8a4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3699	DRV_PINGROUP(lcd2,  0x8a8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3700	DRV_PINGROUP(owr,   0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3701	DRV_PINGROUP(sdio1, 0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
3702	DRV_PINGROUP(sdio2, 0x8ac,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
3703	DRV_PINGROUP(sdio3, 0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
3704	DRV_PINGROUP(spi,   0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3705	DRV_PINGROUP(uaa,   0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3706	DRV_PINGROUP(uab,   0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3707	DRV_PINGROUP(uart2, 0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3708	DRV_PINGROUP(uart3, 0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3709	DRV_PINGROUP(uda,   0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3710	DRV_PINGROUP(vi1,   0x8c8, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
3711};
3712
3713static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
3714	.ngpios = NUM_GPIOS,
3715	.pins = tegra30_pins,
3716	.npins = ARRAY_SIZE(tegra30_pins),
3717	.functions = tegra30_functions,
3718	.nfunctions = ARRAY_SIZE(tegra30_functions),
3719	.groups = tegra30_groups,
3720	.ngroups = ARRAY_SIZE(tegra30_groups),
3721};
3722
3723void __devinit tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc)
3724{
3725	*soc = &tegra30_pinctrl;
3726}
3727