aic7xxx.h revision 2a40342e0e72a2ba89aaa9e6c9a9eceb04741b24
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#79 $ 41 * 42 * $FreeBSD$ 43 */ 44 45#ifndef _AIC7XXX_H_ 46#define _AIC7XXX_H_ 47 48/* Register Definitions */ 49#include "aic7xxx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahc_platform_data; 53struct scb_platform_data; 54struct seeprom_descriptor; 55 56/****************************** Useful Macros *********************************/ 57#ifndef MAX 58#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 59#endif 60 61#ifndef MIN 62#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 63#endif 64 65#ifndef TRUE 66#define TRUE 1 67#endif 68#ifndef FALSE 69#define FALSE 0 70#endif 71 72#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 73 74#define ALL_CHANNELS '\0' 75#define ALL_TARGETS_MASK 0xFFFF 76#define INITIATOR_WILDCARD (~0) 77 78#define SCSIID_TARGET(ahc, scsiid) \ 79 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 80 >> TID_SHIFT) 81#define SCSIID_OUR_ID(scsiid) \ 82 ((scsiid) & OID) 83#define SCSIID_CHANNEL(ahc, scsiid) \ 84 ((((ahc)->features & AHC_TWIN) != 0) \ 85 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 86 : 'A') 87#define SCB_IS_SCSIBUS_B(ahc, scb) \ 88 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 89#define SCB_GET_OUR_ID(scb) \ 90 SCSIID_OUR_ID((scb)->hscb->scsiid) 91#define SCB_GET_TARGET(ahc, scb) \ 92 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 93#define SCB_GET_CHANNEL(ahc, scb) \ 94 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 95#define SCB_GET_LUN(scb) \ 96 ((scb)->hscb->lun & LID) 97#define SCB_GET_TARGET_OFFSET(ahc, scb) \ 98 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 99#define SCB_GET_TARGET_MASK(ahc, scb) \ 100 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 101#ifdef AHC_DEBUG 102#define SCB_IS_SILENT(scb) \ 103 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \ 104 && (((scb)->flags & SCB_SILENT) != 0)) 105#else 106#define SCB_IS_SILENT(scb) \ 107 (((scb)->flags & SCB_SILENT) != 0) 108#endif 109#define TCL_TARGET_OFFSET(tcl) \ 110 ((((tcl) >> 4) & TID) >> 4) 111#define TCL_LUN(tcl) \ 112 (tcl & (AHC_NUM_LUNS - 1)) 113#define BUILD_TCL(scsiid, lun) \ 114 ((lun) | (((scsiid) & TID) << 4)) 115 116#ifndef AHC_TARGET_MODE 117#undef AHC_TMODE_ENABLE 118#define AHC_TMODE_ENABLE 0 119#endif 120 121/**************************** Driver Constants ********************************/ 122/* 123 * The maximum number of supported targets. 124 */ 125#define AHC_NUM_TARGETS 16 126 127/* 128 * The maximum number of supported luns. 129 * The identify message only supports 64 luns in SPI3. 130 * You can have 2^64 luns when information unit transfers are enabled, 131 * but it is doubtful this driver will ever support IUTs. 132 */ 133#define AHC_NUM_LUNS 64 134 135/* 136 * The maximum transfer per S/G segment. 137 */ 138#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 139 140/* 141 * The maximum amount of SCB storage in hardware on a controller. 142 * This value represents an upper bound. Controllers vary in the number 143 * they actually support. 144 */ 145#define AHC_SCB_MAX 255 146 147/* 148 * The maximum number of concurrent transactions supported per driver instance. 149 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 150 * the space for SCBs on the host adapter varies by model, the driver will 151 * page the SCBs between host and controller memory as needed. We are limited 152 * to 253 because: 153 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 154 * 2) We reserve one value, 255, to represent the invalid element. 155 * 3) Our input queue scheme requires one SCB to always be reserved 156 * in advance of queuing any SCBs. This takes us down to 254. 157 * 4) To handle our output queue correctly on machines that only 158 * support 32bit stores, we must clear the array 4 bytes at a 159 * time. To avoid colliding with a DMA write from the sequencer, 160 * we must be sure that 4 slots are empty when we write to clear 161 * the queue. This reduces us to 253 SCBs: 1 that just completed 162 * and the known three additional empty slots in the queue that 163 * precede it. 164 */ 165#define AHC_MAX_QUEUE 253 166 167/* 168 * The maximum amount of SCB storage we allocate in host memory. This 169 * number should reflect the 1 additional SCB we require to handle our 170 * qinfifo mechanism. 171 */ 172#define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 173 174/* 175 * Ring Buffer of incoming target commands. 176 * We allocate 256 to simplify the logic in the sequencer 177 * by using the natural wrap point of an 8bit counter. 178 */ 179#define AHC_TMODE_CMDS 256 180 181/* Reset line assertion time in us */ 182#define AHC_BUSRESET_DELAY 25 183 184/******************* Chip Characteristics/Operating Settings *****************/ 185/* 186 * Chip Type 187 * The chip order is from least sophisticated to most sophisticated. 188 */ 189typedef enum { 190 AHC_NONE = 0x0000, 191 AHC_CHIPID_MASK = 0x00FF, 192 AHC_AIC7770 = 0x0001, 193 AHC_AIC7850 = 0x0002, 194 AHC_AIC7855 = 0x0003, 195 AHC_AIC7859 = 0x0004, 196 AHC_AIC7860 = 0x0005, 197 AHC_AIC7870 = 0x0006, 198 AHC_AIC7880 = 0x0007, 199 AHC_AIC7895 = 0x0008, 200 AHC_AIC7895C = 0x0009, 201 AHC_AIC7890 = 0x000a, 202 AHC_AIC7896 = 0x000b, 203 AHC_AIC7892 = 0x000c, 204 AHC_AIC7899 = 0x000d, 205 AHC_VL = 0x0100, /* Bus type VL */ 206 AHC_EISA = 0x0200, /* Bus type EISA */ 207 AHC_PCI = 0x0400, /* Bus type PCI */ 208 AHC_BUS_MASK = 0x0F00 209} ahc_chip; 210 211/* 212 * Features available in each chip type. 213 */ 214typedef enum { 215 AHC_FENONE = 0x00000, 216 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 217 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 218 AHC_WIDE = 0x00004, /* Wide Channel */ 219 AHC_TWIN = 0x00008, /* Twin Channel */ 220 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 221 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 222 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 223 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 224 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 225 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 226 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 227 AHC_DT = 0x00800, /* Double Transition transfers */ 228 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 229 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 230 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 231 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 232 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 233 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 234 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 235 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 236 AHC_AIC7770_FE = AHC_FENONE, 237 /* 238 * The real 7850 does not support Ultra modes, but there are 239 * several cards that use the generic 7850 PCI ID even though 240 * they are using an Ultra capable chip (7859/7860). We start 241 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 242 * register to determine if the capability is really present. 243 */ 244 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 245 AHC_AIC7860_FE = AHC_AIC7850_FE, 246 AHC_AIC7870_FE = AHC_TARGETMODE, 247 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 248 /* 249 * Although we have space for both the initiator and 250 * target roles on ULTRA2 chips, we currently disable 251 * the initiator role to allow multi-scsi-id target mode 252 * configurations. We can only respond on the same SCSI 253 * ID as our initiator role if we allow initiator operation. 254 * At some point, we should add a configuration knob to 255 * allow both roles to be loaded. 256 */ 257 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 258 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 259 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 260 |AHC_TARGETMODE, 261 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 262 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 263 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 264 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 265 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 266 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 267} ahc_feature; 268 269/* 270 * Bugs in the silicon that we work around in software. 271 */ 272typedef enum { 273 AHC_BUGNONE = 0x00, 274 /* 275 * On all chips prior to the U2 product line, 276 * the WIDEODD S/G segment feature does not 277 * work during scsi->HostBus transfers. 278 */ 279 AHC_TMODE_WIDEODD_BUG = 0x01, 280 /* 281 * On the aic7890/91 Rev 0 chips, the autoflush 282 * feature does not work. A manual flush of 283 * the DMA FIFO is required. 284 */ 285 AHC_AUTOFLUSH_BUG = 0x02, 286 /* 287 * On many chips, cacheline streaming does not work. 288 */ 289 AHC_CACHETHEN_BUG = 0x04, 290 /* 291 * On the aic7896/97 chips, cacheline 292 * streaming must be enabled. 293 */ 294 AHC_CACHETHEN_DIS_BUG = 0x08, 295 /* 296 * PCI 2.1 Retry failure on non-empty data fifo. 297 */ 298 AHC_PCI_2_1_RETRY_BUG = 0x10, 299 /* 300 * Controller does not handle cacheline residuals 301 * properly on S/G segments if PCI MWI instructions 302 * are allowed. 303 */ 304 AHC_PCI_MWI_BUG = 0x20, 305 /* 306 * An SCB upload using the SCB channel's 307 * auto array entry copy feature may 308 * corrupt data. This appears to only 309 * occur on 66MHz systems. 310 */ 311 AHC_SCBCHAN_UPLOAD_BUG = 0x40 312} ahc_bug; 313 314/* 315 * Configuration specific settings. 316 * The driver determines these settings by probing the 317 * chip/controller's configuration. 318 */ 319typedef enum { 320 AHC_FNONE = 0x000, 321 AHC_PRIMARY_CHANNEL = 0x003, /* 322 * The channel that should 323 * be probed first. 324 */ 325 AHC_USEDEFAULTS = 0x004, /* 326 * For cards without an seeprom 327 * or a BIOS to initialize the chip's 328 * SRAM, we use the default target 329 * settings. 330 */ 331 AHC_SEQUENCER_DEBUG = 0x008, 332 AHC_SHARED_SRAM = 0x010, 333 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */ 334 AHC_RESET_BUS_A = 0x040, 335 AHC_RESET_BUS_B = 0x080, 336 AHC_EXTENDED_TRANS_A = 0x100, 337 AHC_EXTENDED_TRANS_B = 0x200, 338 AHC_TERM_ENB_A = 0x400, 339 AHC_TERM_ENB_B = 0x800, 340 AHC_INITIATORROLE = 0x1000, /* 341 * Allow initiator operations on 342 * this controller. 343 */ 344 AHC_TARGETROLE = 0x2000, /* 345 * Allow target operations on this 346 * controller. 347 */ 348 AHC_NEWEEPROM_FMT = 0x4000, 349 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */ 350 AHC_INT50_SPEEDFLEX = 0x20000, /* 351 * Internal 50pin connector 352 * sits behind an aic3860 353 */ 354 AHC_SCB_BTT = 0x40000, /* 355 * The busy targets table is 356 * stored in SCB space rather 357 * than SRAM. 358 */ 359 AHC_BIOS_ENABLED = 0x80000, 360 AHC_ALL_INTERRUPTS = 0x100000, 361 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 362 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 363 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 364 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 365 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */ 366 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */ 367 AHC_DISABLE_PCI_PERR = 0x10000000, 368 AHC_HAS_TERM_LOGIC = 0x20000000 369} ahc_flag; 370 371/************************* Hardware SCB Definition ***************************/ 372 373/* 374 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 375 * consists of a "hardware SCB" mirroring the fields available on the card 376 * and additional information the kernel stores for each transaction. 377 * 378 * To minimize space utilization, a portion of the hardware scb stores 379 * different data during different portions of a SCSI transaction. 380 * As initialized by the host driver for the initiator role, this area 381 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 382 * the cdb has been presented to the target, this area serves to store 383 * residual transfer information and the SCSI status byte. 384 * For the target role, the contents of this area do not change, but 385 * still serve a different purpose than for the initiator role. See 386 * struct target_data for details. 387 */ 388 389/* 390 * Status information embedded in the shared poriton of 391 * an SCB after passing the cdb to the target. The kernel 392 * driver will only read this data for transactions that 393 * complete abnormally (non-zero status byte). 394 */ 395struct status_pkt { 396 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 397 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 398 uint8_t scsi_status; /* Standard SCSI status byte */ 399}; 400 401/* 402 * Target mode version of the shared data SCB segment. 403 */ 404struct target_data { 405 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 406 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 407 uint8_t scsi_status; /* SCSI status to give to initiator */ 408 uint8_t target_phases; /* Bitmap of phases to execute */ 409 uint8_t data_phase; /* Data-In or Data-Out */ 410 uint8_t initiator_tag; /* Initiator's transaction tag */ 411}; 412 413struct hardware_scb { 414/*0*/ union { 415 /* 416 * If the cdb is 12 bytes or less, we embed it directly 417 * in the SCB. For longer cdbs, we embed the address 418 * of the cdb payload as seen by the chip and a DMA 419 * is used to pull it in. 420 */ 421 uint8_t cdb[12]; 422 uint32_t cdb_ptr; 423 struct status_pkt status; 424 struct target_data tdata; 425 } shared_data; 426/* 427 * A word about residuals. 428 * The scb is presented to the sequencer with the dataptr and datacnt 429 * fields initialized to the contents of the first S/G element to 430 * transfer. The sgptr field is initialized to the bus address for 431 * the S/G element that follows the first in the in core S/G array 432 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 433 * S/G entry for this transfer (single S/G element transfer with the 434 * first elements address and length preloaded in the dataptr/datacnt 435 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 436 * The SG_FULL_RESID flag ensures that the residual will be correctly 437 * noted even if no data transfers occur. Once the data phase is entered, 438 * the residual sgptr and datacnt are loaded from the sgptr and the 439 * datacnt fields. After each S/G element's dataptr and length are 440 * loaded into the hardware, the residual sgptr is advanced. After 441 * each S/G element is expired, its datacnt field is checked to see 442 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 443 * residual sg ptr and the transfer is considered complete. If the 444 * sequencer determines that there is a residual in the tranfer, it 445 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 446 * host memory. To sumarize: 447 * 448 * Sequencer: 449 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 450 * or residual_sgptr does not have SG_LIST_NULL set. 451 * 452 * o We are transfering the last segment if residual_datacnt has 453 * the SG_LAST_SEG flag set. 454 * 455 * Host: 456 * o A residual has occurred if a completed scb has the 457 * SG_RESID_VALID flag set. 458 * 459 * o residual_sgptr and sgptr refer to the "next" sg entry 460 * and so may point beyond the last valid sg entry for the 461 * transfer. 462 */ 463/*12*/ uint32_t dataptr; 464/*16*/ uint32_t datacnt; /* 465 * Byte 3 (numbered from 0) of 466 * the datacnt is really the 467 * 4th byte in that data address. 468 */ 469/*20*/ uint32_t sgptr; 470#define SG_PTR_MASK 0xFFFFFFF8 471/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 472/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 473/*26*/ uint8_t lun; 474/*27*/ uint8_t tag; /* 475 * Index into our kernel SCB array. 476 * Also used as the tag for tagged I/O 477 */ 478/*28*/ uint8_t cdb_len; 479/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 480/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 481/*31*/ uint8_t next; /* 482 * Used for threading SCBs in the 483 * "Waiting for Selection" and 484 * "Disconnected SCB" lists down 485 * in the sequencer. 486 */ 487/*32*/ uint8_t cdb32[32]; /* 488 * CDB storage for cdbs of size 489 * 13->32. We store them here 490 * because hardware scbs are 491 * allocated from DMA safe 492 * memory so we are guaranteed 493 * the controller can access 494 * this data. 495 */ 496}; 497 498/************************ Kernel SCB Definitions ******************************/ 499/* 500 * Some fields of the SCB are OS dependent. Here we collect the 501 * definitions for elements that all OS platforms need to include 502 * in there SCB definition. 503 */ 504 505/* 506 * Definition of a scatter/gather element as transfered to the controller. 507 * The aic7xxx chips only support a 24bit length. We use the top byte of 508 * the length to store additional address bits and a flag to indicate 509 * that a given segment terminates the transfer. This gives us an 510 * addressable range of 512GB on machines with 64bit PCI or with chips 511 * that can support dual address cycles on 32bit PCI busses. 512 */ 513struct ahc_dma_seg { 514 uint32_t addr; 515 uint32_t len; 516#define AHC_DMA_LAST_SEG 0x80000000 517#define AHC_SG_HIGH_ADDR_MASK 0x7F000000 518#define AHC_SG_LEN_MASK 0x00FFFFFF 519}; 520 521struct sg_map_node { 522 bus_dmamap_t sg_dmamap; 523 dma_addr_t sg_physaddr; 524 struct ahc_dma_seg* sg_vaddr; 525 SLIST_ENTRY(sg_map_node) links; 526}; 527 528/* 529 * The current state of this SCB. 530 */ 531typedef enum { 532 SCB_FREE = 0x0000, 533 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 534 * Another device was active 535 * during the first timeout for 536 * this SCB so we gave ourselves 537 * an additional timeout period 538 * in case it was hogging the 539 * bus. 540 */ 541 SCB_DEVICE_RESET = 0x0004, 542 SCB_SENSE = 0x0008, 543 SCB_CDB32_PTR = 0x0010, 544 SCB_RECOVERY_SCB = 0x0020, 545 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 546 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 547 SCB_ABORT = 0x0100, 548 SCB_UNTAGGEDQ = 0x0200, 549 SCB_ACTIVE = 0x0400, 550 SCB_TARGET_IMMEDIATE = 0x0800, 551 SCB_TRANSMISSION_ERROR = 0x1000,/* 552 * We detected a parity or CRC 553 * error that has effected the 554 * payload of the command. This 555 * flag is checked when normal 556 * status is returned to catch 557 * the case of a target not 558 * responding to our attempt 559 * to report the error. 560 */ 561 SCB_TARGET_SCB = 0x2000, 562 SCB_SILENT = 0x4000 /* 563 * Be quiet about transmission type 564 * errors. They are expected and we 565 * don't want to upset the user. This 566 * flag is typically used during DV. 567 */ 568} scb_flag; 569 570struct scb { 571 struct hardware_scb *hscb; 572 union { 573 SLIST_ENTRY(scb) sle; 574 TAILQ_ENTRY(scb) tqe; 575 } links; 576 LIST_ENTRY(scb) pending_links; 577 ahc_io_ctx_t io_ctx; 578 struct ahc_softc *ahc_softc; 579 scb_flag flags; 580#ifndef __linux__ 581 bus_dmamap_t dmamap; 582#endif 583 struct scb_platform_data *platform_data; 584 struct sg_map_node *sg_map; 585 struct ahc_dma_seg *sg_list; 586 dma_addr_t sg_list_phys; 587 u_int sg_count;/* How full ahc_dma_seg is */ 588}; 589 590struct scb_data { 591 SLIST_HEAD(, scb) free_scbs; /* 592 * Pool of SCBs ready to be assigned 593 * commands to execute. 594 */ 595 struct scb *scbindex[256]; /* 596 * Mapping from tag to SCB. 597 * As tag identifiers are an 598 * 8bit value, we provide space 599 * for all possible tag values. 600 * Any lookups to entries at or 601 * above AHC_SCB_MAX_ALLOC will 602 * always fail. 603 */ 604 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 605 struct scb *scbarray; /* Array of kernel SCBs */ 606 struct scsi_sense_data *sense; /* Per SCB sense data */ 607 608 /* 609 * "Bus" addresses of our data structures. 610 */ 611 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 612 bus_dmamap_t hscb_dmamap; 613 dma_addr_t hscb_busaddr; 614 bus_dma_tag_t sense_dmat; 615 bus_dmamap_t sense_dmamap; 616 dma_addr_t sense_busaddr; 617 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 618 SLIST_HEAD(, sg_map_node) sg_maps; 619 uint8_t numscbs; 620 uint8_t maxhscbs; /* Number of SCBs on the card */ 621 uint8_t init_level; /* 622 * How far we've initialized 623 * this structure. 624 */ 625}; 626 627/************************ Target Mode Definitions *****************************/ 628 629/* 630 * Connection desciptor for select-in requests in target mode. 631 */ 632struct target_cmd { 633 uint8_t scsiid; /* Our ID and the initiator's ID */ 634 uint8_t identify; /* Identify message */ 635 uint8_t bytes[22]; /* 636 * Bytes contains any additional message 637 * bytes terminated by 0xFF. The remainder 638 * is the cdb to execute. 639 */ 640 uint8_t cmd_valid; /* 641 * When a command is complete, the firmware 642 * will set cmd_valid to all bits set. 643 * After the host has seen the command, 644 * the bits are cleared. This allows us 645 * to just peek at host memory to determine 646 * if more work is complete. cmd_valid is on 647 * an 8 byte boundary to simplify setting 648 * it on aic7880 hardware which only has 649 * limited direct access to the DMA FIFO. 650 */ 651 uint8_t pad[7]; 652}; 653 654/* 655 * Number of events we can buffer up if we run out 656 * of immediate notify ccbs. 657 */ 658#define AHC_TMODE_EVENT_BUFFER_SIZE 8 659struct ahc_tmode_event { 660 uint8_t initiator_id; 661 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 662#define EVENT_TYPE_BUS_RESET 0xFF 663 uint8_t event_arg; 664}; 665 666/* 667 * Per enabled lun target mode state. 668 * As this state is directly influenced by the host OS'es target mode 669 * environment, we let the OS module define it. Forward declare the 670 * structure here so we can store arrays of them, etc. in OS neutral 671 * data structures. 672 */ 673#ifdef AHC_TARGET_MODE 674struct ahc_tmode_lstate { 675 struct cam_path *path; 676 struct ccb_hdr_slist accept_tios; 677 struct ccb_hdr_slist immed_notifies; 678 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 679 uint8_t event_r_idx; 680 uint8_t event_w_idx; 681}; 682#else 683struct ahc_tmode_lstate; 684#endif 685 686/******************** Transfer Negotiation Datastructures *********************/ 687#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 688#define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 689#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 690#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 691 692#define AHC_WIDTH_UNKNOWN 0xFF 693#define AHC_PERIOD_UNKNOWN 0xFF 694#define AHC_OFFSET_UNKNOWN 0xFF 695#define AHC_PPR_OPTS_UNKNOWN 0xFF 696 697/* 698 * Transfer Negotiation Information. 699 */ 700struct ahc_transinfo { 701 uint8_t protocol_version; /* SCSI Revision level */ 702 uint8_t transport_version; /* SPI Revision level */ 703 uint8_t width; /* Bus width */ 704 uint8_t period; /* Sync rate factor */ 705 uint8_t offset; /* Sync offset */ 706 uint8_t ppr_options; /* Parallel Protocol Request options */ 707}; 708 709/* 710 * Per-initiator current, goal and user transfer negotiation information. */ 711struct ahc_initiator_tinfo { 712 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 713 struct ahc_transinfo curr; 714 struct ahc_transinfo goal; 715 struct ahc_transinfo user; 716}; 717 718/* 719 * Per enabled target ID state. 720 * Pointers to lun target state as well as sync/wide negotiation information 721 * for each initiator<->target mapping. For the initiator role we pretend 722 * that we are the target and the targets are the initiators since the 723 * negotiation is the same regardless of role. 724 */ 725struct ahc_tmode_tstate { 726 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 727 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 728 729 /* 730 * Per initiator state bitmasks. 731 */ 732 uint16_t auto_negotiate;/* Auto Negotiation Required */ 733 uint16_t ultraenb; /* Using ultra sync rate */ 734 uint16_t discenable; /* Disconnection allowed */ 735 uint16_t tagenable; /* Tagged Queuing allowed */ 736}; 737 738/* 739 * Data structure for our table of allowed synchronous transfer rates. 740 */ 741struct ahc_syncrate { 742 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 743 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 744#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 745#define ST_SXFR 0x010 /* Rate Single Transition Only */ 746#define DT_SXFR 0x040 /* Rate Double Transition Only */ 747 uint8_t period; /* Period to send to SCSI target */ 748 char *rate; 749}; 750 751/* Safe and valid period for async negotiations. */ 752#define AHC_ASYNC_XFER_PERIOD 0x45 753#define AHC_ULTRA2_XFER_PERIOD 0x0a 754 755/* 756 * Indexes into our table of syncronous transfer rates. 757 */ 758#define AHC_SYNCRATE_DT 0 759#define AHC_SYNCRATE_ULTRA2 1 760#define AHC_SYNCRATE_ULTRA 3 761#define AHC_SYNCRATE_FAST 6 762#define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT 763#define AHC_SYNCRATE_MIN 13 764 765/***************************** Lookup Tables **********************************/ 766/* 767 * Phase -> name and message out response 768 * to parity errors in each phase table. 769 */ 770struct ahc_phase_table_entry { 771 uint8_t phase; 772 uint8_t mesg_out; /* Message response to parity errors */ 773 char *phasemsg; 774}; 775 776/************************** Serial EEPROM Format ******************************/ 777 778struct seeprom_config { 779/* 780 * Per SCSI ID Configuration Flags 781 */ 782 uint16_t device_flags[16]; /* words 0-15 */ 783#define CFXFER 0x0007 /* synchronous transfer rate */ 784#define CFSYNCH 0x0008 /* enable synchronous transfer */ 785#define CFDISC 0x0010 /* enable disconnection */ 786#define CFWIDEB 0x0020 /* wide bus device */ 787#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 788#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 789#define CFSTART 0x0100 /* send start unit SCSI command */ 790#define CFINCBIOS 0x0200 /* include in BIOS scan */ 791#define CFRNFOUND 0x0400 /* report even if not found */ 792#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 793#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 794#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 795 796/* 797 * BIOS Control Bits 798 */ 799 uint16_t bios_control; /* word 16 */ 800#define CFSUPREM 0x0001 /* support all removeable drives */ 801#define CFSUPREMB 0x0002 /* support removeable boot drives */ 802#define CFBIOSEN 0x0004 /* BIOS enabled */ 803#define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 804#define CFSM2DRV 0x0010 /* support more than two drives */ 805#define CFSTPWLEVEL 0x0010 /* Termination level control */ 806#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 807#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 808#define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 809#define CFEXTEND 0x0080 /* extended translation enabled */ 810#define CFSCAMEN 0x0100 /* SCAM enable */ 811#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 812#define CFMSG_VERBOSE 0x0000 813#define CFMSG_SILENT 0x0200 814#define CFMSG_DIAG 0x0400 815#define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 816/* UNUSED 0xff00 */ 817 818/* 819 * Host Adapter Control Bits 820 */ 821 uint16_t adapter_control; /* word 17 */ 822#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 823#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 824#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 825#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 826#define CFSTERM 0x0004 /* SCSI low byte termination */ 827#define CFWSTERM 0x0008 /* SCSI high byte termination */ 828#define CFSPARITY 0x0010 /* SCSI parity */ 829#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 830#define CFMULTILUN 0x0020 831#define CFRESETB 0x0040 /* reset SCSI bus at boot */ 832#define CFCLUSTERENB 0x0080 /* Cluster Enable */ 833#define CFBOOTCHAN 0x0300 /* probe this channel first */ 834#define CFBOOTCHANSHIFT 8 835#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 836#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 837#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 838#define CFENABLEDV 0x4000 /* Perform Domain Validation*/ 839 840/* 841 * Bus Release Time, Host Adapter ID 842 */ 843 uint16_t brtime_id; /* word 18 */ 844#define CFSCSIID 0x000f /* host adapter SCSI ID */ 845/* UNUSED 0x00f0 */ 846#define CFBRTIME 0xff00 /* bus release time */ 847 848/* 849 * Maximum targets 850 */ 851 uint16_t max_targets; /* word 19 */ 852#define CFMAXTARG 0x00ff /* maximum targets */ 853#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 854#define CFBOOTID 0xf000 /* Target to boot from */ 855 uint16_t res_1[10]; /* words 20-29 */ 856 uint16_t signature; /* Signature == 0x250 */ 857#define CFSIGNATURE 0x250 858#define CFSIGNATURE2 0x300 859 uint16_t checksum; /* word 31 */ 860}; 861 862/**************************** Message Buffer *********************************/ 863typedef enum { 864 MSG_TYPE_NONE = 0x00, 865 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 866 MSG_TYPE_INITIATOR_MSGIN = 0x02, 867 MSG_TYPE_TARGET_MSGOUT = 0x03, 868 MSG_TYPE_TARGET_MSGIN = 0x04 869} ahc_msg_type; 870 871typedef enum { 872 MSGLOOP_IN_PROG, 873 MSGLOOP_MSGCOMPLETE, 874 MSGLOOP_TERMINATED 875} msg_loop_stat; 876 877/*********************** Software Configuration Structure *********************/ 878TAILQ_HEAD(scb_tailq, scb); 879 880struct ahc_aic7770_softc { 881 /* 882 * Saved register state used for chip_init(). 883 */ 884 uint8_t busspd; 885 uint8_t bustime; 886}; 887 888struct ahc_pci_softc { 889 /* 890 * Saved register state used for chip_init(). 891 */ 892 uint32_t devconfig; 893 uint16_t targcrccnt; 894 uint8_t command; 895 uint8_t csize_lattime; 896 uint8_t optionmode; 897 uint8_t crccontrol1; 898 uint8_t dscommand0; 899 uint8_t dspcistatus; 900 uint8_t scbbaddr; 901 uint8_t dff_thrsh; 902}; 903 904union ahc_bus_softc { 905 struct ahc_aic7770_softc aic7770_softc; 906 struct ahc_pci_softc pci_softc; 907}; 908 909typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 910typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *); 911typedef int (*ahc_bus_suspend_t)(struct ahc_softc *); 912typedef int (*ahc_bus_resume_t)(struct ahc_softc *); 913typedef void ahc_callback_t (void *); 914 915struct ahc_softc { 916 bus_space_tag_t tag; 917 bus_space_handle_t bsh; 918#ifndef __linux__ 919 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 920#endif 921 struct scb_data *scb_data; 922 923 struct scb *next_queued_scb; 924 925 /* 926 * SCBs that have been sent to the controller 927 */ 928 LIST_HEAD(, scb) pending_scbs; 929 930 /* 931 * Counting lock for deferring the release of additional 932 * untagged transactions from the untagged_queues. When 933 * the lock is decremented to 0, all queues in the 934 * untagged_queues array are run. 935 */ 936 u_int untagged_queue_lock; 937 938 /* 939 * Per-target queue of untagged-transactions. The 940 * transaction at the head of the queue is the 941 * currently pending untagged transaction for the 942 * target. The driver only allows a single untagged 943 * transaction per target. 944 */ 945 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 946 947 /* 948 * Bus attachment specific data. 949 */ 950 union ahc_bus_softc bus_softc; 951 952 /* 953 * Platform specific data. 954 */ 955 struct ahc_platform_data *platform_data; 956 957 /* 958 * Platform specific device information. 959 */ 960 ahc_dev_softc_t dev_softc; 961 962 /* 963 * Bus specific device information. 964 */ 965 ahc_bus_intr_t bus_intr; 966 967 /* 968 * Bus specific initialization required 969 * after a chip reset. 970 */ 971 ahc_bus_chip_init_t bus_chip_init; 972 973 /* 974 * Bus specific suspend routine. 975 */ 976 ahc_bus_suspend_t bus_suspend; 977 978 /* 979 * Bus specific resume routine. 980 */ 981 ahc_bus_resume_t bus_resume; 982 983 /* 984 * Target mode related state kept on a per enabled lun basis. 985 * Targets that are not enabled will have null entries. 986 * As an initiator, we keep one target entry for our initiator 987 * ID to store our sync/wide transfer settings. 988 */ 989 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 990 991 /* 992 * The black hole device responsible for handling requests for 993 * disabled luns on enabled targets. 994 */ 995 struct ahc_tmode_lstate *black_hole; 996 997 /* 998 * Device instance currently on the bus awaiting a continue TIO 999 * for a command that was not given the disconnect priveledge. 1000 */ 1001 struct ahc_tmode_lstate *pending_device; 1002 1003 /* 1004 * Card characteristics 1005 */ 1006 ahc_chip chip; 1007 ahc_feature features; 1008 ahc_bug bugs; 1009 ahc_flag flags; 1010 struct seeprom_config *seep_config; 1011 1012 /* Values to store in the SEQCTL register for pause and unpause */ 1013 uint8_t unpause; 1014 uint8_t pause; 1015 1016 /* Command Queues */ 1017 uint8_t qoutfifonext; 1018 uint8_t qinfifonext; 1019 uint8_t *qoutfifo; 1020 uint8_t *qinfifo; 1021 1022 /* Critical Section Data */ 1023 struct cs *critical_sections; 1024 u_int num_critical_sections; 1025 1026 /* Channel Names ('A', 'B', etc.) */ 1027 char channel; 1028 char channel_b; 1029 1030 /* Initiator Bus ID */ 1031 uint8_t our_id; 1032 uint8_t our_id_b; 1033 1034 /* 1035 * PCI error detection. 1036 */ 1037 int unsolicited_ints; 1038 1039 /* 1040 * Target incoming command FIFO. 1041 */ 1042 struct target_cmd *targetcmds; 1043 uint8_t tqinfifonext; 1044 1045 /* 1046 * Cached copy of the sequencer control register. 1047 */ 1048 uint8_t seqctl; 1049 1050 /* 1051 * Incoming and outgoing message handling. 1052 */ 1053 uint8_t send_msg_perror; 1054 ahc_msg_type msg_type; 1055 uint8_t msgout_buf[12];/* Message we are sending */ 1056 uint8_t msgin_buf[12];/* Message we are receiving */ 1057 u_int msgout_len; /* Length of message to send */ 1058 u_int msgout_index; /* Current index in msgout */ 1059 u_int msgin_index; /* Current index in msgin */ 1060 1061 /* 1062 * Mapping information for data structures shared 1063 * between the sequencer and kernel. 1064 */ 1065 bus_dma_tag_t parent_dmat; 1066 bus_dma_tag_t shared_data_dmat; 1067 bus_dmamap_t shared_data_dmamap; 1068 dma_addr_t shared_data_busaddr; 1069 1070 /* 1071 * Bus address of the one byte buffer used to 1072 * work-around a DMA bug for chips <= aic7880 1073 * in target mode. 1074 */ 1075 dma_addr_t dma_bug_buf; 1076 1077 /* Number of enabled target mode device on this card */ 1078 u_int enabled_luns; 1079 1080 /* Initialization level of this data structure */ 1081 u_int init_level; 1082 1083 /* PCI cacheline size. */ 1084 u_int pci_cachesize; 1085 1086 /* 1087 * Count of parity errors we have seen as a target. 1088 * We auto-disable parity error checking after seeing 1089 * AHC_PCI_TARGET_PERR_THRESH number of errors. 1090 */ 1091 u_int pci_target_perr_count; 1092#define AHC_PCI_TARGET_PERR_THRESH 10 1093 1094 /* Maximum number of sequencer instructions supported. */ 1095 u_int instruction_ram_size; 1096 1097 /* Per-Unit descriptive information */ 1098 const char *description; 1099 char *name; 1100 int unit; 1101 1102 /* Selection Timer settings */ 1103 int seltime; 1104 int seltime_b; 1105 1106 uint16_t user_discenable;/* Disconnection allowed */ 1107 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1108}; 1109 1110/************************ Active Device Information ***************************/ 1111typedef enum { 1112 ROLE_UNKNOWN, 1113 ROLE_INITIATOR, 1114 ROLE_TARGET 1115} role_t; 1116 1117struct ahc_devinfo { 1118 int our_scsiid; 1119 int target_offset; 1120 uint16_t target_mask; 1121 u_int target; 1122 u_int lun; 1123 char channel; 1124 role_t role; /* 1125 * Only guaranteed to be correct if not 1126 * in the busfree state. 1127 */ 1128}; 1129 1130/****************************** PCI Structures ********************************/ 1131typedef int (ahc_device_setup_t)(struct ahc_softc *); 1132 1133struct ahc_pci_identity { 1134 uint64_t full_id; 1135 uint64_t id_mask; 1136 char *name; 1137 ahc_device_setup_t *setup; 1138}; 1139extern struct ahc_pci_identity ahc_pci_ident_table[]; 1140extern const u_int ahc_num_pci_devs; 1141 1142/***************************** VL/EISA Declarations ***************************/ 1143struct aic7770_identity { 1144 uint32_t full_id; 1145 uint32_t id_mask; 1146 const char *name; 1147 ahc_device_setup_t *setup; 1148}; 1149extern struct aic7770_identity aic7770_ident_table[]; 1150extern const int ahc_num_aic7770_devs; 1151 1152#define AHC_EISA_SLOT_OFFSET 0xc00 1153#define AHC_EISA_IOSIZE 0x100 1154 1155/*************************** Function Declarations ****************************/ 1156/******************************************************************************/ 1157u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1158void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1159void ahc_busy_tcl(struct ahc_softc *ahc, 1160 u_int tcl, u_int busyid); 1161 1162/***************************** PCI Front End *********************************/ 1163struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); 1164int ahc_pci_config(struct ahc_softc *, 1165 struct ahc_pci_identity *); 1166int ahc_pci_test_register_access(struct ahc_softc *); 1167 1168/*************************** EISA/VL Front End ********************************/ 1169struct aic7770_identity *aic7770_find_device(uint32_t); 1170int aic7770_config(struct ahc_softc *ahc, 1171 struct aic7770_identity *, 1172 u_int port); 1173 1174/************************** SCB and SCB queue management **********************/ 1175int ahc_probe_scbs(struct ahc_softc *); 1176void ahc_run_untagged_queues(struct ahc_softc *ahc); 1177void ahc_run_untagged_queue(struct ahc_softc *ahc, 1178 struct scb_tailq *queue); 1179void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1180 struct scb *scb); 1181int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1182 int target, char channel, int lun, 1183 u_int tag, role_t role); 1184 1185/****************************** Initialization ********************************/ 1186struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1187int ahc_softc_init(struct ahc_softc *); 1188void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1189int ahc_chip_init(struct ahc_softc *ahc); 1190int ahc_init(struct ahc_softc *ahc); 1191void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1192void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1193int ahc_suspend(struct ahc_softc *ahc); 1194int ahc_resume(struct ahc_softc *ahc); 1195void ahc_set_unit(struct ahc_softc *, int); 1196void ahc_set_name(struct ahc_softc *, char *); 1197void ahc_alloc_scbs(struct ahc_softc *ahc); 1198void ahc_free(struct ahc_softc *ahc); 1199int ahc_reset(struct ahc_softc *ahc, int reinit); 1200void ahc_shutdown(void *arg); 1201 1202/*************************** Interrupt Services *******************************/ 1203void ahc_clear_intstat(struct ahc_softc *ahc); 1204void ahc_run_qoutfifo(struct ahc_softc *ahc); 1205#ifdef AHC_TARGET_MODE 1206void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1207#endif 1208void ahc_handle_brkadrint(struct ahc_softc *ahc); 1209void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1210void ahc_handle_scsiint(struct ahc_softc *ahc, 1211 u_int intstat); 1212void ahc_clear_critical_section(struct ahc_softc *ahc); 1213 1214/***************************** Error Recovery *********************************/ 1215typedef enum { 1216 SEARCH_COMPLETE, 1217 SEARCH_COUNT, 1218 SEARCH_REMOVE 1219} ahc_search_action; 1220int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1221 char channel, int lun, u_int tag, 1222 role_t role, uint32_t status, 1223 ahc_search_action action); 1224int ahc_search_untagged_queues(struct ahc_softc *ahc, 1225 ahc_io_ctx_t ctx, 1226 int target, char channel, 1227 int lun, uint32_t status, 1228 ahc_search_action action); 1229int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1230 char channel, int lun, u_int tag, 1231 int stop_on_first, int remove, 1232 int save_state); 1233void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1234int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1235 int initiate_reset); 1236int ahc_abort_scbs(struct ahc_softc *ahc, int target, 1237 char channel, int lun, u_int tag, 1238 role_t role, uint32_t status); 1239void ahc_restart(struct ahc_softc *ahc); 1240void ahc_calc_residual(struct ahc_softc *ahc, 1241 struct scb *scb); 1242/*************************** Utility Functions ********************************/ 1243struct ahc_phase_table_entry* 1244 ahc_lookup_phase_entry(int phase); 1245void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1246 u_int our_id, u_int target, 1247 u_int lun, char channel, 1248 role_t role); 1249/************************** Transfer Negotiation ******************************/ 1250struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1251 u_int *ppr_options, u_int maxsync); 1252u_int ahc_find_period(struct ahc_softc *ahc, 1253 u_int scsirate, u_int maxsync); 1254void ahc_validate_offset(struct ahc_softc *ahc, 1255 struct ahc_initiator_tinfo *tinfo, 1256 struct ahc_syncrate *syncrate, 1257 u_int *offset, int wide, 1258 role_t role); 1259void ahc_validate_width(struct ahc_softc *ahc, 1260 struct ahc_initiator_tinfo *tinfo, 1261 u_int *bus_width, 1262 role_t role); 1263/* 1264 * Negotiation types. These are used to qualify if we should renegotiate 1265 * even if our goal and current transport parameters are identical. 1266 */ 1267typedef enum { 1268 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1269 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1270 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1271} ahc_neg_type; 1272int ahc_update_neg_request(struct ahc_softc*, 1273 struct ahc_devinfo*, 1274 struct ahc_tmode_tstate*, 1275 struct ahc_initiator_tinfo*, 1276 ahc_neg_type); 1277void ahc_set_width(struct ahc_softc *ahc, 1278 struct ahc_devinfo *devinfo, 1279 u_int width, u_int type, int paused); 1280void ahc_set_syncrate(struct ahc_softc *ahc, 1281 struct ahc_devinfo *devinfo, 1282 struct ahc_syncrate *syncrate, 1283 u_int period, u_int offset, 1284 u_int ppr_options, 1285 u_int type, int paused); 1286typedef enum { 1287 AHC_QUEUE_NONE, 1288 AHC_QUEUE_BASIC, 1289 AHC_QUEUE_TAGGED 1290} ahc_queue_alg; 1291 1292void ahc_set_tags(struct ahc_softc *ahc, 1293 struct ahc_devinfo *devinfo, 1294 ahc_queue_alg alg); 1295 1296/**************************** Target Mode *************************************/ 1297#ifdef AHC_TARGET_MODE 1298void ahc_send_lstate_events(struct ahc_softc *, 1299 struct ahc_tmode_lstate *); 1300void ahc_handle_en_lun(struct ahc_softc *ahc, 1301 struct cam_sim *sim, union ccb *ccb); 1302cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1303 struct cam_sim *sim, union ccb *ccb, 1304 struct ahc_tmode_tstate **tstate, 1305 struct ahc_tmode_lstate **lstate, 1306 int notfound_failure); 1307#ifndef AHC_TMODE_ENABLE 1308#define AHC_TMODE_ENABLE 0 1309#endif 1310#endif 1311/******************************* Debug ***************************************/ 1312#ifdef AHC_DEBUG 1313extern uint32_t ahc_debug; 1314#define AHC_SHOW_MISC 0x0001 1315#define AHC_SHOW_SENSE 0x0002 1316#define AHC_DUMP_SEEPROM 0x0004 1317#define AHC_SHOW_TERMCTL 0x0008 1318#define AHC_SHOW_MEMORY 0x0010 1319#define AHC_SHOW_MESSAGES 0x0020 1320#define AHC_SHOW_DV 0x0040 1321#define AHC_SHOW_SELTO 0x0080 1322#define AHC_SHOW_QFULL 0x0200 1323#define AHC_SHOW_QUEUE 0x0400 1324#define AHC_SHOW_TQIN 0x0800 1325#define AHC_SHOW_MASKED_ERRORS 0x1000 1326#define AHC_DEBUG_SEQUENCER 0x2000 1327#endif 1328void ahc_print_scb(struct scb *scb); 1329void ahc_print_devinfo(struct ahc_softc *ahc, 1330 struct ahc_devinfo *dev); 1331void ahc_dump_card_state(struct ahc_softc *ahc); 1332int ahc_print_register(ahc_reg_parse_entry_t *table, 1333 u_int num_entries, 1334 const char *name, 1335 u_int address, 1336 u_int value, 1337 u_int *cur_column, 1338 u_int wrap_point); 1339/******************************* SEEPROM *************************************/ 1340int ahc_acquire_seeprom(struct ahc_softc *ahc, 1341 struct seeprom_descriptor *sd); 1342void ahc_release_seeprom(struct seeprom_descriptor *sd); 1343#endif /* _AIC7XXX_H_ */ 1344