aic7xxx.h revision 6391a11375de5e2bb1eb8481e54619761dc65d9f
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $ 41 * 42 * $FreeBSD$ 43 */ 44 45#ifndef _AIC7XXX_H_ 46#define _AIC7XXX_H_ 47 48/* Register Definitions */ 49#include "aic7xxx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahc_platform_data; 53struct scb_platform_data; 54struct seeprom_descriptor; 55 56/****************************** Useful Macros *********************************/ 57#ifndef MAX 58#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 59#endif 60 61#ifndef MIN 62#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 63#endif 64 65#ifndef TRUE 66#define TRUE 1 67#endif 68#ifndef FALSE 69#define FALSE 0 70#endif 71 72#define ALL_CHANNELS '\0' 73#define ALL_TARGETS_MASK 0xFFFF 74#define INITIATOR_WILDCARD (~0) 75 76#define SCSIID_TARGET(ahc, scsiid) \ 77 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 78 >> TID_SHIFT) 79#define SCSIID_OUR_ID(scsiid) \ 80 ((scsiid) & OID) 81#define SCSIID_CHANNEL(ahc, scsiid) \ 82 ((((ahc)->features & AHC_TWIN) != 0) \ 83 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 84 : 'A') 85#define SCB_IS_SCSIBUS_B(ahc, scb) \ 86 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 87#define SCB_GET_OUR_ID(scb) \ 88 SCSIID_OUR_ID((scb)->hscb->scsiid) 89#define SCB_GET_TARGET(ahc, scb) \ 90 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 91#define SCB_GET_CHANNEL(ahc, scb) \ 92 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 93#define SCB_GET_LUN(scb) \ 94 ((scb)->hscb->lun & LID) 95#define SCB_GET_TARGET_OFFSET(ahc, scb) \ 96 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 97#define SCB_GET_TARGET_MASK(ahc, scb) \ 98 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 99#ifdef AHC_DEBUG 100#define SCB_IS_SILENT(scb) \ 101 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \ 102 && (((scb)->flags & SCB_SILENT) != 0)) 103#else 104#define SCB_IS_SILENT(scb) \ 105 (((scb)->flags & SCB_SILENT) != 0) 106#endif 107#define TCL_TARGET_OFFSET(tcl) \ 108 ((((tcl) >> 4) & TID) >> 4) 109#define TCL_LUN(tcl) \ 110 (tcl & (AHC_NUM_LUNS - 1)) 111#define BUILD_TCL(scsiid, lun) \ 112 ((lun) | (((scsiid) & TID) << 4)) 113 114#ifndef AHC_TARGET_MODE 115#undef AHC_TMODE_ENABLE 116#define AHC_TMODE_ENABLE 0 117#endif 118 119/**************************** Driver Constants ********************************/ 120/* 121 * The maximum number of supported targets. 122 */ 123#define AHC_NUM_TARGETS 16 124 125/* 126 * The maximum number of supported luns. 127 * The identify message only supports 64 luns in SPI3. 128 * You can have 2^64 luns when information unit transfers are enabled, 129 * but it is doubtful this driver will ever support IUTs. 130 */ 131#define AHC_NUM_LUNS 64 132 133/* 134 * The maximum transfer per S/G segment. 135 */ 136#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 137 138/* 139 * The maximum amount of SCB storage in hardware on a controller. 140 * This value represents an upper bound. Controllers vary in the number 141 * they actually support. 142 */ 143#define AHC_SCB_MAX 255 144 145/* 146 * The maximum number of concurrent transactions supported per driver instance. 147 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 148 * the space for SCBs on the host adapter varies by model, the driver will 149 * page the SCBs between host and controller memory as needed. We are limited 150 * to 253 because: 151 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 152 * 2) We reserve one value, 255, to represent the invalid element. 153 * 3) Our input queue scheme requires one SCB to always be reserved 154 * in advance of queuing any SCBs. This takes us down to 254. 155 * 4) To handle our output queue correctly on machines that only 156 * support 32bit stores, we must clear the array 4 bytes at a 157 * time. To avoid colliding with a DMA write from the sequencer, 158 * we must be sure that 4 slots are empty when we write to clear 159 * the queue. This reduces us to 253 SCBs: 1 that just completed 160 * and the known three additional empty slots in the queue that 161 * precede it. 162 */ 163#define AHC_MAX_QUEUE 253 164 165/* 166 * The maximum amount of SCB storage we allocate in host memory. This 167 * number should reflect the 1 additional SCB we require to handle our 168 * qinfifo mechanism. 169 */ 170#define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 171 172/* 173 * Ring Buffer of incoming target commands. 174 * We allocate 256 to simplify the logic in the sequencer 175 * by using the natural wrap point of an 8bit counter. 176 */ 177#define AHC_TMODE_CMDS 256 178 179/* Reset line assertion time in us */ 180#define AHC_BUSRESET_DELAY 25 181 182/******************* Chip Characteristics/Operating Settings *****************/ 183/* 184 * Chip Type 185 * The chip order is from least sophisticated to most sophisticated. 186 */ 187typedef enum { 188 AHC_NONE = 0x0000, 189 AHC_CHIPID_MASK = 0x00FF, 190 AHC_AIC7770 = 0x0001, 191 AHC_AIC7850 = 0x0002, 192 AHC_AIC7855 = 0x0003, 193 AHC_AIC7859 = 0x0004, 194 AHC_AIC7860 = 0x0005, 195 AHC_AIC7870 = 0x0006, 196 AHC_AIC7880 = 0x0007, 197 AHC_AIC7895 = 0x0008, 198 AHC_AIC7895C = 0x0009, 199 AHC_AIC7890 = 0x000a, 200 AHC_AIC7896 = 0x000b, 201 AHC_AIC7892 = 0x000c, 202 AHC_AIC7899 = 0x000d, 203 AHC_VL = 0x0100, /* Bus type VL */ 204 AHC_EISA = 0x0200, /* Bus type EISA */ 205 AHC_PCI = 0x0400, /* Bus type PCI */ 206 AHC_BUS_MASK = 0x0F00 207} ahc_chip; 208 209/* 210 * Features available in each chip type. 211 */ 212typedef enum { 213 AHC_FENONE = 0x00000, 214 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 215 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 216 AHC_WIDE = 0x00004, /* Wide Channel */ 217 AHC_TWIN = 0x00008, /* Twin Channel */ 218 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 219 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 220 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 221 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 222 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 223 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 224 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 225 AHC_DT = 0x00800, /* Double Transition transfers */ 226 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 227 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 228 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 229 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 230 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 231 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 232 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 233 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 234 AHC_AIC7770_FE = AHC_FENONE, 235 /* 236 * The real 7850 does not support Ultra modes, but there are 237 * several cards that use the generic 7850 PCI ID even though 238 * they are using an Ultra capable chip (7859/7860). We start 239 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 240 * register to determine if the capability is really present. 241 */ 242 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 243 AHC_AIC7860_FE = AHC_AIC7850_FE, 244 AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE, 245 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 246 /* 247 * Although we have space for both the initiator and 248 * target roles on ULTRA2 chips, we currently disable 249 * the initiator role to allow multi-scsi-id target mode 250 * configurations. We can only respond on the same SCSI 251 * ID as our initiator role if we allow initiator operation. 252 * At some point, we should add a configuration knob to 253 * allow both roles to be loaded. 254 */ 255 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 256 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 257 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 258 |AHC_TARGETMODE, 259 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 260 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 261 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 262 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 263 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 264 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 265} ahc_feature; 266 267/* 268 * Bugs in the silicon that we work around in software. 269 */ 270typedef enum { 271 AHC_BUGNONE = 0x00, 272 /* 273 * On all chips prior to the U2 product line, 274 * the WIDEODD S/G segment feature does not 275 * work during scsi->HostBus transfers. 276 */ 277 AHC_TMODE_WIDEODD_BUG = 0x01, 278 /* 279 * On the aic7890/91 Rev 0 chips, the autoflush 280 * feature does not work. A manual flush of 281 * the DMA FIFO is required. 282 */ 283 AHC_AUTOFLUSH_BUG = 0x02, 284 /* 285 * On many chips, cacheline streaming does not work. 286 */ 287 AHC_CACHETHEN_BUG = 0x04, 288 /* 289 * On the aic7896/97 chips, cacheline 290 * streaming must be enabled. 291 */ 292 AHC_CACHETHEN_DIS_BUG = 0x08, 293 /* 294 * PCI 2.1 Retry failure on non-empty data fifo. 295 */ 296 AHC_PCI_2_1_RETRY_BUG = 0x10, 297 /* 298 * Controller does not handle cacheline residuals 299 * properly on S/G segments if PCI MWI instructions 300 * are allowed. 301 */ 302 AHC_PCI_MWI_BUG = 0x20, 303 /* 304 * An SCB upload using the SCB channel's 305 * auto array entry copy feature may 306 * corrupt data. This appears to only 307 * occur on 66MHz systems. 308 */ 309 AHC_SCBCHAN_UPLOAD_BUG = 0x40 310} ahc_bug; 311 312/* 313 * Configuration specific settings. 314 * The driver determines these settings by probing the 315 * chip/controller's configuration. 316 */ 317typedef enum { 318 AHC_FNONE = 0x000, 319 AHC_PRIMARY_CHANNEL = 0x003, /* 320 * The channel that should 321 * be probed first. 322 */ 323 AHC_USEDEFAULTS = 0x004, /* 324 * For cards without an seeprom 325 * or a BIOS to initialize the chip's 326 * SRAM, we use the default target 327 * settings. 328 */ 329 AHC_SEQUENCER_DEBUG = 0x008, 330 AHC_SHARED_SRAM = 0x010, 331 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */ 332 AHC_RESET_BUS_A = 0x040, 333 AHC_RESET_BUS_B = 0x080, 334 AHC_EXTENDED_TRANS_A = 0x100, 335 AHC_EXTENDED_TRANS_B = 0x200, 336 AHC_TERM_ENB_A = 0x400, 337 AHC_TERM_ENB_B = 0x800, 338 AHC_INITIATORROLE = 0x1000, /* 339 * Allow initiator operations on 340 * this controller. 341 */ 342 AHC_TARGETROLE = 0x2000, /* 343 * Allow target operations on this 344 * controller. 345 */ 346 AHC_NEWEEPROM_FMT = 0x4000, 347 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */ 348 AHC_INT50_SPEEDFLEX = 0x20000, /* 349 * Internal 50pin connector 350 * sits behind an aic3860 351 */ 352 AHC_SCB_BTT = 0x40000, /* 353 * The busy targets table is 354 * stored in SCB space rather 355 * than SRAM. 356 */ 357 AHC_BIOS_ENABLED = 0x80000, 358 AHC_ALL_INTERRUPTS = 0x100000, 359 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 360 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 361 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 362 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 363 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */ 364 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */ 365 AHC_DISABLE_PCI_PERR = 0x10000000, 366 AHC_HAS_TERM_LOGIC = 0x20000000 367} ahc_flag; 368 369/************************* Hardware SCB Definition ***************************/ 370 371/* 372 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 373 * consists of a "hardware SCB" mirroring the fields available on the card 374 * and additional information the kernel stores for each transaction. 375 * 376 * To minimize space utilization, a portion of the hardware scb stores 377 * different data during different portions of a SCSI transaction. 378 * As initialized by the host driver for the initiator role, this area 379 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 380 * the cdb has been presented to the target, this area serves to store 381 * residual transfer information and the SCSI status byte. 382 * For the target role, the contents of this area do not change, but 383 * still serve a different purpose than for the initiator role. See 384 * struct target_data for details. 385 */ 386 387/* 388 * Status information embedded in the shared poriton of 389 * an SCB after passing the cdb to the target. The kernel 390 * driver will only read this data for transactions that 391 * complete abnormally (non-zero status byte). 392 */ 393struct status_pkt { 394 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 395 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 396 uint8_t scsi_status; /* Standard SCSI status byte */ 397}; 398 399/* 400 * Target mode version of the shared data SCB segment. 401 */ 402struct target_data { 403 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 404 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 405 uint8_t scsi_status; /* SCSI status to give to initiator */ 406 uint8_t target_phases; /* Bitmap of phases to execute */ 407 uint8_t data_phase; /* Data-In or Data-Out */ 408 uint8_t initiator_tag; /* Initiator's transaction tag */ 409}; 410 411struct hardware_scb { 412/*0*/ union { 413 /* 414 * If the cdb is 12 bytes or less, we embed it directly 415 * in the SCB. For longer cdbs, we embed the address 416 * of the cdb payload as seen by the chip and a DMA 417 * is used to pull it in. 418 */ 419 uint8_t cdb[12]; 420 uint32_t cdb_ptr; 421 struct status_pkt status; 422 struct target_data tdata; 423 } shared_data; 424/* 425 * A word about residuals. 426 * The scb is presented to the sequencer with the dataptr and datacnt 427 * fields initialized to the contents of the first S/G element to 428 * transfer. The sgptr field is initialized to the bus address for 429 * the S/G element that follows the first in the in core S/G array 430 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 431 * S/G entry for this transfer (single S/G element transfer with the 432 * first elements address and length preloaded in the dataptr/datacnt 433 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 434 * The SG_FULL_RESID flag ensures that the residual will be correctly 435 * noted even if no data transfers occur. Once the data phase is entered, 436 * the residual sgptr and datacnt are loaded from the sgptr and the 437 * datacnt fields. After each S/G element's dataptr and length are 438 * loaded into the hardware, the residual sgptr is advanced. After 439 * each S/G element is expired, its datacnt field is checked to see 440 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 441 * residual sg ptr and the transfer is considered complete. If the 442 * sequencer determines that there is a residual in the tranfer, it 443 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 444 * host memory. To sumarize: 445 * 446 * Sequencer: 447 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 448 * or residual_sgptr does not have SG_LIST_NULL set. 449 * 450 * o We are transfering the last segment if residual_datacnt has 451 * the SG_LAST_SEG flag set. 452 * 453 * Host: 454 * o A residual has occurred if a completed scb has the 455 * SG_RESID_VALID flag set. 456 * 457 * o residual_sgptr and sgptr refer to the "next" sg entry 458 * and so may point beyond the last valid sg entry for the 459 * transfer. 460 */ 461/*12*/ uint32_t dataptr; 462/*16*/ uint32_t datacnt; /* 463 * Byte 3 (numbered from 0) of 464 * the datacnt is really the 465 * 4th byte in that data address. 466 */ 467/*20*/ uint32_t sgptr; 468#define SG_PTR_MASK 0xFFFFFFF8 469/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 470/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 471/*26*/ uint8_t lun; 472/*27*/ uint8_t tag; /* 473 * Index into our kernel SCB array. 474 * Also used as the tag for tagged I/O 475 */ 476/*28*/ uint8_t cdb_len; 477/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 478/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 479/*31*/ uint8_t next; /* 480 * Used for threading SCBs in the 481 * "Waiting for Selection" and 482 * "Disconnected SCB" lists down 483 * in the sequencer. 484 */ 485/*32*/ uint8_t cdb32[32]; /* 486 * CDB storage for cdbs of size 487 * 13->32. We store them here 488 * because hardware scbs are 489 * allocated from DMA safe 490 * memory so we are guaranteed 491 * the controller can access 492 * this data. 493 */ 494}; 495 496/************************ Kernel SCB Definitions ******************************/ 497/* 498 * Some fields of the SCB are OS dependent. Here we collect the 499 * definitions for elements that all OS platforms need to include 500 * in there SCB definition. 501 */ 502 503/* 504 * Definition of a scatter/gather element as transfered to the controller. 505 * The aic7xxx chips only support a 24bit length. We use the top byte of 506 * the length to store additional address bits and a flag to indicate 507 * that a given segment terminates the transfer. This gives us an 508 * addressable range of 512GB on machines with 64bit PCI or with chips 509 * that can support dual address cycles on 32bit PCI busses. 510 */ 511struct ahc_dma_seg { 512 uint32_t addr; 513 uint32_t len; 514#define AHC_DMA_LAST_SEG 0x80000000 515#define AHC_SG_HIGH_ADDR_MASK 0x7F000000 516#define AHC_SG_LEN_MASK 0x00FFFFFF 517}; 518 519struct sg_map_node { 520 bus_dmamap_t sg_dmamap; 521 dma_addr_t sg_physaddr; 522 struct ahc_dma_seg* sg_vaddr; 523 SLIST_ENTRY(sg_map_node) links; 524}; 525 526/* 527 * The current state of this SCB. 528 */ 529typedef enum { 530 SCB_FREE = 0x0000, 531 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 532 * Another device was active 533 * during the first timeout for 534 * this SCB so we gave ourselves 535 * an additional timeout period 536 * in case it was hogging the 537 * bus. 538 */ 539 SCB_DEVICE_RESET = 0x0004, 540 SCB_SENSE = 0x0008, 541 SCB_CDB32_PTR = 0x0010, 542 SCB_RECOVERY_SCB = 0x0020, 543 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 544 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 545 SCB_ABORT = 0x0100, 546 SCB_UNTAGGEDQ = 0x0200, 547 SCB_ACTIVE = 0x0400, 548 SCB_TARGET_IMMEDIATE = 0x0800, 549 SCB_TRANSMISSION_ERROR = 0x1000,/* 550 * We detected a parity or CRC 551 * error that has effected the 552 * payload of the command. This 553 * flag is checked when normal 554 * status is returned to catch 555 * the case of a target not 556 * responding to our attempt 557 * to report the error. 558 */ 559 SCB_TARGET_SCB = 0x2000, 560 SCB_SILENT = 0x4000 /* 561 * Be quiet about transmission type 562 * errors. They are expected and we 563 * don't want to upset the user. This 564 * flag is typically used during DV. 565 */ 566} scb_flag; 567 568struct scb { 569 struct hardware_scb *hscb; 570 union { 571 SLIST_ENTRY(scb) sle; 572 TAILQ_ENTRY(scb) tqe; 573 } links; 574 LIST_ENTRY(scb) pending_links; 575 ahc_io_ctx_t io_ctx; 576 struct ahc_softc *ahc_softc; 577 scb_flag flags; 578#ifndef __linux__ 579 bus_dmamap_t dmamap; 580#endif 581 struct scb_platform_data *platform_data; 582 struct sg_map_node *sg_map; 583 struct ahc_dma_seg *sg_list; 584 dma_addr_t sg_list_phys; 585 u_int sg_count;/* How full ahc_dma_seg is */ 586}; 587 588struct scb_data { 589 SLIST_HEAD(, scb) free_scbs; /* 590 * Pool of SCBs ready to be assigned 591 * commands to execute. 592 */ 593 struct scb *scbindex[256]; /* 594 * Mapping from tag to SCB. 595 * As tag identifiers are an 596 * 8bit value, we provide space 597 * for all possible tag values. 598 * Any lookups to entries at or 599 * above AHC_SCB_MAX_ALLOC will 600 * always fail. 601 */ 602 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 603 struct scb *scbarray; /* Array of kernel SCBs */ 604 struct scsi_sense_data *sense; /* Per SCB sense data */ 605 606 /* 607 * "Bus" addresses of our data structures. 608 */ 609 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 610 bus_dmamap_t hscb_dmamap; 611 dma_addr_t hscb_busaddr; 612 bus_dma_tag_t sense_dmat; 613 bus_dmamap_t sense_dmamap; 614 dma_addr_t sense_busaddr; 615 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 616 SLIST_HEAD(, sg_map_node) sg_maps; 617 uint8_t numscbs; 618 uint8_t maxhscbs; /* Number of SCBs on the card */ 619 uint8_t init_level; /* 620 * How far we've initialized 621 * this structure. 622 */ 623}; 624 625/************************ Target Mode Definitions *****************************/ 626 627/* 628 * Connection desciptor for select-in requests in target mode. 629 */ 630struct target_cmd { 631 uint8_t scsiid; /* Our ID and the initiator's ID */ 632 uint8_t identify; /* Identify message */ 633 uint8_t bytes[22]; /* 634 * Bytes contains any additional message 635 * bytes terminated by 0xFF. The remainder 636 * is the cdb to execute. 637 */ 638 uint8_t cmd_valid; /* 639 * When a command is complete, the firmware 640 * will set cmd_valid to all bits set. 641 * After the host has seen the command, 642 * the bits are cleared. This allows us 643 * to just peek at host memory to determine 644 * if more work is complete. cmd_valid is on 645 * an 8 byte boundary to simplify setting 646 * it on aic7880 hardware which only has 647 * limited direct access to the DMA FIFO. 648 */ 649 uint8_t pad[7]; 650}; 651 652/* 653 * Number of events we can buffer up if we run out 654 * of immediate notify ccbs. 655 */ 656#define AHC_TMODE_EVENT_BUFFER_SIZE 8 657struct ahc_tmode_event { 658 uint8_t initiator_id; 659 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 660#define EVENT_TYPE_BUS_RESET 0xFF 661 uint8_t event_arg; 662}; 663 664/* 665 * Per enabled lun target mode state. 666 * As this state is directly influenced by the host OS'es target mode 667 * environment, we let the OS module define it. Forward declare the 668 * structure here so we can store arrays of them, etc. in OS neutral 669 * data structures. 670 */ 671#ifdef AHC_TARGET_MODE 672struct ahc_tmode_lstate { 673 struct cam_path *path; 674 struct ccb_hdr_slist accept_tios; 675 struct ccb_hdr_slist immed_notifies; 676 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 677 uint8_t event_r_idx; 678 uint8_t event_w_idx; 679}; 680#else 681struct ahc_tmode_lstate; 682#endif 683 684/******************** Transfer Negotiation Datastructures *********************/ 685#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 686#define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 687#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 688#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 689 690#define AHC_WIDTH_UNKNOWN 0xFF 691#define AHC_PERIOD_UNKNOWN 0xFF 692#define AHC_OFFSET_UNKNOWN 0xFF 693#define AHC_PPR_OPTS_UNKNOWN 0xFF 694 695/* 696 * Transfer Negotiation Information. 697 */ 698struct ahc_transinfo { 699 uint8_t protocol_version; /* SCSI Revision level */ 700 uint8_t transport_version; /* SPI Revision level */ 701 uint8_t width; /* Bus width */ 702 uint8_t period; /* Sync rate factor */ 703 uint8_t offset; /* Sync offset */ 704 uint8_t ppr_options; /* Parallel Protocol Request options */ 705}; 706 707/* 708 * Per-initiator current, goal and user transfer negotiation information. */ 709struct ahc_initiator_tinfo { 710 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 711 struct ahc_transinfo curr; 712 struct ahc_transinfo goal; 713 struct ahc_transinfo user; 714}; 715 716/* 717 * Per enabled target ID state. 718 * Pointers to lun target state as well as sync/wide negotiation information 719 * for each initiator<->target mapping. For the initiator role we pretend 720 * that we are the target and the targets are the initiators since the 721 * negotiation is the same regardless of role. 722 */ 723struct ahc_tmode_tstate { 724 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 725 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 726 727 /* 728 * Per initiator state bitmasks. 729 */ 730 uint16_t auto_negotiate;/* Auto Negotiation Required */ 731 uint16_t ultraenb; /* Using ultra sync rate */ 732 uint16_t discenable; /* Disconnection allowed */ 733 uint16_t tagenable; /* Tagged Queuing allowed */ 734}; 735 736/* 737 * Data structure for our table of allowed synchronous transfer rates. 738 */ 739struct ahc_syncrate { 740 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 741 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 742#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 743#define ST_SXFR 0x010 /* Rate Single Transition Only */ 744#define DT_SXFR 0x040 /* Rate Double Transition Only */ 745 uint8_t period; /* Period to send to SCSI target */ 746 char *rate; 747}; 748 749/* Safe and valid period for async negotiations. */ 750#define AHC_ASYNC_XFER_PERIOD 0x45 751#define AHC_ULTRA2_XFER_PERIOD 0x0a 752 753/* 754 * Indexes into our table of syncronous transfer rates. 755 */ 756#define AHC_SYNCRATE_DT 0 757#define AHC_SYNCRATE_ULTRA2 1 758#define AHC_SYNCRATE_ULTRA 3 759#define AHC_SYNCRATE_FAST 6 760#define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT 761#define AHC_SYNCRATE_MIN 13 762 763/***************************** Lookup Tables **********************************/ 764/* 765 * Phase -> name and message out response 766 * to parity errors in each phase table. 767 */ 768struct ahc_phase_table_entry { 769 uint8_t phase; 770 uint8_t mesg_out; /* Message response to parity errors */ 771 char *phasemsg; 772}; 773 774/************************** Serial EEPROM Format ******************************/ 775 776struct seeprom_config { 777/* 778 * Per SCSI ID Configuration Flags 779 */ 780 uint16_t device_flags[16]; /* words 0-15 */ 781#define CFXFER 0x0007 /* synchronous transfer rate */ 782#define CFSYNCH 0x0008 /* enable synchronous transfer */ 783#define CFDISC 0x0010 /* enable disconnection */ 784#define CFWIDEB 0x0020 /* wide bus device */ 785#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 786#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 787#define CFSTART 0x0100 /* send start unit SCSI command */ 788#define CFINCBIOS 0x0200 /* include in BIOS scan */ 789#define CFRNFOUND 0x0400 /* report even if not found */ 790#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 791#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 792#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 793 794/* 795 * BIOS Control Bits 796 */ 797 uint16_t bios_control; /* word 16 */ 798#define CFSUPREM 0x0001 /* support all removeable drives */ 799#define CFSUPREMB 0x0002 /* support removeable boot drives */ 800#define CFBIOSEN 0x0004 /* BIOS enabled */ 801#define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 802#define CFSM2DRV 0x0010 /* support more than two drives */ 803#define CFSTPWLEVEL 0x0010 /* Termination level control */ 804#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 805#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 806#define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 807#define CFEXTEND 0x0080 /* extended translation enabled */ 808#define CFSCAMEN 0x0100 /* SCAM enable */ 809#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 810#define CFMSG_VERBOSE 0x0000 811#define CFMSG_SILENT 0x0200 812#define CFMSG_DIAG 0x0400 813#define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 814/* UNUSED 0xff00 */ 815 816/* 817 * Host Adapter Control Bits 818 */ 819 uint16_t adapter_control; /* word 17 */ 820#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 821#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 822#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 823#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 824#define CFSTERM 0x0004 /* SCSI low byte termination */ 825#define CFWSTERM 0x0008 /* SCSI high byte termination */ 826#define CFSPARITY 0x0010 /* SCSI parity */ 827#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 828#define CFMULTILUN 0x0020 829#define CFRESETB 0x0040 /* reset SCSI bus at boot */ 830#define CFCLUSTERENB 0x0080 /* Cluster Enable */ 831#define CFBOOTCHAN 0x0300 /* probe this channel first */ 832#define CFBOOTCHANSHIFT 8 833#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 834#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 835#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 836#define CFENABLEDV 0x4000 /* Perform Domain Validation*/ 837 838/* 839 * Bus Release Time, Host Adapter ID 840 */ 841 uint16_t brtime_id; /* word 18 */ 842#define CFSCSIID 0x000f /* host adapter SCSI ID */ 843/* UNUSED 0x00f0 */ 844#define CFBRTIME 0xff00 /* bus release time */ 845 846/* 847 * Maximum targets 848 */ 849 uint16_t max_targets; /* word 19 */ 850#define CFMAXTARG 0x00ff /* maximum targets */ 851#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 852#define CFBOOTID 0xf000 /* Target to boot from */ 853 uint16_t res_1[10]; /* words 20-29 */ 854 uint16_t signature; /* Signature == 0x250 */ 855#define CFSIGNATURE 0x250 856#define CFSIGNATURE2 0x300 857 uint16_t checksum; /* word 31 */ 858}; 859 860/**************************** Message Buffer *********************************/ 861typedef enum { 862 MSG_TYPE_NONE = 0x00, 863 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 864 MSG_TYPE_INITIATOR_MSGIN = 0x02, 865 MSG_TYPE_TARGET_MSGOUT = 0x03, 866 MSG_TYPE_TARGET_MSGIN = 0x04 867} ahc_msg_type; 868 869typedef enum { 870 MSGLOOP_IN_PROG, 871 MSGLOOP_MSGCOMPLETE, 872 MSGLOOP_TERMINATED 873} msg_loop_stat; 874 875/*********************** Software Configuration Structure *********************/ 876TAILQ_HEAD(scb_tailq, scb); 877 878struct ahc_aic7770_softc { 879 /* 880 * Saved register state used for chip_init(). 881 */ 882 uint8_t busspd; 883 uint8_t bustime; 884}; 885 886struct ahc_pci_softc { 887 /* 888 * Saved register state used for chip_init(). 889 */ 890 uint32_t devconfig; 891 uint16_t targcrccnt; 892 uint8_t command; 893 uint8_t csize_lattime; 894 uint8_t optionmode; 895 uint8_t crccontrol1; 896 uint8_t dscommand0; 897 uint8_t dspcistatus; 898 uint8_t scbbaddr; 899 uint8_t dff_thrsh; 900}; 901 902union ahc_bus_softc { 903 struct ahc_aic7770_softc aic7770_softc; 904 struct ahc_pci_softc pci_softc; 905}; 906 907typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 908typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *); 909typedef int (*ahc_bus_suspend_t)(struct ahc_softc *); 910typedef int (*ahc_bus_resume_t)(struct ahc_softc *); 911typedef void ahc_callback_t (void *); 912 913struct ahc_softc { 914 bus_space_tag_t tag; 915 bus_space_handle_t bsh; 916#ifndef __linux__ 917 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 918#endif 919 struct scb_data *scb_data; 920 921 struct scb *next_queued_scb; 922 923 /* 924 * SCBs that have been sent to the controller 925 */ 926 LIST_HEAD(, scb) pending_scbs; 927 928 /* 929 * Counting lock for deferring the release of additional 930 * untagged transactions from the untagged_queues. When 931 * the lock is decremented to 0, all queues in the 932 * untagged_queues array are run. 933 */ 934 u_int untagged_queue_lock; 935 936 /* 937 * Per-target queue of untagged-transactions. The 938 * transaction at the head of the queue is the 939 * currently pending untagged transaction for the 940 * target. The driver only allows a single untagged 941 * transaction per target. 942 */ 943 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 944 945 /* 946 * Bus attachment specific data. 947 */ 948 union ahc_bus_softc bus_softc; 949 950 /* 951 * Platform specific data. 952 */ 953 struct ahc_platform_data *platform_data; 954 955 /* 956 * Platform specific device information. 957 */ 958 ahc_dev_softc_t dev_softc; 959 960 /* 961 * Bus specific device information. 962 */ 963 ahc_bus_intr_t bus_intr; 964 965 /* 966 * Bus specific initialization required 967 * after a chip reset. 968 */ 969 ahc_bus_chip_init_t bus_chip_init; 970 971 /* 972 * Bus specific suspend routine. 973 */ 974 ahc_bus_suspend_t bus_suspend; 975 976 /* 977 * Bus specific resume routine. 978 */ 979 ahc_bus_resume_t bus_resume; 980 981 /* 982 * Target mode related state kept on a per enabled lun basis. 983 * Targets that are not enabled will have null entries. 984 * As an initiator, we keep one target entry for our initiator 985 * ID to store our sync/wide transfer settings. 986 */ 987 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 988 989 /* 990 * The black hole device responsible for handling requests for 991 * disabled luns on enabled targets. 992 */ 993 struct ahc_tmode_lstate *black_hole; 994 995 /* 996 * Device instance currently on the bus awaiting a continue TIO 997 * for a command that was not given the disconnect priveledge. 998 */ 999 struct ahc_tmode_lstate *pending_device; 1000 1001 /* 1002 * Card characteristics 1003 */ 1004 ahc_chip chip; 1005 ahc_feature features; 1006 ahc_bug bugs; 1007 ahc_flag flags; 1008 struct seeprom_config *seep_config; 1009 1010 /* Values to store in the SEQCTL register for pause and unpause */ 1011 uint8_t unpause; 1012 uint8_t pause; 1013 1014 /* Command Queues */ 1015 uint8_t qoutfifonext; 1016 uint8_t qinfifonext; 1017 uint8_t *qoutfifo; 1018 uint8_t *qinfifo; 1019 1020 /* Critical Section Data */ 1021 struct cs *critical_sections; 1022 u_int num_critical_sections; 1023 1024 /* Channel Names ('A', 'B', etc.) */ 1025 char channel; 1026 char channel_b; 1027 1028 /* Initiator Bus ID */ 1029 uint8_t our_id; 1030 uint8_t our_id_b; 1031 1032 /* 1033 * PCI error detection. 1034 */ 1035 int unsolicited_ints; 1036 1037 /* 1038 * Target incoming command FIFO. 1039 */ 1040 struct target_cmd *targetcmds; 1041 uint8_t tqinfifonext; 1042 1043 /* 1044 * Cached copy of the sequencer control register. 1045 */ 1046 uint8_t seqctl; 1047 1048 /* 1049 * Incoming and outgoing message handling. 1050 */ 1051 uint8_t send_msg_perror; 1052 ahc_msg_type msg_type; 1053 uint8_t msgout_buf[12];/* Message we are sending */ 1054 uint8_t msgin_buf[12];/* Message we are receiving */ 1055 u_int msgout_len; /* Length of message to send */ 1056 u_int msgout_index; /* Current index in msgout */ 1057 u_int msgin_index; /* Current index in msgin */ 1058 1059 /* 1060 * Mapping information for data structures shared 1061 * between the sequencer and kernel. 1062 */ 1063 bus_dma_tag_t parent_dmat; 1064 bus_dma_tag_t shared_data_dmat; 1065 bus_dmamap_t shared_data_dmamap; 1066 dma_addr_t shared_data_busaddr; 1067 1068 /* 1069 * Bus address of the one byte buffer used to 1070 * work-around a DMA bug for chips <= aic7880 1071 * in target mode. 1072 */ 1073 dma_addr_t dma_bug_buf; 1074 1075 /* Number of enabled target mode device on this card */ 1076 u_int enabled_luns; 1077 1078 /* Initialization level of this data structure */ 1079 u_int init_level; 1080 1081 /* PCI cacheline size. */ 1082 u_int pci_cachesize; 1083 1084 /* 1085 * Count of parity errors we have seen as a target. 1086 * We auto-disable parity error checking after seeing 1087 * AHC_PCI_TARGET_PERR_THRESH number of errors. 1088 */ 1089 u_int pci_target_perr_count; 1090#define AHC_PCI_TARGET_PERR_THRESH 10 1091 1092 /* Maximum number of sequencer instructions supported. */ 1093 u_int instruction_ram_size; 1094 1095 /* Per-Unit descriptive information */ 1096 const char *description; 1097 char *name; 1098 int unit; 1099 1100 /* Selection Timer settings */ 1101 int seltime; 1102 int seltime_b; 1103 1104 uint16_t user_discenable;/* Disconnection allowed */ 1105 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1106}; 1107 1108/************************ Active Device Information ***************************/ 1109typedef enum { 1110 ROLE_UNKNOWN, 1111 ROLE_INITIATOR, 1112 ROLE_TARGET 1113} role_t; 1114 1115struct ahc_devinfo { 1116 int our_scsiid; 1117 int target_offset; 1118 uint16_t target_mask; 1119 u_int target; 1120 u_int lun; 1121 char channel; 1122 role_t role; /* 1123 * Only guaranteed to be correct if not 1124 * in the busfree state. 1125 */ 1126}; 1127 1128/****************************** PCI Structures ********************************/ 1129typedef int (ahc_device_setup_t)(struct ahc_softc *); 1130 1131struct ahc_pci_identity { 1132 uint64_t full_id; 1133 uint64_t id_mask; 1134 char *name; 1135 ahc_device_setup_t *setup; 1136}; 1137extern struct ahc_pci_identity ahc_pci_ident_table[]; 1138extern const u_int ahc_num_pci_devs; 1139 1140/***************************** VL/EISA Declarations ***************************/ 1141struct aic7770_identity { 1142 uint32_t full_id; 1143 uint32_t id_mask; 1144 const char *name; 1145 ahc_device_setup_t *setup; 1146}; 1147extern struct aic7770_identity aic7770_ident_table[]; 1148extern const int ahc_num_aic7770_devs; 1149 1150#define AHC_EISA_SLOT_OFFSET 0xc00 1151#define AHC_EISA_IOSIZE 0x100 1152 1153/*************************** Function Declarations ****************************/ 1154/******************************************************************************/ 1155u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1156void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1157void ahc_busy_tcl(struct ahc_softc *ahc, 1158 u_int tcl, u_int busyid); 1159 1160/***************************** PCI Front End *********************************/ 1161struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); 1162int ahc_pci_config(struct ahc_softc *, 1163 struct ahc_pci_identity *); 1164int ahc_pci_test_register_access(struct ahc_softc *); 1165 1166/*************************** EISA/VL Front End ********************************/ 1167struct aic7770_identity *aic7770_find_device(uint32_t); 1168int aic7770_config(struct ahc_softc *ahc, 1169 struct aic7770_identity *, 1170 u_int port); 1171 1172/************************** SCB and SCB queue management **********************/ 1173int ahc_probe_scbs(struct ahc_softc *); 1174void ahc_run_untagged_queues(struct ahc_softc *ahc); 1175void ahc_run_untagged_queue(struct ahc_softc *ahc, 1176 struct scb_tailq *queue); 1177void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1178 struct scb *scb); 1179int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1180 int target, char channel, int lun, 1181 u_int tag, role_t role); 1182 1183/****************************** Initialization ********************************/ 1184struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1185int ahc_softc_init(struct ahc_softc *); 1186void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1187int ahc_chip_init(struct ahc_softc *ahc); 1188int ahc_init(struct ahc_softc *ahc); 1189void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1190void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1191int ahc_suspend(struct ahc_softc *ahc); 1192int ahc_resume(struct ahc_softc *ahc); 1193void ahc_set_unit(struct ahc_softc *, int); 1194void ahc_set_name(struct ahc_softc *, char *); 1195void ahc_alloc_scbs(struct ahc_softc *ahc); 1196void ahc_free(struct ahc_softc *ahc); 1197int ahc_reset(struct ahc_softc *ahc, int reinit); 1198void ahc_shutdown(void *arg); 1199 1200/*************************** Interrupt Services *******************************/ 1201void ahc_clear_intstat(struct ahc_softc *ahc); 1202void ahc_run_qoutfifo(struct ahc_softc *ahc); 1203#ifdef AHC_TARGET_MODE 1204void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1205#endif 1206void ahc_handle_brkadrint(struct ahc_softc *ahc); 1207void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1208void ahc_handle_scsiint(struct ahc_softc *ahc, 1209 u_int intstat); 1210void ahc_clear_critical_section(struct ahc_softc *ahc); 1211 1212/***************************** Error Recovery *********************************/ 1213typedef enum { 1214 SEARCH_COMPLETE, 1215 SEARCH_COUNT, 1216 SEARCH_REMOVE 1217} ahc_search_action; 1218int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1219 char channel, int lun, u_int tag, 1220 role_t role, uint32_t status, 1221 ahc_search_action action); 1222int ahc_search_untagged_queues(struct ahc_softc *ahc, 1223 ahc_io_ctx_t ctx, 1224 int target, char channel, 1225 int lun, uint32_t status, 1226 ahc_search_action action); 1227int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1228 char channel, int lun, u_int tag, 1229 int stop_on_first, int remove, 1230 int save_state); 1231void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1232int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1233 int initiate_reset); 1234int ahc_abort_scbs(struct ahc_softc *ahc, int target, 1235 char channel, int lun, u_int tag, 1236 role_t role, uint32_t status); 1237void ahc_restart(struct ahc_softc *ahc); 1238void ahc_calc_residual(struct ahc_softc *ahc, 1239 struct scb *scb); 1240/*************************** Utility Functions ********************************/ 1241struct ahc_phase_table_entry* 1242 ahc_lookup_phase_entry(int phase); 1243void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1244 u_int our_id, u_int target, 1245 u_int lun, char channel, 1246 role_t role); 1247/************************** Transfer Negotiation ******************************/ 1248struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1249 u_int *ppr_options, u_int maxsync); 1250u_int ahc_find_period(struct ahc_softc *ahc, 1251 u_int scsirate, u_int maxsync); 1252void ahc_validate_offset(struct ahc_softc *ahc, 1253 struct ahc_initiator_tinfo *tinfo, 1254 struct ahc_syncrate *syncrate, 1255 u_int *offset, int wide, 1256 role_t role); 1257void ahc_validate_width(struct ahc_softc *ahc, 1258 struct ahc_initiator_tinfo *tinfo, 1259 u_int *bus_width, 1260 role_t role); 1261/* 1262 * Negotiation types. These are used to qualify if we should renegotiate 1263 * even if our goal and current transport parameters are identical. 1264 */ 1265typedef enum { 1266 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1267 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1268 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1269} ahc_neg_type; 1270int ahc_update_neg_request(struct ahc_softc*, 1271 struct ahc_devinfo*, 1272 struct ahc_tmode_tstate*, 1273 struct ahc_initiator_tinfo*, 1274 ahc_neg_type); 1275void ahc_set_width(struct ahc_softc *ahc, 1276 struct ahc_devinfo *devinfo, 1277 u_int width, u_int type, int paused); 1278void ahc_set_syncrate(struct ahc_softc *ahc, 1279 struct ahc_devinfo *devinfo, 1280 struct ahc_syncrate *syncrate, 1281 u_int period, u_int offset, 1282 u_int ppr_options, 1283 u_int type, int paused); 1284typedef enum { 1285 AHC_QUEUE_NONE, 1286 AHC_QUEUE_BASIC, 1287 AHC_QUEUE_TAGGED 1288} ahc_queue_alg; 1289 1290void ahc_set_tags(struct ahc_softc *ahc, 1291 struct ahc_devinfo *devinfo, 1292 ahc_queue_alg alg); 1293 1294/**************************** Target Mode *************************************/ 1295#ifdef AHC_TARGET_MODE 1296void ahc_send_lstate_events(struct ahc_softc *, 1297 struct ahc_tmode_lstate *); 1298void ahc_handle_en_lun(struct ahc_softc *ahc, 1299 struct cam_sim *sim, union ccb *ccb); 1300cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1301 struct cam_sim *sim, union ccb *ccb, 1302 struct ahc_tmode_tstate **tstate, 1303 struct ahc_tmode_lstate **lstate, 1304 int notfound_failure); 1305#ifndef AHC_TMODE_ENABLE 1306#define AHC_TMODE_ENABLE 0 1307#endif 1308#endif 1309/******************************* Debug ***************************************/ 1310#ifdef AHC_DEBUG 1311extern uint32_t ahc_debug; 1312#define AHC_SHOW_MISC 0x0001 1313#define AHC_SHOW_SENSE 0x0002 1314#define AHC_DUMP_SEEPROM 0x0004 1315#define AHC_SHOW_TERMCTL 0x0008 1316#define AHC_SHOW_MEMORY 0x0010 1317#define AHC_SHOW_MESSAGES 0x0020 1318#define AHC_SHOW_DV 0x0040 1319#define AHC_SHOW_SELTO 0x0080 1320#define AHC_SHOW_QFULL 0x0200 1321#define AHC_SHOW_QUEUE 0x0400 1322#define AHC_SHOW_TQIN 0x0800 1323#define AHC_SHOW_MASKED_ERRORS 0x1000 1324#define AHC_DEBUG_SEQUENCER 0x2000 1325#endif 1326void ahc_print_scb(struct scb *scb); 1327void ahc_print_devinfo(struct ahc_softc *ahc, 1328 struct ahc_devinfo *dev); 1329void ahc_dump_card_state(struct ahc_softc *ahc); 1330int ahc_print_register(ahc_reg_parse_entry_t *table, 1331 u_int num_entries, 1332 const char *name, 1333 u_int address, 1334 u_int value, 1335 u_int *cur_column, 1336 u_int wrap_point); 1337/******************************* SEEPROM *************************************/ 1338int ahc_acquire_seeprom(struct ahc_softc *ahc, 1339 struct seeprom_descriptor *sd); 1340void ahc_release_seeprom(struct seeprom_descriptor *sd); 1341#endif /* _AIC7XXX_H_ */ 1342