aic7xxx_pci.c revision 980b306a297725d4f25c779ca15086de757acadf
1/* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#79 $ 43 */ 44 45#ifdef __linux__ 46#include "aic7xxx_osm.h" 47#include "aic7xxx_inline.h" 48#include "aic7xxx_93cx6.h" 49#else 50#include <dev/aic7xxx/aic7xxx_osm.h> 51#include <dev/aic7xxx/aic7xxx_inline.h> 52#include <dev/aic7xxx/aic7xxx_93cx6.h> 53#endif 54 55#include "aic7xxx_pci.h" 56 57static __inline uint64_t 58ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 59{ 60 uint64_t id; 61 62 id = subvendor 63 | (subdevice << 16) 64 | ((uint64_t)vendor << 32) 65 | ((uint64_t)device << 48); 66 67 return (id); 68} 69 70#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 71#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 72 73#define DEVID_9005_TYPE(id) ((id) & 0xF) 74#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 75#define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 76#define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 77#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 78 79#define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 80#define DEVID_9005_MAXRATE_U160 0x0 81#define DEVID_9005_MAXRATE_ULTRA2 0x1 82#define DEVID_9005_MAXRATE_ULTRA 0x2 83#define DEVID_9005_MAXRATE_FAST 0x3 84 85#define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 86 87#define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 88#define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 89 90#define SUBID_9005_TYPE(id) ((id) & 0xF) 91#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 92#define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 93#define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 94#define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 95 96#define SUBID_9005_TYPE_KNOWN(id) \ 97 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 98 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 99 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 100 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 101 102#define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 103#define SUBID_9005_MAXRATE_ULTRA2 0x0 104#define SUBID_9005_MAXRATE_ULTRA 0x1 105#define SUBID_9005_MAXRATE_U160 0x2 106#define SUBID_9005_MAXRATE_RESERVED 0x3 107 108#define SUBID_9005_SEEPTYPE(id) \ 109 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 110 ? ((id) & 0xC0) >> 6 \ 111 : ((id) & 0x300) >> 8) 112#define SUBID_9005_SEEPTYPE_NONE 0x0 113#define SUBID_9005_SEEPTYPE_1K 0x1 114#define SUBID_9005_SEEPTYPE_2K_4K 0x2 115#define SUBID_9005_SEEPTYPE_RESERVED 0x3 116#define SUBID_9005_AUTOTERM(id) \ 117 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 118 ? (((id) & 0x400) >> 10) == 0 \ 119 : (((id) & 0x40) >> 6) == 0) 120 121#define SUBID_9005_NUMCHAN(id) \ 122 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 123 ? ((id) & 0x300) >> 8 \ 124 : ((id) & 0xC00) >> 10) 125 126#define SUBID_9005_LEGACYCONN(id) \ 127 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 128 ? 0 \ 129 : ((id) & 0x80) >> 7) 130 131#define SUBID_9005_MFUNCENB(id) \ 132 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 133 ? ((id) & 0x800) >> 11 \ 134 : ((id) & 0x1000) >> 12) 135/* 136 * Informational only. Should use chip register to be 137 * certain, but may be use in identification strings. 138 */ 139#define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 140#define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 141#define SUBID_9005_CARD_SEDIFF_MASK 0x8000 142 143static ahc_device_setup_t ahc_aic785X_setup; 144static ahc_device_setup_t ahc_aic7860_setup; 145static ahc_device_setup_t ahc_apa1480_setup; 146static ahc_device_setup_t ahc_aic7870_setup; 147static ahc_device_setup_t ahc_aic7870h_setup; 148static ahc_device_setup_t ahc_aha394X_setup; 149static ahc_device_setup_t ahc_aha394Xh_setup; 150static ahc_device_setup_t ahc_aha494X_setup; 151static ahc_device_setup_t ahc_aha494Xh_setup; 152static ahc_device_setup_t ahc_aha398X_setup; 153static ahc_device_setup_t ahc_aic7880_setup; 154static ahc_device_setup_t ahc_aic7880h_setup; 155static ahc_device_setup_t ahc_aha2940Pro_setup; 156static ahc_device_setup_t ahc_aha394XU_setup; 157static ahc_device_setup_t ahc_aha394XUh_setup; 158static ahc_device_setup_t ahc_aha398XU_setup; 159static ahc_device_setup_t ahc_aic7890_setup; 160static ahc_device_setup_t ahc_aic7892_setup; 161static ahc_device_setup_t ahc_aic7895_setup; 162static ahc_device_setup_t ahc_aic7895h_setup; 163static ahc_device_setup_t ahc_aic7896_setup; 164static ahc_device_setup_t ahc_aic7899_setup; 165static ahc_device_setup_t ahc_aha29160C_setup; 166static ahc_device_setup_t ahc_raid_setup; 167static ahc_device_setup_t ahc_aha394XX_setup; 168static ahc_device_setup_t ahc_aha494XX_setup; 169static ahc_device_setup_t ahc_aha398XX_setup; 170 171static const struct ahc_pci_identity ahc_pci_ident_table[] = { 172 /* aic7850 based controllers */ 173 { 174 ID_AHA_2902_04_10_15_20C_30C, 175 ID_ALL_MASK, 176 "Adaptec 2902/04/10/15/20C/30C SCSI adapter", 177 ahc_aic785X_setup 178 }, 179 /* aic7860 based controllers */ 180 { 181 ID_AHA_2930CU, 182 ID_ALL_MASK, 183 "Adaptec 2930CU SCSI adapter", 184 ahc_aic7860_setup 185 }, 186 { 187 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 188 ID_DEV_VENDOR_MASK, 189 "Adaptec 1480A Ultra SCSI adapter", 190 ahc_apa1480_setup 191 }, 192 { 193 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 194 ID_DEV_VENDOR_MASK, 195 "Adaptec 2940A Ultra SCSI adapter", 196 ahc_aic7860_setup 197 }, 198 { 199 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 200 ID_DEV_VENDOR_MASK, 201 "Adaptec 2940A/CN Ultra SCSI adapter", 202 ahc_aic7860_setup 203 }, 204 { 205 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 206 ID_DEV_VENDOR_MASK, 207 "Adaptec 2930C Ultra SCSI adapter (VAR)", 208 ahc_aic7860_setup 209 }, 210 /* aic7870 based controllers */ 211 { 212 ID_AHA_2940, 213 ID_ALL_MASK, 214 "Adaptec 2940 SCSI adapter", 215 ahc_aic7870_setup 216 }, 217 { 218 ID_AHA_3940, 219 ID_ALL_MASK, 220 "Adaptec 3940 SCSI adapter", 221 ahc_aha394X_setup 222 }, 223 { 224 ID_AHA_398X, 225 ID_ALL_MASK, 226 "Adaptec 398X SCSI RAID adapter", 227 ahc_aha398X_setup 228 }, 229 { 230 ID_AHA_2944, 231 ID_ALL_MASK, 232 "Adaptec 2944 SCSI adapter", 233 ahc_aic7870h_setup 234 }, 235 { 236 ID_AHA_3944, 237 ID_ALL_MASK, 238 "Adaptec 3944 SCSI adapter", 239 ahc_aha394Xh_setup 240 }, 241 { 242 ID_AHA_4944, 243 ID_ALL_MASK, 244 "Adaptec 4944 SCSI adapter", 245 ahc_aha494Xh_setup 246 }, 247 /* aic7880 based controllers */ 248 { 249 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 250 ID_DEV_VENDOR_MASK, 251 "Adaptec 2940 Ultra SCSI adapter", 252 ahc_aic7880_setup 253 }, 254 { 255 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 256 ID_DEV_VENDOR_MASK, 257 "Adaptec 3940 Ultra SCSI adapter", 258 ahc_aha394XU_setup 259 }, 260 { 261 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 2944 Ultra SCSI adapter", 264 ahc_aic7880h_setup 265 }, 266 { 267 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 3944 Ultra SCSI adapter", 270 ahc_aha394XUh_setup 271 }, 272 { 273 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 398X Ultra SCSI RAID adapter", 276 ahc_aha398XU_setup 277 }, 278 { 279 /* 280 * XXX Don't know the slot numbers 281 * so we can't identify channels 282 */ 283 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 284 ID_DEV_VENDOR_MASK, 285 "Adaptec 4944 Ultra SCSI adapter", 286 ahc_aic7880h_setup 287 }, 288 { 289 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 290 ID_DEV_VENDOR_MASK, 291 "Adaptec 2930 Ultra SCSI adapter", 292 ahc_aic7880_setup 293 }, 294 { 295 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 296 ID_DEV_VENDOR_MASK, 297 "Adaptec 2940 Pro Ultra SCSI adapter", 298 ahc_aha2940Pro_setup 299 }, 300 { 301 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 302 ID_DEV_VENDOR_MASK, 303 "Adaptec 2940/CN Ultra SCSI adapter", 304 ahc_aic7880_setup 305 }, 306 /* Ignore all SISL (AAC on MB) based controllers. */ 307 { 308 ID_9005_SISL_ID, 309 ID_9005_SISL_MASK, 310 NULL, 311 NULL 312 }, 313 /* aic7890 based controllers */ 314 { 315 ID_AHA_2930U2, 316 ID_ALL_MASK, 317 "Adaptec 2930 Ultra2 SCSI adapter", 318 ahc_aic7890_setup 319 }, 320 { 321 ID_AHA_2940U2B, 322 ID_ALL_MASK, 323 "Adaptec 2940B Ultra2 SCSI adapter", 324 ahc_aic7890_setup 325 }, 326 { 327 ID_AHA_2940U2_OEM, 328 ID_ALL_MASK, 329 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 330 ahc_aic7890_setup 331 }, 332 { 333 ID_AHA_2940U2, 334 ID_ALL_MASK, 335 "Adaptec 2940 Ultra2 SCSI adapter", 336 ahc_aic7890_setup 337 }, 338 { 339 ID_AHA_2950U2B, 340 ID_ALL_MASK, 341 "Adaptec 2950 Ultra2 SCSI adapter", 342 ahc_aic7890_setup 343 }, 344 { 345 ID_AIC7890_ARO, 346 ID_ALL_MASK, 347 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 348 ahc_aic7890_setup 349 }, 350 { 351 ID_AAA_131U2, 352 ID_ALL_MASK, 353 "Adaptec AAA-131 Ultra2 RAID adapter", 354 ahc_aic7890_setup 355 }, 356 /* aic7892 based controllers */ 357 { 358 ID_AHA_29160, 359 ID_ALL_MASK, 360 "Adaptec 29160 Ultra160 SCSI adapter", 361 ahc_aic7892_setup 362 }, 363 { 364 ID_AHA_29160_CPQ, 365 ID_ALL_MASK, 366 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 367 ahc_aic7892_setup 368 }, 369 { 370 ID_AHA_29160N, 371 ID_ALL_MASK, 372 "Adaptec 29160N Ultra160 SCSI adapter", 373 ahc_aic7892_setup 374 }, 375 { 376 ID_AHA_29160C, 377 ID_ALL_MASK, 378 "Adaptec 29160C Ultra160 SCSI adapter", 379 ahc_aha29160C_setup 380 }, 381 { 382 ID_AHA_29160B, 383 ID_ALL_MASK, 384 "Adaptec 29160B Ultra160 SCSI adapter", 385 ahc_aic7892_setup 386 }, 387 { 388 ID_AHA_19160B, 389 ID_ALL_MASK, 390 "Adaptec 19160B Ultra160 SCSI adapter", 391 ahc_aic7892_setup 392 }, 393 { 394 ID_AIC7892_ARO, 395 ID_ALL_MASK, 396 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 397 ahc_aic7892_setup 398 }, 399 { 400 ID_AHA_2915_30LP, 401 ID_ALL_MASK, 402 "Adaptec 2915/30LP Ultra160 SCSI adapter", 403 ahc_aic7892_setup 404 }, 405 /* aic7895 based controllers */ 406 { 407 ID_AHA_2940U_DUAL, 408 ID_ALL_MASK, 409 "Adaptec 2940/DUAL Ultra SCSI adapter", 410 ahc_aic7895_setup 411 }, 412 { 413 ID_AHA_3940AU, 414 ID_ALL_MASK, 415 "Adaptec 3940A Ultra SCSI adapter", 416 ahc_aic7895_setup 417 }, 418 { 419 ID_AHA_3944AU, 420 ID_ALL_MASK, 421 "Adaptec 3944A Ultra SCSI adapter", 422 ahc_aic7895h_setup 423 }, 424 { 425 ID_AIC7895_ARO, 426 ID_AIC7895_ARO_MASK, 427 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 428 ahc_aic7895_setup 429 }, 430 /* aic7896/97 based controllers */ 431 { 432 ID_AHA_3950U2B_0, 433 ID_ALL_MASK, 434 "Adaptec 3950B Ultra2 SCSI adapter", 435 ahc_aic7896_setup 436 }, 437 { 438 ID_AHA_3950U2B_1, 439 ID_ALL_MASK, 440 "Adaptec 3950B Ultra2 SCSI adapter", 441 ahc_aic7896_setup 442 }, 443 { 444 ID_AHA_3950U2D_0, 445 ID_ALL_MASK, 446 "Adaptec 3950D Ultra2 SCSI adapter", 447 ahc_aic7896_setup 448 }, 449 { 450 ID_AHA_3950U2D_1, 451 ID_ALL_MASK, 452 "Adaptec 3950D Ultra2 SCSI adapter", 453 ahc_aic7896_setup 454 }, 455 { 456 ID_AIC7896_ARO, 457 ID_ALL_MASK, 458 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 459 ahc_aic7896_setup 460 }, 461 /* aic7899 based controllers */ 462 { 463 ID_AHA_3960D, 464 ID_ALL_MASK, 465 "Adaptec 3960D Ultra160 SCSI adapter", 466 ahc_aic7899_setup 467 }, 468 { 469 ID_AHA_3960D_CPQ, 470 ID_ALL_MASK, 471 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 472 ahc_aic7899_setup 473 }, 474 { 475 ID_AIC7899_ARO, 476 ID_ALL_MASK, 477 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 478 ahc_aic7899_setup 479 }, 480 /* Generic chip probes for devices we don't know 'exactly' */ 481 { 482 ID_AIC7850 & ID_DEV_VENDOR_MASK, 483 ID_DEV_VENDOR_MASK, 484 "Adaptec aic7850 SCSI adapter", 485 ahc_aic785X_setup 486 }, 487 { 488 ID_AIC7855 & ID_DEV_VENDOR_MASK, 489 ID_DEV_VENDOR_MASK, 490 "Adaptec aic7855 SCSI adapter", 491 ahc_aic785X_setup 492 }, 493 { 494 ID_AIC7859 & ID_DEV_VENDOR_MASK, 495 ID_DEV_VENDOR_MASK, 496 "Adaptec aic7859 SCSI adapter", 497 ahc_aic7860_setup 498 }, 499 { 500 ID_AIC7860 & ID_DEV_VENDOR_MASK, 501 ID_DEV_VENDOR_MASK, 502 "Adaptec aic7860 Ultra SCSI adapter", 503 ahc_aic7860_setup 504 }, 505 { 506 ID_AIC7870 & ID_DEV_VENDOR_MASK, 507 ID_DEV_VENDOR_MASK, 508 "Adaptec aic7870 SCSI adapter", 509 ahc_aic7870_setup 510 }, 511 { 512 ID_AIC7880 & ID_DEV_VENDOR_MASK, 513 ID_DEV_VENDOR_MASK, 514 "Adaptec aic7880 Ultra SCSI adapter", 515 ahc_aic7880_setup 516 }, 517 { 518 ID_AIC7890 & ID_9005_GENERIC_MASK, 519 ID_9005_GENERIC_MASK, 520 "Adaptec aic7890/91 Ultra2 SCSI adapter", 521 ahc_aic7890_setup 522 }, 523 { 524 ID_AIC7892 & ID_9005_GENERIC_MASK, 525 ID_9005_GENERIC_MASK, 526 "Adaptec aic7892 Ultra160 SCSI adapter", 527 ahc_aic7892_setup 528 }, 529 { 530 ID_AIC7895 & ID_DEV_VENDOR_MASK, 531 ID_DEV_VENDOR_MASK, 532 "Adaptec aic7895 Ultra SCSI adapter", 533 ahc_aic7895_setup 534 }, 535 { 536 ID_AIC7896 & ID_9005_GENERIC_MASK, 537 ID_9005_GENERIC_MASK, 538 "Adaptec aic7896/97 Ultra2 SCSI adapter", 539 ahc_aic7896_setup 540 }, 541 { 542 ID_AIC7899 & ID_9005_GENERIC_MASK, 543 ID_9005_GENERIC_MASK, 544 "Adaptec aic7899 Ultra160 SCSI adapter", 545 ahc_aic7899_setup 546 }, 547 { 548 ID_AIC7810 & ID_DEV_VENDOR_MASK, 549 ID_DEV_VENDOR_MASK, 550 "Adaptec aic7810 RAID memory controller", 551 ahc_raid_setup 552 }, 553 { 554 ID_AIC7815 & ID_DEV_VENDOR_MASK, 555 ID_DEV_VENDOR_MASK, 556 "Adaptec aic7815 RAID memory controller", 557 ahc_raid_setup 558 } 559}; 560 561static const u_int ahc_num_pci_devs = ARRAY_SIZE(ahc_pci_ident_table); 562 563#define AHC_394X_SLOT_CHANNEL_A 4 564#define AHC_394X_SLOT_CHANNEL_B 5 565 566#define AHC_398X_SLOT_CHANNEL_A 4 567#define AHC_398X_SLOT_CHANNEL_B 8 568#define AHC_398X_SLOT_CHANNEL_C 12 569 570#define AHC_494X_SLOT_CHANNEL_A 4 571#define AHC_494X_SLOT_CHANNEL_B 5 572#define AHC_494X_SLOT_CHANNEL_C 6 573#define AHC_494X_SLOT_CHANNEL_D 7 574 575#define DEVCONFIG 0x40 576#define PCIERRGENDIS 0x80000000ul 577#define SCBSIZE32 0x00010000ul /* aic789X only */ 578#define REXTVALID 0x00001000ul /* ultra cards only */ 579#define MPORTMODE 0x00000400ul /* aic7870+ only */ 580#define RAMPSM 0x00000200ul /* aic7870+ only */ 581#define VOLSENSE 0x00000100ul 582#define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 583#define SCBRAMSEL 0x00000080ul 584#define MRDCEN 0x00000040ul 585#define EXTSCBTIME 0x00000020ul /* aic7870 only */ 586#define EXTSCBPEN 0x00000010ul /* aic7870 only */ 587#define BERREN 0x00000008ul 588#define DACEN 0x00000004ul 589#define STPWLEVEL 0x00000002ul 590#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 591 592#define CSIZE_LATTIME 0x0c 593#define CACHESIZE 0x0000003ful /* only 5 bits */ 594#define LATTIME 0x0000ff00ul 595 596/* PCI STATUS definitions */ 597#define DPE 0x80 598#define SSE 0x40 599#define RMA 0x20 600#define RTA 0x10 601#define STA 0x08 602#define DPR 0x01 603 604static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 605 uint16_t subvendor, uint16_t subdevice); 606static int ahc_ext_scbram_present(struct ahc_softc *ahc); 607static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 608 int pcheck, int fast, int large); 609static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 610static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 611static void ahc_parse_pci_eeprom(struct ahc_softc *ahc, 612 struct seeprom_config *sc); 613static void configure_termination(struct ahc_softc *ahc, 614 struct seeprom_descriptor *sd, 615 u_int adapter_control, 616 u_int *sxfrctl1); 617 618static void ahc_new_term_detect(struct ahc_softc *ahc, 619 int *enableSEC_low, 620 int *enableSEC_high, 621 int *enablePRI_low, 622 int *enablePRI_high, 623 int *eeprom_present); 624static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 625 int *internal68_present, 626 int *externalcable_present, 627 int *eeprom_present); 628static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 629 int *externalcable_present, 630 int *eeprom_present); 631static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 632static uint8_t read_brdctl(struct ahc_softc *ahc); 633static void ahc_pci_intr(struct ahc_softc *ahc); 634static int ahc_pci_chip_init(struct ahc_softc *ahc); 635 636static int 637ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 638 uint16_t subdevice, uint16_t subvendor) 639{ 640 int result; 641 642 /* Default to invalid. */ 643 result = 0; 644 if (vendor == 0x9005 645 && subvendor == 0x9005 646 && subdevice != device 647 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 648 649 switch (SUBID_9005_TYPE(subdevice)) { 650 case SUBID_9005_TYPE_MB: 651 break; 652 case SUBID_9005_TYPE_CARD: 653 case SUBID_9005_TYPE_LCCARD: 654 /* 655 * Currently only trust Adaptec cards to 656 * get the sub device info correct. 657 */ 658 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 659 result = 1; 660 break; 661 case SUBID_9005_TYPE_RAID: 662 break; 663 default: 664 break; 665 } 666 } 667 return (result); 668} 669 670const struct ahc_pci_identity * 671ahc_find_pci_device(ahc_dev_softc_t pci) 672{ 673 uint64_t full_id; 674 uint16_t device; 675 uint16_t vendor; 676 uint16_t subdevice; 677 uint16_t subvendor; 678 const struct ahc_pci_identity *entry; 679 u_int i; 680 681 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 682 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 683 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 684 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 685 full_id = ahc_compose_id(device, vendor, subdevice, subvendor); 686 687 /* 688 * If the second function is not hooked up, ignore it. 689 * Unfortunately, not all MB vendors implement the 690 * subdevice ID as per the Adaptec spec, so do our best 691 * to sanity check it prior to accepting the subdevice 692 * ID as valid. 693 */ 694 if (ahc_get_pci_function(pci) > 0 695 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice) 696 && SUBID_9005_MFUNCENB(subdevice) == 0) 697 return (NULL); 698 699 for (i = 0; i < ahc_num_pci_devs; i++) { 700 entry = &ahc_pci_ident_table[i]; 701 if (entry->full_id == (full_id & entry->id_mask)) { 702 /* Honor exclusion entries. */ 703 if (entry->name == NULL) 704 return (NULL); 705 return (entry); 706 } 707 } 708 return (NULL); 709} 710 711int 712ahc_pci_config(struct ahc_softc *ahc, const struct ahc_pci_identity *entry) 713{ 714 u_int command; 715 u_int our_id; 716 u_int sxfrctl1; 717 u_int scsiseq; 718 u_int dscommand0; 719 uint32_t devconfig; 720 int error; 721 uint8_t sblkctl; 722 723 our_id = 0; 724 error = entry->setup(ahc); 725 if (error != 0) 726 return (error); 727 ahc->chip |= AHC_PCI; 728 ahc->description = entry->name; 729 730 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0); 731 732 error = ahc_pci_map_registers(ahc); 733 if (error != 0) 734 return (error); 735 736 /* 737 * Before we continue probing the card, ensure that 738 * its interrupts are *disabled*. We don't want 739 * a misstep to hang the machine in an interrupt 740 * storm. 741 */ 742 ahc_intr_enable(ahc, FALSE); 743 744 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 745 746 /* 747 * If we need to support high memory, enable dual 748 * address cycles. This bit must be set to enable 749 * high address bit generation even if we are on a 750 * 64bit bus (PCI64BIT set in devconfig). 751 */ 752 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 753 754 if (bootverbose) 755 printf("%s: Enabling 39Bit Addressing\n", 756 ahc_name(ahc)); 757 devconfig |= DACEN; 758 } 759 760 /* Ensure that pci error generation, a test feature, is disabled. */ 761 devconfig |= PCIERRGENDIS; 762 763 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 764 765 /* Ensure busmastering is enabled */ 766 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 767 command |= PCIM_CMD_BUSMASTEREN; 768 769 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 770 771 /* On all PCI adapters, we allow SCB paging */ 772 ahc->flags |= AHC_PAGESCBS; 773 774 error = ahc_softc_init(ahc); 775 if (error != 0) 776 return (error); 777 778 /* 779 * Disable PCI parity error checking. Users typically 780 * do this to work around broken PCI chipsets that get 781 * the parity timing wrong and thus generate lots of spurious 782 * errors. The chip only allows us to disable *all* parity 783 * error reporting when doing this, so CIO bus, scb ram, and 784 * scratch ram parity errors will be ignored too. 785 */ 786 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 787 ahc->seqctl |= FAILDIS; 788 789 ahc->bus_intr = ahc_pci_intr; 790 ahc->bus_chip_init = ahc_pci_chip_init; 791 792 /* Remeber how the card was setup in case there is no SEEPROM */ 793 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 794 ahc_pause(ahc); 795 if ((ahc->features & AHC_ULTRA2) != 0) 796 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 797 else 798 our_id = ahc_inb(ahc, SCSIID) & OID; 799 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 800 scsiseq = ahc_inb(ahc, SCSISEQ); 801 } else { 802 sxfrctl1 = STPWEN; 803 our_id = 7; 804 scsiseq = 0; 805 } 806 807 error = ahc_reset(ahc, /*reinit*/FALSE); 808 if (error != 0) 809 return (ENXIO); 810 811 if ((ahc->features & AHC_DT) != 0) { 812 u_int sfunct; 813 814 /* Perform ALT-Mode Setup */ 815 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 816 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 817 ahc_outb(ahc, OPTIONMODE, 818 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 819 ahc_outb(ahc, SFUNCT, sfunct); 820 821 /* Normal mode setup */ 822 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 823 |TARGCRCENDEN); 824 } 825 826 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 827 dscommand0 |= MPARCKEN|CACHETHEN; 828 if ((ahc->features & AHC_ULTRA2) != 0) { 829 830 /* 831 * DPARCKEN doesn't work correctly on 832 * some MBs so don't use it. 833 */ 834 dscommand0 &= ~DPARCKEN; 835 } 836 837 /* 838 * Handle chips that must have cache line 839 * streaming (dis/en)abled. 840 */ 841 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 842 dscommand0 |= CACHETHEN; 843 844 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 845 dscommand0 &= ~CACHETHEN; 846 847 ahc_outb(ahc, DSCOMMAND0, dscommand0); 848 849 ahc->pci_cachesize = 850 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 851 /*bytes*/1) & CACHESIZE; 852 ahc->pci_cachesize *= 4; 853 854 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 855 && ahc->pci_cachesize == 4) { 856 857 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 858 0, /*bytes*/1); 859 ahc->pci_cachesize = 0; 860 } 861 862 /* 863 * We cannot perform ULTRA speeds without the presense 864 * of the external precision resistor. 865 */ 866 if ((ahc->features & AHC_ULTRA) != 0) { 867 uint32_t devconfig; 868 869 devconfig = ahc_pci_read_config(ahc->dev_softc, 870 DEVCONFIG, /*bytes*/4); 871 if ((devconfig & REXTVALID) == 0) 872 ahc->features &= ~AHC_ULTRA; 873 } 874 875 /* See if we have a SEEPROM and perform auto-term */ 876 check_extport(ahc, &sxfrctl1); 877 878 /* 879 * Take the LED out of diagnostic mode 880 */ 881 sblkctl = ahc_inb(ahc, SBLKCTL); 882 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 883 884 if ((ahc->features & AHC_ULTRA2) != 0) { 885 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 886 } else { 887 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 888 } 889 890 if (ahc->flags & AHC_USEDEFAULTS) { 891 /* 892 * PCI Adapter default setup 893 * Should only be used if the adapter does not have 894 * a SEEPROM. 895 */ 896 /* See if someone else set us up already */ 897 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 898 && scsiseq != 0) { 899 printf("%s: Using left over BIOS settings\n", 900 ahc_name(ahc)); 901 ahc->flags &= ~AHC_USEDEFAULTS; 902 ahc->flags |= AHC_BIOS_ENABLED; 903 } else { 904 /* 905 * Assume only one connector and always turn 906 * on termination. 907 */ 908 our_id = 0x07; 909 sxfrctl1 = STPWEN; 910 } 911 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 912 913 ahc->our_id = our_id; 914 } 915 916 /* 917 * Take a look to see if we have external SRAM. 918 * We currently do not attempt to use SRAM that is 919 * shared among multiple controllers. 920 */ 921 ahc_probe_ext_scbram(ahc); 922 923 /* 924 * Record our termination setting for the 925 * generic initialization routine. 926 */ 927 if ((sxfrctl1 & STPWEN) != 0) 928 ahc->flags |= AHC_TERM_ENB_A; 929 930 /* 931 * Save chip register configuration data for chip resets 932 * that occur during runtime and resume events. 933 */ 934 ahc->bus_softc.pci_softc.devconfig = 935 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 936 ahc->bus_softc.pci_softc.command = 937 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 938 ahc->bus_softc.pci_softc.csize_lattime = 939 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1); 940 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 941 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 942 if ((ahc->features & AHC_DT) != 0) { 943 u_int sfunct; 944 945 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 946 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 947 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); 948 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); 949 ahc_outb(ahc, SFUNCT, sfunct); 950 ahc->bus_softc.pci_softc.crccontrol1 = 951 ahc_inb(ahc, CRCCONTROL1); 952 } 953 if ((ahc->features & AHC_MULTI_FUNC) != 0) 954 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); 955 956 if ((ahc->features & AHC_ULTRA2) != 0) 957 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 958 959 /* Core initialization */ 960 error = ahc_init(ahc); 961 if (error != 0) 962 return (error); 963 964 /* 965 * Allow interrupts now that we are completely setup. 966 */ 967 error = ahc_pci_map_int(ahc); 968 if (error != 0) 969 return (error); 970 971 ahc->init_level++; 972 return (0); 973} 974 975/* 976 * Test for the presense of external sram in an 977 * "unshared" configuration. 978 */ 979static int 980ahc_ext_scbram_present(struct ahc_softc *ahc) 981{ 982 u_int chip; 983 int ramps; 984 int single_user; 985 uint32_t devconfig; 986 987 chip = ahc->chip & AHC_CHIPID_MASK; 988 devconfig = ahc_pci_read_config(ahc->dev_softc, 989 DEVCONFIG, /*bytes*/4); 990 single_user = (devconfig & MPORTMODE) != 0; 991 992 if ((ahc->features & AHC_ULTRA2) != 0) 993 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 994 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 995 /* 996 * External SCBRAM arbitration is flakey 997 * on these chips. Unfortunately this means 998 * we don't use the extra SCB ram space on the 999 * 3940AUW. 1000 */ 1001 ramps = 0; 1002 else if (chip >= AHC_AIC7870) 1003 ramps = (devconfig & RAMPSM) != 0; 1004 else 1005 ramps = 0; 1006 1007 if (ramps && single_user) 1008 return (1); 1009 return (0); 1010} 1011 1012/* 1013 * Enable external scbram. 1014 */ 1015static void 1016ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1017 int fast, int large) 1018{ 1019 uint32_t devconfig; 1020 1021 if (ahc->features & AHC_MULTI_FUNC) { 1022 /* 1023 * Set the SCB Base addr (highest address bit) 1024 * depending on which channel we are. 1025 */ 1026 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 1027 } 1028 1029 ahc->flags &= ~AHC_LSCBS_ENABLED; 1030 if (large) 1031 ahc->flags |= AHC_LSCBS_ENABLED; 1032 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1033 if ((ahc->features & AHC_ULTRA2) != 0) { 1034 u_int dscommand0; 1035 1036 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1037 if (enable) 1038 dscommand0 &= ~INTSCBRAMSEL; 1039 else 1040 dscommand0 |= INTSCBRAMSEL; 1041 if (large) 1042 dscommand0 &= ~USCBSIZE32; 1043 else 1044 dscommand0 |= USCBSIZE32; 1045 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1046 } else { 1047 if (fast) 1048 devconfig &= ~EXTSCBTIME; 1049 else 1050 devconfig |= EXTSCBTIME; 1051 if (enable) 1052 devconfig &= ~SCBRAMSEL; 1053 else 1054 devconfig |= SCBRAMSEL; 1055 if (large) 1056 devconfig &= ~SCBSIZE32; 1057 else 1058 devconfig |= SCBSIZE32; 1059 } 1060 if (pcheck) 1061 devconfig |= EXTSCBPEN; 1062 else 1063 devconfig &= ~EXTSCBPEN; 1064 1065 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1066} 1067 1068/* 1069 * Take a look to see if we have external SRAM. 1070 * We currently do not attempt to use SRAM that is 1071 * shared among multiple controllers. 1072 */ 1073static void 1074ahc_probe_ext_scbram(struct ahc_softc *ahc) 1075{ 1076 int num_scbs; 1077 int test_num_scbs; 1078 int enable; 1079 int pcheck; 1080 int fast; 1081 int large; 1082 1083 enable = FALSE; 1084 pcheck = FALSE; 1085 fast = FALSE; 1086 large = FALSE; 1087 num_scbs = 0; 1088 1089 if (ahc_ext_scbram_present(ahc) == 0) 1090 goto done; 1091 1092 /* 1093 * Probe for the best parameters to use. 1094 */ 1095 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1096 num_scbs = ahc_probe_scbs(ahc); 1097 if (num_scbs == 0) { 1098 /* The SRAM wasn't really present. */ 1099 goto done; 1100 } 1101 enable = TRUE; 1102 1103 /* 1104 * Clear any outstanding parity error 1105 * and ensure that parity error reporting 1106 * is enabled. 1107 */ 1108 ahc_outb(ahc, SEQCTL, 0); 1109 ahc_outb(ahc, CLRINT, CLRPARERR); 1110 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1111 1112 /* Now see if we can do parity */ 1113 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1114 num_scbs = ahc_probe_scbs(ahc); 1115 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1116 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1117 pcheck = TRUE; 1118 1119 /* Clear any resulting parity error */ 1120 ahc_outb(ahc, CLRINT, CLRPARERR); 1121 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1122 1123 /* Now see if we can do fast timing */ 1124 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1125 test_num_scbs = ahc_probe_scbs(ahc); 1126 if (test_num_scbs == num_scbs 1127 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1128 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1129 fast = TRUE; 1130 1131 /* 1132 * See if we can use large SCBs and still maintain 1133 * the same overall count of SCBs. 1134 */ 1135 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1136 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1137 test_num_scbs = ahc_probe_scbs(ahc); 1138 if (test_num_scbs >= num_scbs) { 1139 large = TRUE; 1140 num_scbs = test_num_scbs; 1141 if (num_scbs >= 64) { 1142 /* 1143 * We have enough space to move the 1144 * "busy targets table" into SCB space 1145 * and make it qualify all the way to the 1146 * lun level. 1147 */ 1148 ahc->flags |= AHC_SCB_BTT; 1149 } 1150 } 1151 } 1152done: 1153 /* 1154 * Disable parity error reporting until we 1155 * can load instruction ram. 1156 */ 1157 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1158 /* Clear any latched parity error */ 1159 ahc_outb(ahc, CLRINT, CLRPARERR); 1160 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1161 if (bootverbose && enable) { 1162 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1163 ahc_name(ahc), fast ? "fast" : "slow", 1164 pcheck ? ", parity checking enabled" : "", 1165 large ? 64 : 32); 1166 } 1167 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1168} 1169 1170/* 1171 * Perform some simple tests that should catch situations where 1172 * our registers are invalidly mapped. 1173 */ 1174int 1175ahc_pci_test_register_access(struct ahc_softc *ahc) 1176{ 1177 int error; 1178 u_int status1; 1179 uint32_t cmd; 1180 uint8_t hcntrl; 1181 1182 error = EIO; 1183 1184 /* 1185 * Enable PCI error interrupt status, but suppress NMIs 1186 * generated by SERR raised due to target aborts. 1187 */ 1188 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 1189 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 1190 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 1191 1192 /* 1193 * First a simple test to see if any 1194 * registers can be read. Reading 1195 * HCNTRL has no side effects and has 1196 * at least one bit that is guaranteed to 1197 * be zero so it is a good register to 1198 * use for this test. 1199 */ 1200 hcntrl = ahc_inb(ahc, HCNTRL); 1201 1202 if (hcntrl == 0xFF) 1203 goto fail; 1204 1205 if ((hcntrl & CHIPRST) != 0) { 1206 /* 1207 * The chip has not been initialized since 1208 * PCI/EISA/VLB bus reset. Don't trust 1209 * "left over BIOS data". 1210 */ 1211 ahc->flags |= AHC_NO_BIOS_INIT; 1212 } 1213 1214 /* 1215 * Next create a situation where write combining 1216 * or read prefetching could be initiated by the 1217 * CPU or host bridge. Our device does not support 1218 * either, so look for data corruption and/or flagged 1219 * PCI errors. First pause without causing another 1220 * chip reset. 1221 */ 1222 hcntrl &= ~CHIPRST; 1223 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1224 while (ahc_is_paused(ahc) == 0) 1225 ; 1226 1227 /* Clear any PCI errors that occurred before our driver attached. */ 1228 status1 = ahc_pci_read_config(ahc->dev_softc, 1229 PCIR_STATUS + 1, /*bytes*/1); 1230 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1231 status1, /*bytes*/1); 1232 ahc_outb(ahc, CLRINT, CLRPARERR); 1233 1234 ahc_outb(ahc, SEQCTL, PERRORDIS); 1235 ahc_outb(ahc, SCBPTR, 0); 1236 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1237 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1238 goto fail; 1239 1240 status1 = ahc_pci_read_config(ahc->dev_softc, 1241 PCIR_STATUS + 1, /*bytes*/1); 1242 if ((status1 & STA) != 0) 1243 goto fail; 1244 1245 error = 0; 1246 1247fail: 1248 /* Silently clear any latched errors. */ 1249 status1 = ahc_pci_read_config(ahc->dev_softc, 1250 PCIR_STATUS + 1, /*bytes*/1); 1251 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1252 status1, /*bytes*/1); 1253 ahc_outb(ahc, CLRINT, CLRPARERR); 1254 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1255 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1256 return (error); 1257} 1258 1259/* 1260 * Check the external port logic for a serial eeprom 1261 * and termination/cable detection contrls. 1262 */ 1263static void 1264check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1265{ 1266 struct seeprom_descriptor sd; 1267 struct seeprom_config *sc; 1268 int have_seeprom; 1269 int have_autoterm; 1270 1271 sd.sd_ahc = ahc; 1272 sd.sd_control_offset = SEECTL; 1273 sd.sd_status_offset = SEECTL; 1274 sd.sd_dataout_offset = SEECTL; 1275 sc = ahc->seep_config; 1276 1277 /* 1278 * For some multi-channel devices, the c46 is simply too 1279 * small to work. For the other controller types, we can 1280 * get our information from either SEEPROM type. Set the 1281 * type to start our probe with accordingly. 1282 */ 1283 if (ahc->flags & AHC_LARGE_SEEPROM) 1284 sd.sd_chip = C56_66; 1285 else 1286 sd.sd_chip = C46; 1287 1288 sd.sd_MS = SEEMS; 1289 sd.sd_RDY = SEERDY; 1290 sd.sd_CS = SEECS; 1291 sd.sd_CK = SEECK; 1292 sd.sd_DO = SEEDO; 1293 sd.sd_DI = SEEDI; 1294 1295 have_seeprom = ahc_acquire_seeprom(ahc, &sd); 1296 if (have_seeprom) { 1297 1298 if (bootverbose) 1299 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1300 1301 for (;;) { 1302 u_int start_addr; 1303 1304 start_addr = 32 * (ahc->channel - 'A'); 1305 1306 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc, 1307 start_addr, 1308 sizeof(*sc)/2); 1309 1310 if (have_seeprom) 1311 have_seeprom = ahc_verify_cksum(sc); 1312 1313 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1314 if (bootverbose) { 1315 if (have_seeprom == 0) 1316 printf ("checksum error\n"); 1317 else 1318 printf ("done.\n"); 1319 } 1320 break; 1321 } 1322 sd.sd_chip = C56_66; 1323 } 1324 ahc_release_seeprom(&sd); 1325 1326 /* Remember the SEEPROM type for later */ 1327 if (sd.sd_chip == C56_66) 1328 ahc->flags |= AHC_LARGE_SEEPROM; 1329 } 1330 1331 if (!have_seeprom) { 1332 /* 1333 * Pull scratch ram settings and treat them as 1334 * if they are the contents of an seeprom if 1335 * the 'ADPT' signature is found in SCB2. 1336 * We manually compose the data as 16bit values 1337 * to avoid endian issues. 1338 */ 1339 ahc_outb(ahc, SCBPTR, 2); 1340 if (ahc_inb(ahc, SCB_BASE) == 'A' 1341 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1342 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1343 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1344 uint16_t *sc_data; 1345 int i; 1346 1347 sc_data = (uint16_t *)sc; 1348 for (i = 0; i < 32; i++, sc_data++) { 1349 int j; 1350 1351 j = i * 2; 1352 *sc_data = ahc_inb(ahc, SRAM_BASE + j) 1353 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1354 } 1355 have_seeprom = ahc_verify_cksum(sc); 1356 if (have_seeprom) 1357 ahc->flags |= AHC_SCB_CONFIG_USED; 1358 } 1359 /* 1360 * Clear any SCB parity errors in case this data and 1361 * its associated parity was not initialized by the BIOS 1362 */ 1363 ahc_outb(ahc, CLRINT, CLRPARERR); 1364 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1365 } 1366 1367 if (!have_seeprom) { 1368 if (bootverbose) 1369 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1370 ahc->flags |= AHC_USEDEFAULTS; 1371 free(ahc->seep_config, M_DEVBUF); 1372 ahc->seep_config = NULL; 1373 sc = NULL; 1374 } else { 1375 ahc_parse_pci_eeprom(ahc, sc); 1376 } 1377 1378 /* 1379 * Cards that have the external logic necessary to talk to 1380 * a SEEPROM, are almost certain to have the remaining logic 1381 * necessary for auto-termination control. This assumption 1382 * hasn't failed yet... 1383 */ 1384 have_autoterm = have_seeprom; 1385 1386 /* 1387 * Some low-cost chips have SEEPROM and auto-term control built 1388 * in, instead of using a GAL. They can tell us directly 1389 * if the termination logic is enabled. 1390 */ 1391 if ((ahc->features & AHC_SPIOCAP) != 0) { 1392 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0) 1393 have_autoterm = FALSE; 1394 } 1395 1396 if (have_autoterm) { 1397 ahc->flags |= AHC_HAS_TERM_LOGIC; 1398 ahc_acquire_seeprom(ahc, &sd); 1399 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1); 1400 ahc_release_seeprom(&sd); 1401 } else if (have_seeprom) { 1402 *sxfrctl1 &= ~STPWEN; 1403 if ((sc->adapter_control & CFSTERM) != 0) 1404 *sxfrctl1 |= STPWEN; 1405 if (bootverbose) 1406 printf("%s: Low byte termination %sabled\n", 1407 ahc_name(ahc), 1408 (*sxfrctl1 & STPWEN) ? "en" : "dis"); 1409 } 1410} 1411 1412static void 1413ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc) 1414{ 1415 /* 1416 * Put the data we've collected down into SRAM 1417 * where ahc_init will find it. 1418 */ 1419 int i; 1420 int max_targ = sc->max_targets & CFMAXTARG; 1421 u_int scsi_conf; 1422 uint16_t discenable; 1423 uint16_t ultraenb; 1424 1425 discenable = 0; 1426 ultraenb = 0; 1427 if ((sc->adapter_control & CFULTRAEN) != 0) { 1428 /* 1429 * Determine if this adapter has a "newstyle" 1430 * SEEPROM format. 1431 */ 1432 for (i = 0; i < max_targ; i++) { 1433 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) { 1434 ahc->flags |= AHC_NEWEEPROM_FMT; 1435 break; 1436 } 1437 } 1438 } 1439 1440 for (i = 0; i < max_targ; i++) { 1441 u_int scsirate; 1442 uint16_t target_mask; 1443 1444 target_mask = 0x01 << i; 1445 if (sc->device_flags[i] & CFDISC) 1446 discenable |= target_mask; 1447 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1448 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) 1449 ultraenb |= target_mask; 1450 } else if ((sc->adapter_control & CFULTRAEN) != 0) { 1451 ultraenb |= target_mask; 1452 } 1453 if ((sc->device_flags[i] & CFXFER) == 0x04 1454 && (ultraenb & target_mask) != 0) { 1455 /* Treat 10MHz as a non-ultra speed */ 1456 sc->device_flags[i] &= ~CFXFER; 1457 ultraenb &= ~target_mask; 1458 } 1459 if ((ahc->features & AHC_ULTRA2) != 0) { 1460 u_int offset; 1461 1462 if (sc->device_flags[i] & CFSYNCH) 1463 offset = MAX_OFFSET_ULTRA2; 1464 else 1465 offset = 0; 1466 ahc_outb(ahc, TARG_OFFSET + i, offset); 1467 1468 /* 1469 * The ultra enable bits contain the 1470 * high bit of the ultra2 sync rate 1471 * field. 1472 */ 1473 scsirate = (sc->device_flags[i] & CFXFER) 1474 | ((ultraenb & target_mask) ? 0x8 : 0x0); 1475 if (sc->device_flags[i] & CFWIDEB) 1476 scsirate |= WIDEXFER; 1477 } else { 1478 scsirate = (sc->device_flags[i] & CFXFER) << 4; 1479 if (sc->device_flags[i] & CFSYNCH) 1480 scsirate |= SOFS; 1481 if (sc->device_flags[i] & CFWIDEB) 1482 scsirate |= WIDEXFER; 1483 } 1484 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1485 } 1486 ahc->our_id = sc->brtime_id & CFSCSIID; 1487 1488 scsi_conf = (ahc->our_id & 0x7); 1489 if (sc->adapter_control & CFSPARITY) 1490 scsi_conf |= ENSPCHK; 1491 if (sc->adapter_control & CFRESETB) 1492 scsi_conf |= RESET_SCSI; 1493 1494 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1495 1496 if (sc->bios_control & CFEXTEND) 1497 ahc->flags |= AHC_EXTENDED_TRANS_A; 1498 1499 if (sc->bios_control & CFBIOSEN) 1500 ahc->flags |= AHC_BIOS_ENABLED; 1501 if (ahc->features & AHC_ULTRA 1502 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1503 /* Should we enable Ultra mode? */ 1504 if (!(sc->adapter_control & CFULTRAEN)) 1505 /* Treat us as a non-ultra card */ 1506 ultraenb = 0; 1507 } 1508 1509 if (sc->signature == CFSIGNATURE 1510 || sc->signature == CFSIGNATURE2) { 1511 uint32_t devconfig; 1512 1513 /* Honor the STPWLEVEL settings */ 1514 devconfig = ahc_pci_read_config(ahc->dev_softc, 1515 DEVCONFIG, /*bytes*/4); 1516 devconfig &= ~STPWLEVEL; 1517 if ((sc->bios_control & CFSTPWLEVEL) != 0) 1518 devconfig |= STPWLEVEL; 1519 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1520 devconfig, /*bytes*/4); 1521 } 1522 /* Set SCSICONF info */ 1523 ahc_outb(ahc, SCSICONF, scsi_conf); 1524 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1525 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1526 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1527 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1528} 1529 1530static void 1531configure_termination(struct ahc_softc *ahc, 1532 struct seeprom_descriptor *sd, 1533 u_int adapter_control, 1534 u_int *sxfrctl1) 1535{ 1536 uint8_t brddat; 1537 1538 brddat = 0; 1539 1540 /* 1541 * Update the settings in sxfrctl1 to match the 1542 * termination settings 1543 */ 1544 *sxfrctl1 = 0; 1545 1546 /* 1547 * SEECS must be on for the GALS to latch 1548 * the data properly. Be sure to leave MS 1549 * on or we will release the seeprom. 1550 */ 1551 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1552 if ((adapter_control & CFAUTOTERM) != 0 1553 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1554 int internal50_present; 1555 int internal68_present; 1556 int externalcable_present; 1557 int eeprom_present; 1558 int enableSEC_low; 1559 int enableSEC_high; 1560 int enablePRI_low; 1561 int enablePRI_high; 1562 int sum; 1563 1564 enableSEC_low = 0; 1565 enableSEC_high = 0; 1566 enablePRI_low = 0; 1567 enablePRI_high = 0; 1568 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1569 ahc_new_term_detect(ahc, &enableSEC_low, 1570 &enableSEC_high, 1571 &enablePRI_low, 1572 &enablePRI_high, 1573 &eeprom_present); 1574 if ((adapter_control & CFSEAUTOTERM) == 0) { 1575 if (bootverbose) 1576 printf("%s: Manual SE Termination\n", 1577 ahc_name(ahc)); 1578 enableSEC_low = (adapter_control & CFSELOWTERM); 1579 enableSEC_high = 1580 (adapter_control & CFSEHIGHTERM); 1581 } 1582 if ((adapter_control & CFAUTOTERM) == 0) { 1583 if (bootverbose) 1584 printf("%s: Manual LVD Termination\n", 1585 ahc_name(ahc)); 1586 enablePRI_low = (adapter_control & CFSTERM); 1587 enablePRI_high = (adapter_control & CFWSTERM); 1588 } 1589 /* Make the table calculations below happy */ 1590 internal50_present = 0; 1591 internal68_present = 1; 1592 externalcable_present = 1; 1593 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1594 aic785X_cable_detect(ahc, &internal50_present, 1595 &externalcable_present, 1596 &eeprom_present); 1597 /* Can never support a wide connector. */ 1598 internal68_present = 0; 1599 } else { 1600 aic787X_cable_detect(ahc, &internal50_present, 1601 &internal68_present, 1602 &externalcable_present, 1603 &eeprom_present); 1604 } 1605 1606 if ((ahc->features & AHC_WIDE) == 0) 1607 internal68_present = 0; 1608 1609 if (bootverbose 1610 && (ahc->features & AHC_ULTRA2) == 0) { 1611 printf("%s: internal 50 cable %s present", 1612 ahc_name(ahc), 1613 internal50_present ? "is":"not"); 1614 1615 if ((ahc->features & AHC_WIDE) != 0) 1616 printf(", internal 68 cable %s present", 1617 internal68_present ? "is":"not"); 1618 printf("\n%s: external cable %s present\n", 1619 ahc_name(ahc), 1620 externalcable_present ? "is":"not"); 1621 } 1622 if (bootverbose) 1623 printf("%s: BIOS eeprom %s present\n", 1624 ahc_name(ahc), eeprom_present ? "is" : "not"); 1625 1626 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1627 /* 1628 * The 50 pin connector is a separate bus, 1629 * so force it to always be terminated. 1630 * In the future, perform current sensing 1631 * to determine if we are in the middle of 1632 * a properly terminated bus. 1633 */ 1634 internal50_present = 0; 1635 } 1636 1637 /* 1638 * Now set the termination based on what 1639 * we found. 1640 * Flash Enable = BRDDAT7 1641 * Secondary High Term Enable = BRDDAT6 1642 * Secondary Low Term Enable = BRDDAT5 (7890) 1643 * Primary High Term Enable = BRDDAT4 (7890) 1644 */ 1645 if ((ahc->features & AHC_ULTRA2) == 0 1646 && (internal50_present != 0) 1647 && (internal68_present != 0) 1648 && (externalcable_present != 0)) { 1649 printf("%s: Illegal cable configuration!!. " 1650 "Only two connectors on the " 1651 "adapter may be used at a " 1652 "time!\n", ahc_name(ahc)); 1653 1654 /* 1655 * Pretend there are no cables in the hope 1656 * that having all of the termination on 1657 * gives us a more stable bus. 1658 */ 1659 internal50_present = 0; 1660 internal68_present = 0; 1661 externalcable_present = 0; 1662 } 1663 1664 if ((ahc->features & AHC_WIDE) != 0 1665 && ((externalcable_present == 0) 1666 || (internal68_present == 0) 1667 || (enableSEC_high != 0))) { 1668 brddat |= BRDDAT6; 1669 if (bootverbose) { 1670 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1671 printf("%s: 68 pin termination " 1672 "Enabled\n", ahc_name(ahc)); 1673 else 1674 printf("%s: %sHigh byte termination " 1675 "Enabled\n", ahc_name(ahc), 1676 enableSEC_high ? "Secondary " 1677 : ""); 1678 } 1679 } 1680 1681 sum = internal50_present + internal68_present 1682 + externalcable_present; 1683 if (sum < 2 || (enableSEC_low != 0)) { 1684 if ((ahc->features & AHC_ULTRA2) != 0) 1685 brddat |= BRDDAT5; 1686 else 1687 *sxfrctl1 |= STPWEN; 1688 if (bootverbose) { 1689 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1690 printf("%s: 50 pin termination " 1691 "Enabled\n", ahc_name(ahc)); 1692 else 1693 printf("%s: %sLow byte termination " 1694 "Enabled\n", ahc_name(ahc), 1695 enableSEC_low ? "Secondary " 1696 : ""); 1697 } 1698 } 1699 1700 if (enablePRI_low != 0) { 1701 *sxfrctl1 |= STPWEN; 1702 if (bootverbose) 1703 printf("%s: Primary Low Byte termination " 1704 "Enabled\n", ahc_name(ahc)); 1705 } 1706 1707 /* 1708 * Setup STPWEN before setting up the rest of 1709 * the termination per the tech note on the U160 cards. 1710 */ 1711 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1712 1713 if (enablePRI_high != 0) { 1714 brddat |= BRDDAT4; 1715 if (bootverbose) 1716 printf("%s: Primary High Byte " 1717 "termination Enabled\n", 1718 ahc_name(ahc)); 1719 } 1720 1721 write_brdctl(ahc, brddat); 1722 1723 } else { 1724 if ((adapter_control & CFSTERM) != 0) { 1725 *sxfrctl1 |= STPWEN; 1726 1727 if (bootverbose) 1728 printf("%s: %sLow byte termination Enabled\n", 1729 ahc_name(ahc), 1730 (ahc->features & AHC_ULTRA2) ? "Primary " 1731 : ""); 1732 } 1733 1734 if ((adapter_control & CFWSTERM) != 0 1735 && (ahc->features & AHC_WIDE) != 0) { 1736 brddat |= BRDDAT6; 1737 if (bootverbose) 1738 printf("%s: %sHigh byte termination Enabled\n", 1739 ahc_name(ahc), 1740 (ahc->features & AHC_ULTRA2) 1741 ? "Secondary " : ""); 1742 } 1743 1744 /* 1745 * Setup STPWEN before setting up the rest of 1746 * the termination per the tech note on the U160 cards. 1747 */ 1748 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1749 1750 if ((ahc->features & AHC_WIDE) != 0) 1751 write_brdctl(ahc, brddat); 1752 } 1753 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1754} 1755 1756static void 1757ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1758 int *enableSEC_high, int *enablePRI_low, 1759 int *enablePRI_high, int *eeprom_present) 1760{ 1761 uint8_t brdctl; 1762 1763 /* 1764 * BRDDAT7 = Eeprom 1765 * BRDDAT6 = Enable Secondary High Byte termination 1766 * BRDDAT5 = Enable Secondary Low Byte termination 1767 * BRDDAT4 = Enable Primary high byte termination 1768 * BRDDAT3 = Enable Primary low byte termination 1769 */ 1770 brdctl = read_brdctl(ahc); 1771 *eeprom_present = brdctl & BRDDAT7; 1772 *enableSEC_high = (brdctl & BRDDAT6); 1773 *enableSEC_low = (brdctl & BRDDAT5); 1774 *enablePRI_high = (brdctl & BRDDAT4); 1775 *enablePRI_low = (brdctl & BRDDAT3); 1776} 1777 1778static void 1779aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1780 int *internal68_present, int *externalcable_present, 1781 int *eeprom_present) 1782{ 1783 uint8_t brdctl; 1784 1785 /* 1786 * First read the status of our cables. 1787 * Set the rom bank to 0 since the 1788 * bank setting serves as a multiplexor 1789 * for the cable detection logic. 1790 * BRDDAT5 controls the bank switch. 1791 */ 1792 write_brdctl(ahc, 0); 1793 1794 /* 1795 * Now read the state of the internal 1796 * connectors. BRDDAT6 is INT50 and 1797 * BRDDAT7 is INT68. 1798 */ 1799 brdctl = read_brdctl(ahc); 1800 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1801 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1802 1803 /* 1804 * Set the rom bank to 1 and determine 1805 * the other signals. 1806 */ 1807 write_brdctl(ahc, BRDDAT5); 1808 1809 /* 1810 * Now read the state of the external 1811 * connectors. BRDDAT6 is EXT68 and 1812 * BRDDAT7 is EPROMPS. 1813 */ 1814 brdctl = read_brdctl(ahc); 1815 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1816 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1817} 1818 1819static void 1820aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1821 int *externalcable_present, int *eeprom_present) 1822{ 1823 uint8_t brdctl; 1824 uint8_t spiocap; 1825 1826 spiocap = ahc_inb(ahc, SPIOCAP); 1827 spiocap &= ~SOFTCMDEN; 1828 spiocap |= EXT_BRDCTL; 1829 ahc_outb(ahc, SPIOCAP, spiocap); 1830 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1831 ahc_flush_device_writes(ahc); 1832 ahc_delay(500); 1833 ahc_outb(ahc, BRDCTL, 0); 1834 ahc_flush_device_writes(ahc); 1835 ahc_delay(500); 1836 brdctl = ahc_inb(ahc, BRDCTL); 1837 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1838 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1839 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1840} 1841 1842int 1843ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1844{ 1845 int wait; 1846 1847 if ((ahc->features & AHC_SPIOCAP) != 0 1848 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1849 return (0); 1850 1851 /* 1852 * Request access of the memory port. When access is 1853 * granted, SEERDY will go high. We use a 1 second 1854 * timeout which should be near 1 second more than 1855 * is needed. Reason: after the chip reset, there 1856 * should be no contention. 1857 */ 1858 SEEPROM_OUTB(sd, sd->sd_MS); 1859 wait = 1000; /* 1 second timeout in msec */ 1860 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1861 ahc_delay(1000); /* delay 1 msec */ 1862 } 1863 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1864 SEEPROM_OUTB(sd, 0); 1865 return (0); 1866 } 1867 return(1); 1868} 1869 1870void 1871ahc_release_seeprom(struct seeprom_descriptor *sd) 1872{ 1873 /* Release access to the memory port and the serial EEPROM. */ 1874 SEEPROM_OUTB(sd, 0); 1875} 1876 1877static void 1878write_brdctl(struct ahc_softc *ahc, uint8_t value) 1879{ 1880 uint8_t brdctl; 1881 1882 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1883 brdctl = BRDSTB; 1884 if (ahc->channel == 'B') 1885 brdctl |= BRDCS; 1886 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1887 brdctl = 0; 1888 } else { 1889 brdctl = BRDSTB|BRDCS; 1890 } 1891 ahc_outb(ahc, BRDCTL, brdctl); 1892 ahc_flush_device_writes(ahc); 1893 brdctl |= value; 1894 ahc_outb(ahc, BRDCTL, brdctl); 1895 ahc_flush_device_writes(ahc); 1896 if ((ahc->features & AHC_ULTRA2) != 0) 1897 brdctl |= BRDSTB_ULTRA2; 1898 else 1899 brdctl &= ~BRDSTB; 1900 ahc_outb(ahc, BRDCTL, brdctl); 1901 ahc_flush_device_writes(ahc); 1902 if ((ahc->features & AHC_ULTRA2) != 0) 1903 brdctl = 0; 1904 else 1905 brdctl &= ~BRDCS; 1906 ahc_outb(ahc, BRDCTL, brdctl); 1907} 1908 1909static uint8_t 1910read_brdctl(struct ahc_softc *ahc) 1911{ 1912 uint8_t brdctl; 1913 uint8_t value; 1914 1915 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1916 brdctl = BRDRW; 1917 if (ahc->channel == 'B') 1918 brdctl |= BRDCS; 1919 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1920 brdctl = BRDRW_ULTRA2; 1921 } else { 1922 brdctl = BRDRW|BRDCS; 1923 } 1924 ahc_outb(ahc, BRDCTL, brdctl); 1925 ahc_flush_device_writes(ahc); 1926 value = ahc_inb(ahc, BRDCTL); 1927 ahc_outb(ahc, BRDCTL, 0); 1928 return (value); 1929} 1930 1931static void 1932ahc_pci_intr(struct ahc_softc *ahc) 1933{ 1934 u_int error; 1935 u_int status1; 1936 1937 error = ahc_inb(ahc, ERROR); 1938 if ((error & PCIERRSTAT) == 0) 1939 return; 1940 1941 status1 = ahc_pci_read_config(ahc->dev_softc, 1942 PCIR_STATUS + 1, /*bytes*/1); 1943 1944 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1945 ahc_name(ahc), 1946 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1947 1948 if (status1 & DPE) { 1949 ahc->pci_target_perr_count++; 1950 printf("%s: Data Parity Error Detected during address " 1951 "or write data phase\n", ahc_name(ahc)); 1952 } 1953 if (status1 & SSE) { 1954 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1955 } 1956 if (status1 & RMA) { 1957 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1958 } 1959 if (status1 & RTA) { 1960 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1961 } 1962 if (status1 & STA) { 1963 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1964 } 1965 if (status1 & DPR) { 1966 printf("%s: Data Parity Error has been reported via PERR#\n", 1967 ahc_name(ahc)); 1968 } 1969 1970 /* Clear latched errors. */ 1971 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1972 status1, /*bytes*/1); 1973 1974 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1975 printf("%s: Latched PCIERR interrupt with " 1976 "no status bits set\n", ahc_name(ahc)); 1977 } else { 1978 ahc_outb(ahc, CLRINT, CLRPARERR); 1979 } 1980 1981 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) { 1982 printf( 1983"%s: WARNING WARNING WARNING WARNING\n" 1984"%s: Too many PCI parity errors observed as a target.\n" 1985"%s: Some device on this bus is generating bad parity.\n" 1986"%s: This is an error *observed by*, not *generated by*, this controller.\n" 1987"%s: PCI parity error checking has been disabled.\n" 1988"%s: WARNING WARNING WARNING WARNING\n", 1989 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc), 1990 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc)); 1991 ahc->seqctl |= FAILDIS; 1992 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1993 } 1994 ahc_unpause(ahc); 1995} 1996 1997static int 1998ahc_pci_chip_init(struct ahc_softc *ahc) 1999{ 2000 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); 2001 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); 2002 if ((ahc->features & AHC_DT) != 0) { 2003 u_int sfunct; 2004 2005 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 2006 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 2007 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); 2008 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); 2009 ahc_outb(ahc, SFUNCT, sfunct); 2010 ahc_outb(ahc, CRCCONTROL1, 2011 ahc->bus_softc.pci_softc.crccontrol1); 2012 } 2013 if ((ahc->features & AHC_MULTI_FUNC) != 0) 2014 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); 2015 2016 if ((ahc->features & AHC_ULTRA2) != 0) 2017 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); 2018 2019 return (ahc_chip_init(ahc)); 2020} 2021 2022#ifdef CONFIG_PM 2023void 2024ahc_pci_resume(struct ahc_softc *ahc) 2025{ 2026 /* 2027 * We assume that the OS has restored our register 2028 * mappings, etc. Just update the config space registers 2029 * that the OS doesn't know about and rely on our chip 2030 * reset handler to handle the rest. 2031 */ 2032 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 2033 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4); 2034 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 2035 ahc->bus_softc.pci_softc.command, /*bytes*/1); 2036 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 2037 ahc->bus_softc.pci_softc.csize_lattime, /*bytes*/1); 2038 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) { 2039 struct seeprom_descriptor sd; 2040 u_int sxfrctl1; 2041 2042 sd.sd_ahc = ahc; 2043 sd.sd_control_offset = SEECTL; 2044 sd.sd_status_offset = SEECTL; 2045 sd.sd_dataout_offset = SEECTL; 2046 2047 ahc_acquire_seeprom(ahc, &sd); 2048 configure_termination(ahc, &sd, 2049 ahc->seep_config->adapter_control, 2050 &sxfrctl1); 2051 ahc_release_seeprom(&sd); 2052 } 2053} 2054#endif 2055 2056static int 2057ahc_aic785X_setup(struct ahc_softc *ahc) 2058{ 2059 ahc_dev_softc_t pci; 2060 uint8_t rev; 2061 2062 pci = ahc->dev_softc; 2063 ahc->channel = 'A'; 2064 ahc->chip = AHC_AIC7850; 2065 ahc->features = AHC_AIC7850_FE; 2066 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2067 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2068 if (rev >= 1) 2069 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2070 ahc->instruction_ram_size = 512; 2071 return (0); 2072} 2073 2074static int 2075ahc_aic7860_setup(struct ahc_softc *ahc) 2076{ 2077 ahc_dev_softc_t pci; 2078 uint8_t rev; 2079 2080 pci = ahc->dev_softc; 2081 ahc->channel = 'A'; 2082 ahc->chip = AHC_AIC7860; 2083 ahc->features = AHC_AIC7860_FE; 2084 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2085 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2086 if (rev >= 1) 2087 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2088 ahc->instruction_ram_size = 512; 2089 return (0); 2090} 2091 2092static int 2093ahc_apa1480_setup(struct ahc_softc *ahc) 2094{ 2095 int error; 2096 2097 error = ahc_aic7860_setup(ahc); 2098 if (error != 0) 2099 return (error); 2100 ahc->features |= AHC_REMOVABLE; 2101 return (0); 2102} 2103 2104static int 2105ahc_aic7870_setup(struct ahc_softc *ahc) 2106{ 2107 2108 ahc->channel = 'A'; 2109 ahc->chip = AHC_AIC7870; 2110 ahc->features = AHC_AIC7870_FE; 2111 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2112 ahc->instruction_ram_size = 512; 2113 return (0); 2114} 2115 2116static int 2117ahc_aic7870h_setup(struct ahc_softc *ahc) 2118{ 2119 int error = ahc_aic7870_setup(ahc); 2120 2121 ahc->features |= AHC_HVD; 2122 2123 return error; 2124} 2125 2126static int 2127ahc_aha394X_setup(struct ahc_softc *ahc) 2128{ 2129 int error; 2130 2131 error = ahc_aic7870_setup(ahc); 2132 if (error == 0) 2133 error = ahc_aha394XX_setup(ahc); 2134 return (error); 2135} 2136 2137static int 2138ahc_aha394Xh_setup(struct ahc_softc *ahc) 2139{ 2140 int error = ahc_aha394X_setup(ahc); 2141 2142 ahc->features |= AHC_HVD; 2143 2144 return error; 2145} 2146 2147static int 2148ahc_aha398X_setup(struct ahc_softc *ahc) 2149{ 2150 int error; 2151 2152 error = ahc_aic7870_setup(ahc); 2153 if (error == 0) 2154 error = ahc_aha398XX_setup(ahc); 2155 return (error); 2156} 2157 2158static int 2159ahc_aha494X_setup(struct ahc_softc *ahc) 2160{ 2161 int error; 2162 2163 error = ahc_aic7870_setup(ahc); 2164 if (error == 0) 2165 error = ahc_aha494XX_setup(ahc); 2166 return (error); 2167} 2168 2169static int 2170ahc_aha494Xh_setup(struct ahc_softc *ahc) 2171{ 2172 int error = ahc_aha494X_setup(ahc); 2173 2174 ahc->features |= AHC_HVD; 2175 2176 return error; 2177} 2178 2179static int 2180ahc_aic7880_setup(struct ahc_softc *ahc) 2181{ 2182 ahc_dev_softc_t pci; 2183 uint8_t rev; 2184 2185 pci = ahc->dev_softc; 2186 ahc->channel = 'A'; 2187 ahc->chip = AHC_AIC7880; 2188 ahc->features = AHC_AIC7880_FE; 2189 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 2190 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2191 if (rev >= 1) { 2192 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2193 } else { 2194 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2195 } 2196 ahc->instruction_ram_size = 512; 2197 return (0); 2198} 2199 2200static int 2201ahc_aic7880h_setup(struct ahc_softc *ahc) 2202{ 2203 int error = ahc_aic7880_setup(ahc); 2204 2205 ahc->features |= AHC_HVD; 2206 2207 return error; 2208} 2209 2210 2211static int 2212ahc_aha2940Pro_setup(struct ahc_softc *ahc) 2213{ 2214 2215 ahc->flags |= AHC_INT50_SPEEDFLEX; 2216 return (ahc_aic7880_setup(ahc)); 2217} 2218 2219static int 2220ahc_aha394XU_setup(struct ahc_softc *ahc) 2221{ 2222 int error; 2223 2224 error = ahc_aic7880_setup(ahc); 2225 if (error == 0) 2226 error = ahc_aha394XX_setup(ahc); 2227 return (error); 2228} 2229 2230static int 2231ahc_aha394XUh_setup(struct ahc_softc *ahc) 2232{ 2233 int error = ahc_aha394XU_setup(ahc); 2234 2235 ahc->features |= AHC_HVD; 2236 2237 return error; 2238} 2239 2240static int 2241ahc_aha398XU_setup(struct ahc_softc *ahc) 2242{ 2243 int error; 2244 2245 error = ahc_aic7880_setup(ahc); 2246 if (error == 0) 2247 error = ahc_aha398XX_setup(ahc); 2248 return (error); 2249} 2250 2251static int 2252ahc_aic7890_setup(struct ahc_softc *ahc) 2253{ 2254 ahc_dev_softc_t pci; 2255 uint8_t rev; 2256 2257 pci = ahc->dev_softc; 2258 ahc->channel = 'A'; 2259 ahc->chip = AHC_AIC7890; 2260 ahc->features = AHC_AIC7890_FE; 2261 ahc->flags |= AHC_NEWEEPROM_FMT; 2262 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2263 if (rev == 0) 2264 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 2265 ahc->instruction_ram_size = 768; 2266 return (0); 2267} 2268 2269static int 2270ahc_aic7892_setup(struct ahc_softc *ahc) 2271{ 2272 2273 ahc->channel = 'A'; 2274 ahc->chip = AHC_AIC7892; 2275 ahc->features = AHC_AIC7892_FE; 2276 ahc->flags |= AHC_NEWEEPROM_FMT; 2277 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2278 ahc->instruction_ram_size = 1024; 2279 return (0); 2280} 2281 2282static int 2283ahc_aic7895_setup(struct ahc_softc *ahc) 2284{ 2285 ahc_dev_softc_t pci; 2286 uint8_t rev; 2287 2288 pci = ahc->dev_softc; 2289 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2290 /* 2291 * The 'C' revision of the aic7895 has a few additional features. 2292 */ 2293 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2294 if (rev >= 4) { 2295 ahc->chip = AHC_AIC7895C; 2296 ahc->features = AHC_AIC7895C_FE; 2297 } else { 2298 u_int command; 2299 2300 ahc->chip = AHC_AIC7895; 2301 ahc->features = AHC_AIC7895_FE; 2302 2303 /* 2304 * The BIOS disables the use of MWI transactions 2305 * since it does not have the MWI bug work around 2306 * we have. Disabling MWI reduces performance, so 2307 * turn it on again. 2308 */ 2309 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2310 command |= PCIM_CMD_MWRICEN; 2311 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2312 ahc->bugs |= AHC_PCI_MWI_BUG; 2313 } 2314 /* 2315 * XXX Does CACHETHEN really not work??? What about PCI retry? 2316 * on C level chips. Need to test, but for now, play it safe. 2317 */ 2318 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2319 | AHC_CACHETHEN_BUG; 2320 2321#if 0 2322 uint32_t devconfig; 2323 2324 /* 2325 * Cachesize must also be zero due to stray DAC 2326 * problem when sitting behind some bridges. 2327 */ 2328 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 2329 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 2330 devconfig |= MRDCEN; 2331 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 2332#endif 2333 ahc->flags |= AHC_NEWEEPROM_FMT; 2334 ahc->instruction_ram_size = 512; 2335 return (0); 2336} 2337 2338static int 2339ahc_aic7895h_setup(struct ahc_softc *ahc) 2340{ 2341 int error = ahc_aic7895_setup(ahc); 2342 2343 ahc->features |= AHC_HVD; 2344 2345 return error; 2346} 2347 2348static int 2349ahc_aic7896_setup(struct ahc_softc *ahc) 2350{ 2351 ahc_dev_softc_t pci; 2352 2353 pci = ahc->dev_softc; 2354 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2355 ahc->chip = AHC_AIC7896; 2356 ahc->features = AHC_AIC7896_FE; 2357 ahc->flags |= AHC_NEWEEPROM_FMT; 2358 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2359 ahc->instruction_ram_size = 768; 2360 return (0); 2361} 2362 2363static int 2364ahc_aic7899_setup(struct ahc_softc *ahc) 2365{ 2366 ahc_dev_softc_t pci; 2367 2368 pci = ahc->dev_softc; 2369 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2370 ahc->chip = AHC_AIC7899; 2371 ahc->features = AHC_AIC7899_FE; 2372 ahc->flags |= AHC_NEWEEPROM_FMT; 2373 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2374 ahc->instruction_ram_size = 1024; 2375 return (0); 2376} 2377 2378static int 2379ahc_aha29160C_setup(struct ahc_softc *ahc) 2380{ 2381 int error; 2382 2383 error = ahc_aic7899_setup(ahc); 2384 if (error != 0) 2385 return (error); 2386 ahc->features |= AHC_REMOVABLE; 2387 return (0); 2388} 2389 2390static int 2391ahc_raid_setup(struct ahc_softc *ahc) 2392{ 2393 printf("RAID functionality unsupported\n"); 2394 return (ENXIO); 2395} 2396 2397static int 2398ahc_aha394XX_setup(struct ahc_softc *ahc) 2399{ 2400 ahc_dev_softc_t pci; 2401 2402 pci = ahc->dev_softc; 2403 switch (ahc_get_pci_slot(pci)) { 2404 case AHC_394X_SLOT_CHANNEL_A: 2405 ahc->channel = 'A'; 2406 break; 2407 case AHC_394X_SLOT_CHANNEL_B: 2408 ahc->channel = 'B'; 2409 break; 2410 default: 2411 printf("adapter at unexpected slot %d\n" 2412 "unable to map to a channel\n", 2413 ahc_get_pci_slot(pci)); 2414 ahc->channel = 'A'; 2415 } 2416 return (0); 2417} 2418 2419static int 2420ahc_aha398XX_setup(struct ahc_softc *ahc) 2421{ 2422 ahc_dev_softc_t pci; 2423 2424 pci = ahc->dev_softc; 2425 switch (ahc_get_pci_slot(pci)) { 2426 case AHC_398X_SLOT_CHANNEL_A: 2427 ahc->channel = 'A'; 2428 break; 2429 case AHC_398X_SLOT_CHANNEL_B: 2430 ahc->channel = 'B'; 2431 break; 2432 case AHC_398X_SLOT_CHANNEL_C: 2433 ahc->channel = 'C'; 2434 break; 2435 default: 2436 printf("adapter at unexpected slot %d\n" 2437 "unable to map to a channel\n", 2438 ahc_get_pci_slot(pci)); 2439 ahc->channel = 'A'; 2440 break; 2441 } 2442 ahc->flags |= AHC_LARGE_SEEPROM; 2443 return (0); 2444} 2445 2446static int 2447ahc_aha494XX_setup(struct ahc_softc *ahc) 2448{ 2449 ahc_dev_softc_t pci; 2450 2451 pci = ahc->dev_softc; 2452 switch (ahc_get_pci_slot(pci)) { 2453 case AHC_494X_SLOT_CHANNEL_A: 2454 ahc->channel = 'A'; 2455 break; 2456 case AHC_494X_SLOT_CHANNEL_B: 2457 ahc->channel = 'B'; 2458 break; 2459 case AHC_494X_SLOT_CHANNEL_C: 2460 ahc->channel = 'C'; 2461 break; 2462 case AHC_494X_SLOT_CHANNEL_D: 2463 ahc->channel = 'D'; 2464 break; 2465 default: 2466 printf("adapter at unexpected slot %d\n" 2467 "unable to map to a channel\n", 2468 ahc_get_pci_slot(pci)); 2469 ahc->channel = 'A'; 2470 } 2471 ahc->flags |= AHC_LARGE_SEEPROM; 2472 return (0); 2473} 2474