aic7xxx_pci.c revision f0cd91a68acdc9b49d7f6738b514a426da627649
1/* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#79 $ 43 */ 44 45#ifdef __linux__ 46#include "aic7xxx_osm.h" 47#include "aic7xxx_inline.h" 48#include "aic7xxx_93cx6.h" 49#else 50#include <dev/aic7xxx/aic7xxx_osm.h> 51#include <dev/aic7xxx/aic7xxx_inline.h> 52#include <dev/aic7xxx/aic7xxx_93cx6.h> 53#endif 54 55#include "aic7xxx_pci.h" 56 57static __inline uint64_t 58ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 59{ 60 uint64_t id; 61 62 id = subvendor 63 | (subdevice << 16) 64 | ((uint64_t)vendor << 32) 65 | ((uint64_t)device << 48); 66 67 return (id); 68} 69 70#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 71#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 72 73#define DEVID_9005_TYPE(id) ((id) & 0xF) 74#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 75#define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 76#define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 77#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 78 79#define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 80#define DEVID_9005_MAXRATE_U160 0x0 81#define DEVID_9005_MAXRATE_ULTRA2 0x1 82#define DEVID_9005_MAXRATE_ULTRA 0x2 83#define DEVID_9005_MAXRATE_FAST 0x3 84 85#define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 86 87#define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 88#define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 89 90#define SUBID_9005_TYPE(id) ((id) & 0xF) 91#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 92#define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 93#define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 94#define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 95 96#define SUBID_9005_TYPE_KNOWN(id) \ 97 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 98 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 99 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 100 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 101 102#define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 103#define SUBID_9005_MAXRATE_ULTRA2 0x0 104#define SUBID_9005_MAXRATE_ULTRA 0x1 105#define SUBID_9005_MAXRATE_U160 0x2 106#define SUBID_9005_MAXRATE_RESERVED 0x3 107 108#define SUBID_9005_SEEPTYPE(id) \ 109 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 110 ? ((id) & 0xC0) >> 6 \ 111 : ((id) & 0x300) >> 8) 112#define SUBID_9005_SEEPTYPE_NONE 0x0 113#define SUBID_9005_SEEPTYPE_1K 0x1 114#define SUBID_9005_SEEPTYPE_2K_4K 0x2 115#define SUBID_9005_SEEPTYPE_RESERVED 0x3 116#define SUBID_9005_AUTOTERM(id) \ 117 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 118 ? (((id) & 0x400) >> 10) == 0 \ 119 : (((id) & 0x40) >> 6) == 0) 120 121#define SUBID_9005_NUMCHAN(id) \ 122 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 123 ? ((id) & 0x300) >> 8 \ 124 : ((id) & 0xC00) >> 10) 125 126#define SUBID_9005_LEGACYCONN(id) \ 127 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 128 ? 0 \ 129 : ((id) & 0x80) >> 7) 130 131#define SUBID_9005_MFUNCENB(id) \ 132 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 133 ? ((id) & 0x800) >> 11 \ 134 : ((id) & 0x1000) >> 12) 135/* 136 * Informational only. Should use chip register to be 137 * certain, but may be use in identification strings. 138 */ 139#define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 140#define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 141#define SUBID_9005_CARD_SEDIFF_MASK 0x8000 142 143static ahc_device_setup_t ahc_aic785X_setup; 144static ahc_device_setup_t ahc_aic7860_setup; 145static ahc_device_setup_t ahc_apa1480_setup; 146static ahc_device_setup_t ahc_aic7870_setup; 147static ahc_device_setup_t ahc_aic7870h_setup; 148static ahc_device_setup_t ahc_aha394X_setup; 149static ahc_device_setup_t ahc_aha394Xh_setup; 150static ahc_device_setup_t ahc_aha494X_setup; 151static ahc_device_setup_t ahc_aha494Xh_setup; 152static ahc_device_setup_t ahc_aha398X_setup; 153static ahc_device_setup_t ahc_aic7880_setup; 154static ahc_device_setup_t ahc_aic7880h_setup; 155static ahc_device_setup_t ahc_aha2940Pro_setup; 156static ahc_device_setup_t ahc_aha394XU_setup; 157static ahc_device_setup_t ahc_aha394XUh_setup; 158static ahc_device_setup_t ahc_aha398XU_setup; 159static ahc_device_setup_t ahc_aic7890_setup; 160static ahc_device_setup_t ahc_aic7892_setup; 161static ahc_device_setup_t ahc_aic7895_setup; 162static ahc_device_setup_t ahc_aic7895h_setup; 163static ahc_device_setup_t ahc_aic7896_setup; 164static ahc_device_setup_t ahc_aic7899_setup; 165static ahc_device_setup_t ahc_aha29160C_setup; 166static ahc_device_setup_t ahc_raid_setup; 167static ahc_device_setup_t ahc_aha394XX_setup; 168static ahc_device_setup_t ahc_aha494XX_setup; 169static ahc_device_setup_t ahc_aha398XX_setup; 170 171struct ahc_pci_identity ahc_pci_ident_table [] = 172{ 173 /* aic7850 based controllers */ 174 { 175 ID_AHA_2902_04_10_15_20C_30C, 176 ID_ALL_MASK, 177 "Adaptec 2902/04/10/15/20C/30C SCSI adapter", 178 ahc_aic785X_setup 179 }, 180 /* aic7860 based controllers */ 181 { 182 ID_AHA_2930CU, 183 ID_ALL_MASK, 184 "Adaptec 2930CU SCSI adapter", 185 ahc_aic7860_setup 186 }, 187 { 188 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 189 ID_DEV_VENDOR_MASK, 190 "Adaptec 1480A Ultra SCSI adapter", 191 ahc_apa1480_setup 192 }, 193 { 194 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 195 ID_DEV_VENDOR_MASK, 196 "Adaptec 2940A Ultra SCSI adapter", 197 ahc_aic7860_setup 198 }, 199 { 200 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 201 ID_DEV_VENDOR_MASK, 202 "Adaptec 2940A/CN Ultra SCSI adapter", 203 ahc_aic7860_setup 204 }, 205 { 206 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 207 ID_DEV_VENDOR_MASK, 208 "Adaptec 2930C Ultra SCSI adapter (VAR)", 209 ahc_aic7860_setup 210 }, 211 /* aic7870 based controllers */ 212 { 213 ID_AHA_2940, 214 ID_ALL_MASK, 215 "Adaptec 2940 SCSI adapter", 216 ahc_aic7870_setup 217 }, 218 { 219 ID_AHA_3940, 220 ID_ALL_MASK, 221 "Adaptec 3940 SCSI adapter", 222 ahc_aha394X_setup 223 }, 224 { 225 ID_AHA_398X, 226 ID_ALL_MASK, 227 "Adaptec 398X SCSI RAID adapter", 228 ahc_aha398X_setup 229 }, 230 { 231 ID_AHA_2944, 232 ID_ALL_MASK, 233 "Adaptec 2944 SCSI adapter", 234 ahc_aic7870h_setup 235 }, 236 { 237 ID_AHA_3944, 238 ID_ALL_MASK, 239 "Adaptec 3944 SCSI adapter", 240 ahc_aha394Xh_setup 241 }, 242 { 243 ID_AHA_4944, 244 ID_ALL_MASK, 245 "Adaptec 4944 SCSI adapter", 246 ahc_aha494Xh_setup 247 }, 248 /* aic7880 based controllers */ 249 { 250 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 251 ID_DEV_VENDOR_MASK, 252 "Adaptec 2940 Ultra SCSI adapter", 253 ahc_aic7880_setup 254 }, 255 { 256 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 257 ID_DEV_VENDOR_MASK, 258 "Adaptec 3940 Ultra SCSI adapter", 259 ahc_aha394XU_setup 260 }, 261 { 262 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 263 ID_DEV_VENDOR_MASK, 264 "Adaptec 2944 Ultra SCSI adapter", 265 ahc_aic7880h_setup 266 }, 267 { 268 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 269 ID_DEV_VENDOR_MASK, 270 "Adaptec 3944 Ultra SCSI adapter", 271 ahc_aha394XUh_setup 272 }, 273 { 274 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 275 ID_DEV_VENDOR_MASK, 276 "Adaptec 398X Ultra SCSI RAID adapter", 277 ahc_aha398XU_setup 278 }, 279 { 280 /* 281 * XXX Don't know the slot numbers 282 * so we can't identify channels 283 */ 284 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 285 ID_DEV_VENDOR_MASK, 286 "Adaptec 4944 Ultra SCSI adapter", 287 ahc_aic7880h_setup 288 }, 289 { 290 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 291 ID_DEV_VENDOR_MASK, 292 "Adaptec 2930 Ultra SCSI adapter", 293 ahc_aic7880_setup 294 }, 295 { 296 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 297 ID_DEV_VENDOR_MASK, 298 "Adaptec 2940 Pro Ultra SCSI adapter", 299 ahc_aha2940Pro_setup 300 }, 301 { 302 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 303 ID_DEV_VENDOR_MASK, 304 "Adaptec 2940/CN Ultra SCSI adapter", 305 ahc_aic7880_setup 306 }, 307 /* Ignore all SISL (AAC on MB) based controllers. */ 308 { 309 ID_9005_SISL_ID, 310 ID_9005_SISL_MASK, 311 NULL, 312 NULL 313 }, 314 /* aic7890 based controllers */ 315 { 316 ID_AHA_2930U2, 317 ID_ALL_MASK, 318 "Adaptec 2930 Ultra2 SCSI adapter", 319 ahc_aic7890_setup 320 }, 321 { 322 ID_AHA_2940U2B, 323 ID_ALL_MASK, 324 "Adaptec 2940B Ultra2 SCSI adapter", 325 ahc_aic7890_setup 326 }, 327 { 328 ID_AHA_2940U2_OEM, 329 ID_ALL_MASK, 330 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 331 ahc_aic7890_setup 332 }, 333 { 334 ID_AHA_2940U2, 335 ID_ALL_MASK, 336 "Adaptec 2940 Ultra2 SCSI adapter", 337 ahc_aic7890_setup 338 }, 339 { 340 ID_AHA_2950U2B, 341 ID_ALL_MASK, 342 "Adaptec 2950 Ultra2 SCSI adapter", 343 ahc_aic7890_setup 344 }, 345 { 346 ID_AIC7890_ARO, 347 ID_ALL_MASK, 348 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 349 ahc_aic7890_setup 350 }, 351 { 352 ID_AAA_131U2, 353 ID_ALL_MASK, 354 "Adaptec AAA-131 Ultra2 RAID adapter", 355 ahc_aic7890_setup 356 }, 357 /* aic7892 based controllers */ 358 { 359 ID_AHA_29160, 360 ID_ALL_MASK, 361 "Adaptec 29160 Ultra160 SCSI adapter", 362 ahc_aic7892_setup 363 }, 364 { 365 ID_AHA_29160_CPQ, 366 ID_ALL_MASK, 367 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 368 ahc_aic7892_setup 369 }, 370 { 371 ID_AHA_29160N, 372 ID_ALL_MASK, 373 "Adaptec 29160N Ultra160 SCSI adapter", 374 ahc_aic7892_setup 375 }, 376 { 377 ID_AHA_29160C, 378 ID_ALL_MASK, 379 "Adaptec 29160C Ultra160 SCSI adapter", 380 ahc_aha29160C_setup 381 }, 382 { 383 ID_AHA_29160B, 384 ID_ALL_MASK, 385 "Adaptec 29160B Ultra160 SCSI adapter", 386 ahc_aic7892_setup 387 }, 388 { 389 ID_AHA_19160B, 390 ID_ALL_MASK, 391 "Adaptec 19160B Ultra160 SCSI adapter", 392 ahc_aic7892_setup 393 }, 394 { 395 ID_AIC7892_ARO, 396 ID_ALL_MASK, 397 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 398 ahc_aic7892_setup 399 }, 400 { 401 ID_AHA_2915_30LP, 402 ID_ALL_MASK, 403 "Adaptec 2915/30LP Ultra160 SCSI adapter", 404 ahc_aic7892_setup 405 }, 406 /* aic7895 based controllers */ 407 { 408 ID_AHA_2940U_DUAL, 409 ID_ALL_MASK, 410 "Adaptec 2940/DUAL Ultra SCSI adapter", 411 ahc_aic7895_setup 412 }, 413 { 414 ID_AHA_3940AU, 415 ID_ALL_MASK, 416 "Adaptec 3940A Ultra SCSI adapter", 417 ahc_aic7895_setup 418 }, 419 { 420 ID_AHA_3944AU, 421 ID_ALL_MASK, 422 "Adaptec 3944A Ultra SCSI adapter", 423 ahc_aic7895h_setup 424 }, 425 { 426 ID_AIC7895_ARO, 427 ID_AIC7895_ARO_MASK, 428 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 429 ahc_aic7895_setup 430 }, 431 /* aic7896/97 based controllers */ 432 { 433 ID_AHA_3950U2B_0, 434 ID_ALL_MASK, 435 "Adaptec 3950B Ultra2 SCSI adapter", 436 ahc_aic7896_setup 437 }, 438 { 439 ID_AHA_3950U2B_1, 440 ID_ALL_MASK, 441 "Adaptec 3950B Ultra2 SCSI adapter", 442 ahc_aic7896_setup 443 }, 444 { 445 ID_AHA_3950U2D_0, 446 ID_ALL_MASK, 447 "Adaptec 3950D Ultra2 SCSI adapter", 448 ahc_aic7896_setup 449 }, 450 { 451 ID_AHA_3950U2D_1, 452 ID_ALL_MASK, 453 "Adaptec 3950D Ultra2 SCSI adapter", 454 ahc_aic7896_setup 455 }, 456 { 457 ID_AIC7896_ARO, 458 ID_ALL_MASK, 459 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 460 ahc_aic7896_setup 461 }, 462 /* aic7899 based controllers */ 463 { 464 ID_AHA_3960D, 465 ID_ALL_MASK, 466 "Adaptec 3960D Ultra160 SCSI adapter", 467 ahc_aic7899_setup 468 }, 469 { 470 ID_AHA_3960D_CPQ, 471 ID_ALL_MASK, 472 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 473 ahc_aic7899_setup 474 }, 475 { 476 ID_AIC7899_ARO, 477 ID_ALL_MASK, 478 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 479 ahc_aic7899_setup 480 }, 481 /* Generic chip probes for devices we don't know 'exactly' */ 482 { 483 ID_AIC7850 & ID_DEV_VENDOR_MASK, 484 ID_DEV_VENDOR_MASK, 485 "Adaptec aic7850 SCSI adapter", 486 ahc_aic785X_setup 487 }, 488 { 489 ID_AIC7855 & ID_DEV_VENDOR_MASK, 490 ID_DEV_VENDOR_MASK, 491 "Adaptec aic7855 SCSI adapter", 492 ahc_aic785X_setup 493 }, 494 { 495 ID_AIC7859 & ID_DEV_VENDOR_MASK, 496 ID_DEV_VENDOR_MASK, 497 "Adaptec aic7859 SCSI adapter", 498 ahc_aic7860_setup 499 }, 500 { 501 ID_AIC7860 & ID_DEV_VENDOR_MASK, 502 ID_DEV_VENDOR_MASK, 503 "Adaptec aic7860 Ultra SCSI adapter", 504 ahc_aic7860_setup 505 }, 506 { 507 ID_AIC7870 & ID_DEV_VENDOR_MASK, 508 ID_DEV_VENDOR_MASK, 509 "Adaptec aic7870 SCSI adapter", 510 ahc_aic7870_setup 511 }, 512 { 513 ID_AIC7880 & ID_DEV_VENDOR_MASK, 514 ID_DEV_VENDOR_MASK, 515 "Adaptec aic7880 Ultra SCSI adapter", 516 ahc_aic7880_setup 517 }, 518 { 519 ID_AIC7890 & ID_9005_GENERIC_MASK, 520 ID_9005_GENERIC_MASK, 521 "Adaptec aic7890/91 Ultra2 SCSI adapter", 522 ahc_aic7890_setup 523 }, 524 { 525 ID_AIC7892 & ID_9005_GENERIC_MASK, 526 ID_9005_GENERIC_MASK, 527 "Adaptec aic7892 Ultra160 SCSI adapter", 528 ahc_aic7892_setup 529 }, 530 { 531 ID_AIC7895 & ID_DEV_VENDOR_MASK, 532 ID_DEV_VENDOR_MASK, 533 "Adaptec aic7895 Ultra SCSI adapter", 534 ahc_aic7895_setup 535 }, 536 { 537 ID_AIC7896 & ID_9005_GENERIC_MASK, 538 ID_9005_GENERIC_MASK, 539 "Adaptec aic7896/97 Ultra2 SCSI adapter", 540 ahc_aic7896_setup 541 }, 542 { 543 ID_AIC7899 & ID_9005_GENERIC_MASK, 544 ID_9005_GENERIC_MASK, 545 "Adaptec aic7899 Ultra160 SCSI adapter", 546 ahc_aic7899_setup 547 }, 548 { 549 ID_AIC7810 & ID_DEV_VENDOR_MASK, 550 ID_DEV_VENDOR_MASK, 551 "Adaptec aic7810 RAID memory controller", 552 ahc_raid_setup 553 }, 554 { 555 ID_AIC7815 & ID_DEV_VENDOR_MASK, 556 ID_DEV_VENDOR_MASK, 557 "Adaptec aic7815 RAID memory controller", 558 ahc_raid_setup 559 } 560}; 561 562const u_int ahc_num_pci_devs = ARRAY_SIZE(ahc_pci_ident_table); 563 564#define AHC_394X_SLOT_CHANNEL_A 4 565#define AHC_394X_SLOT_CHANNEL_B 5 566 567#define AHC_398X_SLOT_CHANNEL_A 4 568#define AHC_398X_SLOT_CHANNEL_B 8 569#define AHC_398X_SLOT_CHANNEL_C 12 570 571#define AHC_494X_SLOT_CHANNEL_A 4 572#define AHC_494X_SLOT_CHANNEL_B 5 573#define AHC_494X_SLOT_CHANNEL_C 6 574#define AHC_494X_SLOT_CHANNEL_D 7 575 576#define DEVCONFIG 0x40 577#define PCIERRGENDIS 0x80000000ul 578#define SCBSIZE32 0x00010000ul /* aic789X only */ 579#define REXTVALID 0x00001000ul /* ultra cards only */ 580#define MPORTMODE 0x00000400ul /* aic7870+ only */ 581#define RAMPSM 0x00000200ul /* aic7870+ only */ 582#define VOLSENSE 0x00000100ul 583#define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 584#define SCBRAMSEL 0x00000080ul 585#define MRDCEN 0x00000040ul 586#define EXTSCBTIME 0x00000020ul /* aic7870 only */ 587#define EXTSCBPEN 0x00000010ul /* aic7870 only */ 588#define BERREN 0x00000008ul 589#define DACEN 0x00000004ul 590#define STPWLEVEL 0x00000002ul 591#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 592 593#define CSIZE_LATTIME 0x0c 594#define CACHESIZE 0x0000003ful /* only 5 bits */ 595#define LATTIME 0x0000ff00ul 596 597/* PCI STATUS definitions */ 598#define DPE 0x80 599#define SSE 0x40 600#define RMA 0x20 601#define RTA 0x10 602#define STA 0x08 603#define DPR 0x01 604 605static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 606 uint16_t subvendor, uint16_t subdevice); 607static int ahc_ext_scbram_present(struct ahc_softc *ahc); 608static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 609 int pcheck, int fast, int large); 610static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 611static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 612static void ahc_parse_pci_eeprom(struct ahc_softc *ahc, 613 struct seeprom_config *sc); 614static void configure_termination(struct ahc_softc *ahc, 615 struct seeprom_descriptor *sd, 616 u_int adapter_control, 617 u_int *sxfrctl1); 618 619static void ahc_new_term_detect(struct ahc_softc *ahc, 620 int *enableSEC_low, 621 int *enableSEC_high, 622 int *enablePRI_low, 623 int *enablePRI_high, 624 int *eeprom_present); 625static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 626 int *internal68_present, 627 int *externalcable_present, 628 int *eeprom_present); 629static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 630 int *externalcable_present, 631 int *eeprom_present); 632static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 633static uint8_t read_brdctl(struct ahc_softc *ahc); 634static void ahc_pci_intr(struct ahc_softc *ahc); 635static int ahc_pci_chip_init(struct ahc_softc *ahc); 636static int ahc_pci_suspend(struct ahc_softc *ahc); 637static int ahc_pci_resume(struct ahc_softc *ahc); 638 639static int 640ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 641 uint16_t subdevice, uint16_t subvendor) 642{ 643 int result; 644 645 /* Default to invalid. */ 646 result = 0; 647 if (vendor == 0x9005 648 && subvendor == 0x9005 649 && subdevice != device 650 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 651 652 switch (SUBID_9005_TYPE(subdevice)) { 653 case SUBID_9005_TYPE_MB: 654 break; 655 case SUBID_9005_TYPE_CARD: 656 case SUBID_9005_TYPE_LCCARD: 657 /* 658 * Currently only trust Adaptec cards to 659 * get the sub device info correct. 660 */ 661 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 662 result = 1; 663 break; 664 case SUBID_9005_TYPE_RAID: 665 break; 666 default: 667 break; 668 } 669 } 670 return (result); 671} 672 673struct ahc_pci_identity * 674ahc_find_pci_device(ahc_dev_softc_t pci) 675{ 676 uint64_t full_id; 677 uint16_t device; 678 uint16_t vendor; 679 uint16_t subdevice; 680 uint16_t subvendor; 681 struct ahc_pci_identity *entry; 682 u_int i; 683 684 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 685 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 686 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 687 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 688 full_id = ahc_compose_id(device, vendor, subdevice, subvendor); 689 690 /* 691 * If the second function is not hooked up, ignore it. 692 * Unfortunately, not all MB vendors implement the 693 * subdevice ID as per the Adaptec spec, so do our best 694 * to sanity check it prior to accepting the subdevice 695 * ID as valid. 696 */ 697 if (ahc_get_pci_function(pci) > 0 698 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice) 699 && SUBID_9005_MFUNCENB(subdevice) == 0) 700 return (NULL); 701 702 for (i = 0; i < ahc_num_pci_devs; i++) { 703 entry = &ahc_pci_ident_table[i]; 704 if (entry->full_id == (full_id & entry->id_mask)) { 705 /* Honor exclusion entries. */ 706 if (entry->name == NULL) 707 return (NULL); 708 return (entry); 709 } 710 } 711 return (NULL); 712} 713 714int 715ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 716{ 717 u_int command; 718 u_int our_id; 719 u_int sxfrctl1; 720 u_int scsiseq; 721 u_int dscommand0; 722 uint32_t devconfig; 723 int error; 724 uint8_t sblkctl; 725 726 our_id = 0; 727 error = entry->setup(ahc); 728 if (error != 0) 729 return (error); 730 ahc->chip |= AHC_PCI; 731 ahc->description = entry->name; 732 733 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0); 734 735 error = ahc_pci_map_registers(ahc); 736 if (error != 0) 737 return (error); 738 739 /* 740 * Before we continue probing the card, ensure that 741 * its interrupts are *disabled*. We don't want 742 * a misstep to hang the machine in an interrupt 743 * storm. 744 */ 745 ahc_intr_enable(ahc, FALSE); 746 747 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 748 749 /* 750 * If we need to support high memory, enable dual 751 * address cycles. This bit must be set to enable 752 * high address bit generation even if we are on a 753 * 64bit bus (PCI64BIT set in devconfig). 754 */ 755 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 756 757 if (bootverbose) 758 printf("%s: Enabling 39Bit Addressing\n", 759 ahc_name(ahc)); 760 devconfig |= DACEN; 761 } 762 763 /* Ensure that pci error generation, a test feature, is disabled. */ 764 devconfig |= PCIERRGENDIS; 765 766 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 767 768 /* Ensure busmastering is enabled */ 769 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 770 command |= PCIM_CMD_BUSMASTEREN; 771 772 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 773 774 /* On all PCI adapters, we allow SCB paging */ 775 ahc->flags |= AHC_PAGESCBS; 776 777 error = ahc_softc_init(ahc); 778 if (error != 0) 779 return (error); 780 781 /* 782 * Disable PCI parity error checking. Users typically 783 * do this to work around broken PCI chipsets that get 784 * the parity timing wrong and thus generate lots of spurious 785 * errors. The chip only allows us to disable *all* parity 786 * error reporting when doing this, so CIO bus, scb ram, and 787 * scratch ram parity errors will be ignored too. 788 */ 789 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 790 ahc->seqctl |= FAILDIS; 791 792 ahc->bus_intr = ahc_pci_intr; 793 ahc->bus_chip_init = ahc_pci_chip_init; 794 ahc->bus_suspend = ahc_pci_suspend; 795 ahc->bus_resume = ahc_pci_resume; 796 797 /* Remeber how the card was setup in case there is no SEEPROM */ 798 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 799 ahc_pause(ahc); 800 if ((ahc->features & AHC_ULTRA2) != 0) 801 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 802 else 803 our_id = ahc_inb(ahc, SCSIID) & OID; 804 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 805 scsiseq = ahc_inb(ahc, SCSISEQ); 806 } else { 807 sxfrctl1 = STPWEN; 808 our_id = 7; 809 scsiseq = 0; 810 } 811 812 error = ahc_reset(ahc, /*reinit*/FALSE); 813 if (error != 0) 814 return (ENXIO); 815 816 if ((ahc->features & AHC_DT) != 0) { 817 u_int sfunct; 818 819 /* Perform ALT-Mode Setup */ 820 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 821 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 822 ahc_outb(ahc, OPTIONMODE, 823 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 824 ahc_outb(ahc, SFUNCT, sfunct); 825 826 /* Normal mode setup */ 827 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 828 |TARGCRCENDEN); 829 } 830 831 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 832 dscommand0 |= MPARCKEN|CACHETHEN; 833 if ((ahc->features & AHC_ULTRA2) != 0) { 834 835 /* 836 * DPARCKEN doesn't work correctly on 837 * some MBs so don't use it. 838 */ 839 dscommand0 &= ~DPARCKEN; 840 } 841 842 /* 843 * Handle chips that must have cache line 844 * streaming (dis/en)abled. 845 */ 846 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 847 dscommand0 |= CACHETHEN; 848 849 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 850 dscommand0 &= ~CACHETHEN; 851 852 ahc_outb(ahc, DSCOMMAND0, dscommand0); 853 854 ahc->pci_cachesize = 855 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 856 /*bytes*/1) & CACHESIZE; 857 ahc->pci_cachesize *= 4; 858 859 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 860 && ahc->pci_cachesize == 4) { 861 862 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 863 0, /*bytes*/1); 864 ahc->pci_cachesize = 0; 865 } 866 867 /* 868 * We cannot perform ULTRA speeds without the presense 869 * of the external precision resistor. 870 */ 871 if ((ahc->features & AHC_ULTRA) != 0) { 872 uint32_t devconfig; 873 874 devconfig = ahc_pci_read_config(ahc->dev_softc, 875 DEVCONFIG, /*bytes*/4); 876 if ((devconfig & REXTVALID) == 0) 877 ahc->features &= ~AHC_ULTRA; 878 } 879 880 /* See if we have a SEEPROM and perform auto-term */ 881 check_extport(ahc, &sxfrctl1); 882 883 /* 884 * Take the LED out of diagnostic mode 885 */ 886 sblkctl = ahc_inb(ahc, SBLKCTL); 887 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 888 889 if ((ahc->features & AHC_ULTRA2) != 0) { 890 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 891 } else { 892 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 893 } 894 895 if (ahc->flags & AHC_USEDEFAULTS) { 896 /* 897 * PCI Adapter default setup 898 * Should only be used if the adapter does not have 899 * a SEEPROM. 900 */ 901 /* See if someone else set us up already */ 902 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 903 && scsiseq != 0) { 904 printf("%s: Using left over BIOS settings\n", 905 ahc_name(ahc)); 906 ahc->flags &= ~AHC_USEDEFAULTS; 907 ahc->flags |= AHC_BIOS_ENABLED; 908 } else { 909 /* 910 * Assume only one connector and always turn 911 * on termination. 912 */ 913 our_id = 0x07; 914 sxfrctl1 = STPWEN; 915 } 916 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 917 918 ahc->our_id = our_id; 919 } 920 921 /* 922 * Take a look to see if we have external SRAM. 923 * We currently do not attempt to use SRAM that is 924 * shared among multiple controllers. 925 */ 926 ahc_probe_ext_scbram(ahc); 927 928 /* 929 * Record our termination setting for the 930 * generic initialization routine. 931 */ 932 if ((sxfrctl1 & STPWEN) != 0) 933 ahc->flags |= AHC_TERM_ENB_A; 934 935 /* 936 * Save chip register configuration data for chip resets 937 * that occur during runtime and resume events. 938 */ 939 ahc->bus_softc.pci_softc.devconfig = 940 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 941 ahc->bus_softc.pci_softc.command = 942 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 943 ahc->bus_softc.pci_softc.csize_lattime = 944 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1); 945 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 946 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 947 if ((ahc->features & AHC_DT) != 0) { 948 u_int sfunct; 949 950 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 951 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 952 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); 953 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); 954 ahc_outb(ahc, SFUNCT, sfunct); 955 ahc->bus_softc.pci_softc.crccontrol1 = 956 ahc_inb(ahc, CRCCONTROL1); 957 } 958 if ((ahc->features & AHC_MULTI_FUNC) != 0) 959 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); 960 961 if ((ahc->features & AHC_ULTRA2) != 0) 962 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 963 964 /* Core initialization */ 965 error = ahc_init(ahc); 966 if (error != 0) 967 return (error); 968 969 /* 970 * Allow interrupts now that we are completely setup. 971 */ 972 error = ahc_pci_map_int(ahc); 973 if (error != 0) 974 return (error); 975 976 ahc->init_level++; 977 return (0); 978} 979 980/* 981 * Test for the presense of external sram in an 982 * "unshared" configuration. 983 */ 984static int 985ahc_ext_scbram_present(struct ahc_softc *ahc) 986{ 987 u_int chip; 988 int ramps; 989 int single_user; 990 uint32_t devconfig; 991 992 chip = ahc->chip & AHC_CHIPID_MASK; 993 devconfig = ahc_pci_read_config(ahc->dev_softc, 994 DEVCONFIG, /*bytes*/4); 995 single_user = (devconfig & MPORTMODE) != 0; 996 997 if ((ahc->features & AHC_ULTRA2) != 0) 998 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 999 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1000 /* 1001 * External SCBRAM arbitration is flakey 1002 * on these chips. Unfortunately this means 1003 * we don't use the extra SCB ram space on the 1004 * 3940AUW. 1005 */ 1006 ramps = 0; 1007 else if (chip >= AHC_AIC7870) 1008 ramps = (devconfig & RAMPSM) != 0; 1009 else 1010 ramps = 0; 1011 1012 if (ramps && single_user) 1013 return (1); 1014 return (0); 1015} 1016 1017/* 1018 * Enable external scbram. 1019 */ 1020static void 1021ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1022 int fast, int large) 1023{ 1024 uint32_t devconfig; 1025 1026 if (ahc->features & AHC_MULTI_FUNC) { 1027 /* 1028 * Set the SCB Base addr (highest address bit) 1029 * depending on which channel we are. 1030 */ 1031 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 1032 } 1033 1034 ahc->flags &= ~AHC_LSCBS_ENABLED; 1035 if (large) 1036 ahc->flags |= AHC_LSCBS_ENABLED; 1037 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1038 if ((ahc->features & AHC_ULTRA2) != 0) { 1039 u_int dscommand0; 1040 1041 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1042 if (enable) 1043 dscommand0 &= ~INTSCBRAMSEL; 1044 else 1045 dscommand0 |= INTSCBRAMSEL; 1046 if (large) 1047 dscommand0 &= ~USCBSIZE32; 1048 else 1049 dscommand0 |= USCBSIZE32; 1050 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1051 } else { 1052 if (fast) 1053 devconfig &= ~EXTSCBTIME; 1054 else 1055 devconfig |= EXTSCBTIME; 1056 if (enable) 1057 devconfig &= ~SCBRAMSEL; 1058 else 1059 devconfig |= SCBRAMSEL; 1060 if (large) 1061 devconfig &= ~SCBSIZE32; 1062 else 1063 devconfig |= SCBSIZE32; 1064 } 1065 if (pcheck) 1066 devconfig |= EXTSCBPEN; 1067 else 1068 devconfig &= ~EXTSCBPEN; 1069 1070 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1071} 1072 1073/* 1074 * Take a look to see if we have external SRAM. 1075 * We currently do not attempt to use SRAM that is 1076 * shared among multiple controllers. 1077 */ 1078static void 1079ahc_probe_ext_scbram(struct ahc_softc *ahc) 1080{ 1081 int num_scbs; 1082 int test_num_scbs; 1083 int enable; 1084 int pcheck; 1085 int fast; 1086 int large; 1087 1088 enable = FALSE; 1089 pcheck = FALSE; 1090 fast = FALSE; 1091 large = FALSE; 1092 num_scbs = 0; 1093 1094 if (ahc_ext_scbram_present(ahc) == 0) 1095 goto done; 1096 1097 /* 1098 * Probe for the best parameters to use. 1099 */ 1100 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1101 num_scbs = ahc_probe_scbs(ahc); 1102 if (num_scbs == 0) { 1103 /* The SRAM wasn't really present. */ 1104 goto done; 1105 } 1106 enable = TRUE; 1107 1108 /* 1109 * Clear any outstanding parity error 1110 * and ensure that parity error reporting 1111 * is enabled. 1112 */ 1113 ahc_outb(ahc, SEQCTL, 0); 1114 ahc_outb(ahc, CLRINT, CLRPARERR); 1115 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1116 1117 /* Now see if we can do parity */ 1118 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1119 num_scbs = ahc_probe_scbs(ahc); 1120 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1121 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1122 pcheck = TRUE; 1123 1124 /* Clear any resulting parity error */ 1125 ahc_outb(ahc, CLRINT, CLRPARERR); 1126 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1127 1128 /* Now see if we can do fast timing */ 1129 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1130 test_num_scbs = ahc_probe_scbs(ahc); 1131 if (test_num_scbs == num_scbs 1132 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1133 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1134 fast = TRUE; 1135 1136 /* 1137 * See if we can use large SCBs and still maintain 1138 * the same overall count of SCBs. 1139 */ 1140 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1141 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1142 test_num_scbs = ahc_probe_scbs(ahc); 1143 if (test_num_scbs >= num_scbs) { 1144 large = TRUE; 1145 num_scbs = test_num_scbs; 1146 if (num_scbs >= 64) { 1147 /* 1148 * We have enough space to move the 1149 * "busy targets table" into SCB space 1150 * and make it qualify all the way to the 1151 * lun level. 1152 */ 1153 ahc->flags |= AHC_SCB_BTT; 1154 } 1155 } 1156 } 1157done: 1158 /* 1159 * Disable parity error reporting until we 1160 * can load instruction ram. 1161 */ 1162 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1163 /* Clear any latched parity error */ 1164 ahc_outb(ahc, CLRINT, CLRPARERR); 1165 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1166 if (bootverbose && enable) { 1167 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1168 ahc_name(ahc), fast ? "fast" : "slow", 1169 pcheck ? ", parity checking enabled" : "", 1170 large ? 64 : 32); 1171 } 1172 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1173} 1174 1175/* 1176 * Perform some simple tests that should catch situations where 1177 * our registers are invalidly mapped. 1178 */ 1179int 1180ahc_pci_test_register_access(struct ahc_softc *ahc) 1181{ 1182 int error; 1183 u_int status1; 1184 uint32_t cmd; 1185 uint8_t hcntrl; 1186 1187 error = EIO; 1188 1189 /* 1190 * Enable PCI error interrupt status, but suppress NMIs 1191 * generated by SERR raised due to target aborts. 1192 */ 1193 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 1194 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 1195 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 1196 1197 /* 1198 * First a simple test to see if any 1199 * registers can be read. Reading 1200 * HCNTRL has no side effects and has 1201 * at least one bit that is guaranteed to 1202 * be zero so it is a good register to 1203 * use for this test. 1204 */ 1205 hcntrl = ahc_inb(ahc, HCNTRL); 1206 1207 if (hcntrl == 0xFF) 1208 goto fail; 1209 1210 if ((hcntrl & CHIPRST) != 0) { 1211 /* 1212 * The chip has not been initialized since 1213 * PCI/EISA/VLB bus reset. Don't trust 1214 * "left over BIOS data". 1215 */ 1216 ahc->flags |= AHC_NO_BIOS_INIT; 1217 } 1218 1219 /* 1220 * Next create a situation where write combining 1221 * or read prefetching could be initiated by the 1222 * CPU or host bridge. Our device does not support 1223 * either, so look for data corruption and/or flagged 1224 * PCI errors. First pause without causing another 1225 * chip reset. 1226 */ 1227 hcntrl &= ~CHIPRST; 1228 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1229 while (ahc_is_paused(ahc) == 0) 1230 ; 1231 1232 /* Clear any PCI errors that occurred before our driver attached. */ 1233 status1 = ahc_pci_read_config(ahc->dev_softc, 1234 PCIR_STATUS + 1, /*bytes*/1); 1235 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1236 status1, /*bytes*/1); 1237 ahc_outb(ahc, CLRINT, CLRPARERR); 1238 1239 ahc_outb(ahc, SEQCTL, PERRORDIS); 1240 ahc_outb(ahc, SCBPTR, 0); 1241 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1242 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1243 goto fail; 1244 1245 status1 = ahc_pci_read_config(ahc->dev_softc, 1246 PCIR_STATUS + 1, /*bytes*/1); 1247 if ((status1 & STA) != 0) 1248 goto fail; 1249 1250 error = 0; 1251 1252fail: 1253 /* Silently clear any latched errors. */ 1254 status1 = ahc_pci_read_config(ahc->dev_softc, 1255 PCIR_STATUS + 1, /*bytes*/1); 1256 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1257 status1, /*bytes*/1); 1258 ahc_outb(ahc, CLRINT, CLRPARERR); 1259 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1260 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1261 return (error); 1262} 1263 1264/* 1265 * Check the external port logic for a serial eeprom 1266 * and termination/cable detection contrls. 1267 */ 1268static void 1269check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1270{ 1271 struct seeprom_descriptor sd; 1272 struct seeprom_config *sc; 1273 int have_seeprom; 1274 int have_autoterm; 1275 1276 sd.sd_ahc = ahc; 1277 sd.sd_control_offset = SEECTL; 1278 sd.sd_status_offset = SEECTL; 1279 sd.sd_dataout_offset = SEECTL; 1280 sc = ahc->seep_config; 1281 1282 /* 1283 * For some multi-channel devices, the c46 is simply too 1284 * small to work. For the other controller types, we can 1285 * get our information from either SEEPROM type. Set the 1286 * type to start our probe with accordingly. 1287 */ 1288 if (ahc->flags & AHC_LARGE_SEEPROM) 1289 sd.sd_chip = C56_66; 1290 else 1291 sd.sd_chip = C46; 1292 1293 sd.sd_MS = SEEMS; 1294 sd.sd_RDY = SEERDY; 1295 sd.sd_CS = SEECS; 1296 sd.sd_CK = SEECK; 1297 sd.sd_DO = SEEDO; 1298 sd.sd_DI = SEEDI; 1299 1300 have_seeprom = ahc_acquire_seeprom(ahc, &sd); 1301 if (have_seeprom) { 1302 1303 if (bootverbose) 1304 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1305 1306 for (;;) { 1307 u_int start_addr; 1308 1309 start_addr = 32 * (ahc->channel - 'A'); 1310 1311 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc, 1312 start_addr, 1313 sizeof(*sc)/2); 1314 1315 if (have_seeprom) 1316 have_seeprom = ahc_verify_cksum(sc); 1317 1318 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1319 if (bootverbose) { 1320 if (have_seeprom == 0) 1321 printf ("checksum error\n"); 1322 else 1323 printf ("done.\n"); 1324 } 1325 break; 1326 } 1327 sd.sd_chip = C56_66; 1328 } 1329 ahc_release_seeprom(&sd); 1330 1331 /* Remember the SEEPROM type for later */ 1332 if (sd.sd_chip == C56_66) 1333 ahc->flags |= AHC_LARGE_SEEPROM; 1334 } 1335 1336 if (!have_seeprom) { 1337 /* 1338 * Pull scratch ram settings and treat them as 1339 * if they are the contents of an seeprom if 1340 * the 'ADPT' signature is found in SCB2. 1341 * We manually compose the data as 16bit values 1342 * to avoid endian issues. 1343 */ 1344 ahc_outb(ahc, SCBPTR, 2); 1345 if (ahc_inb(ahc, SCB_BASE) == 'A' 1346 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1347 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1348 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1349 uint16_t *sc_data; 1350 int i; 1351 1352 sc_data = (uint16_t *)sc; 1353 for (i = 0; i < 32; i++, sc_data++) { 1354 int j; 1355 1356 j = i * 2; 1357 *sc_data = ahc_inb(ahc, SRAM_BASE + j) 1358 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1359 } 1360 have_seeprom = ahc_verify_cksum(sc); 1361 if (have_seeprom) 1362 ahc->flags |= AHC_SCB_CONFIG_USED; 1363 } 1364 /* 1365 * Clear any SCB parity errors in case this data and 1366 * its associated parity was not initialized by the BIOS 1367 */ 1368 ahc_outb(ahc, CLRINT, CLRPARERR); 1369 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1370 } 1371 1372 if (!have_seeprom) { 1373 if (bootverbose) 1374 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1375 ahc->flags |= AHC_USEDEFAULTS; 1376 free(ahc->seep_config, M_DEVBUF); 1377 ahc->seep_config = NULL; 1378 sc = NULL; 1379 } else { 1380 ahc_parse_pci_eeprom(ahc, sc); 1381 } 1382 1383 /* 1384 * Cards that have the external logic necessary to talk to 1385 * a SEEPROM, are almost certain to have the remaining logic 1386 * necessary for auto-termination control. This assumption 1387 * hasn't failed yet... 1388 */ 1389 have_autoterm = have_seeprom; 1390 1391 /* 1392 * Some low-cost chips have SEEPROM and auto-term control built 1393 * in, instead of using a GAL. They can tell us directly 1394 * if the termination logic is enabled. 1395 */ 1396 if ((ahc->features & AHC_SPIOCAP) != 0) { 1397 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0) 1398 have_autoterm = FALSE; 1399 } 1400 1401 if (have_autoterm) { 1402 ahc->flags |= AHC_HAS_TERM_LOGIC; 1403 ahc_acquire_seeprom(ahc, &sd); 1404 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1); 1405 ahc_release_seeprom(&sd); 1406 } else if (have_seeprom) { 1407 *sxfrctl1 &= ~STPWEN; 1408 if ((sc->adapter_control & CFSTERM) != 0) 1409 *sxfrctl1 |= STPWEN; 1410 if (bootverbose) 1411 printf("%s: Low byte termination %sabled\n", 1412 ahc_name(ahc), 1413 (*sxfrctl1 & STPWEN) ? "en" : "dis"); 1414 } 1415} 1416 1417static void 1418ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc) 1419{ 1420 /* 1421 * Put the data we've collected down into SRAM 1422 * where ahc_init will find it. 1423 */ 1424 int i; 1425 int max_targ = sc->max_targets & CFMAXTARG; 1426 u_int scsi_conf; 1427 uint16_t discenable; 1428 uint16_t ultraenb; 1429 1430 discenable = 0; 1431 ultraenb = 0; 1432 if ((sc->adapter_control & CFULTRAEN) != 0) { 1433 /* 1434 * Determine if this adapter has a "newstyle" 1435 * SEEPROM format. 1436 */ 1437 for (i = 0; i < max_targ; i++) { 1438 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) { 1439 ahc->flags |= AHC_NEWEEPROM_FMT; 1440 break; 1441 } 1442 } 1443 } 1444 1445 for (i = 0; i < max_targ; i++) { 1446 u_int scsirate; 1447 uint16_t target_mask; 1448 1449 target_mask = 0x01 << i; 1450 if (sc->device_flags[i] & CFDISC) 1451 discenable |= target_mask; 1452 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1453 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) 1454 ultraenb |= target_mask; 1455 } else if ((sc->adapter_control & CFULTRAEN) != 0) { 1456 ultraenb |= target_mask; 1457 } 1458 if ((sc->device_flags[i] & CFXFER) == 0x04 1459 && (ultraenb & target_mask) != 0) { 1460 /* Treat 10MHz as a non-ultra speed */ 1461 sc->device_flags[i] &= ~CFXFER; 1462 ultraenb &= ~target_mask; 1463 } 1464 if ((ahc->features & AHC_ULTRA2) != 0) { 1465 u_int offset; 1466 1467 if (sc->device_flags[i] & CFSYNCH) 1468 offset = MAX_OFFSET_ULTRA2; 1469 else 1470 offset = 0; 1471 ahc_outb(ahc, TARG_OFFSET + i, offset); 1472 1473 /* 1474 * The ultra enable bits contain the 1475 * high bit of the ultra2 sync rate 1476 * field. 1477 */ 1478 scsirate = (sc->device_flags[i] & CFXFER) 1479 | ((ultraenb & target_mask) ? 0x8 : 0x0); 1480 if (sc->device_flags[i] & CFWIDEB) 1481 scsirate |= WIDEXFER; 1482 } else { 1483 scsirate = (sc->device_flags[i] & CFXFER) << 4; 1484 if (sc->device_flags[i] & CFSYNCH) 1485 scsirate |= SOFS; 1486 if (sc->device_flags[i] & CFWIDEB) 1487 scsirate |= WIDEXFER; 1488 } 1489 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1490 } 1491 ahc->our_id = sc->brtime_id & CFSCSIID; 1492 1493 scsi_conf = (ahc->our_id & 0x7); 1494 if (sc->adapter_control & CFSPARITY) 1495 scsi_conf |= ENSPCHK; 1496 if (sc->adapter_control & CFRESETB) 1497 scsi_conf |= RESET_SCSI; 1498 1499 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1500 1501 if (sc->bios_control & CFEXTEND) 1502 ahc->flags |= AHC_EXTENDED_TRANS_A; 1503 1504 if (sc->bios_control & CFBIOSEN) 1505 ahc->flags |= AHC_BIOS_ENABLED; 1506 if (ahc->features & AHC_ULTRA 1507 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1508 /* Should we enable Ultra mode? */ 1509 if (!(sc->adapter_control & CFULTRAEN)) 1510 /* Treat us as a non-ultra card */ 1511 ultraenb = 0; 1512 } 1513 1514 if (sc->signature == CFSIGNATURE 1515 || sc->signature == CFSIGNATURE2) { 1516 uint32_t devconfig; 1517 1518 /* Honor the STPWLEVEL settings */ 1519 devconfig = ahc_pci_read_config(ahc->dev_softc, 1520 DEVCONFIG, /*bytes*/4); 1521 devconfig &= ~STPWLEVEL; 1522 if ((sc->bios_control & CFSTPWLEVEL) != 0) 1523 devconfig |= STPWLEVEL; 1524 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1525 devconfig, /*bytes*/4); 1526 } 1527 /* Set SCSICONF info */ 1528 ahc_outb(ahc, SCSICONF, scsi_conf); 1529 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1530 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1531 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1532 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1533} 1534 1535static void 1536configure_termination(struct ahc_softc *ahc, 1537 struct seeprom_descriptor *sd, 1538 u_int adapter_control, 1539 u_int *sxfrctl1) 1540{ 1541 uint8_t brddat; 1542 1543 brddat = 0; 1544 1545 /* 1546 * Update the settings in sxfrctl1 to match the 1547 * termination settings 1548 */ 1549 *sxfrctl1 = 0; 1550 1551 /* 1552 * SEECS must be on for the GALS to latch 1553 * the data properly. Be sure to leave MS 1554 * on or we will release the seeprom. 1555 */ 1556 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1557 if ((adapter_control & CFAUTOTERM) != 0 1558 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1559 int internal50_present; 1560 int internal68_present; 1561 int externalcable_present; 1562 int eeprom_present; 1563 int enableSEC_low; 1564 int enableSEC_high; 1565 int enablePRI_low; 1566 int enablePRI_high; 1567 int sum; 1568 1569 enableSEC_low = 0; 1570 enableSEC_high = 0; 1571 enablePRI_low = 0; 1572 enablePRI_high = 0; 1573 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1574 ahc_new_term_detect(ahc, &enableSEC_low, 1575 &enableSEC_high, 1576 &enablePRI_low, 1577 &enablePRI_high, 1578 &eeprom_present); 1579 if ((adapter_control & CFSEAUTOTERM) == 0) { 1580 if (bootverbose) 1581 printf("%s: Manual SE Termination\n", 1582 ahc_name(ahc)); 1583 enableSEC_low = (adapter_control & CFSELOWTERM); 1584 enableSEC_high = 1585 (adapter_control & CFSEHIGHTERM); 1586 } 1587 if ((adapter_control & CFAUTOTERM) == 0) { 1588 if (bootverbose) 1589 printf("%s: Manual LVD Termination\n", 1590 ahc_name(ahc)); 1591 enablePRI_low = (adapter_control & CFSTERM); 1592 enablePRI_high = (adapter_control & CFWSTERM); 1593 } 1594 /* Make the table calculations below happy */ 1595 internal50_present = 0; 1596 internal68_present = 1; 1597 externalcable_present = 1; 1598 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1599 aic785X_cable_detect(ahc, &internal50_present, 1600 &externalcable_present, 1601 &eeprom_present); 1602 /* Can never support a wide connector. */ 1603 internal68_present = 0; 1604 } else { 1605 aic787X_cable_detect(ahc, &internal50_present, 1606 &internal68_present, 1607 &externalcable_present, 1608 &eeprom_present); 1609 } 1610 1611 if ((ahc->features & AHC_WIDE) == 0) 1612 internal68_present = 0; 1613 1614 if (bootverbose 1615 && (ahc->features & AHC_ULTRA2) == 0) { 1616 printf("%s: internal 50 cable %s present", 1617 ahc_name(ahc), 1618 internal50_present ? "is":"not"); 1619 1620 if ((ahc->features & AHC_WIDE) != 0) 1621 printf(", internal 68 cable %s present", 1622 internal68_present ? "is":"not"); 1623 printf("\n%s: external cable %s present\n", 1624 ahc_name(ahc), 1625 externalcable_present ? "is":"not"); 1626 } 1627 if (bootverbose) 1628 printf("%s: BIOS eeprom %s present\n", 1629 ahc_name(ahc), eeprom_present ? "is" : "not"); 1630 1631 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1632 /* 1633 * The 50 pin connector is a separate bus, 1634 * so force it to always be terminated. 1635 * In the future, perform current sensing 1636 * to determine if we are in the middle of 1637 * a properly terminated bus. 1638 */ 1639 internal50_present = 0; 1640 } 1641 1642 /* 1643 * Now set the termination based on what 1644 * we found. 1645 * Flash Enable = BRDDAT7 1646 * Secondary High Term Enable = BRDDAT6 1647 * Secondary Low Term Enable = BRDDAT5 (7890) 1648 * Primary High Term Enable = BRDDAT4 (7890) 1649 */ 1650 if ((ahc->features & AHC_ULTRA2) == 0 1651 && (internal50_present != 0) 1652 && (internal68_present != 0) 1653 && (externalcable_present != 0)) { 1654 printf("%s: Illegal cable configuration!!. " 1655 "Only two connectors on the " 1656 "adapter may be used at a " 1657 "time!\n", ahc_name(ahc)); 1658 1659 /* 1660 * Pretend there are no cables in the hope 1661 * that having all of the termination on 1662 * gives us a more stable bus. 1663 */ 1664 internal50_present = 0; 1665 internal68_present = 0; 1666 externalcable_present = 0; 1667 } 1668 1669 if ((ahc->features & AHC_WIDE) != 0 1670 && ((externalcable_present == 0) 1671 || (internal68_present == 0) 1672 || (enableSEC_high != 0))) { 1673 brddat |= BRDDAT6; 1674 if (bootverbose) { 1675 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1676 printf("%s: 68 pin termination " 1677 "Enabled\n", ahc_name(ahc)); 1678 else 1679 printf("%s: %sHigh byte termination " 1680 "Enabled\n", ahc_name(ahc), 1681 enableSEC_high ? "Secondary " 1682 : ""); 1683 } 1684 } 1685 1686 sum = internal50_present + internal68_present 1687 + externalcable_present; 1688 if (sum < 2 || (enableSEC_low != 0)) { 1689 if ((ahc->features & AHC_ULTRA2) != 0) 1690 brddat |= BRDDAT5; 1691 else 1692 *sxfrctl1 |= STPWEN; 1693 if (bootverbose) { 1694 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1695 printf("%s: 50 pin termination " 1696 "Enabled\n", ahc_name(ahc)); 1697 else 1698 printf("%s: %sLow byte termination " 1699 "Enabled\n", ahc_name(ahc), 1700 enableSEC_low ? "Secondary " 1701 : ""); 1702 } 1703 } 1704 1705 if (enablePRI_low != 0) { 1706 *sxfrctl1 |= STPWEN; 1707 if (bootverbose) 1708 printf("%s: Primary Low Byte termination " 1709 "Enabled\n", ahc_name(ahc)); 1710 } 1711 1712 /* 1713 * Setup STPWEN before setting up the rest of 1714 * the termination per the tech note on the U160 cards. 1715 */ 1716 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1717 1718 if (enablePRI_high != 0) { 1719 brddat |= BRDDAT4; 1720 if (bootverbose) 1721 printf("%s: Primary High Byte " 1722 "termination Enabled\n", 1723 ahc_name(ahc)); 1724 } 1725 1726 write_brdctl(ahc, brddat); 1727 1728 } else { 1729 if ((adapter_control & CFSTERM) != 0) { 1730 *sxfrctl1 |= STPWEN; 1731 1732 if (bootverbose) 1733 printf("%s: %sLow byte termination Enabled\n", 1734 ahc_name(ahc), 1735 (ahc->features & AHC_ULTRA2) ? "Primary " 1736 : ""); 1737 } 1738 1739 if ((adapter_control & CFWSTERM) != 0 1740 && (ahc->features & AHC_WIDE) != 0) { 1741 brddat |= BRDDAT6; 1742 if (bootverbose) 1743 printf("%s: %sHigh byte termination Enabled\n", 1744 ahc_name(ahc), 1745 (ahc->features & AHC_ULTRA2) 1746 ? "Secondary " : ""); 1747 } 1748 1749 /* 1750 * Setup STPWEN before setting up the rest of 1751 * the termination per the tech note on the U160 cards. 1752 */ 1753 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1754 1755 if ((ahc->features & AHC_WIDE) != 0) 1756 write_brdctl(ahc, brddat); 1757 } 1758 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1759} 1760 1761static void 1762ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1763 int *enableSEC_high, int *enablePRI_low, 1764 int *enablePRI_high, int *eeprom_present) 1765{ 1766 uint8_t brdctl; 1767 1768 /* 1769 * BRDDAT7 = Eeprom 1770 * BRDDAT6 = Enable Secondary High Byte termination 1771 * BRDDAT5 = Enable Secondary Low Byte termination 1772 * BRDDAT4 = Enable Primary high byte termination 1773 * BRDDAT3 = Enable Primary low byte termination 1774 */ 1775 brdctl = read_brdctl(ahc); 1776 *eeprom_present = brdctl & BRDDAT7; 1777 *enableSEC_high = (brdctl & BRDDAT6); 1778 *enableSEC_low = (brdctl & BRDDAT5); 1779 *enablePRI_high = (brdctl & BRDDAT4); 1780 *enablePRI_low = (brdctl & BRDDAT3); 1781} 1782 1783static void 1784aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1785 int *internal68_present, int *externalcable_present, 1786 int *eeprom_present) 1787{ 1788 uint8_t brdctl; 1789 1790 /* 1791 * First read the status of our cables. 1792 * Set the rom bank to 0 since the 1793 * bank setting serves as a multiplexor 1794 * for the cable detection logic. 1795 * BRDDAT5 controls the bank switch. 1796 */ 1797 write_brdctl(ahc, 0); 1798 1799 /* 1800 * Now read the state of the internal 1801 * connectors. BRDDAT6 is INT50 and 1802 * BRDDAT7 is INT68. 1803 */ 1804 brdctl = read_brdctl(ahc); 1805 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1806 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1807 1808 /* 1809 * Set the rom bank to 1 and determine 1810 * the other signals. 1811 */ 1812 write_brdctl(ahc, BRDDAT5); 1813 1814 /* 1815 * Now read the state of the external 1816 * connectors. BRDDAT6 is EXT68 and 1817 * BRDDAT7 is EPROMPS. 1818 */ 1819 brdctl = read_brdctl(ahc); 1820 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1821 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1822} 1823 1824static void 1825aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1826 int *externalcable_present, int *eeprom_present) 1827{ 1828 uint8_t brdctl; 1829 uint8_t spiocap; 1830 1831 spiocap = ahc_inb(ahc, SPIOCAP); 1832 spiocap &= ~SOFTCMDEN; 1833 spiocap |= EXT_BRDCTL; 1834 ahc_outb(ahc, SPIOCAP, spiocap); 1835 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1836 ahc_flush_device_writes(ahc); 1837 ahc_delay(500); 1838 ahc_outb(ahc, BRDCTL, 0); 1839 ahc_flush_device_writes(ahc); 1840 ahc_delay(500); 1841 brdctl = ahc_inb(ahc, BRDCTL); 1842 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1843 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1844 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1845} 1846 1847int 1848ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1849{ 1850 int wait; 1851 1852 if ((ahc->features & AHC_SPIOCAP) != 0 1853 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1854 return (0); 1855 1856 /* 1857 * Request access of the memory port. When access is 1858 * granted, SEERDY will go high. We use a 1 second 1859 * timeout which should be near 1 second more than 1860 * is needed. Reason: after the chip reset, there 1861 * should be no contention. 1862 */ 1863 SEEPROM_OUTB(sd, sd->sd_MS); 1864 wait = 1000; /* 1 second timeout in msec */ 1865 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1866 ahc_delay(1000); /* delay 1 msec */ 1867 } 1868 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1869 SEEPROM_OUTB(sd, 0); 1870 return (0); 1871 } 1872 return(1); 1873} 1874 1875void 1876ahc_release_seeprom(struct seeprom_descriptor *sd) 1877{ 1878 /* Release access to the memory port and the serial EEPROM. */ 1879 SEEPROM_OUTB(sd, 0); 1880} 1881 1882static void 1883write_brdctl(struct ahc_softc *ahc, uint8_t value) 1884{ 1885 uint8_t brdctl; 1886 1887 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1888 brdctl = BRDSTB; 1889 if (ahc->channel == 'B') 1890 brdctl |= BRDCS; 1891 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1892 brdctl = 0; 1893 } else { 1894 brdctl = BRDSTB|BRDCS; 1895 } 1896 ahc_outb(ahc, BRDCTL, brdctl); 1897 ahc_flush_device_writes(ahc); 1898 brdctl |= value; 1899 ahc_outb(ahc, BRDCTL, brdctl); 1900 ahc_flush_device_writes(ahc); 1901 if ((ahc->features & AHC_ULTRA2) != 0) 1902 brdctl |= BRDSTB_ULTRA2; 1903 else 1904 brdctl &= ~BRDSTB; 1905 ahc_outb(ahc, BRDCTL, brdctl); 1906 ahc_flush_device_writes(ahc); 1907 if ((ahc->features & AHC_ULTRA2) != 0) 1908 brdctl = 0; 1909 else 1910 brdctl &= ~BRDCS; 1911 ahc_outb(ahc, BRDCTL, brdctl); 1912} 1913 1914static uint8_t 1915read_brdctl(struct ahc_softc *ahc) 1916{ 1917 uint8_t brdctl; 1918 uint8_t value; 1919 1920 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1921 brdctl = BRDRW; 1922 if (ahc->channel == 'B') 1923 brdctl |= BRDCS; 1924 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1925 brdctl = BRDRW_ULTRA2; 1926 } else { 1927 brdctl = BRDRW|BRDCS; 1928 } 1929 ahc_outb(ahc, BRDCTL, brdctl); 1930 ahc_flush_device_writes(ahc); 1931 value = ahc_inb(ahc, BRDCTL); 1932 ahc_outb(ahc, BRDCTL, 0); 1933 return (value); 1934} 1935 1936static void 1937ahc_pci_intr(struct ahc_softc *ahc) 1938{ 1939 u_int error; 1940 u_int status1; 1941 1942 error = ahc_inb(ahc, ERROR); 1943 if ((error & PCIERRSTAT) == 0) 1944 return; 1945 1946 status1 = ahc_pci_read_config(ahc->dev_softc, 1947 PCIR_STATUS + 1, /*bytes*/1); 1948 1949 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1950 ahc_name(ahc), 1951 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1952 1953 if (status1 & DPE) { 1954 ahc->pci_target_perr_count++; 1955 printf("%s: Data Parity Error Detected during address " 1956 "or write data phase\n", ahc_name(ahc)); 1957 } 1958 if (status1 & SSE) { 1959 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1960 } 1961 if (status1 & RMA) { 1962 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1963 } 1964 if (status1 & RTA) { 1965 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1966 } 1967 if (status1 & STA) { 1968 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1969 } 1970 if (status1 & DPR) { 1971 printf("%s: Data Parity Error has been reported via PERR#\n", 1972 ahc_name(ahc)); 1973 } 1974 1975 /* Clear latched errors. */ 1976 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1977 status1, /*bytes*/1); 1978 1979 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1980 printf("%s: Latched PCIERR interrupt with " 1981 "no status bits set\n", ahc_name(ahc)); 1982 } else { 1983 ahc_outb(ahc, CLRINT, CLRPARERR); 1984 } 1985 1986 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) { 1987 printf( 1988"%s: WARNING WARNING WARNING WARNING\n" 1989"%s: Too many PCI parity errors observed as a target.\n" 1990"%s: Some device on this bus is generating bad parity.\n" 1991"%s: This is an error *observed by*, not *generated by*, this controller.\n" 1992"%s: PCI parity error checking has been disabled.\n" 1993"%s: WARNING WARNING WARNING WARNING\n", 1994 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc), 1995 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc)); 1996 ahc->seqctl |= FAILDIS; 1997 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1998 } 1999 ahc_unpause(ahc); 2000} 2001 2002static int 2003ahc_pci_chip_init(struct ahc_softc *ahc) 2004{ 2005 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); 2006 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); 2007 if ((ahc->features & AHC_DT) != 0) { 2008 u_int sfunct; 2009 2010 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 2011 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 2012 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); 2013 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); 2014 ahc_outb(ahc, SFUNCT, sfunct); 2015 ahc_outb(ahc, CRCCONTROL1, 2016 ahc->bus_softc.pci_softc.crccontrol1); 2017 } 2018 if ((ahc->features & AHC_MULTI_FUNC) != 0) 2019 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); 2020 2021 if ((ahc->features & AHC_ULTRA2) != 0) 2022 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); 2023 2024 return (ahc_chip_init(ahc)); 2025} 2026 2027static int 2028ahc_pci_suspend(struct ahc_softc *ahc) 2029{ 2030 return (ahc_suspend(ahc)); 2031} 2032 2033static int 2034ahc_pci_resume(struct ahc_softc *ahc) 2035{ 2036 2037 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0); 2038 2039 /* 2040 * We assume that the OS has restored our register 2041 * mappings, etc. Just update the config space registers 2042 * that the OS doesn't know about and rely on our chip 2043 * reset handler to handle the rest. 2044 */ 2045 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 2046 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4); 2047 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 2048 ahc->bus_softc.pci_softc.command, /*bytes*/1); 2049 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 2050 ahc->bus_softc.pci_softc.csize_lattime, /*bytes*/1); 2051 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) { 2052 struct seeprom_descriptor sd; 2053 u_int sxfrctl1; 2054 2055 sd.sd_ahc = ahc; 2056 sd.sd_control_offset = SEECTL; 2057 sd.sd_status_offset = SEECTL; 2058 sd.sd_dataout_offset = SEECTL; 2059 2060 ahc_acquire_seeprom(ahc, &sd); 2061 configure_termination(ahc, &sd, 2062 ahc->seep_config->adapter_control, 2063 &sxfrctl1); 2064 ahc_release_seeprom(&sd); 2065 } 2066 return (ahc_resume(ahc)); 2067} 2068 2069static int 2070ahc_aic785X_setup(struct ahc_softc *ahc) 2071{ 2072 ahc_dev_softc_t pci; 2073 uint8_t rev; 2074 2075 pci = ahc->dev_softc; 2076 ahc->channel = 'A'; 2077 ahc->chip = AHC_AIC7850; 2078 ahc->features = AHC_AIC7850_FE; 2079 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2080 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2081 if (rev >= 1) 2082 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2083 ahc->instruction_ram_size = 512; 2084 return (0); 2085} 2086 2087static int 2088ahc_aic7860_setup(struct ahc_softc *ahc) 2089{ 2090 ahc_dev_softc_t pci; 2091 uint8_t rev; 2092 2093 pci = ahc->dev_softc; 2094 ahc->channel = 'A'; 2095 ahc->chip = AHC_AIC7860; 2096 ahc->features = AHC_AIC7860_FE; 2097 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2098 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2099 if (rev >= 1) 2100 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2101 ahc->instruction_ram_size = 512; 2102 return (0); 2103} 2104 2105static int 2106ahc_apa1480_setup(struct ahc_softc *ahc) 2107{ 2108 int error; 2109 2110 error = ahc_aic7860_setup(ahc); 2111 if (error != 0) 2112 return (error); 2113 ahc->features |= AHC_REMOVABLE; 2114 return (0); 2115} 2116 2117static int 2118ahc_aic7870_setup(struct ahc_softc *ahc) 2119{ 2120 2121 ahc->channel = 'A'; 2122 ahc->chip = AHC_AIC7870; 2123 ahc->features = AHC_AIC7870_FE; 2124 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2125 ahc->instruction_ram_size = 512; 2126 return (0); 2127} 2128 2129static int 2130ahc_aic7870h_setup(struct ahc_softc *ahc) 2131{ 2132 int error = ahc_aic7870_setup(ahc); 2133 2134 ahc->features |= AHC_HVD; 2135 2136 return error; 2137} 2138 2139static int 2140ahc_aha394X_setup(struct ahc_softc *ahc) 2141{ 2142 int error; 2143 2144 error = ahc_aic7870_setup(ahc); 2145 if (error == 0) 2146 error = ahc_aha394XX_setup(ahc); 2147 return (error); 2148} 2149 2150static int 2151ahc_aha394Xh_setup(struct ahc_softc *ahc) 2152{ 2153 int error = ahc_aha394X_setup(ahc); 2154 2155 ahc->features |= AHC_HVD; 2156 2157 return error; 2158} 2159 2160static int 2161ahc_aha398X_setup(struct ahc_softc *ahc) 2162{ 2163 int error; 2164 2165 error = ahc_aic7870_setup(ahc); 2166 if (error == 0) 2167 error = ahc_aha398XX_setup(ahc); 2168 return (error); 2169} 2170 2171static int 2172ahc_aha494X_setup(struct ahc_softc *ahc) 2173{ 2174 int error; 2175 2176 error = ahc_aic7870_setup(ahc); 2177 if (error == 0) 2178 error = ahc_aha494XX_setup(ahc); 2179 return (error); 2180} 2181 2182static int 2183ahc_aha494Xh_setup(struct ahc_softc *ahc) 2184{ 2185 int error = ahc_aha494X_setup(ahc); 2186 2187 ahc->features |= AHC_HVD; 2188 2189 return error; 2190} 2191 2192static int 2193ahc_aic7880_setup(struct ahc_softc *ahc) 2194{ 2195 ahc_dev_softc_t pci; 2196 uint8_t rev; 2197 2198 pci = ahc->dev_softc; 2199 ahc->channel = 'A'; 2200 ahc->chip = AHC_AIC7880; 2201 ahc->features = AHC_AIC7880_FE; 2202 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 2203 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2204 if (rev >= 1) { 2205 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2206 } else { 2207 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2208 } 2209 ahc->instruction_ram_size = 512; 2210 return (0); 2211} 2212 2213static int 2214ahc_aic7880h_setup(struct ahc_softc *ahc) 2215{ 2216 int error = ahc_aic7880_setup(ahc); 2217 2218 ahc->features |= AHC_HVD; 2219 2220 return error; 2221} 2222 2223 2224static int 2225ahc_aha2940Pro_setup(struct ahc_softc *ahc) 2226{ 2227 2228 ahc->flags |= AHC_INT50_SPEEDFLEX; 2229 return (ahc_aic7880_setup(ahc)); 2230} 2231 2232static int 2233ahc_aha394XU_setup(struct ahc_softc *ahc) 2234{ 2235 int error; 2236 2237 error = ahc_aic7880_setup(ahc); 2238 if (error == 0) 2239 error = ahc_aha394XX_setup(ahc); 2240 return (error); 2241} 2242 2243static int 2244ahc_aha394XUh_setup(struct ahc_softc *ahc) 2245{ 2246 int error = ahc_aha394XU_setup(ahc); 2247 2248 ahc->features |= AHC_HVD; 2249 2250 return error; 2251} 2252 2253static int 2254ahc_aha398XU_setup(struct ahc_softc *ahc) 2255{ 2256 int error; 2257 2258 error = ahc_aic7880_setup(ahc); 2259 if (error == 0) 2260 error = ahc_aha398XX_setup(ahc); 2261 return (error); 2262} 2263 2264static int 2265ahc_aic7890_setup(struct ahc_softc *ahc) 2266{ 2267 ahc_dev_softc_t pci; 2268 uint8_t rev; 2269 2270 pci = ahc->dev_softc; 2271 ahc->channel = 'A'; 2272 ahc->chip = AHC_AIC7890; 2273 ahc->features = AHC_AIC7890_FE; 2274 ahc->flags |= AHC_NEWEEPROM_FMT; 2275 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2276 if (rev == 0) 2277 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 2278 ahc->instruction_ram_size = 768; 2279 return (0); 2280} 2281 2282static int 2283ahc_aic7892_setup(struct ahc_softc *ahc) 2284{ 2285 2286 ahc->channel = 'A'; 2287 ahc->chip = AHC_AIC7892; 2288 ahc->features = AHC_AIC7892_FE; 2289 ahc->flags |= AHC_NEWEEPROM_FMT; 2290 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2291 ahc->instruction_ram_size = 1024; 2292 return (0); 2293} 2294 2295static int 2296ahc_aic7895_setup(struct ahc_softc *ahc) 2297{ 2298 ahc_dev_softc_t pci; 2299 uint8_t rev; 2300 2301 pci = ahc->dev_softc; 2302 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2303 /* 2304 * The 'C' revision of the aic7895 has a few additional features. 2305 */ 2306 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2307 if (rev >= 4) { 2308 ahc->chip = AHC_AIC7895C; 2309 ahc->features = AHC_AIC7895C_FE; 2310 } else { 2311 u_int command; 2312 2313 ahc->chip = AHC_AIC7895; 2314 ahc->features = AHC_AIC7895_FE; 2315 2316 /* 2317 * The BIOS disables the use of MWI transactions 2318 * since it does not have the MWI bug work around 2319 * we have. Disabling MWI reduces performance, so 2320 * turn it on again. 2321 */ 2322 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2323 command |= PCIM_CMD_MWRICEN; 2324 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2325 ahc->bugs |= AHC_PCI_MWI_BUG; 2326 } 2327 /* 2328 * XXX Does CACHETHEN really not work??? What about PCI retry? 2329 * on C level chips. Need to test, but for now, play it safe. 2330 */ 2331 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2332 | AHC_CACHETHEN_BUG; 2333 2334#if 0 2335 uint32_t devconfig; 2336 2337 /* 2338 * Cachesize must also be zero due to stray DAC 2339 * problem when sitting behind some bridges. 2340 */ 2341 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 2342 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 2343 devconfig |= MRDCEN; 2344 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 2345#endif 2346 ahc->flags |= AHC_NEWEEPROM_FMT; 2347 ahc->instruction_ram_size = 512; 2348 return (0); 2349} 2350 2351static int 2352ahc_aic7895h_setup(struct ahc_softc *ahc) 2353{ 2354 int error = ahc_aic7895_setup(ahc); 2355 2356 ahc->features |= AHC_HVD; 2357 2358 return error; 2359} 2360 2361static int 2362ahc_aic7896_setup(struct ahc_softc *ahc) 2363{ 2364 ahc_dev_softc_t pci; 2365 2366 pci = ahc->dev_softc; 2367 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2368 ahc->chip = AHC_AIC7896; 2369 ahc->features = AHC_AIC7896_FE; 2370 ahc->flags |= AHC_NEWEEPROM_FMT; 2371 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2372 ahc->instruction_ram_size = 768; 2373 return (0); 2374} 2375 2376static int 2377ahc_aic7899_setup(struct ahc_softc *ahc) 2378{ 2379 ahc_dev_softc_t pci; 2380 2381 pci = ahc->dev_softc; 2382 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2383 ahc->chip = AHC_AIC7899; 2384 ahc->features = AHC_AIC7899_FE; 2385 ahc->flags |= AHC_NEWEEPROM_FMT; 2386 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2387 ahc->instruction_ram_size = 1024; 2388 return (0); 2389} 2390 2391static int 2392ahc_aha29160C_setup(struct ahc_softc *ahc) 2393{ 2394 int error; 2395 2396 error = ahc_aic7899_setup(ahc); 2397 if (error != 0) 2398 return (error); 2399 ahc->features |= AHC_REMOVABLE; 2400 return (0); 2401} 2402 2403static int 2404ahc_raid_setup(struct ahc_softc *ahc) 2405{ 2406 printf("RAID functionality unsupported\n"); 2407 return (ENXIO); 2408} 2409 2410static int 2411ahc_aha394XX_setup(struct ahc_softc *ahc) 2412{ 2413 ahc_dev_softc_t pci; 2414 2415 pci = ahc->dev_softc; 2416 switch (ahc_get_pci_slot(pci)) { 2417 case AHC_394X_SLOT_CHANNEL_A: 2418 ahc->channel = 'A'; 2419 break; 2420 case AHC_394X_SLOT_CHANNEL_B: 2421 ahc->channel = 'B'; 2422 break; 2423 default: 2424 printf("adapter at unexpected slot %d\n" 2425 "unable to map to a channel\n", 2426 ahc_get_pci_slot(pci)); 2427 ahc->channel = 'A'; 2428 } 2429 return (0); 2430} 2431 2432static int 2433ahc_aha398XX_setup(struct ahc_softc *ahc) 2434{ 2435 ahc_dev_softc_t pci; 2436 2437 pci = ahc->dev_softc; 2438 switch (ahc_get_pci_slot(pci)) { 2439 case AHC_398X_SLOT_CHANNEL_A: 2440 ahc->channel = 'A'; 2441 break; 2442 case AHC_398X_SLOT_CHANNEL_B: 2443 ahc->channel = 'B'; 2444 break; 2445 case AHC_398X_SLOT_CHANNEL_C: 2446 ahc->channel = 'C'; 2447 break; 2448 default: 2449 printf("adapter at unexpected slot %d\n" 2450 "unable to map to a channel\n", 2451 ahc_get_pci_slot(pci)); 2452 ahc->channel = 'A'; 2453 break; 2454 } 2455 ahc->flags |= AHC_LARGE_SEEPROM; 2456 return (0); 2457} 2458 2459static int 2460ahc_aha494XX_setup(struct ahc_softc *ahc) 2461{ 2462 ahc_dev_softc_t pci; 2463 2464 pci = ahc->dev_softc; 2465 switch (ahc_get_pci_slot(pci)) { 2466 case AHC_494X_SLOT_CHANNEL_A: 2467 ahc->channel = 'A'; 2468 break; 2469 case AHC_494X_SLOT_CHANNEL_B: 2470 ahc->channel = 'B'; 2471 break; 2472 case AHC_494X_SLOT_CHANNEL_C: 2473 ahc->channel = 'C'; 2474 break; 2475 case AHC_494X_SLOT_CHANNEL_D: 2476 ahc->channel = 'D'; 2477 break; 2478 default: 2479 printf("adapter at unexpected slot %d\n" 2480 "unable to map to a channel\n", 2481 ahc_get_pci_slot(pci)); 2482 ahc->channel = 'A'; 2483 } 2484 ahc->flags |= AHC_LARGE_SEEPROM; 2485 return (0); 2486} 2487