1d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams/* 2d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * This file is provided under a dual BSD/GPLv2 license. When using or 3d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * redistributing this file, you may do so under either license. 4d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * 5d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * GPL LICENSE SUMMARY 6d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * 7d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * 9d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * This program is free software; you can redistribute it and/or modify 10d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * it under the terms of version 2 of the GNU General Public License as 11d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * published by the Free Software Foundation. 12d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * 13d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * This program is distributed in the hope that it will be useful, but 14d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * WITHOUT ANY WARRANTY; without even the implied warranty of 15d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * General Public License for more details. 17d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * 18d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * You should have received a copy of the GNU General Public License 19d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * along with this program; if not, write to the Free Software 20d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * The full GNU General Public License is included in this distribution 22d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * in the file called LICENSE.GPL. 23d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * 24d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * BSD LICENSE 25d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * 26d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * All rights reserved. 28d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * 29d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * Redistribution and use in source and binary forms, with or without 30d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * modification, are permitted provided that the following conditions 31d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * are met: 32d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * 33d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * * Redistributions of source code must retain the above copyright 34d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * notice, this list of conditions and the following disclaimer. 35d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * * Redistributions in binary form must reproduce the above copyright 36d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * notice, this list of conditions and the following disclaimer in 37d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * the documentation and/or other materials provided with the 38d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * distribution. 39d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * * Neither the name of Intel Corporation nor the names of its 40d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * contributors may be used to endorse or promote products derived 41d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * from this software without specific prior written permission. 42d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * 43d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams */ 55d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#ifndef _ISCI_PROBE_ROMS_H_ 56d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#define _ISCI_PROBE_ROMS_H_ 57d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 58d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#ifdef __KERNEL__ 59d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#include <linux/firmware.h> 60d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#include <linux/pci.h> 61bf482c6069b514b7fe57a048ae1b6f11cf3bb10cDave Jiang#include <linux/efi.h> 62ce2b3261b6765c3b80fda95426c73e8d3bb1b035Dan Williams#include "isci.h" 63d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 64e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams#define SCIC_SDS_PARM_NO_SPEED 0 65e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 66e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams/* generation 1 (i.e. 1.5 Gb/s) */ 67e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams#define SCIC_SDS_PARM_GEN1_SPEED 1 68e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 69e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams/* generation 2 (i.e. 3.0 Gb/s) */ 70e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams#define SCIC_SDS_PARM_GEN2_SPEED 2 71e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 72e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams/* generation 3 (i.e. 6.0 Gb/s) */ 73e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams#define SCIC_SDS_PARM_GEN3_SPEED 3 74e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams#define SCIC_SDS_PARM_MAX_SPEED SCIC_SDS_PARM_GEN3_SPEED 75e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 76e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams/* parameters that can be set by module parameters */ 7789a7301f21fb00e753089671eb9e4132aab8ea08Dan Williamsstruct sci_user_parameters { 78e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams struct sci_phy_user_params { 79e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams /** 80e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * This field specifies the NOTIFY (ENABLE SPIN UP) primitive 81e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * insertion frequency for this phy index. 82e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams */ 83e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams u32 notify_enable_spin_up_insertion_frequency; 84e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 85e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams /** 86e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * This method specifies the number of transmitted DWORDs within which 87e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * to transmit a single ALIGN primitive. This value applies regardless 88e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * of what type of device is attached or connection state. A value of 89e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * 0 indicates that no ALIGN primitives will be inserted. 90e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams */ 91e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams u16 align_insertion_frequency; 92e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 93e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams /** 94e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * This method specifies the number of transmitted DWORDs within which 95e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * to transmit 2 ALIGN primitives. This applies for SAS connections 96e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * only. A minimum value of 3 is required for this field. 97e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams */ 98e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams u16 in_connection_align_insertion_frequency; 99e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 100e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams /** 101e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * This field indicates the maximum speed generation to be utilized 102e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * by phys in the supplied port. 103e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s). 104e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s). 105e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s). 106e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams */ 107e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams u8 max_speed_generation; 108e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 109e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams } phys[SCI_MAX_PHYS]; 110e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 111e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams /** 112e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * This field specifies the maximum number of direct attached devices 113e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * that can have power supplied to them simultaneously. 114e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams */ 1157000f7c71e2457391e3249eac1ae53c91f49a8c0Andrzej Jakowski u8 max_concurr_spinup; 116e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 117e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams /** 118e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * This field specifies the number of seconds to allow a phy to consume 119e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * power before yielding to another phy. 120e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * 121e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams */ 122e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams u8 phy_spin_up_delay_interval; 123e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 124e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams /** 125e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * These timer values specifies how long a link will remain open with no 126e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * activity in increments of a microsecond, it can be in increments of 127e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * 100 microseconds if the upper most bit is set. 128e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * 129e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams */ 130e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams u16 stp_inactivity_timeout; 131e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams u16 ssp_inactivity_timeout; 132e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 133e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams /** 134e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * These timer values specifies how long a link will remain open in increments 135e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * of 100 microseconds. 136e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * 137e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams */ 138e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams u16 stp_max_occupancy_timeout; 139e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams u16 ssp_max_occupancy_timeout; 140e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 141e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams /** 142e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * This timer value specifies how long a link will remain open with no 143e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * outbound traffic in increments of a microsecond. 144e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams * 145e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams */ 146e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams u8 no_outbound_task_timeout; 147e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 148e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams}; 149e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 150e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams#define SCIC_SDS_PARM_PHY_MASK_MIN 0x0 151e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams#define SCIC_SDS_PARM_PHY_MASK_MAX 0xF 152e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams#define MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT 4 153e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams 15489a7301f21fb00e753089671eb9e4132aab8ea08Dan Williamsstruct sci_oem_params; 155594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiangint sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version); 156d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 157e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williamsstruct isci_orom; 158e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williamsstruct isci_orom *isci_request_oprom(struct pci_dev *pdev); 15989a7301f21fb00e753089671eb9e4132aab8ea08Dan Williamsenum sci_status isci_parse_oem_parameters(struct sci_oem_params *oem, 160e2f8db509fdd354bb7a68c86515e9d2d8909ccc9Dan Williams struct isci_orom *orom, int scu_index); 161d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williamsstruct isci_orom *isci_request_firmware(struct pci_dev *pdev, const struct firmware *fw); 1628db37aabaceb3dcd18754c1e782d4474e4052c81Dave Jiangstruct isci_orom *isci_get_efi_var(struct pci_dev *pdev); 1633b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams 1643b67c1f376acb24b7c6679f75275ac5a96792986Dan Williamsstruct isci_oem_hdr { 1653b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams u8 sig[4]; 1663b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams u8 rev_major; 1673b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams u8 rev_minor; 1683b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams u16 len; 1693b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams u8 checksum; 1703b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams u8 reserved1; 1713b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams u16 reserved2; 1723b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams} __attribute__ ((packed)); 1733b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams 174d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#else 175d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#define SCI_MAX_PORTS 4 176d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#define SCI_MAX_PHYS 4 177ca507b98e65f539e0b3866b6aa8efd76c13be285Dave Jiang#define SCI_MAX_CONTROLLERS 2 178d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#endif 179d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 180d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#define ISCI_FW_NAME "isci/isci_firmware.bin" 181d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 182d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#define ROMSIGNATURE 0xaa55 183d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 1843b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams#define ISCI_OEM_SIG "$OEM" 1853b67c1f376acb24b7c6679f75275ac5a96792986Dan Williams#define ISCI_OEM_SIG_SIZE 4 186d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#define ISCI_ROM_SIG "ISCUOEMB" 187d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#define ISCI_ROM_SIG_SIZE 8 188d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 189ca507b98e65f539e0b3866b6aa8efd76c13be285Dave Jiang#define ISCI_EFI_VENDOR_GUID \ 190ca507b98e65f539e0b3866b6aa8efd76c13be285Dave Jiang EFI_GUID(0x193dfefa, 0xa445, 0x4302, 0x99, 0xd8, 0xef, 0x3a, 0xad, \ 191ca507b98e65f539e0b3866b6aa8efd76c13be285Dave Jiang 0x1a, 0x04, 0xc6) 1922e8320f751030a12efc3e64ee857bfa4647f81feDave Jiang#define ISCI_EFI_VAR_NAME "RstScuO" 193d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 194594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang#define ISCI_ROM_VER_1_0 0x10 195594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang#define ISCI_ROM_VER_1_1 0x11 1969fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin#define ISCI_ROM_VER_1_3 0x13 1979fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin#define ISCI_ROM_VER_LATEST ISCI_ROM_VER_1_3 198594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang 19907373a5caa29e4159ef1ea5e72985ddaf013519aHenryk Dembkowski/* Allowed PORT configuration modes APC Automatic PORT configuration mode is 20007373a5caa29e4159ef1ea5e72985ddaf013519aHenryk Dembkowski * defined by the OEM configuration parameters providing no PHY_MASK parameters 20107373a5caa29e4159ef1ea5e72985ddaf013519aHenryk Dembkowski * for any PORT. i.e. There are no phys assigned to any of the ports at start. 20207373a5caa29e4159ef1ea5e72985ddaf013519aHenryk Dembkowski * MPC Manual PORT configuration mode is defined by the OEM configuration 20307373a5caa29e4159ef1ea5e72985ddaf013519aHenryk Dembkowski * parameters providing a PHY_MASK value for any PORT. It is assumed that any 20407373a5caa29e4159ef1ea5e72985ddaf013519aHenryk Dembkowski * PORT with no PHY_MASK is an invalid port and not all PHYs must be assigned. 20507373a5caa29e4159ef1ea5e72985ddaf013519aHenryk Dembkowski * A PORT_PHY mask that assigns just a single PHY to a port and no other PHYs 20607373a5caa29e4159ef1ea5e72985ddaf013519aHenryk Dembkowski * being assigned is sufficient to declare manual PORT configuration. 20707373a5caa29e4159ef1ea5e72985ddaf013519aHenryk Dembkowski */ 20889a7301f21fb00e753089671eb9e4132aab8ea08Dan Williamsenum sci_port_configuration_mode { 2094eefd2518aa04e1c69118252dc23e3444e694bc1Dan Williams SCIC_PORT_MANUAL_CONFIGURATION_MODE = 0, 2104eefd2518aa04e1c69118252dc23e3444e694bc1Dan Williams SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE = 1 21107373a5caa29e4159ef1ea5e72985ddaf013519aHenryk Dembkowski}; 21207373a5caa29e4159ef1ea5e72985ddaf013519aHenryk Dembkowski 213d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williamsstruct sci_bios_oem_param_block_hdr { 214d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint8_t signature[ISCI_ROM_SIG_SIZE]; 215d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint16_t total_block_length; 216d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint8_t hdr_length; 217d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint8_t version; 218d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint8_t preboot_source; 219d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint8_t num_elements; 220f22be5d8386d9da67bfe02693806fbaff7b078daDan Williams uint16_t element_length; 221d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint8_t reserved[8]; 222d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams} __attribute__ ((packed)); 223d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 22489a7301f21fb00e753089671eb9e4132aab8ea08Dan Williamsstruct sci_oem_params { 225d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams struct { 226d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint8_t mode_type; 2277000f7c71e2457391e3249eac1ae53c91f49a8c0Andrzej Jakowski uint8_t max_concurr_spin_up; 228594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang /* 229594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * This bitfield indicates the OEM's desired default Tx 230594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * Spread Spectrum Clocking (SSC) settings for SATA and SAS. 231594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * NOTE: Default SSC Modulation Frequency is 31.5KHz. 232594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang */ 233594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang union { 234594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang struct { 235594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang /* 236594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * NOTE: Max spread for SATA is +0 / -5000 PPM. 237594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * Down-spreading SSC (only method allowed for SATA): 238594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * SATA SSC Tx Disabled = 0x0 239594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 240594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 241594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 242594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 243594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang */ 244594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang uint8_t ssc_sata_tx_spread_level:4; 245594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang /* 246594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * SAS SSC Tx Disabled = 0x0 247594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * 248594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * NOTE: Max spread for SAS down-spreading +0 / 249594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * -2300 PPM 250594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * Down-spreading SSC: 251594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 252594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 253594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * 254594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * NOTE: Max spread for SAS center-spreading +2300 / 255594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * -2300 PPM 256594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * Center-spreading SSC: 257594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 258594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 259594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang */ 260594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang uint8_t ssc_sas_tx_spread_level:3; 261594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang /* 262594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * NOTE: Refer to the SSC section of the SAS 2.x 263594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * Specification for proper setting of this field. 264594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * For standard SAS Initiator SAS PHY operation it 265594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * should be 0 for Down-spreading. 266594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * SAS SSC Tx spread type: 267594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * Down-spreading SSC = 0 268594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang * Center-spreading SSC = 1 269594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang */ 270594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang uint8_t ssc_sas_tx_type:1; 271594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang }; 272594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang uint8_t do_enable_ssc; 273594e566ae5985e0cc3185ac21509a86e90aad577Dave Jiang }; 2749fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin /* 2759fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * This field indicates length of the SAS/SATA cable between 2769fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * host and device. 2779fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * This field is used make relationship between analog 2789fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * parameters of the phy in the silicon and length of the cable. 2799fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * Supported cable attenuation levels: 2809fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * "short"- up to 3m, "medium"-3m to 6m, and "long"- more than 2819fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * 6m. 2829fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * 2839fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * This is bit mask field: 2849fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * 2859fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * BIT: (MSB) 7 6 5 4 2869fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Medium cable 2879fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * length assignment 2889fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * BIT: 3 2 1 0 (LSB) 2899fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Long cable length 2909fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * assignment 2919fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * 2929fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * BITS 7-4 are set when the cable length is assigned to medium 2939fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * BITS 3-0 are set when the cable length is assigned to long 2949fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * 2959fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * The BIT positions are clear when the cable length is 2969fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * assigned to short. 2979fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * 2989fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * Setting the bits for both long and medium cable length is 2999fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * undefined. 3009fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * 3019fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * A value of 0x84 would assign 3029fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * phy3 - medium 3039fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * phy2 - long 3049fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * phy1 - short 3059fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin * phy0 - short 3069fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin */ 3079fee607f0b29adabd72265a847b8e421dff10d66Jeff Skirvin uint8_t cable_selection_mask; 308d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams } controller; 309d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 310d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams struct { 311d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint8_t phy_mask; 312d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams } ports[SCI_MAX_PORTS]; 313d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 314d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams struct sci_phy_oem_params { 315d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams struct { 316d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint32_t high; 317d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint32_t low; 318d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams } sas_address; 319d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 320d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint32_t afe_tx_amp_control0; 321d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint32_t afe_tx_amp_control1; 322d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint32_t afe_tx_amp_control2; 323d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams uint32_t afe_tx_amp_control3; 324d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams } phys[SCI_MAX_PHYS]; 325d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams} __attribute__ ((packed)); 326d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 327d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williamsstruct isci_orom { 328d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams struct sci_bios_oem_param_block_hdr hdr; 32989a7301f21fb00e753089671eb9e4132aab8ea08Dan Williams struct sci_oem_params ctrl[SCI_MAX_CONTROLLERS]; 330d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams} __attribute__ ((packed)); 331d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams 332d044af17aacd03a1f4fced1af4b7570d205c8fd9Dan Williams#endif 333