mv_chips.h revision 0b15fb1fdfd403726542cb6111bc916b7a9f7fad
1/* 2 * Marvell 88SE64xx/88SE94xx register IO interface 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24*/ 25 26 27#ifndef _MV_CHIPS_H_ 28#define _MV_CHIPS_H_ 29 30#define mr32(reg) readl(regs + reg) 31#define mw32(reg, val) writel((val), regs + reg) 32#define mw32_f(reg, val) do { \ 33 mw32(reg, val); \ 34 mr32(reg); \ 35 } while (0) 36 37#define iow32(reg, val) outl(val, (unsigned long)(regs + reg)) 38#define ior32(reg) inl((unsigned long)(regs + reg)) 39#define iow16(reg, val) outw((unsigned long)(val, regs + reg)) 40#define ior16(reg) inw((unsigned long)(regs + reg)) 41#define iow8(reg, val) outb((unsigned long)(val, regs + reg)) 42#define ior8(reg) inb((unsigned long)(regs + reg)) 43 44static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr) 45{ 46 void __iomem *regs = mvi->regs; 47 mw32(MVS_CMD_ADDR, addr); 48 return mr32(MVS_CMD_DATA); 49} 50 51static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val) 52{ 53 void __iomem *regs = mvi->regs; 54 mw32(MVS_CMD_ADDR, addr); 55 mw32(MVS_CMD_DATA, val); 56} 57 58static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port) 59{ 60 void __iomem *regs = mvi->regs; 61 return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) : 62 mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4); 63} 64 65static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val) 66{ 67 void __iomem *regs = mvi->regs; 68 if (port < 4) 69 mw32(MVS_P0_SER_CTLSTAT + port * 4, val); 70 else 71 mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val); 72} 73 74static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off, 75 u32 off2, u32 port) 76{ 77 void __iomem *regs = mvi->regs + off; 78 void __iomem *regs2 = mvi->regs + off2; 79 return (port < 4) ? readl(regs + port * 8) : 80 readl(regs2 + (port - 4) * 8); 81} 82 83static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2, 84 u32 port, u32 val) 85{ 86 void __iomem *regs = mvi->regs + off; 87 void __iomem *regs2 = mvi->regs + off2; 88 if (port < 4) 89 writel(val, regs + port * 8); 90 else 91 writel(val, regs2 + (port - 4) * 8); 92} 93 94static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port) 95{ 96 return mvs_read_port(mvi, MVS_P0_CFG_DATA, 97 MVS_P4_CFG_DATA, port); 98} 99 100static inline void mvs_write_port_cfg_data(struct mvs_info *mvi, 101 u32 port, u32 val) 102{ 103 mvs_write_port(mvi, MVS_P0_CFG_DATA, 104 MVS_P4_CFG_DATA, port, val); 105} 106 107static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi, 108 u32 port, u32 addr) 109{ 110 mvs_write_port(mvi, MVS_P0_CFG_ADDR, 111 MVS_P4_CFG_ADDR, port, addr); 112 mdelay(10); 113} 114 115static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port) 116{ 117 return mvs_read_port(mvi, MVS_P0_VSR_DATA, 118 MVS_P4_VSR_DATA, port); 119} 120 121static inline void mvs_write_port_vsr_data(struct mvs_info *mvi, 122 u32 port, u32 val) 123{ 124 mvs_write_port(mvi, MVS_P0_VSR_DATA, 125 MVS_P4_VSR_DATA, port, val); 126} 127 128static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi, 129 u32 port, u32 addr) 130{ 131 mvs_write_port(mvi, MVS_P0_VSR_ADDR, 132 MVS_P4_VSR_ADDR, port, addr); 133 mdelay(10); 134} 135 136static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port) 137{ 138 return mvs_read_port(mvi, MVS_P0_INT_STAT, 139 MVS_P4_INT_STAT, port); 140} 141 142static inline void mvs_write_port_irq_stat(struct mvs_info *mvi, 143 u32 port, u32 val) 144{ 145 mvs_write_port(mvi, MVS_P0_INT_STAT, 146 MVS_P4_INT_STAT, port, val); 147} 148 149static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port) 150{ 151 return mvs_read_port(mvi, MVS_P0_INT_MASK, 152 MVS_P4_INT_MASK, port); 153 154} 155 156static inline void mvs_write_port_irq_mask(struct mvs_info *mvi, 157 u32 port, u32 val) 158{ 159 mvs_write_port(mvi, MVS_P0_INT_MASK, 160 MVS_P4_INT_MASK, port, val); 161} 162 163static inline void __devinit mvs_phy_hacks(struct mvs_info *mvi) 164{ 165 u32 tmp; 166 167 /* workaround for SATA R-ERR, to ignore phy glitch */ 168 tmp = mvs_cr32(mvi, CMD_PHY_TIMER); 169 tmp &= ~(1 << 9); 170 tmp |= (1 << 10); 171 mvs_cw32(mvi, CMD_PHY_TIMER, tmp); 172 173 /* enable retry 127 times */ 174 mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f); 175 176 /* extend open frame timeout to max */ 177 tmp = mvs_cr32(mvi, CMD_SAS_CTL0); 178 tmp &= ~0xffff; 179 tmp |= 0x3fff; 180 mvs_cw32(mvi, CMD_SAS_CTL0, tmp); 181 182 /* workaround for WDTIMEOUT , set to 550 ms */ 183 mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000); 184 185 /* not to halt for different port op during wideport link change */ 186 mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d); 187 188 /* workaround for Seagate disk not-found OOB sequence, recv 189 * COMINIT before sending out COMWAKE */ 190 tmp = mvs_cr32(mvi, CMD_PHY_MODE_21); 191 tmp &= 0x0000ffff; 192 tmp |= 0x00fa0000; 193 mvs_cw32(mvi, CMD_PHY_MODE_21, tmp); 194 195 tmp = mvs_cr32(mvi, CMD_PHY_TIMER); 196 tmp &= 0x1fffffff; 197 tmp |= (2U << 29); /* 8 ms retry */ 198 mvs_cw32(mvi, CMD_PHY_TIMER, tmp); 199} 200 201static inline void mvs_int_sata(struct mvs_info *mvi) 202{ 203 u32 tmp; 204 void __iomem *regs = mvi->regs; 205 tmp = mr32(MVS_INT_STAT_SRS_0); 206 if (tmp) 207 mw32(MVS_INT_STAT_SRS_0, tmp); 208 MVS_CHIP_DISP->clear_active_cmds(mvi); 209} 210 211static inline void mvs_int_full(struct mvs_info *mvi) 212{ 213 void __iomem *regs = mvi->regs; 214 u32 tmp, stat; 215 int i; 216 217 stat = mr32(MVS_INT_STAT); 218 mvs_int_rx(mvi, false); 219 220 for (i = 0; i < mvi->chip->n_phy; i++) { 221 tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED); 222 if (tmp) 223 mvs_int_port(mvi, i, tmp); 224 } 225 226 if (stat & CINT_SRS) 227 mvs_int_sata(mvi); 228 229 mw32(MVS_INT_STAT, stat); 230} 231 232static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx) 233{ 234 void __iomem *regs = mvi->regs; 235 mw32(MVS_TX_PROD_IDX, tx); 236} 237 238static inline u32 mvs_rx_update(struct mvs_info *mvi) 239{ 240 void __iomem *regs = mvi->regs; 241 return mr32(MVS_RX_CONS_IDX); 242} 243 244static inline u32 mvs_get_prd_size(void) 245{ 246 return sizeof(struct mvs_prd); 247} 248 249static inline u32 mvs_get_prd_count(void) 250{ 251 return MAX_SG_ENTRY; 252} 253 254static inline void mvs_show_pcie_usage(struct mvs_info *mvi) 255{ 256 u16 link_stat, link_spd; 257 const char *spd[] = { 258 "UnKnown", 259 "2.5", 260 "5.0", 261 }; 262 if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0) 263 return; 264 265 pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat); 266 link_spd = (link_stat & PLS_LINK_SPD) >> PLS_LINK_SPD_OFFS; 267 if (link_spd >= 3) 268 link_spd = 0; 269 dev_printk(KERN_INFO, mvi->dev, 270 "mvsas: PCI-E x%u, Bandwidth Usage: %s Gbps\n", 271 (link_stat & PLS_NEG_LINK_WD) >> PLS_NEG_LINK_WD_OFFS, 272 spd[link_spd]); 273} 274 275static inline u32 mvs_hw_max_link_rate(void) 276{ 277 return MAX_LINK_RATE; 278} 279 280#endif /* _MV_CHIPS_H_ */ 281 282