mv_chips.h revision dd4969a892ea522ecf9d7d826ba1531ce044d46f 
1#ifndef _MV_CHIPS_H_
2#define _MV_CHIPS_H_
3
4#define mr32(reg)	readl(regs + MVS_##reg)
5#define mw32(reg,val)	writel((val), regs + MVS_##reg)
6#define mw32_f(reg,val)	do {			\
7	writel((val), regs + MVS_##reg);	\
8	readl(regs + MVS_##reg);		\
9	} while (0)
10
11static inline u32 mvs_cr32(void __iomem *regs, u32 addr)
12{
13	mw32(CMD_ADDR, addr);
14	return mr32(CMD_DATA);
15}
16
17static inline void mvs_cw32(void __iomem *regs, u32 addr, u32 val)
18{
19	mw32(CMD_ADDR, addr);
20	mw32(CMD_DATA, val);
21}
22
23static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
24{
25	void __iomem *regs = mvi->regs;
26	return (port < 4)?mr32(P0_SER_CTLSTAT + port * 4):
27		mr32(P4_SER_CTLSTAT + (port - 4) * 4);
28}
29
30static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
31{
32	void __iomem *regs = mvi->regs;
33	if (port < 4)
34		mw32(P0_SER_CTLSTAT + port * 4, val);
35	else
36		mw32(P4_SER_CTLSTAT + (port - 4) * 4, val);
37}
38
39static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off, u32 off2, u32 port)
40{
41	void __iomem *regs = mvi->regs + off;
42	void __iomem *regs2 = mvi->regs + off2;
43	return (port < 4)?readl(regs + port * 8):
44		readl(regs2 + (port - 4) * 8);
45}
46
47static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
48				u32 port, u32 val)
49{
50	void __iomem *regs = mvi->regs + off;
51	void __iomem *regs2 = mvi->regs + off2;
52	if (port < 4)
53		writel(val, regs + port * 8);
54	else
55		writel(val, regs2 + (port - 4) * 8);
56}
57
58static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
59{
60	return mvs_read_port(mvi, MVS_P0_CFG_DATA,
61			MVS_P4_CFG_DATA, port);
62}
63
64static inline void mvs_write_port_cfg_data(struct mvs_info *mvi, u32 port, u32 val)
65{
66	mvs_write_port(mvi, MVS_P0_CFG_DATA,
67			MVS_P4_CFG_DATA, port, val);
68}
69
70static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi, u32 port, u32 addr)
71{
72	mvs_write_port(mvi, MVS_P0_CFG_ADDR,
73			MVS_P4_CFG_ADDR, port, addr);
74}
75
76static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
77{
78	return mvs_read_port(mvi, MVS_P0_VSR_DATA,
79			MVS_P4_VSR_DATA, port);
80}
81
82static inline void mvs_write_port_vsr_data(struct mvs_info *mvi, u32 port, u32 val)
83{
84	mvs_write_port(mvi, MVS_P0_VSR_DATA,
85			MVS_P4_VSR_DATA, port, val);
86}
87
88static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi, u32 port, u32 addr)
89{
90	mvs_write_port(mvi, MVS_P0_VSR_ADDR,
91			MVS_P4_VSR_ADDR, port, addr);
92}
93
94static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
95{
96	return mvs_read_port(mvi, MVS_P0_INT_STAT,
97			MVS_P4_INT_STAT, port);
98}
99
100static inline void mvs_write_port_irq_stat(struct mvs_info *mvi, u32 port, u32 val)
101{
102	mvs_write_port(mvi, MVS_P0_INT_STAT,
103			MVS_P4_INT_STAT, port, val);
104}
105
106static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
107{
108	return mvs_read_port(mvi, MVS_P0_INT_MASK,
109			MVS_P4_INT_MASK, port);
110}
111
112static inline void mvs_write_port_irq_mask(struct mvs_info *mvi, u32 port, u32 val)
113{
114	mvs_write_port(mvi, MVS_P0_INT_MASK,
115			MVS_P4_INT_MASK, port, val);
116}
117
118#endif
119