1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2011 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7#ifndef __QLA_DEF_H 8#define __QLA_DEF_H 9 10#include <linux/kernel.h> 11#include <linux/init.h> 12#include <linux/types.h> 13#include <linux/module.h> 14#include <linux/list.h> 15#include <linux/pci.h> 16#include <linux/dma-mapping.h> 17#include <linux/sched.h> 18#include <linux/slab.h> 19#include <linux/dmapool.h> 20#include <linux/mempool.h> 21#include <linux/spinlock.h> 22#include <linux/completion.h> 23#include <linux/interrupt.h> 24#include <linux/workqueue.h> 25#include <linux/firmware.h> 26#include <linux/aer.h> 27#include <linux/mutex.h> 28 29#include <scsi/scsi.h> 30#include <scsi/scsi_host.h> 31#include <scsi/scsi_device.h> 32#include <scsi/scsi_cmnd.h> 33#include <scsi/scsi_transport_fc.h> 34#include <scsi/scsi_bsg_fc.h> 35 36#include "qla_bsg.h" 37#include "qla_nx.h" 38#define QLA2XXX_DRIVER_NAME "qla2xxx" 39#define QLA2XXX_APIDEV "ql2xapidev" 40 41/* 42 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 43 * but that's fine as we don't look at the last 24 ones for 44 * ISP2100 HBAs. 45 */ 46#define MAILBOX_REGISTER_COUNT_2100 8 47#define MAILBOX_REGISTER_COUNT_2200 24 48#define MAILBOX_REGISTER_COUNT 32 49 50#define QLA2200A_RISC_ROM_VER 4 51#define FPM_2300 6 52#define FPM_2310 7 53 54#include "qla_settings.h" 55 56/* 57 * Data bit definitions 58 */ 59#define BIT_0 0x1 60#define BIT_1 0x2 61#define BIT_2 0x4 62#define BIT_3 0x8 63#define BIT_4 0x10 64#define BIT_5 0x20 65#define BIT_6 0x40 66#define BIT_7 0x80 67#define BIT_8 0x100 68#define BIT_9 0x200 69#define BIT_10 0x400 70#define BIT_11 0x800 71#define BIT_12 0x1000 72#define BIT_13 0x2000 73#define BIT_14 0x4000 74#define BIT_15 0x8000 75#define BIT_16 0x10000 76#define BIT_17 0x20000 77#define BIT_18 0x40000 78#define BIT_19 0x80000 79#define BIT_20 0x100000 80#define BIT_21 0x200000 81#define BIT_22 0x400000 82#define BIT_23 0x800000 83#define BIT_24 0x1000000 84#define BIT_25 0x2000000 85#define BIT_26 0x4000000 86#define BIT_27 0x8000000 87#define BIT_28 0x10000000 88#define BIT_29 0x20000000 89#define BIT_30 0x40000000 90#define BIT_31 0x80000000 91 92#define LSB(x) ((uint8_t)(x)) 93#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 94 95#define LSW(x) ((uint16_t)(x)) 96#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 97 98#define LSD(x) ((uint32_t)((uint64_t)(x))) 99#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 100 101#define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 102 103/* 104 * I/O register 105*/ 106 107#define RD_REG_BYTE(addr) readb(addr) 108#define RD_REG_WORD(addr) readw(addr) 109#define RD_REG_DWORD(addr) readl(addr) 110#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 111#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 112#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 113#define WRT_REG_BYTE(addr, data) writeb(data,addr) 114#define WRT_REG_WORD(addr, data) writew(data,addr) 115#define WRT_REG_DWORD(addr, data) writel(data,addr) 116 117/* 118 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 119 * 133Mhz slot. 120 */ 121#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 122#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 123 124/* 125 * Fibre Channel device definitions. 126 */ 127#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 128#define MAX_FIBRE_DEVICES_2100 512 129#define MAX_FIBRE_DEVICES_2400 2048 130#define MAX_FIBRE_DEVICES_LOOP 128 131#define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 132#define MAX_FIBRE_LUNS 0xFFFF 133#define MAX_HOST_COUNT 16 134 135/* 136 * Host adapter default definitions. 137 */ 138#define MAX_BUSES 1 /* We only have one bus today */ 139#define MIN_LUNS 8 140#define MAX_LUNS MAX_FIBRE_LUNS 141#define MAX_CMDS_PER_LUN 255 142 143/* 144 * Fibre Channel device definitions. 145 */ 146#define SNS_LAST_LOOP_ID_2100 0xfe 147#define SNS_LAST_LOOP_ID_2300 0x7ff 148 149#define LAST_LOCAL_LOOP_ID 0x7d 150#define SNS_FL_PORT 0x7e 151#define FABRIC_CONTROLLER 0x7f 152#define SIMPLE_NAME_SERVER 0x80 153#define SNS_FIRST_LOOP_ID 0x81 154#define MANAGEMENT_SERVER 0xfe 155#define BROADCAST 0xff 156 157/* 158 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 159 * valid range of an N-PORT id is 0 through 0x7ef. 160 */ 161#define NPH_LAST_HANDLE 0x7ef 162#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ 163#define NPH_SNS 0x7fc /* FFFFFC */ 164#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 165#define NPH_F_PORT 0x7fe /* FFFFFE */ 166#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 167 168#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 169#include "qla_fw.h" 170 171/* 172 * Timeout timer counts in seconds 173 */ 174#define PORT_RETRY_TIME 1 175#define LOOP_DOWN_TIMEOUT 60 176#define LOOP_DOWN_TIME 255 /* 240 */ 177#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 178 179/* Maximum outstanding commands in ISP queues (1-65535) */ 180#define MAX_OUTSTANDING_COMMANDS 1024 181 182/* ISP request and response entry counts (37-65535) */ 183#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 184#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 185#define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 186#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 187#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 188#define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 189 190struct req_que; 191 192/* 193 * (sd.h is not exported, hence local inclusion) 194 * Data Integrity Field tuple. 195 */ 196struct sd_dif_tuple { 197 __be16 guard_tag; /* Checksum */ 198 __be16 app_tag; /* Opaque storage */ 199 __be32 ref_tag; /* Target LBA or indirect LBA */ 200}; 201 202/* 203 * SCSI Request Block 204 */ 205struct srb_cmd { 206 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 207 uint32_t request_sense_length; 208 uint8_t *request_sense_ptr; 209 void *ctx; 210}; 211 212/* 213 * SRB flag definitions 214 */ 215#define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 216#define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 217#define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 218#define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 219#define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 220 221/* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 222#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 223 224/* 225 * SRB extensions. 226 */ 227struct srb_iocb { 228 union { 229 struct { 230 uint16_t flags; 231#define SRB_LOGIN_RETRIED BIT_0 232#define SRB_LOGIN_COND_PLOGI BIT_1 233#define SRB_LOGIN_SKIP_PRLI BIT_2 234 uint16_t data[2]; 235 } logio; 236 struct { 237 /* 238 * Values for flags field below are as 239 * defined in tsk_mgmt_entry struct 240 * for control_flags field in qla_fw.h. 241 */ 242 uint32_t flags; 243 uint32_t lun; 244 uint32_t data; 245 } tmf; 246 } u; 247 248 struct timer_list timer; 249 void (*timeout)(void *); 250}; 251 252/* Values for srb_ctx type */ 253#define SRB_LOGIN_CMD 1 254#define SRB_LOGOUT_CMD 2 255#define SRB_ELS_CMD_RPT 3 256#define SRB_ELS_CMD_HST 4 257#define SRB_CT_CMD 5 258#define SRB_ADISC_CMD 6 259#define SRB_TM_CMD 7 260#define SRB_SCSI_CMD 8 261 262typedef struct srb { 263 atomic_t ref_count; 264 struct fc_port *fcport; 265 uint32_t handle; 266 uint16_t flags; 267 uint16_t type; 268 char *name; 269 int iocbs; 270 union { 271 struct srb_iocb iocb_cmd; 272 struct fc_bsg_job *bsg_job; 273 struct srb_cmd scmd; 274 } u; 275 void (*done)(void *, void *, int); 276 void (*free)(void *, void *); 277} srb_t; 278 279#define GET_CMD_SP(sp) (sp->u.scmd.cmd) 280#define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 281#define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 282 283#define GET_CMD_SENSE_LEN(sp) \ 284 (sp->u.scmd.request_sense_length) 285#define SET_CMD_SENSE_LEN(sp, len) \ 286 (sp->u.scmd.request_sense_length = len) 287#define GET_CMD_SENSE_PTR(sp) \ 288 (sp->u.scmd.request_sense_ptr) 289#define SET_CMD_SENSE_PTR(sp, ptr) \ 290 (sp->u.scmd.request_sense_ptr = ptr) 291 292struct msg_echo_lb { 293 dma_addr_t send_dma; 294 dma_addr_t rcv_dma; 295 uint16_t req_sg_cnt; 296 uint16_t rsp_sg_cnt; 297 uint16_t options; 298 uint32_t transfer_size; 299}; 300 301/* 302 * ISP I/O Register Set structure definitions. 303 */ 304struct device_reg_2xxx { 305 uint16_t flash_address; /* Flash BIOS address */ 306 uint16_t flash_data; /* Flash BIOS data */ 307 uint16_t unused_1[1]; /* Gap */ 308 uint16_t ctrl_status; /* Control/Status */ 309#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 310#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 311#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 312 313 uint16_t ictrl; /* Interrupt control */ 314#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 315#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 316 317 uint16_t istatus; /* Interrupt status */ 318#define ISR_RISC_INT BIT_3 /* RISC interrupt */ 319 320 uint16_t semaphore; /* Semaphore */ 321 uint16_t nvram; /* NVRAM register. */ 322#define NVR_DESELECT 0 323#define NVR_BUSY BIT_15 324#define NVR_WRT_ENABLE BIT_14 /* Write enable */ 325#define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 326#define NVR_DATA_IN BIT_3 327#define NVR_DATA_OUT BIT_2 328#define NVR_SELECT BIT_1 329#define NVR_CLOCK BIT_0 330 331#define NVR_WAIT_CNT 20000 332 333 union { 334 struct { 335 uint16_t mailbox0; 336 uint16_t mailbox1; 337 uint16_t mailbox2; 338 uint16_t mailbox3; 339 uint16_t mailbox4; 340 uint16_t mailbox5; 341 uint16_t mailbox6; 342 uint16_t mailbox7; 343 uint16_t unused_2[59]; /* Gap */ 344 } __attribute__((packed)) isp2100; 345 struct { 346 /* Request Queue */ 347 uint16_t req_q_in; /* In-Pointer */ 348 uint16_t req_q_out; /* Out-Pointer */ 349 /* Response Queue */ 350 uint16_t rsp_q_in; /* In-Pointer */ 351 uint16_t rsp_q_out; /* Out-Pointer */ 352 353 /* RISC to Host Status */ 354 uint32_t host_status; 355#define HSR_RISC_INT BIT_15 /* RISC interrupt */ 356#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 357 358 /* Host to Host Semaphore */ 359 uint16_t host_semaphore; 360 uint16_t unused_3[17]; /* Gap */ 361 uint16_t mailbox0; 362 uint16_t mailbox1; 363 uint16_t mailbox2; 364 uint16_t mailbox3; 365 uint16_t mailbox4; 366 uint16_t mailbox5; 367 uint16_t mailbox6; 368 uint16_t mailbox7; 369 uint16_t mailbox8; 370 uint16_t mailbox9; 371 uint16_t mailbox10; 372 uint16_t mailbox11; 373 uint16_t mailbox12; 374 uint16_t mailbox13; 375 uint16_t mailbox14; 376 uint16_t mailbox15; 377 uint16_t mailbox16; 378 uint16_t mailbox17; 379 uint16_t mailbox18; 380 uint16_t mailbox19; 381 uint16_t mailbox20; 382 uint16_t mailbox21; 383 uint16_t mailbox22; 384 uint16_t mailbox23; 385 uint16_t mailbox24; 386 uint16_t mailbox25; 387 uint16_t mailbox26; 388 uint16_t mailbox27; 389 uint16_t mailbox28; 390 uint16_t mailbox29; 391 uint16_t mailbox30; 392 uint16_t mailbox31; 393 uint16_t fb_cmd; 394 uint16_t unused_4[10]; /* Gap */ 395 } __attribute__((packed)) isp2300; 396 } u; 397 398 uint16_t fpm_diag_config; 399 uint16_t unused_5[0x4]; /* Gap */ 400 uint16_t risc_hw; 401 uint16_t unused_5_1; /* Gap */ 402 uint16_t pcr; /* Processor Control Register. */ 403 uint16_t unused_6[0x5]; /* Gap */ 404 uint16_t mctr; /* Memory Configuration and Timing. */ 405 uint16_t unused_7[0x3]; /* Gap */ 406 uint16_t fb_cmd_2100; /* Unused on 23XX */ 407 uint16_t unused_8[0x3]; /* Gap */ 408 uint16_t hccr; /* Host command & control register. */ 409#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 410#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 411 /* HCCR commands */ 412#define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 413#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 414#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 415#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 416#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 417#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 418#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 419#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 420 421 uint16_t unused_9[5]; /* Gap */ 422 uint16_t gpiod; /* GPIO Data register. */ 423 uint16_t gpioe; /* GPIO Enable register. */ 424#define GPIO_LED_MASK 0x00C0 425#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 426#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 427#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 428#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 429#define GPIO_LED_ALL_OFF 0x0000 430#define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 431#define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 432 433 union { 434 struct { 435 uint16_t unused_10[8]; /* Gap */ 436 uint16_t mailbox8; 437 uint16_t mailbox9; 438 uint16_t mailbox10; 439 uint16_t mailbox11; 440 uint16_t mailbox12; 441 uint16_t mailbox13; 442 uint16_t mailbox14; 443 uint16_t mailbox15; 444 uint16_t mailbox16; 445 uint16_t mailbox17; 446 uint16_t mailbox18; 447 uint16_t mailbox19; 448 uint16_t mailbox20; 449 uint16_t mailbox21; 450 uint16_t mailbox22; 451 uint16_t mailbox23; /* Also probe reg. */ 452 } __attribute__((packed)) isp2200; 453 } u_end; 454}; 455 456struct device_reg_25xxmq { 457 uint32_t req_q_in; 458 uint32_t req_q_out; 459 uint32_t rsp_q_in; 460 uint32_t rsp_q_out; 461}; 462 463typedef union { 464 struct device_reg_2xxx isp; 465 struct device_reg_24xx isp24; 466 struct device_reg_25xxmq isp25mq; 467 struct device_reg_82xx isp82; 468} device_reg_t; 469 470#define ISP_REQ_Q_IN(ha, reg) \ 471 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 472 &(reg)->u.isp2100.mailbox4 : \ 473 &(reg)->u.isp2300.req_q_in) 474#define ISP_REQ_Q_OUT(ha, reg) \ 475 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 476 &(reg)->u.isp2100.mailbox4 : \ 477 &(reg)->u.isp2300.req_q_out) 478#define ISP_RSP_Q_IN(ha, reg) \ 479 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 480 &(reg)->u.isp2100.mailbox5 : \ 481 &(reg)->u.isp2300.rsp_q_in) 482#define ISP_RSP_Q_OUT(ha, reg) \ 483 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 484 &(reg)->u.isp2100.mailbox5 : \ 485 &(reg)->u.isp2300.rsp_q_out) 486 487#define MAILBOX_REG(ha, reg, num) \ 488 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 489 (num < 8 ? \ 490 &(reg)->u.isp2100.mailbox0 + (num) : \ 491 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 492 &(reg)->u.isp2300.mailbox0 + (num)) 493#define RD_MAILBOX_REG(ha, reg, num) \ 494 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 495#define WRT_MAILBOX_REG(ha, reg, num, data) \ 496 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 497 498#define FB_CMD_REG(ha, reg) \ 499 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 500 &(reg)->fb_cmd_2100 : \ 501 &(reg)->u.isp2300.fb_cmd) 502#define RD_FB_CMD_REG(ha, reg) \ 503 RD_REG_WORD(FB_CMD_REG(ha, reg)) 504#define WRT_FB_CMD_REG(ha, reg, data) \ 505 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 506 507typedef struct { 508 uint32_t out_mb; /* outbound from driver */ 509 uint32_t in_mb; /* Incoming from RISC */ 510 uint16_t mb[MAILBOX_REGISTER_COUNT]; 511 long buf_size; 512 void *bufp; 513 uint32_t tov; 514 uint8_t flags; 515#define MBX_DMA_IN BIT_0 516#define MBX_DMA_OUT BIT_1 517#define IOCTL_CMD BIT_2 518} mbx_cmd_t; 519 520#define MBX_TOV_SECONDS 30 521 522/* 523 * ISP product identification definitions in mailboxes after reset. 524 */ 525#define PROD_ID_1 0x4953 526#define PROD_ID_2 0x0000 527#define PROD_ID_2a 0x5020 528#define PROD_ID_3 0x2020 529 530/* 531 * ISP mailbox Self-Test status codes 532 */ 533#define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 534#define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 535#define MBS_BUSY 4 /* Busy. */ 536 537/* 538 * ISP mailbox command complete status codes 539 */ 540#define MBS_COMMAND_COMPLETE 0x4000 541#define MBS_INVALID_COMMAND 0x4001 542#define MBS_HOST_INTERFACE_ERROR 0x4002 543#define MBS_TEST_FAILED 0x4003 544#define MBS_COMMAND_ERROR 0x4005 545#define MBS_COMMAND_PARAMETER_ERROR 0x4006 546#define MBS_PORT_ID_USED 0x4007 547#define MBS_LOOP_ID_USED 0x4008 548#define MBS_ALL_IDS_IN_USE 0x4009 549#define MBS_NOT_LOGGED_IN 0x400A 550#define MBS_LINK_DOWN_ERROR 0x400B 551#define MBS_DIAG_ECHO_TEST_ERROR 0x400C 552 553/* 554 * ISP mailbox asynchronous event status codes 555 */ 556#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 557#define MBA_RESET 0x8001 /* Reset Detected. */ 558#define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 559#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 560#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 561#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 562#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 563 /* occurred. */ 564#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 565#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 566#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 567#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 568#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 569#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 570#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 571#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 572#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 573#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 574#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 575#define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 576#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 577#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 578#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 579#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 580 /* used. */ 581#define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 582#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 583#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 584#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 585#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 586#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 587#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 588#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 589#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 590#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 591#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 592#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 593#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 594#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 595 596/* ISP mailbox loopback echo diagnostic error code */ 597#define MBS_LB_RESET 0x17 598/* 599 * Firmware options 1, 2, 3. 600 */ 601#define FO1_AE_ON_LIPF8 BIT_0 602#define FO1_AE_ALL_LIP_RESET BIT_1 603#define FO1_CTIO_RETRY BIT_3 604#define FO1_DISABLE_LIP_F7_SW BIT_4 605#define FO1_DISABLE_100MS_LOS_WAIT BIT_5 606#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 607#define FO1_AE_ON_LOOP_INIT_ERR BIT_7 608#define FO1_SET_EMPHASIS_SWING BIT_8 609#define FO1_AE_AUTO_BYPASS BIT_9 610#define FO1_ENABLE_PURE_IOCB BIT_10 611#define FO1_AE_PLOGI_RJT BIT_11 612#define FO1_ENABLE_ABORT_SEQUENCE BIT_12 613#define FO1_AE_QUEUE_FULL BIT_13 614 615#define FO2_ENABLE_ATIO_TYPE_3 BIT_0 616#define FO2_REV_LOOPBACK BIT_1 617 618#define FO3_ENABLE_EMERG_IOCB BIT_0 619#define FO3_AE_RND_ERROR BIT_1 620 621/* 24XX additional firmware options */ 622#define ADD_FO_COUNT 3 623#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 624#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 625 626#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 627 628#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 629 630/* 631 * ISP mailbox commands 632 */ 633#define MBC_LOAD_RAM 1 /* Load RAM. */ 634#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 635#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ 636#define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 637#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 638#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 639#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 640#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 641#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 642#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 643#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 644#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 645#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 646#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 647#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 648#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 649#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 650#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 651#define MBC_RESET 0x18 /* Reset. */ 652#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 653#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 654#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 655#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 656#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 657#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 658#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 659#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 660#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 661#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 662#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 663#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 664#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 665#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 666#define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 667#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 668#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 669#define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 670#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 671#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 672#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */ 673#define MBC_DATA_RATE 0x5d /* Get RNID parameters */ 674#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 675#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 676 /* Initialization Procedure */ 677#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 678#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 679#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 680#define MBC_TARGET_RESET 0x66 /* Target Reset. */ 681#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 682#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 683#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 684#define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 685#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 686#define MBC_LIP_RESET 0x6c /* LIP reset. */ 687#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 688 /* commandd. */ 689#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 690#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 691#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 692#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 693#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 694#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 695#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 696#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 697#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 698#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 699#define MBC_LUN_RESET 0x7E /* Send LUN reset */ 700 701/* 702 * ISP24xx mailbox commands 703 */ 704#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 705#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 706#define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 707#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 708#define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 709#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 710#define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 711#define MBC_READ_SFP 0x31 /* Read SFP Data. */ 712#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 713#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 714#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 715#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 716#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 717#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 718#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 719#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 720#define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 721#define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 722 723/* 724 * ISP81xx mailbox commands 725 */ 726#define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 727 728/* Firmware return data sizes */ 729#define FCAL_MAP_SIZE 128 730 731/* Mailbox bit definitions for out_mb and in_mb */ 732#define MBX_31 BIT_31 733#define MBX_30 BIT_30 734#define MBX_29 BIT_29 735#define MBX_28 BIT_28 736#define MBX_27 BIT_27 737#define MBX_26 BIT_26 738#define MBX_25 BIT_25 739#define MBX_24 BIT_24 740#define MBX_23 BIT_23 741#define MBX_22 BIT_22 742#define MBX_21 BIT_21 743#define MBX_20 BIT_20 744#define MBX_19 BIT_19 745#define MBX_18 BIT_18 746#define MBX_17 BIT_17 747#define MBX_16 BIT_16 748#define MBX_15 BIT_15 749#define MBX_14 BIT_14 750#define MBX_13 BIT_13 751#define MBX_12 BIT_12 752#define MBX_11 BIT_11 753#define MBX_10 BIT_10 754#define MBX_9 BIT_9 755#define MBX_8 BIT_8 756#define MBX_7 BIT_7 757#define MBX_6 BIT_6 758#define MBX_5 BIT_5 759#define MBX_4 BIT_4 760#define MBX_3 BIT_3 761#define MBX_2 BIT_2 762#define MBX_1 BIT_1 763#define MBX_0 BIT_0 764 765/* 766 * Firmware state codes from get firmware state mailbox command 767 */ 768#define FSTATE_CONFIG_WAIT 0 769#define FSTATE_WAIT_AL_PA 1 770#define FSTATE_WAIT_LOGIN 2 771#define FSTATE_READY 3 772#define FSTATE_LOSS_OF_SYNC 4 773#define FSTATE_ERROR 5 774#define FSTATE_REINIT 6 775#define FSTATE_NON_PART 7 776 777#define FSTATE_CONFIG_CORRECT 0 778#define FSTATE_P2P_RCV_LIP 1 779#define FSTATE_P2P_CHOOSE_LOOP 2 780#define FSTATE_P2P_RCV_UNIDEN_LIP 3 781#define FSTATE_FATAL_ERROR 4 782#define FSTATE_LOOP_BACK_CONN 5 783 784/* 785 * Port Database structure definition 786 * Little endian except where noted. 787 */ 788#define PORT_DATABASE_SIZE 128 /* bytes */ 789typedef struct { 790 uint8_t options; 791 uint8_t control; 792 uint8_t master_state; 793 uint8_t slave_state; 794 uint8_t reserved[2]; 795 uint8_t hard_address; 796 uint8_t reserved_1; 797 uint8_t port_id[4]; 798 uint8_t node_name[WWN_SIZE]; 799 uint8_t port_name[WWN_SIZE]; 800 uint16_t execution_throttle; 801 uint16_t execution_count; 802 uint8_t reset_count; 803 uint8_t reserved_2; 804 uint16_t resource_allocation; 805 uint16_t current_allocation; 806 uint16_t queue_head; 807 uint16_t queue_tail; 808 uint16_t transmit_execution_list_next; 809 uint16_t transmit_execution_list_previous; 810 uint16_t common_features; 811 uint16_t total_concurrent_sequences; 812 uint16_t RO_by_information_category; 813 uint8_t recipient; 814 uint8_t initiator; 815 uint16_t receive_data_size; 816 uint16_t concurrent_sequences; 817 uint16_t open_sequences_per_exchange; 818 uint16_t lun_abort_flags; 819 uint16_t lun_stop_flags; 820 uint16_t stop_queue_head; 821 uint16_t stop_queue_tail; 822 uint16_t port_retry_timer; 823 uint16_t next_sequence_id; 824 uint16_t frame_count; 825 uint16_t PRLI_payload_length; 826 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 827 /* Bits 15-0 of word 0 */ 828 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 829 /* Bits 15-0 of word 3 */ 830 uint16_t loop_id; 831 uint16_t extended_lun_info_list_pointer; 832 uint16_t extended_lun_stop_list_pointer; 833} port_database_t; 834 835/* 836 * Port database slave/master states 837 */ 838#define PD_STATE_DISCOVERY 0 839#define PD_STATE_WAIT_DISCOVERY_ACK 1 840#define PD_STATE_PORT_LOGIN 2 841#define PD_STATE_WAIT_PORT_LOGIN_ACK 3 842#define PD_STATE_PROCESS_LOGIN 4 843#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 844#define PD_STATE_PORT_LOGGED_IN 6 845#define PD_STATE_PORT_UNAVAILABLE 7 846#define PD_STATE_PROCESS_LOGOUT 8 847#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 848#define PD_STATE_PORT_LOGOUT 10 849#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 850 851 852#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 853#define QLA_ZIO_DISABLED 0 854#define QLA_ZIO_DEFAULT_TIMER 2 855 856/* 857 * ISP Initialization Control Block. 858 * Little endian except where noted. 859 */ 860#define ICB_VERSION 1 861typedef struct { 862 uint8_t version; 863 uint8_t reserved_1; 864 865 /* 866 * LSB BIT 0 = Enable Hard Loop Id 867 * LSB BIT 1 = Enable Fairness 868 * LSB BIT 2 = Enable Full-Duplex 869 * LSB BIT 3 = Enable Fast Posting 870 * LSB BIT 4 = Enable Target Mode 871 * LSB BIT 5 = Disable Initiator Mode 872 * LSB BIT 6 = Enable ADISC 873 * LSB BIT 7 = Enable Target Inquiry Data 874 * 875 * MSB BIT 0 = Enable PDBC Notify 876 * MSB BIT 1 = Non Participating LIP 877 * MSB BIT 2 = Descending Loop ID Search 878 * MSB BIT 3 = Acquire Loop ID in LIPA 879 * MSB BIT 4 = Stop PortQ on Full Status 880 * MSB BIT 5 = Full Login after LIP 881 * MSB BIT 6 = Node Name Option 882 * MSB BIT 7 = Ext IFWCB enable bit 883 */ 884 uint8_t firmware_options[2]; 885 886 uint16_t frame_payload_size; 887 uint16_t max_iocb_allocation; 888 uint16_t execution_throttle; 889 uint8_t retry_count; 890 uint8_t retry_delay; /* unused */ 891 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 892 uint16_t hard_address; 893 uint8_t inquiry_data; 894 uint8_t login_timeout; 895 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 896 897 uint16_t request_q_outpointer; 898 uint16_t response_q_inpointer; 899 uint16_t request_q_length; 900 uint16_t response_q_length; 901 uint32_t request_q_address[2]; 902 uint32_t response_q_address[2]; 903 904 uint16_t lun_enables; 905 uint8_t command_resource_count; 906 uint8_t immediate_notify_resource_count; 907 uint16_t timeout; 908 uint8_t reserved_2[2]; 909 910 /* 911 * LSB BIT 0 = Timer Operation mode bit 0 912 * LSB BIT 1 = Timer Operation mode bit 1 913 * LSB BIT 2 = Timer Operation mode bit 2 914 * LSB BIT 3 = Timer Operation mode bit 3 915 * LSB BIT 4 = Init Config Mode bit 0 916 * LSB BIT 5 = Init Config Mode bit 1 917 * LSB BIT 6 = Init Config Mode bit 2 918 * LSB BIT 7 = Enable Non part on LIHA failure 919 * 920 * MSB BIT 0 = Enable class 2 921 * MSB BIT 1 = Enable ACK0 922 * MSB BIT 2 = 923 * MSB BIT 3 = 924 * MSB BIT 4 = FC Tape Enable 925 * MSB BIT 5 = Enable FC Confirm 926 * MSB BIT 6 = Enable command queuing in target mode 927 * MSB BIT 7 = No Logo On Link Down 928 */ 929 uint8_t add_firmware_options[2]; 930 931 uint8_t response_accumulation_timer; 932 uint8_t interrupt_delay_timer; 933 934 /* 935 * LSB BIT 0 = Enable Read xfr_rdy 936 * LSB BIT 1 = Soft ID only 937 * LSB BIT 2 = 938 * LSB BIT 3 = 939 * LSB BIT 4 = FCP RSP Payload [0] 940 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 941 * LSB BIT 6 = Enable Out-of-Order frame handling 942 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 943 * 944 * MSB BIT 0 = Sbus enable - 2300 945 * MSB BIT 1 = 946 * MSB BIT 2 = 947 * MSB BIT 3 = 948 * MSB BIT 4 = LED mode 949 * MSB BIT 5 = enable 50 ohm termination 950 * MSB BIT 6 = Data Rate (2300 only) 951 * MSB BIT 7 = Data Rate (2300 only) 952 */ 953 uint8_t special_options[2]; 954 955 uint8_t reserved_3[26]; 956} init_cb_t; 957 958/* 959 * Get Link Status mailbox command return buffer. 960 */ 961#define GLSO_SEND_RPS BIT_0 962#define GLSO_USE_DID BIT_3 963 964struct link_statistics { 965 uint32_t link_fail_cnt; 966 uint32_t loss_sync_cnt; 967 uint32_t loss_sig_cnt; 968 uint32_t prim_seq_err_cnt; 969 uint32_t inval_xmit_word_cnt; 970 uint32_t inval_crc_cnt; 971 uint32_t lip_cnt; 972 uint32_t unused1[0x1a]; 973 uint32_t tx_frames; 974 uint32_t rx_frames; 975 uint32_t dumped_frames; 976 uint32_t unused2[2]; 977 uint32_t nos_rcvd; 978}; 979 980/* 981 * NVRAM Command values. 982 */ 983#define NV_START_BIT BIT_2 984#define NV_WRITE_OP (BIT_26+BIT_24) 985#define NV_READ_OP (BIT_26+BIT_25) 986#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 987#define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 988#define NV_DELAY_COUNT 10 989 990/* 991 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 992 */ 993typedef struct { 994 /* 995 * NVRAM header 996 */ 997 uint8_t id[4]; 998 uint8_t nvram_version; 999 uint8_t reserved_0; 1000 1001 /* 1002 * NVRAM RISC parameter block 1003 */ 1004 uint8_t parameter_block_version; 1005 uint8_t reserved_1; 1006 1007 /* 1008 * LSB BIT 0 = Enable Hard Loop Id 1009 * LSB BIT 1 = Enable Fairness 1010 * LSB BIT 2 = Enable Full-Duplex 1011 * LSB BIT 3 = Enable Fast Posting 1012 * LSB BIT 4 = Enable Target Mode 1013 * LSB BIT 5 = Disable Initiator Mode 1014 * LSB BIT 6 = Enable ADISC 1015 * LSB BIT 7 = Enable Target Inquiry Data 1016 * 1017 * MSB BIT 0 = Enable PDBC Notify 1018 * MSB BIT 1 = Non Participating LIP 1019 * MSB BIT 2 = Descending Loop ID Search 1020 * MSB BIT 3 = Acquire Loop ID in LIPA 1021 * MSB BIT 4 = Stop PortQ on Full Status 1022 * MSB BIT 5 = Full Login after LIP 1023 * MSB BIT 6 = Node Name Option 1024 * MSB BIT 7 = Ext IFWCB enable bit 1025 */ 1026 uint8_t firmware_options[2]; 1027 1028 uint16_t frame_payload_size; 1029 uint16_t max_iocb_allocation; 1030 uint16_t execution_throttle; 1031 uint8_t retry_count; 1032 uint8_t retry_delay; /* unused */ 1033 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1034 uint16_t hard_address; 1035 uint8_t inquiry_data; 1036 uint8_t login_timeout; 1037 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1038 1039 /* 1040 * LSB BIT 0 = Timer Operation mode bit 0 1041 * LSB BIT 1 = Timer Operation mode bit 1 1042 * LSB BIT 2 = Timer Operation mode bit 2 1043 * LSB BIT 3 = Timer Operation mode bit 3 1044 * LSB BIT 4 = Init Config Mode bit 0 1045 * LSB BIT 5 = Init Config Mode bit 1 1046 * LSB BIT 6 = Init Config Mode bit 2 1047 * LSB BIT 7 = Enable Non part on LIHA failure 1048 * 1049 * MSB BIT 0 = Enable class 2 1050 * MSB BIT 1 = Enable ACK0 1051 * MSB BIT 2 = 1052 * MSB BIT 3 = 1053 * MSB BIT 4 = FC Tape Enable 1054 * MSB BIT 5 = Enable FC Confirm 1055 * MSB BIT 6 = Enable command queuing in target mode 1056 * MSB BIT 7 = No Logo On Link Down 1057 */ 1058 uint8_t add_firmware_options[2]; 1059 1060 uint8_t response_accumulation_timer; 1061 uint8_t interrupt_delay_timer; 1062 1063 /* 1064 * LSB BIT 0 = Enable Read xfr_rdy 1065 * LSB BIT 1 = Soft ID only 1066 * LSB BIT 2 = 1067 * LSB BIT 3 = 1068 * LSB BIT 4 = FCP RSP Payload [0] 1069 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1070 * LSB BIT 6 = Enable Out-of-Order frame handling 1071 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1072 * 1073 * MSB BIT 0 = Sbus enable - 2300 1074 * MSB BIT 1 = 1075 * MSB BIT 2 = 1076 * MSB BIT 3 = 1077 * MSB BIT 4 = LED mode 1078 * MSB BIT 5 = enable 50 ohm termination 1079 * MSB BIT 6 = Data Rate (2300 only) 1080 * MSB BIT 7 = Data Rate (2300 only) 1081 */ 1082 uint8_t special_options[2]; 1083 1084 /* Reserved for expanded RISC parameter block */ 1085 uint8_t reserved_2[22]; 1086 1087 /* 1088 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1089 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1090 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1091 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1092 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1093 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1094 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1095 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1096 * 1097 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1098 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1099 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1100 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1101 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1102 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1103 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1104 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1105 * 1106 * LSB BIT 0 = Output Swing 1G bit 0 1107 * LSB BIT 1 = Output Swing 1G bit 1 1108 * LSB BIT 2 = Output Swing 1G bit 2 1109 * LSB BIT 3 = Output Emphasis 1G bit 0 1110 * LSB BIT 4 = Output Emphasis 1G bit 1 1111 * LSB BIT 5 = Output Swing 2G bit 0 1112 * LSB BIT 6 = Output Swing 2G bit 1 1113 * LSB BIT 7 = Output Swing 2G bit 2 1114 * 1115 * MSB BIT 0 = Output Emphasis 2G bit 0 1116 * MSB BIT 1 = Output Emphasis 2G bit 1 1117 * MSB BIT 2 = Output Enable 1118 * MSB BIT 3 = 1119 * MSB BIT 4 = 1120 * MSB BIT 5 = 1121 * MSB BIT 6 = 1122 * MSB BIT 7 = 1123 */ 1124 uint8_t seriallink_options[4]; 1125 1126 /* 1127 * NVRAM host parameter block 1128 * 1129 * LSB BIT 0 = Enable spinup delay 1130 * LSB BIT 1 = Disable BIOS 1131 * LSB BIT 2 = Enable Memory Map BIOS 1132 * LSB BIT 3 = Enable Selectable Boot 1133 * LSB BIT 4 = Disable RISC code load 1134 * LSB BIT 5 = Set cache line size 1 1135 * LSB BIT 6 = PCI Parity Disable 1136 * LSB BIT 7 = Enable extended logging 1137 * 1138 * MSB BIT 0 = Enable 64bit addressing 1139 * MSB BIT 1 = Enable lip reset 1140 * MSB BIT 2 = Enable lip full login 1141 * MSB BIT 3 = Enable target reset 1142 * MSB BIT 4 = Enable database storage 1143 * MSB BIT 5 = Enable cache flush read 1144 * MSB BIT 6 = Enable database load 1145 * MSB BIT 7 = Enable alternate WWN 1146 */ 1147 uint8_t host_p[2]; 1148 1149 uint8_t boot_node_name[WWN_SIZE]; 1150 uint8_t boot_lun_number; 1151 uint8_t reset_delay; 1152 uint8_t port_down_retry_count; 1153 uint8_t boot_id_number; 1154 uint16_t max_luns_per_target; 1155 uint8_t fcode_boot_port_name[WWN_SIZE]; 1156 uint8_t alternate_port_name[WWN_SIZE]; 1157 uint8_t alternate_node_name[WWN_SIZE]; 1158 1159 /* 1160 * BIT 0 = Selective Login 1161 * BIT 1 = Alt-Boot Enable 1162 * BIT 2 = 1163 * BIT 3 = Boot Order List 1164 * BIT 4 = 1165 * BIT 5 = Selective LUN 1166 * BIT 6 = 1167 * BIT 7 = unused 1168 */ 1169 uint8_t efi_parameters; 1170 1171 uint8_t link_down_timeout; 1172 1173 uint8_t adapter_id[16]; 1174 1175 uint8_t alt1_boot_node_name[WWN_SIZE]; 1176 uint16_t alt1_boot_lun_number; 1177 uint8_t alt2_boot_node_name[WWN_SIZE]; 1178 uint16_t alt2_boot_lun_number; 1179 uint8_t alt3_boot_node_name[WWN_SIZE]; 1180 uint16_t alt3_boot_lun_number; 1181 uint8_t alt4_boot_node_name[WWN_SIZE]; 1182 uint16_t alt4_boot_lun_number; 1183 uint8_t alt5_boot_node_name[WWN_SIZE]; 1184 uint16_t alt5_boot_lun_number; 1185 uint8_t alt6_boot_node_name[WWN_SIZE]; 1186 uint16_t alt6_boot_lun_number; 1187 uint8_t alt7_boot_node_name[WWN_SIZE]; 1188 uint16_t alt7_boot_lun_number; 1189 1190 uint8_t reserved_3[2]; 1191 1192 /* Offset 200-215 : Model Number */ 1193 uint8_t model_number[16]; 1194 1195 /* OEM related items */ 1196 uint8_t oem_specific[16]; 1197 1198 /* 1199 * NVRAM Adapter Features offset 232-239 1200 * 1201 * LSB BIT 0 = External GBIC 1202 * LSB BIT 1 = Risc RAM parity 1203 * LSB BIT 2 = Buffer Plus Module 1204 * LSB BIT 3 = Multi Chip Adapter 1205 * LSB BIT 4 = Internal connector 1206 * LSB BIT 5 = 1207 * LSB BIT 6 = 1208 * LSB BIT 7 = 1209 * 1210 * MSB BIT 0 = 1211 * MSB BIT 1 = 1212 * MSB BIT 2 = 1213 * MSB BIT 3 = 1214 * MSB BIT 4 = 1215 * MSB BIT 5 = 1216 * MSB BIT 6 = 1217 * MSB BIT 7 = 1218 */ 1219 uint8_t adapter_features[2]; 1220 1221 uint8_t reserved_4[16]; 1222 1223 /* Subsystem vendor ID for ISP2200 */ 1224 uint16_t subsystem_vendor_id_2200; 1225 1226 /* Subsystem device ID for ISP2200 */ 1227 uint16_t subsystem_device_id_2200; 1228 1229 uint8_t reserved_5; 1230 uint8_t checksum; 1231} nvram_t; 1232 1233/* 1234 * ISP queue - response queue entry definition. 1235 */ 1236typedef struct { 1237 uint8_t data[60]; 1238 uint32_t signature; 1239#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1240} response_t; 1241 1242typedef union { 1243 uint16_t extended; 1244 struct { 1245 uint8_t reserved; 1246 uint8_t standard; 1247 } id; 1248} target_id_t; 1249 1250#define SET_TARGET_ID(ha, to, from) \ 1251do { \ 1252 if (HAS_EXTENDED_IDS(ha)) \ 1253 to.extended = cpu_to_le16(from); \ 1254 else \ 1255 to.id.standard = (uint8_t)from; \ 1256} while (0) 1257 1258/* 1259 * ISP queue - command entry structure definition. 1260 */ 1261#define COMMAND_TYPE 0x11 /* Command entry */ 1262typedef struct { 1263 uint8_t entry_type; /* Entry type. */ 1264 uint8_t entry_count; /* Entry count. */ 1265 uint8_t sys_define; /* System defined. */ 1266 uint8_t entry_status; /* Entry Status. */ 1267 uint32_t handle; /* System handle. */ 1268 target_id_t target; /* SCSI ID */ 1269 uint16_t lun; /* SCSI LUN */ 1270 uint16_t control_flags; /* Control flags. */ 1271#define CF_WRITE BIT_6 1272#define CF_READ BIT_5 1273#define CF_SIMPLE_TAG BIT_3 1274#define CF_ORDERED_TAG BIT_2 1275#define CF_HEAD_TAG BIT_1 1276 uint16_t reserved_1; 1277 uint16_t timeout; /* Command timeout. */ 1278 uint16_t dseg_count; /* Data segment count. */ 1279 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1280 uint32_t byte_count; /* Total byte count. */ 1281 uint32_t dseg_0_address; /* Data segment 0 address. */ 1282 uint32_t dseg_0_length; /* Data segment 0 length. */ 1283 uint32_t dseg_1_address; /* Data segment 1 address. */ 1284 uint32_t dseg_1_length; /* Data segment 1 length. */ 1285 uint32_t dseg_2_address; /* Data segment 2 address. */ 1286 uint32_t dseg_2_length; /* Data segment 2 length. */ 1287} cmd_entry_t; 1288 1289/* 1290 * ISP queue - 64-Bit addressing, command entry structure definition. 1291 */ 1292#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1293typedef struct { 1294 uint8_t entry_type; /* Entry type. */ 1295 uint8_t entry_count; /* Entry count. */ 1296 uint8_t sys_define; /* System defined. */ 1297 uint8_t entry_status; /* Entry Status. */ 1298 uint32_t handle; /* System handle. */ 1299 target_id_t target; /* SCSI ID */ 1300 uint16_t lun; /* SCSI LUN */ 1301 uint16_t control_flags; /* Control flags. */ 1302 uint16_t reserved_1; 1303 uint16_t timeout; /* Command timeout. */ 1304 uint16_t dseg_count; /* Data segment count. */ 1305 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1306 uint32_t byte_count; /* Total byte count. */ 1307 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1308 uint32_t dseg_0_length; /* Data segment 0 length. */ 1309 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1310 uint32_t dseg_1_length; /* Data segment 1 length. */ 1311} cmd_a64_entry_t, request_t; 1312 1313/* 1314 * ISP queue - continuation entry structure definition. 1315 */ 1316#define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1317typedef struct { 1318 uint8_t entry_type; /* Entry type. */ 1319 uint8_t entry_count; /* Entry count. */ 1320 uint8_t sys_define; /* System defined. */ 1321 uint8_t entry_status; /* Entry Status. */ 1322 uint32_t reserved; 1323 uint32_t dseg_0_address; /* Data segment 0 address. */ 1324 uint32_t dseg_0_length; /* Data segment 0 length. */ 1325 uint32_t dseg_1_address; /* Data segment 1 address. */ 1326 uint32_t dseg_1_length; /* Data segment 1 length. */ 1327 uint32_t dseg_2_address; /* Data segment 2 address. */ 1328 uint32_t dseg_2_length; /* Data segment 2 length. */ 1329 uint32_t dseg_3_address; /* Data segment 3 address. */ 1330 uint32_t dseg_3_length; /* Data segment 3 length. */ 1331 uint32_t dseg_4_address; /* Data segment 4 address. */ 1332 uint32_t dseg_4_length; /* Data segment 4 length. */ 1333 uint32_t dseg_5_address; /* Data segment 5 address. */ 1334 uint32_t dseg_5_length; /* Data segment 5 length. */ 1335 uint32_t dseg_6_address; /* Data segment 6 address. */ 1336 uint32_t dseg_6_length; /* Data segment 6 length. */ 1337} cont_entry_t; 1338 1339/* 1340 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1341 */ 1342#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1343typedef struct { 1344 uint8_t entry_type; /* Entry type. */ 1345 uint8_t entry_count; /* Entry count. */ 1346 uint8_t sys_define; /* System defined. */ 1347 uint8_t entry_status; /* Entry Status. */ 1348 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1349 uint32_t dseg_0_length; /* Data segment 0 length. */ 1350 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1351 uint32_t dseg_1_length; /* Data segment 1 length. */ 1352 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1353 uint32_t dseg_2_length; /* Data segment 2 length. */ 1354 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1355 uint32_t dseg_3_length; /* Data segment 3 length. */ 1356 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1357 uint32_t dseg_4_length; /* Data segment 4 length. */ 1358} cont_a64_entry_t; 1359 1360#define PO_MODE_DIF_INSERT 0 1361#define PO_MODE_DIF_REMOVE BIT_0 1362#define PO_MODE_DIF_PASS BIT_1 1363#define PO_MODE_DIF_REPLACE (BIT_0 + BIT_1) 1364#define PO_ENABLE_DIF_BUNDLING BIT_8 1365#define PO_ENABLE_INCR_GUARD_SEED BIT_3 1366#define PO_DISABLE_INCR_REF_TAG BIT_5 1367#define PO_DISABLE_GUARD_CHECK BIT_4 1368/* 1369 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1370 */ 1371struct crc_context { 1372 uint32_t handle; /* System handle. */ 1373 uint32_t ref_tag; 1374 uint16_t app_tag; 1375 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1376 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1377 uint16_t guard_seed; /* Initial Guard Seed */ 1378 uint16_t prot_opts; /* Requested Data Protection Mode */ 1379 uint16_t blk_size; /* Data size in bytes */ 1380 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1381 * only) */ 1382 uint32_t byte_count; /* Total byte count/ total data 1383 * transfer count */ 1384 union { 1385 struct { 1386 uint32_t reserved_1; 1387 uint16_t reserved_2; 1388 uint16_t reserved_3; 1389 uint32_t reserved_4; 1390 uint32_t data_address[2]; 1391 uint32_t data_length; 1392 uint32_t reserved_5[2]; 1393 uint32_t reserved_6; 1394 } nobundling; 1395 struct { 1396 uint32_t dif_byte_count; /* Total DIF byte 1397 * count */ 1398 uint16_t reserved_1; 1399 uint16_t dseg_count; /* Data segment count */ 1400 uint32_t reserved_2; 1401 uint32_t data_address[2]; 1402 uint32_t data_length; 1403 uint32_t dif_address[2]; 1404 uint32_t dif_length; /* Data segment 0 1405 * length */ 1406 } bundling; 1407 } u; 1408 1409 struct fcp_cmnd fcp_cmnd; 1410 dma_addr_t crc_ctx_dma; 1411 /* List of DMA context transfers */ 1412 struct list_head dsd_list; 1413 1414 /* This structure should not exceed 512 bytes */ 1415}; 1416 1417#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1418#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1419 1420/* 1421 * ISP queue - status entry structure definition. 1422 */ 1423#define STATUS_TYPE 0x03 /* Status entry. */ 1424typedef struct { 1425 uint8_t entry_type; /* Entry type. */ 1426 uint8_t entry_count; /* Entry count. */ 1427 uint8_t sys_define; /* System defined. */ 1428 uint8_t entry_status; /* Entry Status. */ 1429 uint32_t handle; /* System handle. */ 1430 uint16_t scsi_status; /* SCSI status. */ 1431 uint16_t comp_status; /* Completion status. */ 1432 uint16_t state_flags; /* State flags. */ 1433 uint16_t status_flags; /* Status flags. */ 1434 uint16_t rsp_info_len; /* Response Info Length. */ 1435 uint16_t req_sense_length; /* Request sense data length. */ 1436 uint32_t residual_length; /* Residual transfer length. */ 1437 uint8_t rsp_info[8]; /* FCP response information. */ 1438 uint8_t req_sense_data[32]; /* Request sense data. */ 1439} sts_entry_t; 1440 1441/* 1442 * Status entry entry status 1443 */ 1444#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1445#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1446#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1447#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1448#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1449#define RF_BUSY BIT_1 /* Busy */ 1450#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1451 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1452#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1453 RF_INV_E_TYPE) 1454 1455/* 1456 * Status entry SCSI status bit definitions. 1457 */ 1458#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1459#define SS_RESIDUAL_UNDER BIT_11 1460#define SS_RESIDUAL_OVER BIT_10 1461#define SS_SENSE_LEN_VALID BIT_9 1462#define SS_RESPONSE_INFO_LEN_VALID BIT_8 1463 1464#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1465#define SS_BUSY_CONDITION BIT_3 1466#define SS_CONDITION_MET BIT_2 1467#define SS_CHECK_CONDITION BIT_1 1468 1469/* 1470 * Status entry completion status 1471 */ 1472#define CS_COMPLETE 0x0 /* No errors */ 1473#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1474#define CS_DMA 0x2 /* A DMA direction error. */ 1475#define CS_TRANSPORT 0x3 /* Transport error. */ 1476#define CS_RESET 0x4 /* SCSI bus reset occurred */ 1477#define CS_ABORTED 0x5 /* System aborted command. */ 1478#define CS_TIMEOUT 0x6 /* Timeout error. */ 1479#define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1480#define CS_DIF_ERROR 0xC /* DIF error detected */ 1481 1482#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1483#define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1484#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1485 /* (selection timeout) */ 1486#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1487#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1488#define CS_PORT_BUSY 0x2B /* Port Busy */ 1489#define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1490#define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1491#define CS_UNKNOWN 0x81 /* Driver defined */ 1492#define CS_RETRY 0x82 /* Driver defined */ 1493#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1494 1495/* 1496 * Status entry status flags 1497 */ 1498#define SF_ABTS_TERMINATED BIT_10 1499#define SF_LOGOUT_SENT BIT_13 1500 1501/* 1502 * ISP queue - status continuation entry structure definition. 1503 */ 1504#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1505typedef struct { 1506 uint8_t entry_type; /* Entry type. */ 1507 uint8_t entry_count; /* Entry count. */ 1508 uint8_t sys_define; /* System defined. */ 1509 uint8_t entry_status; /* Entry Status. */ 1510 uint8_t data[60]; /* data */ 1511} sts_cont_entry_t; 1512 1513/* 1514 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1515 * structure definition. 1516 */ 1517#define STATUS_TYPE_21 0x21 /* Status entry. */ 1518typedef struct { 1519 uint8_t entry_type; /* Entry type. */ 1520 uint8_t entry_count; /* Entry count. */ 1521 uint8_t handle_count; /* Handle count. */ 1522 uint8_t entry_status; /* Entry Status. */ 1523 uint32_t handle[15]; /* System handles. */ 1524} sts21_entry_t; 1525 1526/* 1527 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1528 * structure definition. 1529 */ 1530#define STATUS_TYPE_22 0x22 /* Status entry. */ 1531typedef struct { 1532 uint8_t entry_type; /* Entry type. */ 1533 uint8_t entry_count; /* Entry count. */ 1534 uint8_t handle_count; /* Handle count. */ 1535 uint8_t entry_status; /* Entry Status. */ 1536 uint16_t handle[30]; /* System handles. */ 1537} sts22_entry_t; 1538 1539/* 1540 * ISP queue - marker entry structure definition. 1541 */ 1542#define MARKER_TYPE 0x04 /* Marker entry. */ 1543typedef struct { 1544 uint8_t entry_type; /* Entry type. */ 1545 uint8_t entry_count; /* Entry count. */ 1546 uint8_t handle_count; /* Handle count. */ 1547 uint8_t entry_status; /* Entry Status. */ 1548 uint32_t sys_define_2; /* System defined. */ 1549 target_id_t target; /* SCSI ID */ 1550 uint8_t modifier; /* Modifier (7-0). */ 1551#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1552#define MK_SYNC_ID 1 /* Synchronize ID */ 1553#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1554#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 1555 /* clear port changed, */ 1556 /* use sequence number. */ 1557 uint8_t reserved_1; 1558 uint16_t sequence_number; /* Sequence number of event */ 1559 uint16_t lun; /* SCSI LUN */ 1560 uint8_t reserved_2[48]; 1561} mrk_entry_t; 1562 1563/* 1564 * ISP queue - Management Server entry structure definition. 1565 */ 1566#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 1567typedef struct { 1568 uint8_t entry_type; /* Entry type. */ 1569 uint8_t entry_count; /* Entry count. */ 1570 uint8_t handle_count; /* Handle count. */ 1571 uint8_t entry_status; /* Entry Status. */ 1572 uint32_t handle1; /* System handle. */ 1573 target_id_t loop_id; 1574 uint16_t status; 1575 uint16_t control_flags; /* Control flags. */ 1576 uint16_t reserved2; 1577 uint16_t timeout; 1578 uint16_t cmd_dsd_count; 1579 uint16_t total_dsd_count; 1580 uint8_t type; 1581 uint8_t r_ctl; 1582 uint16_t rx_id; 1583 uint16_t reserved3; 1584 uint32_t handle2; 1585 uint32_t rsp_bytecount; 1586 uint32_t req_bytecount; 1587 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 1588 uint32_t dseg_req_length; /* Data segment 0 length. */ 1589 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 1590 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 1591} ms_iocb_entry_t; 1592 1593 1594/* 1595 * ISP queue - Mailbox Command entry structure definition. 1596 */ 1597#define MBX_IOCB_TYPE 0x39 1598struct mbx_entry { 1599 uint8_t entry_type; 1600 uint8_t entry_count; 1601 uint8_t sys_define1; 1602 /* Use sys_define1 for source type */ 1603#define SOURCE_SCSI 0x00 1604#define SOURCE_IP 0x01 1605#define SOURCE_VI 0x02 1606#define SOURCE_SCTP 0x03 1607#define SOURCE_MP 0x04 1608#define SOURCE_MPIOCTL 0x05 1609#define SOURCE_ASYNC_IOCB 0x07 1610 1611 uint8_t entry_status; 1612 1613 uint32_t handle; 1614 target_id_t loop_id; 1615 1616 uint16_t status; 1617 uint16_t state_flags; 1618 uint16_t status_flags; 1619 1620 uint32_t sys_define2[2]; 1621 1622 uint16_t mb0; 1623 uint16_t mb1; 1624 uint16_t mb2; 1625 uint16_t mb3; 1626 uint16_t mb6; 1627 uint16_t mb7; 1628 uint16_t mb9; 1629 uint16_t mb10; 1630 uint32_t reserved_2[2]; 1631 uint8_t node_name[WWN_SIZE]; 1632 uint8_t port_name[WWN_SIZE]; 1633}; 1634 1635/* 1636 * ISP request and response queue entry sizes 1637 */ 1638#define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 1639#define REQUEST_ENTRY_SIZE (sizeof(request_t)) 1640 1641 1642/* 1643 * 24 bit port ID type definition. 1644 */ 1645typedef union { 1646 uint32_t b24 : 24; 1647 1648 struct { 1649#ifdef __BIG_ENDIAN 1650 uint8_t domain; 1651 uint8_t area; 1652 uint8_t al_pa; 1653#elif defined(__LITTLE_ENDIAN) 1654 uint8_t al_pa; 1655 uint8_t area; 1656 uint8_t domain; 1657#else 1658#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 1659#endif 1660 uint8_t rsvd_1; 1661 } b; 1662} port_id_t; 1663#define INVALID_PORT_ID 0xFFFFFF 1664 1665/* 1666 * Switch info gathering structure. 1667 */ 1668typedef struct { 1669 port_id_t d_id; 1670 uint8_t node_name[WWN_SIZE]; 1671 uint8_t port_name[WWN_SIZE]; 1672 uint8_t fabric_port_name[WWN_SIZE]; 1673 uint16_t fp_speed; 1674 uint8_t fc4_type; 1675} sw_info_t; 1676 1677/* FCP-4 types */ 1678#define FC4_TYPE_FCP_SCSI 0x08 1679#define FC4_TYPE_OTHER 0x0 1680#define FC4_TYPE_UNKNOWN 0xff 1681 1682/* 1683 * Fibre channel port type. 1684 */ 1685 typedef enum { 1686 FCT_UNKNOWN, 1687 FCT_RSCN, 1688 FCT_SWITCH, 1689 FCT_BROADCAST, 1690 FCT_INITIATOR, 1691 FCT_TARGET 1692} fc_port_type_t; 1693 1694/* 1695 * Fibre channel port structure. 1696 */ 1697typedef struct fc_port { 1698 struct list_head list; 1699 struct scsi_qla_host *vha; 1700 1701 uint8_t node_name[WWN_SIZE]; 1702 uint8_t port_name[WWN_SIZE]; 1703 port_id_t d_id; 1704 uint16_t loop_id; 1705 uint16_t old_loop_id; 1706 1707 uint8_t fcp_prio; 1708 1709 uint8_t fabric_port_name[WWN_SIZE]; 1710 uint16_t fp_speed; 1711 1712 fc_port_type_t port_type; 1713 1714 atomic_t state; 1715 uint32_t flags; 1716 1717 int login_retry; 1718 1719 struct fc_rport *rport, *drport; 1720 u32 supported_classes; 1721 1722 uint16_t vp_idx; 1723 uint8_t fc4_type; 1724 uint8_t scan_state; 1725} fc_port_t; 1726 1727/* 1728 * Fibre channel port/lun states. 1729 */ 1730#define FCS_UNCONFIGURED 1 1731#define FCS_DEVICE_DEAD 2 1732#define FCS_DEVICE_LOST 3 1733#define FCS_ONLINE 4 1734 1735static const char * const port_state_str[] = { 1736 "Unknown", 1737 "UNCONFIGURED", 1738 "DEAD", 1739 "LOST", 1740 "ONLINE" 1741}; 1742 1743/* 1744 * FC port flags. 1745 */ 1746#define FCF_FABRIC_DEVICE BIT_0 1747#define FCF_LOGIN_NEEDED BIT_1 1748#define FCF_FCP2_DEVICE BIT_2 1749#define FCF_ASYNC_SENT BIT_3 1750 1751/* No loop ID flag. */ 1752#define FC_NO_LOOP_ID 0x1000 1753 1754/* 1755 * FC-CT interface 1756 * 1757 * NOTE: All structures are big-endian in form. 1758 */ 1759 1760#define CT_REJECT_RESPONSE 0x8001 1761#define CT_ACCEPT_RESPONSE 0x8002 1762#define CT_REASON_INVALID_COMMAND_CODE 0x01 1763#define CT_REASON_CANNOT_PERFORM 0x09 1764#define CT_REASON_COMMAND_UNSUPPORTED 0x0b 1765#define CT_EXPL_ALREADY_REGISTERED 0x10 1766 1767#define NS_N_PORT_TYPE 0x01 1768#define NS_NL_PORT_TYPE 0x02 1769#define NS_NX_PORT_TYPE 0x7F 1770 1771#define GA_NXT_CMD 0x100 1772#define GA_NXT_REQ_SIZE (16 + 4) 1773#define GA_NXT_RSP_SIZE (16 + 620) 1774 1775#define GID_PT_CMD 0x1A1 1776#define GID_PT_REQ_SIZE (16 + 4) 1777 1778#define GPN_ID_CMD 0x112 1779#define GPN_ID_REQ_SIZE (16 + 4) 1780#define GPN_ID_RSP_SIZE (16 + 8) 1781 1782#define GNN_ID_CMD 0x113 1783#define GNN_ID_REQ_SIZE (16 + 4) 1784#define GNN_ID_RSP_SIZE (16 + 8) 1785 1786#define GFT_ID_CMD 0x117 1787#define GFT_ID_REQ_SIZE (16 + 4) 1788#define GFT_ID_RSP_SIZE (16 + 32) 1789 1790#define RFT_ID_CMD 0x217 1791#define RFT_ID_REQ_SIZE (16 + 4 + 32) 1792#define RFT_ID_RSP_SIZE 16 1793 1794#define RFF_ID_CMD 0x21F 1795#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 1796#define RFF_ID_RSP_SIZE 16 1797 1798#define RNN_ID_CMD 0x213 1799#define RNN_ID_REQ_SIZE (16 + 4 + 8) 1800#define RNN_ID_RSP_SIZE 16 1801 1802#define RSNN_NN_CMD 0x239 1803#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 1804#define RSNN_NN_RSP_SIZE 16 1805 1806#define GFPN_ID_CMD 0x11C 1807#define GFPN_ID_REQ_SIZE (16 + 4) 1808#define GFPN_ID_RSP_SIZE (16 + 8) 1809 1810#define GPSC_CMD 0x127 1811#define GPSC_REQ_SIZE (16 + 8) 1812#define GPSC_RSP_SIZE (16 + 2 + 2) 1813 1814#define GFF_ID_CMD 0x011F 1815#define GFF_ID_REQ_SIZE (16 + 4) 1816#define GFF_ID_RSP_SIZE (16 + 128) 1817 1818/* 1819 * HBA attribute types. 1820 */ 1821#define FDMI_HBA_ATTR_COUNT 9 1822#define FDMI_HBA_NODE_NAME 1 1823#define FDMI_HBA_MANUFACTURER 2 1824#define FDMI_HBA_SERIAL_NUMBER 3 1825#define FDMI_HBA_MODEL 4 1826#define FDMI_HBA_MODEL_DESCRIPTION 5 1827#define FDMI_HBA_HARDWARE_VERSION 6 1828#define FDMI_HBA_DRIVER_VERSION 7 1829#define FDMI_HBA_OPTION_ROM_VERSION 8 1830#define FDMI_HBA_FIRMWARE_VERSION 9 1831#define FDMI_HBA_OS_NAME_AND_VERSION 0xa 1832#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 1833 1834struct ct_fdmi_hba_attr { 1835 uint16_t type; 1836 uint16_t len; 1837 union { 1838 uint8_t node_name[WWN_SIZE]; 1839 uint8_t manufacturer[32]; 1840 uint8_t serial_num[8]; 1841 uint8_t model[16]; 1842 uint8_t model_desc[80]; 1843 uint8_t hw_version[16]; 1844 uint8_t driver_version[32]; 1845 uint8_t orom_version[16]; 1846 uint8_t fw_version[16]; 1847 uint8_t os_version[128]; 1848 uint8_t max_ct_len[4]; 1849 } a; 1850}; 1851 1852struct ct_fdmi_hba_attributes { 1853 uint32_t count; 1854 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 1855}; 1856 1857/* 1858 * Port attribute types. 1859 */ 1860#define FDMI_PORT_ATTR_COUNT 6 1861#define FDMI_PORT_FC4_TYPES 1 1862#define FDMI_PORT_SUPPORT_SPEED 2 1863#define FDMI_PORT_CURRENT_SPEED 3 1864#define FDMI_PORT_MAX_FRAME_SIZE 4 1865#define FDMI_PORT_OS_DEVICE_NAME 5 1866#define FDMI_PORT_HOST_NAME 6 1867 1868#define FDMI_PORT_SPEED_1GB 0x1 1869#define FDMI_PORT_SPEED_2GB 0x2 1870#define FDMI_PORT_SPEED_10GB 0x4 1871#define FDMI_PORT_SPEED_4GB 0x8 1872#define FDMI_PORT_SPEED_8GB 0x10 1873#define FDMI_PORT_SPEED_16GB 0x20 1874#define FDMI_PORT_SPEED_UNKNOWN 0x8000 1875 1876struct ct_fdmi_port_attr { 1877 uint16_t type; 1878 uint16_t len; 1879 union { 1880 uint8_t fc4_types[32]; 1881 uint32_t sup_speed; 1882 uint32_t cur_speed; 1883 uint32_t max_frame_size; 1884 uint8_t os_dev_name[32]; 1885 uint8_t host_name[32]; 1886 } a; 1887}; 1888 1889/* 1890 * Port Attribute Block. 1891 */ 1892struct ct_fdmi_port_attributes { 1893 uint32_t count; 1894 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 1895}; 1896 1897/* FDMI definitions. */ 1898#define GRHL_CMD 0x100 1899#define GHAT_CMD 0x101 1900#define GRPL_CMD 0x102 1901#define GPAT_CMD 0x110 1902 1903#define RHBA_CMD 0x200 1904#define RHBA_RSP_SIZE 16 1905 1906#define RHAT_CMD 0x201 1907#define RPRT_CMD 0x210 1908 1909#define RPA_CMD 0x211 1910#define RPA_RSP_SIZE 16 1911 1912#define DHBA_CMD 0x300 1913#define DHBA_REQ_SIZE (16 + 8) 1914#define DHBA_RSP_SIZE 16 1915 1916#define DHAT_CMD 0x301 1917#define DPRT_CMD 0x310 1918#define DPA_CMD 0x311 1919 1920/* CT command header -- request/response common fields */ 1921struct ct_cmd_hdr { 1922 uint8_t revision; 1923 uint8_t in_id[3]; 1924 uint8_t gs_type; 1925 uint8_t gs_subtype; 1926 uint8_t options; 1927 uint8_t reserved; 1928}; 1929 1930/* CT command request */ 1931struct ct_sns_req { 1932 struct ct_cmd_hdr header; 1933 uint16_t command; 1934 uint16_t max_rsp_size; 1935 uint8_t fragment_id; 1936 uint8_t reserved[3]; 1937 1938 union { 1939 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 1940 struct { 1941 uint8_t reserved; 1942 uint8_t port_id[3]; 1943 } port_id; 1944 1945 struct { 1946 uint8_t port_type; 1947 uint8_t domain; 1948 uint8_t area; 1949 uint8_t reserved; 1950 } gid_pt; 1951 1952 struct { 1953 uint8_t reserved; 1954 uint8_t port_id[3]; 1955 uint8_t fc4_types[32]; 1956 } rft_id; 1957 1958 struct { 1959 uint8_t reserved; 1960 uint8_t port_id[3]; 1961 uint16_t reserved2; 1962 uint8_t fc4_feature; 1963 uint8_t fc4_type; 1964 } rff_id; 1965 1966 struct { 1967 uint8_t reserved; 1968 uint8_t port_id[3]; 1969 uint8_t node_name[8]; 1970 } rnn_id; 1971 1972 struct { 1973 uint8_t node_name[8]; 1974 uint8_t name_len; 1975 uint8_t sym_node_name[255]; 1976 } rsnn_nn; 1977 1978 struct { 1979 uint8_t hba_indentifier[8]; 1980 } ghat; 1981 1982 struct { 1983 uint8_t hba_identifier[8]; 1984 uint32_t entry_count; 1985 uint8_t port_name[8]; 1986 struct ct_fdmi_hba_attributes attrs; 1987 } rhba; 1988 1989 struct { 1990 uint8_t hba_identifier[8]; 1991 struct ct_fdmi_hba_attributes attrs; 1992 } rhat; 1993 1994 struct { 1995 uint8_t port_name[8]; 1996 struct ct_fdmi_port_attributes attrs; 1997 } rpa; 1998 1999 struct { 2000 uint8_t port_name[8]; 2001 } dhba; 2002 2003 struct { 2004 uint8_t port_name[8]; 2005 } dhat; 2006 2007 struct { 2008 uint8_t port_name[8]; 2009 } dprt; 2010 2011 struct { 2012 uint8_t port_name[8]; 2013 } dpa; 2014 2015 struct { 2016 uint8_t port_name[8]; 2017 } gpsc; 2018 2019 struct { 2020 uint8_t reserved; 2021 uint8_t port_name[3]; 2022 } gff_id; 2023 } req; 2024}; 2025 2026/* CT command response header */ 2027struct ct_rsp_hdr { 2028 struct ct_cmd_hdr header; 2029 uint16_t response; 2030 uint16_t residual; 2031 uint8_t fragment_id; 2032 uint8_t reason_code; 2033 uint8_t explanation_code; 2034 uint8_t vendor_unique; 2035}; 2036 2037struct ct_sns_gid_pt_data { 2038 uint8_t control_byte; 2039 uint8_t port_id[3]; 2040}; 2041 2042struct ct_sns_rsp { 2043 struct ct_rsp_hdr header; 2044 2045 union { 2046 struct { 2047 uint8_t port_type; 2048 uint8_t port_id[3]; 2049 uint8_t port_name[8]; 2050 uint8_t sym_port_name_len; 2051 uint8_t sym_port_name[255]; 2052 uint8_t node_name[8]; 2053 uint8_t sym_node_name_len; 2054 uint8_t sym_node_name[255]; 2055 uint8_t init_proc_assoc[8]; 2056 uint8_t node_ip_addr[16]; 2057 uint8_t class_of_service[4]; 2058 uint8_t fc4_types[32]; 2059 uint8_t ip_address[16]; 2060 uint8_t fabric_port_name[8]; 2061 uint8_t reserved; 2062 uint8_t hard_address[3]; 2063 } ga_nxt; 2064 2065 struct { 2066 /* Assume the largest number of targets for the union */ 2067 struct ct_sns_gid_pt_data 2068 entries[MAX_FIBRE_DEVICES_MAX]; 2069 } gid_pt; 2070 2071 struct { 2072 uint8_t port_name[8]; 2073 } gpn_id; 2074 2075 struct { 2076 uint8_t node_name[8]; 2077 } gnn_id; 2078 2079 struct { 2080 uint8_t fc4_types[32]; 2081 } gft_id; 2082 2083 struct { 2084 uint32_t entry_count; 2085 uint8_t port_name[8]; 2086 struct ct_fdmi_hba_attributes attrs; 2087 } ghat; 2088 2089 struct { 2090 uint8_t port_name[8]; 2091 } gfpn_id; 2092 2093 struct { 2094 uint16_t speeds; 2095 uint16_t speed; 2096 } gpsc; 2097 2098#define GFF_FCP_SCSI_OFFSET 7 2099 struct { 2100 uint8_t fc4_features[128]; 2101 } gff_id; 2102 } rsp; 2103}; 2104 2105struct ct_sns_pkt { 2106 union { 2107 struct ct_sns_req req; 2108 struct ct_sns_rsp rsp; 2109 } p; 2110}; 2111 2112/* 2113 * SNS command structures -- for 2200 compatibility. 2114 */ 2115#define RFT_ID_SNS_SCMD_LEN 22 2116#define RFT_ID_SNS_CMD_SIZE 60 2117#define RFT_ID_SNS_DATA_SIZE 16 2118 2119#define RNN_ID_SNS_SCMD_LEN 10 2120#define RNN_ID_SNS_CMD_SIZE 36 2121#define RNN_ID_SNS_DATA_SIZE 16 2122 2123#define GA_NXT_SNS_SCMD_LEN 6 2124#define GA_NXT_SNS_CMD_SIZE 28 2125#define GA_NXT_SNS_DATA_SIZE (620 + 16) 2126 2127#define GID_PT_SNS_SCMD_LEN 6 2128#define GID_PT_SNS_CMD_SIZE 28 2129/* 2130 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 2131 * adapters. 2132 */ 2133#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 2134 2135#define GPN_ID_SNS_SCMD_LEN 6 2136#define GPN_ID_SNS_CMD_SIZE 28 2137#define GPN_ID_SNS_DATA_SIZE (8 + 16) 2138 2139#define GNN_ID_SNS_SCMD_LEN 6 2140#define GNN_ID_SNS_CMD_SIZE 28 2141#define GNN_ID_SNS_DATA_SIZE (8 + 16) 2142 2143struct sns_cmd_pkt { 2144 union { 2145 struct { 2146 uint16_t buffer_length; 2147 uint16_t reserved_1; 2148 uint32_t buffer_address[2]; 2149 uint16_t subcommand_length; 2150 uint16_t reserved_2; 2151 uint16_t subcommand; 2152 uint16_t size; 2153 uint32_t reserved_3; 2154 uint8_t param[36]; 2155 } cmd; 2156 2157 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 2158 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 2159 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 2160 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 2161 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 2162 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 2163 } p; 2164}; 2165 2166struct fw_blob { 2167 char *name; 2168 uint32_t segs[4]; 2169 const struct firmware *fw; 2170}; 2171 2172/* Return data from MBC_GET_ID_LIST call. */ 2173struct gid_list_info { 2174 uint8_t al_pa; 2175 uint8_t area; 2176 uint8_t domain; 2177 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2178 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2179 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 2180}; 2181 2182/* NPIV */ 2183typedef struct vport_info { 2184 uint8_t port_name[WWN_SIZE]; 2185 uint8_t node_name[WWN_SIZE]; 2186 int vp_id; 2187 uint16_t loop_id; 2188 unsigned long host_no; 2189 uint8_t port_id[3]; 2190 int loop_state; 2191} vport_info_t; 2192 2193typedef struct vport_params { 2194 uint8_t port_name[WWN_SIZE]; 2195 uint8_t node_name[WWN_SIZE]; 2196 uint32_t options; 2197#define VP_OPTS_RETRY_ENABLE BIT_0 2198#define VP_OPTS_VP_DISABLE BIT_1 2199} vport_params_t; 2200 2201/* NPIV - return codes of VP create and modify */ 2202#define VP_RET_CODE_OK 0 2203#define VP_RET_CODE_FATAL 1 2204#define VP_RET_CODE_WRONG_ID 2 2205#define VP_RET_CODE_WWPN 3 2206#define VP_RET_CODE_RESOURCES 4 2207#define VP_RET_CODE_NO_MEM 5 2208#define VP_RET_CODE_NOT_FOUND 6 2209 2210struct qla_hw_data; 2211struct rsp_que; 2212/* 2213 * ISP operations 2214 */ 2215struct isp_operations { 2216 2217 int (*pci_config) (struct scsi_qla_host *); 2218 void (*reset_chip) (struct scsi_qla_host *); 2219 int (*chip_diag) (struct scsi_qla_host *); 2220 void (*config_rings) (struct scsi_qla_host *); 2221 void (*reset_adapter) (struct scsi_qla_host *); 2222 int (*nvram_config) (struct scsi_qla_host *); 2223 void (*update_fw_options) (struct scsi_qla_host *); 2224 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 2225 2226 char * (*pci_info_str) (struct scsi_qla_host *, char *); 2227 char * (*fw_version_str) (struct scsi_qla_host *, char *); 2228 2229 irq_handler_t intr_handler; 2230 void (*enable_intrs) (struct qla_hw_data *); 2231 void (*disable_intrs) (struct qla_hw_data *); 2232 2233 int (*abort_command) (srb_t *); 2234 int (*target_reset) (struct fc_port *, unsigned int, int); 2235 int (*lun_reset) (struct fc_port *, unsigned int, int); 2236 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 2237 uint8_t, uint8_t, uint16_t *, uint8_t); 2238 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 2239 uint8_t, uint8_t); 2240 2241 uint16_t (*calc_req_entries) (uint16_t); 2242 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 2243 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t); 2244 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 2245 uint32_t); 2246 2247 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *, 2248 uint32_t, uint32_t); 2249 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 2250 uint32_t); 2251 2252 void (*fw_dump) (struct scsi_qla_host *, int); 2253 2254 int (*beacon_on) (struct scsi_qla_host *); 2255 int (*beacon_off) (struct scsi_qla_host *); 2256 void (*beacon_blink) (struct scsi_qla_host *); 2257 2258 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 2259 uint32_t, uint32_t); 2260 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 2261 uint32_t); 2262 2263 int (*get_flash_version) (struct scsi_qla_host *, void *); 2264 int (*start_scsi) (srb_t *); 2265 int (*abort_isp) (struct scsi_qla_host *); 2266 int (*iospace_config)(struct qla_hw_data*); 2267}; 2268 2269/* MSI-X Support *************************************************************/ 2270 2271#define QLA_MSIX_CHIP_REV_24XX 3 2272#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 2273#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 2274 2275#define QLA_MSIX_DEFAULT 0x00 2276#define QLA_MSIX_RSP_Q 0x01 2277 2278#define QLA_MIDX_DEFAULT 0 2279#define QLA_MIDX_RSP_Q 1 2280#define QLA_PCI_MSIX_CONTROL 0xa2 2281#define QLA_83XX_PCI_MSIX_CONTROL 0x92 2282 2283struct scsi_qla_host; 2284 2285struct qla_msix_entry { 2286 int have_irq; 2287 uint32_t vector; 2288 uint16_t entry; 2289 struct rsp_que *rsp; 2290}; 2291 2292#define WATCH_INTERVAL 1 /* number of seconds */ 2293 2294/* Work events. */ 2295enum qla_work_type { 2296 QLA_EVT_AEN, 2297 QLA_EVT_IDC_ACK, 2298 QLA_EVT_ASYNC_LOGIN, 2299 QLA_EVT_ASYNC_LOGIN_DONE, 2300 QLA_EVT_ASYNC_LOGOUT, 2301 QLA_EVT_ASYNC_LOGOUT_DONE, 2302 QLA_EVT_ASYNC_ADISC, 2303 QLA_EVT_ASYNC_ADISC_DONE, 2304 QLA_EVT_UEVENT, 2305}; 2306 2307 2308struct qla_work_evt { 2309 struct list_head list; 2310 enum qla_work_type type; 2311 u32 flags; 2312#define QLA_EVT_FLAG_FREE 0x1 2313 2314 union { 2315 struct { 2316 enum fc_host_event_code code; 2317 u32 data; 2318 } aen; 2319 struct { 2320#define QLA_IDC_ACK_REGS 7 2321 uint16_t mb[QLA_IDC_ACK_REGS]; 2322 } idc_ack; 2323 struct { 2324 struct fc_port *fcport; 2325#define QLA_LOGIO_LOGIN_RETRIED BIT_0 2326 u16 data[2]; 2327 } logio; 2328 struct { 2329 u32 code; 2330#define QLA_UEVENT_CODE_FW_DUMP 0 2331 } uevent; 2332 } u; 2333}; 2334 2335struct qla_chip_state_84xx { 2336 struct list_head list; 2337 struct kref kref; 2338 2339 void *bus; 2340 spinlock_t access_lock; 2341 struct mutex fw_update_mutex; 2342 uint32_t fw_update; 2343 uint32_t op_fw_version; 2344 uint32_t op_fw_size; 2345 uint32_t op_fw_seq_size; 2346 uint32_t diag_fw_version; 2347 uint32_t gold_fw_version; 2348}; 2349 2350struct qla_statistics { 2351 uint32_t total_isp_aborts; 2352 uint64_t input_bytes; 2353 uint64_t output_bytes; 2354}; 2355 2356/* Multi queue support */ 2357#define MBC_INITIALIZE_MULTIQ 0x1f 2358#define QLA_QUE_PAGE 0X1000 2359#define QLA_MQ_SIZE 32 2360#define QLA_MAX_QUEUES 256 2361#define ISP_QUE_REG(ha, id) \ 2362 ((ha->mqenable || IS_QLA83XX(ha)) ? \ 2363 ((void *)(ha->mqiobase) +\ 2364 (QLA_QUE_PAGE * id)) :\ 2365 ((void *)(ha->iobase))) 2366#define QLA_REQ_QUE_ID(tag) \ 2367 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 2368#define QLA_DEFAULT_QUE_QOS 5 2369#define QLA_PRECONFIG_VPORTS 32 2370#define QLA_MAX_VPORTS_QLA24XX 128 2371#define QLA_MAX_VPORTS_QLA25XX 256 2372/* Response queue data structure */ 2373struct rsp_que { 2374 dma_addr_t dma; 2375 response_t *ring; 2376 response_t *ring_ptr; 2377 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 2378 uint32_t __iomem *rsp_q_out; 2379 uint16_t ring_index; 2380 uint16_t out_ptr; 2381 uint16_t length; 2382 uint16_t options; 2383 uint16_t rid; 2384 uint16_t id; 2385 uint16_t vp_idx; 2386 struct qla_hw_data *hw; 2387 struct qla_msix_entry *msix; 2388 struct req_que *req; 2389 srb_t *status_srb; /* status continuation entry */ 2390 struct work_struct q_work; 2391}; 2392 2393/* Request queue data structure */ 2394struct req_que { 2395 dma_addr_t dma; 2396 request_t *ring; 2397 request_t *ring_ptr; 2398 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 2399 uint32_t __iomem *req_q_out; 2400 uint16_t ring_index; 2401 uint16_t in_ptr; 2402 uint16_t cnt; 2403 uint16_t length; 2404 uint16_t options; 2405 uint16_t rid; 2406 uint16_t id; 2407 uint16_t qos; 2408 uint16_t vp_idx; 2409 struct rsp_que *rsp; 2410 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; 2411 uint32_t current_outstanding_cmd; 2412 int max_q_depth; 2413}; 2414 2415/* Place holder for FW buffer parameters */ 2416struct qlfc_fw { 2417 void *fw_buf; 2418 dma_addr_t fw_dma; 2419 uint32_t len; 2420}; 2421 2422/* 2423 * Qlogic host adapter specific data structure. 2424*/ 2425struct qla_hw_data { 2426 struct pci_dev *pdev; 2427 /* SRB cache. */ 2428#define SRB_MIN_REQ 128 2429 mempool_t *srb_mempool; 2430 2431 volatile struct { 2432 uint32_t mbox_int :1; 2433 uint32_t mbox_busy :1; 2434 uint32_t disable_risc_code_load :1; 2435 uint32_t enable_64bit_addressing :1; 2436 uint32_t enable_lip_reset :1; 2437 uint32_t enable_target_reset :1; 2438 uint32_t enable_lip_full_login :1; 2439 uint32_t enable_led_scheme :1; 2440 2441 uint32_t msi_enabled :1; 2442 uint32_t msix_enabled :1; 2443 uint32_t disable_serdes :1; 2444 uint32_t gpsc_supported :1; 2445 uint32_t npiv_supported :1; 2446 uint32_t pci_channel_io_perm_failure :1; 2447 uint32_t fce_enabled :1; 2448 uint32_t fac_supported :1; 2449 2450 uint32_t chip_reset_done :1; 2451 uint32_t port0 :1; 2452 uint32_t running_gold_fw :1; 2453 uint32_t eeh_busy :1; 2454 uint32_t cpu_affinity_enabled :1; 2455 uint32_t disable_msix_handshake :1; 2456 uint32_t fcp_prio_enabled :1; 2457 uint32_t isp82xx_fw_hung:1; 2458 2459 uint32_t quiesce_owner:1; 2460 uint32_t thermal_supported:1; 2461 uint32_t isp82xx_reset_hdlr_active:1; 2462 uint32_t isp82xx_reset_owner:1; 2463 /* 28 bits */ 2464 } flags; 2465 2466 /* This spinlock is used to protect "io transactions", you must 2467 * acquire it before doing any IO to the card, eg with RD_REG*() and 2468 * WRT_REG*() for the duration of your entire commandtransaction. 2469 * 2470 * This spinlock is of lower priority than the io request lock. 2471 */ 2472 2473 spinlock_t hardware_lock ____cacheline_aligned; 2474 int bars; 2475 int mem_only; 2476 device_reg_t __iomem *iobase; /* Base I/O address */ 2477 resource_size_t pio_address; 2478 2479#define MIN_IOBASE_LEN 0x100 2480/* Multi queue data structs */ 2481 device_reg_t __iomem *mqiobase; 2482 device_reg_t __iomem *msixbase; 2483 uint16_t msix_count; 2484 uint8_t mqenable; 2485 struct req_que **req_q_map; 2486 struct rsp_que **rsp_q_map; 2487 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 2488 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 2489 uint8_t max_req_queues; 2490 uint8_t max_rsp_queues; 2491 struct qla_npiv_entry *npiv_info; 2492 uint16_t nvram_npiv_size; 2493 2494 uint16_t switch_cap; 2495#define FLOGI_SEQ_DEL BIT_8 2496#define FLOGI_MID_SUPPORT BIT_10 2497#define FLOGI_VSAN_SUPPORT BIT_12 2498#define FLOGI_SP_SUPPORT BIT_13 2499 2500 uint8_t port_no; /* Physical port of adapter */ 2501 2502 /* Timeout timers. */ 2503 uint8_t loop_down_abort_time; /* port down timer */ 2504 atomic_t loop_down_timer; /* loop down timer */ 2505 uint8_t link_down_timeout; /* link down timeout */ 2506 uint16_t max_loop_id; 2507 uint16_t max_fibre_devices; /* Maximum number of targets */ 2508 2509 uint16_t fb_rev; 2510 uint16_t min_external_loopid; /* First external loop Id */ 2511 2512#define PORT_SPEED_UNKNOWN 0xFFFF 2513#define PORT_SPEED_1GB 0x00 2514#define PORT_SPEED_2GB 0x01 2515#define PORT_SPEED_4GB 0x03 2516#define PORT_SPEED_8GB 0x04 2517#define PORT_SPEED_16GB 0x05 2518#define PORT_SPEED_10GB 0x13 2519 uint16_t link_data_rate; /* F/W operating speed */ 2520 2521 uint8_t current_topology; 2522 uint8_t prev_topology; 2523#define ISP_CFG_NL 1 2524#define ISP_CFG_N 2 2525#define ISP_CFG_FL 4 2526#define ISP_CFG_F 8 2527 2528 uint8_t operating_mode; /* F/W operating mode */ 2529#define LOOP 0 2530#define P2P 1 2531#define LOOP_P2P 2 2532#define P2P_LOOP 3 2533 uint8_t interrupts_on; 2534 uint32_t isp_abort_cnt; 2535 2536#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 2537#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 2538#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 2539#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 2540#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 2541 uint32_t device_type; 2542#define DT_ISP2100 BIT_0 2543#define DT_ISP2200 BIT_1 2544#define DT_ISP2300 BIT_2 2545#define DT_ISP2312 BIT_3 2546#define DT_ISP2322 BIT_4 2547#define DT_ISP6312 BIT_5 2548#define DT_ISP6322 BIT_6 2549#define DT_ISP2422 BIT_7 2550#define DT_ISP2432 BIT_8 2551#define DT_ISP5422 BIT_9 2552#define DT_ISP5432 BIT_10 2553#define DT_ISP2532 BIT_11 2554#define DT_ISP8432 BIT_12 2555#define DT_ISP8001 BIT_13 2556#define DT_ISP8021 BIT_14 2557#define DT_ISP2031 BIT_15 2558#define DT_ISP8031 BIT_16 2559#define DT_ISP_LAST (DT_ISP8031 << 1) 2560 2561#define DT_T10_PI BIT_25 2562#define DT_IIDMA BIT_26 2563#define DT_FWI2 BIT_27 2564#define DT_ZIO_SUPPORTED BIT_28 2565#define DT_OEM_001 BIT_29 2566#define DT_ISP2200A BIT_30 2567#define DT_EXTENDED_IDS BIT_31 2568#define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1)) 2569#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 2570#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 2571#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 2572#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 2573#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 2574#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 2575#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 2576#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 2577#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 2578#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 2579#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 2580#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 2581#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 2582#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 2583#define IS_QLA81XX(ha) (IS_QLA8001(ha)) 2584#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 2585#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 2586#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 2587 2588#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 2589 IS_QLA6312(ha) || IS_QLA6322(ha)) 2590#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 2591#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 2592#define IS_QLA25XX(ha) (IS_QLA2532(ha)) 2593#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 2594#define IS_QLA84XX(ha) (IS_QLA8432(ha)) 2595#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 2596 IS_QLA84XX(ha)) 2597#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 2598 IS_QLA8031(ha)) 2599#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 2600 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 2601 IS_QLA82XX(ha) || IS_QLA83XX(ha)) 2602#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) 2603#define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 2604 IS_QLA83XX(ha)) && (ha)->flags.msix_enabled) 2605#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) 2606#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) 2607#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 2608 2609#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 2610#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 2611#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 2612#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 2613#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 2614#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 2615#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 2616#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha)) 2617 2618 /* HBA serial number */ 2619 uint8_t serial0; 2620 uint8_t serial1; 2621 uint8_t serial2; 2622 2623 /* NVRAM configuration data */ 2624#define MAX_NVRAM_SIZE 4096 2625#define VPD_OFFSET MAX_NVRAM_SIZE / 2 2626 uint16_t nvram_size; 2627 uint16_t nvram_base; 2628 void *nvram; 2629 uint16_t vpd_size; 2630 uint16_t vpd_base; 2631 void *vpd; 2632 2633 uint16_t loop_reset_delay; 2634 uint8_t retry_count; 2635 uint8_t login_timeout; 2636 uint16_t r_a_tov; 2637 int port_down_retry_count; 2638 uint8_t mbx_count; 2639 2640 uint32_t login_retry_count; 2641 /* SNS command interfaces. */ 2642 ms_iocb_entry_t *ms_iocb; 2643 dma_addr_t ms_iocb_dma; 2644 struct ct_sns_pkt *ct_sns; 2645 dma_addr_t ct_sns_dma; 2646 /* SNS command interfaces for 2200. */ 2647 struct sns_cmd_pkt *sns_cmd; 2648 dma_addr_t sns_cmd_dma; 2649 2650#define SFP_DEV_SIZE 256 2651#define SFP_BLOCK_SIZE 64 2652 void *sfp_data; 2653 dma_addr_t sfp_data_dma; 2654 2655#define XGMAC_DATA_SIZE 4096 2656 void *xgmac_data; 2657 dma_addr_t xgmac_data_dma; 2658 2659#define DCBX_TLV_DATA_SIZE 4096 2660 void *dcbx_tlv; 2661 dma_addr_t dcbx_tlv_dma; 2662 2663 struct task_struct *dpc_thread; 2664 uint8_t dpc_active; /* DPC routine is active */ 2665 2666 dma_addr_t gid_list_dma; 2667 struct gid_list_info *gid_list; 2668 int gid_list_info_size; 2669 2670 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 2671#define DMA_POOL_SIZE 256 2672 struct dma_pool *s_dma_pool; 2673 2674 dma_addr_t init_cb_dma; 2675 init_cb_t *init_cb; 2676 int init_cb_size; 2677 dma_addr_t ex_init_cb_dma; 2678 struct ex_init_cb_81xx *ex_init_cb; 2679 2680 void *async_pd; 2681 dma_addr_t async_pd_dma; 2682 2683 void *swl; 2684 2685 /* These are used by mailbox operations. */ 2686 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 2687 2688 mbx_cmd_t *mcp; 2689 unsigned long mbx_cmd_flags; 2690#define MBX_INTERRUPT 1 2691#define MBX_INTR_WAIT 2 2692#define MBX_UPDATE_FLASH_ACTIVE 3 2693 2694 struct mutex vport_lock; /* Virtual port synchronization */ 2695 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 2696 struct completion mbx_cmd_comp; /* Serialize mbx access */ 2697 struct completion mbx_intr_comp; /* Used for completion notification */ 2698 struct completion dcbx_comp; /* For set port config notification */ 2699 int notify_dcbx_comp; 2700 2701 /* Basic firmware related information. */ 2702 uint16_t fw_major_version; 2703 uint16_t fw_minor_version; 2704 uint16_t fw_subminor_version; 2705 uint16_t fw_attributes; 2706 uint16_t fw_attributes_h; 2707 uint16_t fw_attributes_ext[2]; 2708 uint32_t fw_memory_size; 2709 uint32_t fw_transfer_size; 2710 uint32_t fw_srisc_address; 2711#define RISC_START_ADDRESS_2100 0x1000 2712#define RISC_START_ADDRESS_2300 0x800 2713#define RISC_START_ADDRESS_2400 0x100000 2714 uint16_t fw_xcb_count; 2715 2716 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 2717 uint8_t fw_seriallink_options[4]; 2718 uint16_t fw_seriallink_options24[4]; 2719 2720 uint8_t mpi_version[3]; 2721 uint32_t mpi_capabilities; 2722 uint8_t phy_version[3]; 2723 2724 /* Firmware dump information. */ 2725 struct qla2xxx_fw_dump *fw_dump; 2726 uint32_t fw_dump_len; 2727 int fw_dumped; 2728 int fw_dump_reading; 2729 dma_addr_t eft_dma; 2730 void *eft; 2731 2732 uint32_t chain_offset; 2733 struct dentry *dfs_dir; 2734 struct dentry *dfs_fce; 2735 dma_addr_t fce_dma; 2736 void *fce; 2737 uint32_t fce_bufs; 2738 uint16_t fce_mb[8]; 2739 uint64_t fce_wr, fce_rd; 2740 struct mutex fce_mutex; 2741 2742 uint32_t pci_attr; 2743 uint16_t chip_revision; 2744 2745 uint16_t product_id[4]; 2746 2747 uint8_t model_number[16+1]; 2748#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 2749 char model_desc[80]; 2750 uint8_t adapter_id[16+1]; 2751 2752 /* Option ROM information. */ 2753 char *optrom_buffer; 2754 uint32_t optrom_size; 2755 int optrom_state; 2756#define QLA_SWAITING 0 2757#define QLA_SREADING 1 2758#define QLA_SWRITING 2 2759 uint32_t optrom_region_start; 2760 uint32_t optrom_region_size; 2761 2762/* PCI expansion ROM image information. */ 2763#define ROM_CODE_TYPE_BIOS 0 2764#define ROM_CODE_TYPE_FCODE 1 2765#define ROM_CODE_TYPE_EFI 3 2766 uint8_t bios_revision[2]; 2767 uint8_t efi_revision[2]; 2768 uint8_t fcode_revision[16]; 2769 uint32_t fw_revision[4]; 2770 2771 uint32_t gold_fw_version[4]; 2772 2773 /* Offsets for flash/nvram access (set to ~0 if not used). */ 2774 uint32_t flash_conf_off; 2775 uint32_t flash_data_off; 2776 uint32_t nvram_conf_off; 2777 uint32_t nvram_data_off; 2778 2779 uint32_t fdt_wrt_disable; 2780 uint32_t fdt_erase_cmd; 2781 uint32_t fdt_block_size; 2782 uint32_t fdt_unprotect_sec_cmd; 2783 uint32_t fdt_protect_sec_cmd; 2784 2785 uint32_t flt_region_flt; 2786 uint32_t flt_region_fdt; 2787 uint32_t flt_region_boot; 2788 uint32_t flt_region_fw; 2789 uint32_t flt_region_vpd_nvram; 2790 uint32_t flt_region_vpd; 2791 uint32_t flt_region_nvram; 2792 uint32_t flt_region_npiv_conf; 2793 uint32_t flt_region_gold_fw; 2794 uint32_t flt_region_fcp_prio; 2795 uint32_t flt_region_bootload; 2796 2797 /* Needed for BEACON */ 2798 uint16_t beacon_blink_led; 2799 uint8_t beacon_color_state; 2800#define QLA_LED_GRN_ON 0x01 2801#define QLA_LED_YLW_ON 0x02 2802#define QLA_LED_ABR_ON 0x04 2803#define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 2804 /* ISP2322: red, green, amber. */ 2805 uint16_t zio_mode; 2806 uint16_t zio_timer; 2807 struct fc_host_statistics fc_host_stat; 2808 2809 struct qla_msix_entry *msix_entries; 2810 2811 struct list_head vp_list; /* list of VP */ 2812 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 2813 sizeof(unsigned long)]; 2814 uint16_t num_vhosts; /* number of vports created */ 2815 uint16_t num_vsans; /* number of vsan created */ 2816 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 2817 int cur_vport_count; 2818 2819 struct qla_chip_state_84xx *cs84xx; 2820 struct qla_statistics qla_stats; 2821 struct isp_operations *isp_ops; 2822 struct workqueue_struct *wq; 2823 struct qlfc_fw fw_buf; 2824 2825 /* FCP_CMND priority support */ 2826 struct qla_fcp_prio_cfg *fcp_prio_cfg; 2827 2828 struct dma_pool *dl_dma_pool; 2829#define DSD_LIST_DMA_POOL_SIZE 512 2830 2831 struct dma_pool *fcp_cmnd_dma_pool; 2832 mempool_t *ctx_mempool; 2833#define FCP_CMND_DMA_POOL_SIZE 512 2834 2835 unsigned long nx_pcibase; /* Base I/O address */ 2836 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */ 2837 unsigned long nxdb_wr_ptr; /* Door bell write pointer */ 2838 2839 uint32_t crb_win; 2840 uint32_t curr_window; 2841 uint32_t ddr_mn_window; 2842 unsigned long mn_win_crb; 2843 unsigned long ms_win_crb; 2844 int qdr_sn_window; 2845 uint32_t nx_dev_init_timeout; 2846 uint32_t nx_reset_timeout; 2847 rwlock_t hw_lock; 2848 uint16_t portnum; /* port number */ 2849 int link_width; 2850 struct fw_blob *hablob; 2851 struct qla82xx_legacy_intr_set nx_legacy_intr; 2852 2853 uint16_t gbl_dsd_inuse; 2854 uint16_t gbl_dsd_avail; 2855 struct list_head gbl_dsd_list; 2856#define NUM_DSD_CHAIN 4096 2857 2858 uint8_t fw_type; 2859 __le32 file_prd_off; /* File firmware product offset */ 2860 2861 uint32_t md_template_size; 2862 void *md_tmplt_hdr; 2863 dma_addr_t md_tmplt_hdr_dma; 2864 void *md_dump; 2865 uint32_t md_dump_size; 2866}; 2867 2868/* 2869 * Qlogic scsi host structure 2870 */ 2871typedef struct scsi_qla_host { 2872 struct list_head list; 2873 struct list_head vp_fcports; /* list of fcports */ 2874 struct list_head work_list; 2875 spinlock_t work_lock; 2876 2877 /* Commonly used flags and state information. */ 2878 struct Scsi_Host *host; 2879 unsigned long host_no; 2880 uint8_t host_str[16]; 2881 2882 volatile struct { 2883 uint32_t init_done :1; 2884 uint32_t online :1; 2885 uint32_t reset_active :1; 2886 2887 uint32_t management_server_logged_in :1; 2888 uint32_t process_response_queue :1; 2889 uint32_t difdix_supported:1; 2890 uint32_t delete_progress:1; 2891 } flags; 2892 2893 atomic_t loop_state; 2894#define LOOP_TIMEOUT 1 2895#define LOOP_DOWN 2 2896#define LOOP_UP 3 2897#define LOOP_UPDATE 4 2898#define LOOP_READY 5 2899#define LOOP_DEAD 6 2900 2901 unsigned long dpc_flags; 2902#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 2903#define RESET_ACTIVE 1 2904#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 2905#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 2906#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 2907#define LOOP_RESYNC_ACTIVE 5 2908#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 2909#define RSCN_UPDATE 7 /* Perform an RSCN update. */ 2910#define RELOGIN_NEEDED 8 2911#define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 2912#define ISP_ABORT_RETRY 10 /* ISP aborted. */ 2913#define BEACON_BLINK_NEEDED 11 2914#define REGISTER_FDMI_NEEDED 12 2915#define FCPORT_UPDATE_NEEDED 13 2916#define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 2917#define UNLOADING 15 2918#define NPIV_CONFIG_NEEDED 16 2919#define ISP_UNRECOVERABLE 17 2920#define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 2921#define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 2922#define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 2923 2924 uint32_t device_flags; 2925#define SWITCH_FOUND BIT_0 2926#define DFLG_NO_CABLE BIT_1 2927#define DFLG_DEV_FAILED BIT_5 2928 2929 /* ISP configuration data. */ 2930 uint16_t loop_id; /* Host adapter loop id */ 2931 2932 port_id_t d_id; /* Host adapter port id */ 2933 uint8_t marker_needed; 2934 uint16_t mgmt_svr_loop_id; 2935 2936 2937 2938 /* Timeout timers. */ 2939 uint8_t loop_down_abort_time; /* port down timer */ 2940 atomic_t loop_down_timer; /* loop down timer */ 2941 uint8_t link_down_timeout; /* link down timeout */ 2942 2943 uint32_t timer_active; 2944 struct timer_list timer; 2945 2946 uint8_t node_name[WWN_SIZE]; 2947 uint8_t port_name[WWN_SIZE]; 2948 uint8_t fabric_node_name[WWN_SIZE]; 2949 2950 uint16_t fcoe_vlan_id; 2951 uint16_t fcoe_fcf_idx; 2952 uint8_t fcoe_vn_port_mac[6]; 2953 2954 uint32_t vp_abort_cnt; 2955 2956 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 2957 uint16_t vp_idx; /* vport ID */ 2958 2959 unsigned long vp_flags; 2960#define VP_IDX_ACQUIRED 0 /* bit no 0 */ 2961#define VP_CREATE_NEEDED 1 2962#define VP_BIND_NEEDED 2 2963#define VP_DELETE_NEEDED 3 2964#define VP_SCR_NEEDED 4 /* State Change Request registration */ 2965 atomic_t vp_state; 2966#define VP_OFFLINE 0 2967#define VP_ACTIVE 1 2968#define VP_FAILED 2 2969// #define VP_DISABLE 3 2970 uint16_t vp_err_state; 2971 uint16_t vp_prev_err_state; 2972#define VP_ERR_UNKWN 0 2973#define VP_ERR_PORTDWN 1 2974#define VP_ERR_FAB_UNSUPPORTED 2 2975#define VP_ERR_FAB_NORESOURCES 3 2976#define VP_ERR_FAB_LOGOUT 4 2977#define VP_ERR_ADAP_NORESOURCES 5 2978 struct qla_hw_data *hw; 2979 struct req_que *req; 2980 int fw_heartbeat_counter; 2981 int seconds_since_last_heartbeat; 2982 2983 atomic_t vref_count; 2984} scsi_qla_host_t; 2985 2986/* 2987 * Macros to help code, maintain, etc. 2988 */ 2989#define LOOP_TRANSITION(ha) \ 2990 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 2991 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 2992 atomic_read(&ha->loop_state) == LOOP_DOWN) 2993 2994#define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 2995 atomic_inc(&__vha->vref_count); \ 2996 mb(); \ 2997 if (__vha->flags.delete_progress) { \ 2998 atomic_dec(&__vha->vref_count); \ 2999 __bail = 1; \ 3000 } else { \ 3001 __bail = 0; \ 3002 } \ 3003} while (0) 3004 3005#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 3006 atomic_dec(&__vha->vref_count); \ 3007} while (0) 3008 3009/* 3010 * qla2x00 local function return status codes 3011 */ 3012#define MBS_MASK 0x3fff 3013 3014#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 3015#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 3016#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 3017#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 3018#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 3019#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 3020#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 3021#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 3022#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 3023#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 3024 3025#define QLA_FUNCTION_TIMEOUT 0x100 3026#define QLA_FUNCTION_PARAMETER_ERROR 0x101 3027#define QLA_FUNCTION_FAILED 0x102 3028#define QLA_MEMORY_ALLOC_FAILED 0x103 3029#define QLA_LOCK_TIMEOUT 0x104 3030#define QLA_ABORTED 0x105 3031#define QLA_SUSPENDED 0x106 3032#define QLA_BUSY 0x107 3033#define QLA_ALREADY_REGISTERED 0x109 3034 3035#define NVRAM_DELAY() udelay(10) 3036 3037#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1) 3038 3039/* 3040 * Flash support definitions 3041 */ 3042#define OPTROM_SIZE_2300 0x20000 3043#define OPTROM_SIZE_2322 0x100000 3044#define OPTROM_SIZE_24XX 0x100000 3045#define OPTROM_SIZE_25XX 0x200000 3046#define OPTROM_SIZE_81XX 0x400000 3047#define OPTROM_SIZE_82XX 0x800000 3048#define OPTROM_SIZE_83XX 0x1000000 3049 3050#define OPTROM_BURST_SIZE 0x1000 3051#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3052 3053#define QLA_DSDS_PER_IOCB 37 3054 3055#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 3056 3057#define QLA_SG_ALL 1024 3058 3059enum nexus_wait_type { 3060 WAIT_HOST = 0, 3061 WAIT_TARGET, 3062 WAIT_LUN, 3063}; 3064 3065#include "qla_gbl.h" 3066#include "qla_dbg.h" 3067#include "qla_inline.h" 3068#endif 3069