1fa90c54f6d27664cc67691f9e52d9165e0c25ca7Andrew Vasquez/* 2fa90c54f6d27664cc67691f9e52d9165e0c25ca7Andrew Vasquez * QLogic Fibre Channel HBA Driver 307e264b76d1db5794614ca3d726fdf1c0399dac0Andrew Vasquez * Copyright (c) 2003-2011 QLogic Corporation 4fa90c54f6d27664cc67691f9e52d9165e0c25ca7Andrew Vasquez * 5fa90c54f6d27664cc67691f9e52d9165e0c25ca7Andrew Vasquez * See LICENSE.qla2xxx for copyright and licensing details. 6fa90c54f6d27664cc67691f9e52d9165e0c25ca7Andrew Vasquez */ 73d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#ifndef __QLA_FW_H 83d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define __QLA_FW_H 93d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MBS_CHECKSUM_ERROR 0x4010 11c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez#define MBS_INVALID_PRODUCT_KEY 0x4020 123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * Firmware Options. 153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FO1_ENABLE_PUREX BIT_10 173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FO1_DISABLE_LED_CTRL BIT_6 18c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez#define FO1_ENABLE_8016 BIT_0 193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FO2_ENABLE_SEL_CLASS2 BIT_5 203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FO3_NO_ABTS_ON_LINKDOWN BIT_14 21c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez#define FO3_HOLD_STS_IOCB BIT_12 223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * Port Database structure definition for ISP 24xx. 253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDO_FORCE_ADISC BIT_1 273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDO_FORCE_PLOGI BIT_0 283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PORT_DATABASE_24XX_SIZE 64 313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct port_database_24xx { 323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t flags; 333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_TASK_RETRY_ID BIT_14 343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_FC_TAPE BIT_7 353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_ACK0_CAPABLE BIT_6 363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_FCP2_CONF BIT_5 373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_CLASS_2 BIT_4 383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_HARD_ADDR BIT_1 393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t current_login_state; 413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t last_login_state; 423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PLOGI_PENDING 0x03 433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PLOGI_COMPLETE 0x04 443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PRLI_PENDING 0x05 453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PRLI_COMPLETE 0x06 463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PORT_UNAVAILABLE 0x07 473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PRLO_PENDING 0x09 483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_LOGO_PENDING 0x11 493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PRLI2_PENDING 0x12 503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t hard_address[3]; 523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_1; 533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; 553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sequence_id; 563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t port_timer; 583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t receive_data_size; 623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_2; 633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prli_svc_param_word_0[2]; /* Big endian */ 653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Bits 15-0 of word 0 */ 663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prli_svc_param_word_3[2]; /* Big endian */ 673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Bits 15-0 of word 3 */ 683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name[WWN_SIZE]; 703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name[WWN_SIZE]; 713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_3[24]; 733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 752c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Justruct vp_database_24xx { 762c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t vp_status; 772c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint8_t options; 782c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint8_t id; 792c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint8_t port_name[WWN_SIZE]; 802c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint8_t node_name[WWN_SIZE]; 812c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t port_id_low; 822c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t port_id_high; 832c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju}; 842c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju 853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct nvram_24xx { 863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* NVRAM header. */ 873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t id[4]; 883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nvram_version; 893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_0; 903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Firmware Initialization Control Block. */ 923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t version; 933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t frame_payload_size; 953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t execution_throttle; 963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t exchange_count; 973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t hard_address; 983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name[WWN_SIZE]; 1003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name[WWN_SIZE]; 1013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t login_retry_count; 1033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t link_down_on_nos; 1043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t interrupt_delay_timer; 1053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t login_timeout; 1063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_1; 1083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_2; 1093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_3; 1103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 56. */ 1123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 1143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Control Enable 1153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1-15 = 1163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 1173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0-7 = Reserved 1183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8-10 = Output Swing 1G 1193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11-13 = Output Emphasis 1G 1203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14-15 = Reserved 1213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 1223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0-7 = Reserved 1233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8-10 = Output Swing 2G 1243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11-13 = Output Emphasis 2G 1253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14-15 = Reserved 1263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 1273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0-7 = Reserved 1283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8-10 = Output Swing 4G 1293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11-13 = Output Emphasis 4G 1303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14-15 = Reserved 1313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 1323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t seriallink_options[4]; 1333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_2[16]; 1353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 96. */ 1373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_3[16]; 1383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* PCIe table entries. */ 1403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_4[16]; 1413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 160. */ 1433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_5[16]; 1443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 192. */ 1463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_6[16]; 1473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 224. */ 1493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_7[16]; 1503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 1523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Enable spinup delay 1533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Disable BIOS 1543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = Enable Memory Map BIOS 1553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Enable Selectable Boot 1563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = Disable RISC code load 157d4c760c2119fca982f335d83ff9095479c5d6737Andrew Vasquez * BIT 5 = Disable Serdes 1583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6 = 1593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 7 = 1603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 1613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8 = 1623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 9 = 1633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 10 = Enable lip full login 1643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11 = Enable target reset 1653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 12 = 1663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 13 = 1673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14 = 1683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 15 = Enable alternate WWN 1693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 1703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 16-31 = 1713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 1723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t host_p; 1733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t alternate_port_name[WWN_SIZE]; 1753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t alternate_node_name[WWN_SIZE]; 1763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t boot_port_name[WWN_SIZE]; 1783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t boot_lun_number; 1793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_8; 1803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t alt1_boot_port_name[WWN_SIZE]; 1823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t alt1_boot_lun_number; 1833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_9; 1843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t alt2_boot_port_name[WWN_SIZE]; 1863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t alt2_boot_lun_number; 1873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_10; 1883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t alt3_boot_port_name[WWN_SIZE]; 1903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t alt3_boot_lun_number; 1913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_11; 1923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 1943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Selective Login 1953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Alt-Boot Enable 1963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = Reserved 1973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Boot Order List 1983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = Reserved 1993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 5 = Selective LUN 2003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6 = Reserved 2013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 7-31 = 2023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 2033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t efi_parameters; 2043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reset_delay; 2063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_12; 2073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_13; 2083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t boot_id_number; 2103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_14; 2113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t max_luns_per_target; 2133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_15; 2143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t port_down_retry_count; 2163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t link_down_timeout; 2173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* FCode parameters. */ 2193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t fcode_parameter; 2203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_16[3]; 2223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 352. */ 2243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_drv_ver_major; 2253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_drv_ver_submajob; 2263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_drv_ver_minor; 2273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_drv_ver_subminor; 2283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prev_bios_ver_major; 2303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prev_bios_ver_minor; 2313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prev_efi_ver_major; 2333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prev_efi_ver_minor; 2343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prev_fw_ver_major; 2363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_fw_ver_minor; 2373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_fw_ver_subminor; 2383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_17[8]; 2403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 384. */ 2423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_18[16]; 2433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 416. */ 2453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_19[16]; 2463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 448. */ 2483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_20[16]; 2493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 480. */ 2513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t model_name[16]; 2523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_21[2]; 2543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 500. */ 2563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* HW Parameter Block. */ 2573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t pcie_table_sig; 2583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t pcie_table_offset; 2593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t subsystem_vendor_id; 2613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t subsystem_device_id; 2623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t checksum; 2643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 2653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 2673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP Initialization Control Block. 2683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * Little endian except where noted. 2693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 2703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ICB_VERSION 1 2713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct init_cb_24xx { 2723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t version; 2733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 2743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t frame_payload_size; 2763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t execution_throttle; 2773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t exchange_count; 2783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t hard_address; 2803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name[WWN_SIZE]; /* Big endian. */ 2823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name[WWN_SIZE]; /* Big endian. */ 2833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t response_q_inpointer; 2853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t request_q_outpointer; 2863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t login_retry_count; 2883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prio_request_q_outpointer; 2903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t response_q_length; 2923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t request_q_length; 2933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2943ea66e28c20e3b23749c9001c58b37ad44263442Andrew Vasquez uint16_t link_down_on_nos; /* Milliseconds. */ 2953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prio_request_q_length; 2973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t request_q_address[2]; 2993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t response_q_address[2]; 3003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t prio_request_q_address[2]; 3013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 30273208dfd7ab19f379d73e8a0fbf30f92c203e5e8Anirban Chakraborty uint16_t msix; 30373208dfd7ab19f379d73e8a0fbf30f92c203e5e8Anirban Chakraborty uint8_t reserved_2[6]; 3043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t atio_q_inpointer; 3063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t atio_q_length; 3073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t atio_q_address[2]; 3083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t interrupt_delay_timer; /* 100us increments. */ 3103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t login_timeout; 3113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 3133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Enable Hard Loop Id 3143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Enable Fairness 3153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = Enable Full-Duplex 3163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Reserved 3173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = Enable Target Mode 3183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 5 = Disable Initiator Mode 3193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6 = Reserved 3203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 7 = Reserved 3213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 3223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8 = Reserved 3233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 9 = Non Participating LIP 3243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 10 = Descending Loop ID Search 3253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11 = Acquire Loop ID in LIPA 3263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 12 = Reserved 3273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 13 = Full Login after LIP 3283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14 = Node Name Option 3293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 15-31 = Reserved 3303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 3313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_1; 3323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 3343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Operation Mode bit 0 3353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Operation Mode bit 1 3363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = Operation Mode bit 2 3373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Operation Mode bit 3 3383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = Connection Options bit 0 3393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 5 = Connection Options bit 1 3403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6 = Connection Options bit 2 3413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 7 = Enable Non part on LIHA failure 3423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 3433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8 = Enable Class 2 3443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 9 = Enable ACK0 3453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 10 = Reserved 3463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11 = Enable FC-SP Security 3473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 12 = FC Tape Enable 348c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez * BIT 13 = Reserved 349c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez * BIT 14 = Enable Target PRLI Control 350c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez * BIT 15-31 = Reserved 3513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 3523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_2; 3533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 3553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Reserved 3563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Soft ID only 3573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = Reserved 3583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Reserved 3593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = FCP RSP Payload bit 0 3603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 5 = FCP RSP Payload bit 1 3613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6 = Enable Receive Out-of-Order data frame handling 3623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 7 = Disable Automatic PLOGI on Local Loop 3633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 3643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8 = Reserved 3653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 3663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 10 = Reserved 3673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11 = Reserved 3683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 12 = Reserved 3693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 13 = Data Rate bit 0 3703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14 = Data Rate bit 1 3713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 15 = Data Rate bit 2 372c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez * BIT 16 = Enable 75 ohm Termination Select 373c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez * BIT 17-31 = Reserved 3743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 3753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_3; 37673208dfd7ab19f379d73e8a0fbf30f92c203e5e8Anirban Chakraborty uint16_t qos; 37773208dfd7ab19f379d73e8a0fbf30f92c203e5e8Anirban Chakraborty uint16_t rid; 37873208dfd7ab19f379d73e8a0fbf30f92c203e5e8Anirban Chakraborty uint8_t reserved_3[20]; 3793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 3803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 3823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - command entry structure definition. 3833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 3843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */ 3853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct cmd_type_6 { 3863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 3873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 3883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 3893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 3903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 3923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 3943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t timeout; /* Command timeout. */ 3953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t dseg_count; /* Data segment count. */ 3973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */ 3993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 400661c3f6cc32e1307fc7df724149884c95e98358dAndrew Vasquez struct scsi_lun lun; /* FCP LUN (BE). */ 4013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t control_flags; /* Control flags. */ 403bad750028917a7b804623701d0674e46c6012c18Arun Easi#define CF_DIF_SEG_DESCR_ENABLE BIT_3 4043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CF_DATA_SEG_DESCR_ENABLE BIT_2 4053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CF_READ_DATA BIT_1 4063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CF_WRITE_DATA BIT_0 4073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 4093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 4103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 4123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t byte_count; /* Total byte count. */ 4143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; /* PortID of destination port. */ 4163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 4173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ 419fa96d927362a422405d65491326f8ef763572e84Andrew Vasquez uint32_t fcp_data_dseg_len; /* Data segment length. */ 4203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 4213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */ 4233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct cmd_type_7 { 4243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 4253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 4263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 4273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 4283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 4303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 4323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t timeout; /* Command timeout. */ 4333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FW_MAX_TIMEOUT 0x1999 4343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t dseg_count; /* Data segment count. */ 4363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 4373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 438661c3f6cc32e1307fc7df724149884c95e98358dAndrew Vasquez struct scsi_lun lun; /* FCP LUN (BE). */ 4393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t task_mgmt_flags; /* Task management flags. */ 4413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_CLEAR_ACA BIT_14 4423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_TARGET_RESET BIT_13 4433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_LUN_RESET BIT_12 4443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_CLEAR_TASK_SET BIT_10 4453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_ABORT_TASK_SET BIT_9 446c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez#define TMF_DSD_LIST_ENABLE BIT_2 4473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_READ_DATA BIT_1 4483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_WRITE_DATA BIT_0 4493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t task; 4513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_SIMPLE 0 4523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_HEAD_OF_QUEUE 1 4533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_ORDERED 2 4543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_ACA 4 4553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_UNTAGGED 5 4563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t crn; 4583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ 4603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t byte_count; /* Total byte count. */ 4613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; /* PortID of destination port. */ 4633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 4643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 4663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_0_len; /* Data segment 0 length. */ 4673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 4683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 469bad750028917a7b804623701d0674e46c6012c18Arun Easi#define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6) 470bad750028917a7b804623701d0674e46c6012c18Arun Easi * (T10-DIF) */ 471bad750028917a7b804623701d0674e46c6012c18Arun Easistruct cmd_type_crc_2 { 472bad750028917a7b804623701d0674e46c6012c18Arun Easi uint8_t entry_type; /* Entry type. */ 473bad750028917a7b804623701d0674e46c6012c18Arun Easi uint8_t entry_count; /* Entry count. */ 474bad750028917a7b804623701d0674e46c6012c18Arun Easi uint8_t sys_define; /* System defined. */ 475bad750028917a7b804623701d0674e46c6012c18Arun Easi uint8_t entry_status; /* Entry Status. */ 476bad750028917a7b804623701d0674e46c6012c18Arun Easi 477bad750028917a7b804623701d0674e46c6012c18Arun Easi uint32_t handle; /* System handle. */ 478bad750028917a7b804623701d0674e46c6012c18Arun Easi 479bad750028917a7b804623701d0674e46c6012c18Arun Easi uint16_t nport_handle; /* N_PORT handle. */ 480bad750028917a7b804623701d0674e46c6012c18Arun Easi uint16_t timeout; /* Command timeout. */ 481bad750028917a7b804623701d0674e46c6012c18Arun Easi 482bad750028917a7b804623701d0674e46c6012c18Arun Easi uint16_t dseg_count; /* Data segment count. */ 483bad750028917a7b804623701d0674e46c6012c18Arun Easi 484bad750028917a7b804623701d0674e46c6012c18Arun Easi uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */ 485bad750028917a7b804623701d0674e46c6012c18Arun Easi 486bad750028917a7b804623701d0674e46c6012c18Arun Easi struct scsi_lun lun; /* FCP LUN (BE). */ 487bad750028917a7b804623701d0674e46c6012c18Arun Easi 488bad750028917a7b804623701d0674e46c6012c18Arun Easi uint16_t control_flags; /* Control flags. */ 489bad750028917a7b804623701d0674e46c6012c18Arun Easi 490bad750028917a7b804623701d0674e46c6012c18Arun Easi uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 491bad750028917a7b804623701d0674e46c6012c18Arun Easi uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 492bad750028917a7b804623701d0674e46c6012c18Arun Easi 493bad750028917a7b804623701d0674e46c6012c18Arun Easi uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 494bad750028917a7b804623701d0674e46c6012c18Arun Easi 495bad750028917a7b804623701d0674e46c6012c18Arun Easi uint32_t byte_count; /* Total byte count. */ 496bad750028917a7b804623701d0674e46c6012c18Arun Easi 497bad750028917a7b804623701d0674e46c6012c18Arun Easi uint8_t port_id[3]; /* PortID of destination port. */ 498bad750028917a7b804623701d0674e46c6012c18Arun Easi uint8_t vp_index; 499bad750028917a7b804623701d0674e46c6012c18Arun Easi 500bad750028917a7b804623701d0674e46c6012c18Arun Easi uint32_t crc_context_address[2]; /* Data segment address. */ 501bad750028917a7b804623701d0674e46c6012c18Arun Easi uint16_t crc_context_len; /* Data segment length. */ 502bad750028917a7b804623701d0674e46c6012c18Arun Easi uint16_t reserved_1; /* MUST be set to 0. */ 503bad750028917a7b804623701d0674e46c6012c18Arun Easi}; 504bad750028917a7b804623701d0674e46c6012c18Arun Easi 505bad750028917a7b804623701d0674e46c6012c18Arun Easi 5063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 5073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - status entry structure definition. 5083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 5093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define STATUS_TYPE 0x03 /* Status entry. */ 5103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct sts_entry_24xx { 5113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 5123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 5133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 5143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 5153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 5173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t comp_status; /* Completion status. */ 5193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t ox_id; /* OX_ID used by the firmware. */ 5203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 521ed17c71b5d11327efd40666fd621486f964fae4fRavi Anand uint32_t residual_len; /* FW calc residual transfer length. */ 5223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 5243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t state_flags; /* State flags. */ 5253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define SF_TRANSFERRED_DATA BIT_11 5263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define SF_FCP_RSP_DMA BIT_0 5273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_2; 5293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t scsi_status; /* SCSI status. */ 5303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define SS_CONFIRMATION_REQ BIT_12 5313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rsp_residual_count; /* FCP RSP residual count. */ 5333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t sense_len; /* FCP SENSE length. */ 5353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rsp_data_len; /* FCP response data length. */ 5363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t data[28]; /* FCP response/sense information. */ 537bad750028917a7b804623701d0674e46c6012c18Arun Easi /* 538bad750028917a7b804623701d0674e46c6012c18Arun Easi * If DIF Error is set in comp_status, these additional fields are 539bad750028917a7b804623701d0674e46c6012c18Arun Easi * defined: 5408cb2049c744809193ed3707a37c09676a24599eeArun Easi * 5418cb2049c744809193ed3707a37c09676a24599eeArun Easi * !!! NOTE: Firmware sends expected/actual DIF data in big endian 5428cb2049c744809193ed3707a37c09676a24599eeArun Easi * format; but all of the "data" field gets swab32-d in the beginning 5438cb2049c744809193ed3707a37c09676a24599eeArun Easi * of qla2x00_status_entry(). 5448cb2049c744809193ed3707a37c09676a24599eeArun Easi * 545bad750028917a7b804623701d0674e46c6012c18Arun Easi * &data[10] : uint8_t report_runt_bg[2]; - computed guard 54625985edcedea6396277003854657b5f3cb31a628Lucas De Marchi * &data[12] : uint8_t actual_dif[8]; - DIF Data received 547bad750028917a7b804623701d0674e46c6012c18Arun Easi * &data[20] : uint8_t expected_dif[8]; - DIF Data computed 548bad750028917a7b804623701d0674e46c6012c18Arun Easi */ 5493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 5503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 551bad750028917a7b804623701d0674e46c6012c18Arun Easi 5523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 5533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * Status entry completion status 5543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 5553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */ 5563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */ 5573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */ 5583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */ 5593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */ 5603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 5623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - marker entry structure definition. 5633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 5643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MARKER_TYPE 0x04 /* Marker entry. */ 5653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct mrk_entry_24xx { 5663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 5673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 5683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t handle_count; /* Handle count. */ 5693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 5703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 5723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 5743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t modifier; /* Modifier (7-0). */ 5763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 5773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MK_SYNC_ID 1 /* Synchronize ID */ 5783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 5793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_1; 5803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_2; 5823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 5833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_3; 5853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t lun[8]; /* FCP LUN (BE). */ 5873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_4[40]; 5883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 5893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 5913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - CT Pass-Through entry structure definition. 5923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 5933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */ 5943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct ct_entry_24xx { 5953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 5963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 5973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System Defined. */ 5983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 5993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 6013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t comp_status; /* Completion status. */ 6033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 6053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t cmd_dsd_count; 6073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 6093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_1; 6103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t timeout; /* Command timeout. */ 6123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_2; 6133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t rsp_dsd_count; 6153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_3[10]; 6173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rsp_byte_count; 6193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t cmd_byte_count; 6203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 6223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_0_len; /* Data segment 0 length. */ 6233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 6243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_1_len; /* Data segment 1 length. */ 6253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 6263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 6283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - ELS Pass-Through entry structure definition. 6293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 6303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */ 6313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct els_entry_24xx { 6323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 6333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 6343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System Defined. */ 6353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 6363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 6383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 6403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 6423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t tx_dsd_count; 6443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 6463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sof_type; 6473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EST_SOFI3 (1 << 4) 6483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EST_SOFI2 (3 << 4) 6493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 650c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez uint32_t rx_xchg_address; /* Receive exchange address. */ 6513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t rx_dsd_count; 6523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t opcode; 6543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_2; 6553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; 6573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_3; 6583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_4; 6603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t control_flags; /* Control flags. */ 6623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13) 6633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EPD_ELS_COMMAND (0 << 13) 6643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EPD_ELS_ACC (1 << 13) 6653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EPD_ELS_RJT (2 << 13) 6663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EPD_RX_XCHG (3 << 13) 6673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ECF_CLR_PASSTHRU_PEND BIT_12 6683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ECF_INCL_FRAME_HDR BIT_11 6693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rx_byte_count; 6713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t tx_byte_count; 6723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t tx_address[2]; /* Data segment 0 address. */ 6743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t tx_len; /* Data segment 0 length. */ 6753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rx_address[2]; /* Data segment 1 address. */ 6763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rx_len; /* Data segment 1 length. */ 6773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 6783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6799a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavalistruct els_sts_entry_24xx { 6809a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint8_t entry_type; /* Entry type. */ 6819a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint8_t entry_count; /* Entry count. */ 6829a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint8_t sys_define; /* System Defined. */ 6839a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint8_t entry_status; /* Entry Status. */ 6849a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali 6859a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint32_t handle; /* System handle. */ 6869a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali 6879a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint16_t comp_status; 6889a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali 6899a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint16_t nport_handle; /* N_PORT handle. */ 6909a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali 6919a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint16_t reserved_1; 6929a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali 6939a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint8_t vp_index; 6949a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint8_t sof_type; 6959a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali 6969a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint32_t rx_xchg_address; /* Receive exchange address. */ 6979a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint16_t reserved_2; 6989a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali 6999a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint8_t opcode; 7009a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint8_t reserved_3; 7019a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali 7029a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint8_t port_id[3]; 7039a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint8_t reserved_4; 7049a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali 7059a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint16_t reserved_5; 7069a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali 7079a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint16_t control_flags; /* Control flags. */ 7089a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint32_t total_byte_count; 7099a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint32_t error_subcode_1; 7109a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali uint32_t error_subcode_2; 7119a069e196767d7b87184fd8d8211d22bb5b9c0b8Giridhar Malavali}; 7123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 7133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - Mailbox Command entry structure definition. 7143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 7153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MBX_IOCB_TYPE 0x39 7163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct mbx_entry_24xx { 7173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 7183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 7193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t handle_count; /* Handle count. */ 7203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 7213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 7233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mbx[28]; 7253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 7263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */ 7293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct logio_entry_24xx { 7303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 7313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 7323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 7333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 7343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 7363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t comp_status; /* Completion status. */ 7383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */ 7393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 7413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t control_flags; /* Control flags. */ 7433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Modifiers. */ 744c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez#define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ 7453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ 7463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ 7473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ 7483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */ 7493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */ 7503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */ 7513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */ 7523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */ 7533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */ 7543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Commands. */ 7553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */ 7563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_PRLI 0x01 /* PRLI. */ 7573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_PDISC 0x02 /* PDISC. */ 7583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_ADISC 0x03 /* ADISC. */ 7593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_LOGO 0x08 /* LOGO. */ 7603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_PRLO 0x09 /* PRLO. */ 7613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */ 7623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 7643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_1; 7653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; /* PortID of destination port. */ 7673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t rsp_size; /* Response size in 32bit words. */ 7693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t io_parameter[11]; /* General I/O parameters. */ 7713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOLINK 0x01 7723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOIOCB 0x02 7733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOXCB 0x03 7743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_CMD_FAILED 0x04 7753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOFABRIC 0x05 7763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_FW_NOT_READY 0x07 7773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOT_LOGGED_IN 0x09 7783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOPCB 0x0A 7793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_ELS_REJECT 0x18 7813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_CMD_PARAM_ERR 0x19 7823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_PORTID_USED 0x1A 7833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NPORT_USED 0x1B 7843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NONPORT 0x1C 7853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_LOGGED_IN 0x1D 7863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOFLOGI_ACC 0x1F 7873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 7883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_MGMT_IOCB_TYPE 0x14 7903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct tsk_mgmt_entry { 7913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 7923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 7933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t handle_count; /* Handle count. */ 7943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 7953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 7973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 7993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 8013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t delay; /* Activity delay in seconds. */ 8033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t timeout; /* Command timeout. */ 8053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 806523ec773b8ffb1c607bc3a54c9526558e3b1eab1Andrew Vasquez struct scsi_lun lun; /* FCP LUN (BE). */ 8073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t control_flags; /* Control Flags. */ 8093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_NOTMCMD_TO_TARGET BIT_31 8103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_LUN_RESET BIT_4 8113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_ABORT_TASK_SET BIT_3 8123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_CLEAR_TASK_SET BIT_2 8133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_TARGET_RESET BIT_1 8143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_CLEAR_ACA BIT_0 8153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_2[20]; 8173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; /* PortID of destination port. */ 8193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 8203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_3[12]; 8223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 8233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ABORT_IOCB_TYPE 0x33 8253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct abort_entry_24xx { 8263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 8273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 8283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t handle_count; /* Handle count. */ 8293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 8303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 8323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 8343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* or Completion status. */ 8353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t options; /* Options. */ 8373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ 8383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle_to_abort; /* System handle to abort. */ 8403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 84173208dfd7ab19f379d73e8a0fbf30f92c203e5e8Anirban Chakraborty uint16_t req_que_no; 84273208dfd7ab19f379d73e8a0fbf30f92c203e5e8Anirban Chakraborty uint8_t reserved_1[30]; 8433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; /* PortID of destination port. */ 8453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 8463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_2[12]; 8483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 8493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 8513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP I/O Register Set structure definitions. 8523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 8533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct device_reg_24xx { 8543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t flash_addr; /* Flash/NVRAM BIOS address. */ 8553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FARX_DATA_FLAG BIT_31 8563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FARX_ACCESS_FLASH_CONF 0x7FFD0000 8573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FARX_ACCESS_FLASH_DATA 0x7FF00000 8583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FARX_ACCESS_NVRAM_CONF 0x7FFF0000 8593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FARX_ACCESS_NVRAM_DATA 0x7FFE0000 8603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_NVRAM_FUNC0_ADDR 0x80 8623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_NVRAM_FUNC1_ADDR 0x180 8633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8646f6417905cf272337a9762e1f92a1fffa651fcd3Andrew Vasquez#define FA_NVRAM_VPD_SIZE 0x200 8653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_NVRAM_VPD0_ADDR 0x00 8663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_NVRAM_VPD1_ADDR 0x100 867b7cc176c9eb3aa6989ac099efd8bdd6d0eaa784aJoe Carnuccio 868b7cc176c9eb3aa6989ac099efd8bdd6d0eaa784aJoe Carnuccio#define FA_BOOT_CODE_ADDR 0x00000 8693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 8703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * RISC code begins at offset 512KB 8713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * within flash. Consisting of two 8723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * contiguous RISC code segments. 8733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 8743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_RISC_CODE_ADDR 0x20000 8753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_RISC_CODE_SEGMENTS 2 8763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 877c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FA_FLASH_DESCR_ADDR_24 0x11000 878c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FA_FLASH_LAYOUT_ADDR_24 0x11400 879272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez#define FA_NPIV_CONF0_ADDR_24 0x16000 880272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez#define FA_NPIV_CONF1_ADDR_24 0x17000 881c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez 882c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez#define FA_FW_AREA_ADDR 0x40000 883c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez#define FA_VPD_NVRAM_ADDR 0x48000 884c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez#define FA_FEATURE_ADDR 0x4C000 885c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez#define FA_FLASH_DESCR_ADDR 0x50000 886c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FA_FLASH_LAYOUT_ADDR 0x50400 887cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez#define FA_HW_EVENT0_ADDR 0x54000 888c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FA_HW_EVENT1_ADDR 0x54400 889cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez#define FA_HW_EVENT_SIZE 0x200 890cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez#define FA_HW_EVENT_ENTRY_SIZE 4 891272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez#define FA_NPIV_CONF0_ADDR 0x5C000 892272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez#define FA_NPIV_CONF1_ADDR 0x5D000 89309ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FA_FCP_PRIO0_ADDR 0x10000 89409ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FA_FCP_PRIO1_ADDR 0x12000 895272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez 896cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez/* 897cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez * Flash Error Log Event Codes. 898cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez */ 899cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez#define HW_EVENT_RESET_ERR 0xF00B 900cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez#define HW_EVENT_ISP_ERR 0xF020 901cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez#define HW_EVENT_PARITY_ERR 0xF022 902cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez#define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023 903cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez#define HW_EVENT_FLASH_FW_ERR 0xF024 904cb8dacbf1110d8bd39413f3116ff1720f757854eAndrew Vasquez 9053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t flash_data; /* Flash/NVRAM BIOS data. */ 9063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t ctrl_status; /* Control/Status. */ 9083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */ 9093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */ 9103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */ 9113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_FUNCTION BIT_15 /* Function number. */ 9123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* PCI-X Bus Mode. */ 9133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8) 9143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCI_33MHZ (0 << 8) 9153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M1_66MHZ (1 << 8) 9163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M1_100MHZ (2 << 8) 9173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M1_133MHZ (3 << 8) 9183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M2_66MHZ (5 << 8) 9193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M2_100MHZ (6 << 8) 9203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M2_133MHZ (7 << 8) 9213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCI_66MHZ (8 << 8) 9223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Max Write Burst byte count. */ 9233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4) 9243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MWB_512_BYTES (0 << 4) 9253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MWB_1024_BYTES (1 << 4) 9263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MWB_2048_BYTES (2 << 4) 9273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MWB_4096_BYTES (3 << 4) 9283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */ 9303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */ 9313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ 9323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t ictrl; /* Interrupt control. */ 9343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */ 9353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t istatus; /* Interrupt status. */ 9373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ISRX_RISC_INT BIT_3 /* RISC interrupt. */ 9383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t unused_1[2]; /* Gap. */ 9403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Request Queue. */ 9423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t req_q_in; /* In-Pointer. */ 9433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t req_q_out; /* Out-Pointer. */ 9443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Response Queue. */ 9453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rsp_q_in; /* In-Pointer. */ 9463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rsp_q_out; /* Out-Pointer. */ 9473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Priority Request Queue. */ 9483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t preq_q_in; /* In-Pointer. */ 9493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t preq_q_out; /* Out-Pointer. */ 9503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t unused_2[2]; /* Gap. */ 9523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* ATIO Queue. */ 9543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t atio_q_in; /* In-Pointer. */ 9553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t atio_q_out; /* Out-Pointer. */ 9563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t host_status; 9583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ 9593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ 9603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t hccr; /* Host command & control register. */ 9623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* HCCR statuses. */ 9633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ 9643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 9653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* HCCR commands. */ 9663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* NOOP. */ 9673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_NOOP 0x00000000 9683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Set RISC Reset. */ 9693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_SET_RISC_RESET 0x10000000 9703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Clear RISC Reset. */ 9713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_CLR_RISC_RESET 0x20000000 9723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Set RISC Pause. */ 9733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_SET_RISC_PAUSE 0x30000000 9743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Releases RISC Pause. */ 9753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_REL_RISC_PAUSE 0x40000000 9763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Set HOST to RISC interrupt. */ 9773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_SET_HOST_INT 0x50000000 9783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Clear HOST to RISC interrupt. */ 9793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_CLR_HOST_INT 0x60000000 9803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Clear RISC to PCI interrupt. */ 9813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_CLR_RISC_INT 0xA0000000 9823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t gpiod; /* GPIO Data register. */ 984c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez 9853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* LED update mask. */ 9863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) 9873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Data update mask. */ 9883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) 989c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez /* Data update mask. */ 990c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez#define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 9913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* LED control mask. */ 9923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) 9933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* LED bit values. Color names as 9943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * referenced in fw spec. 9953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 9963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_LED_YELLOW_ON BIT_2 9973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_LED_GREEN_ON BIT_3 9983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_LED_AMBER_ON BIT_4 9993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Data in/out. */ 10003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_DATA_INOUT (BIT_1|BIT_0) 10013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t gpioe; /* GPIO Enable register. */ 10033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Enable update mask. */ 10043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) 1005c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez /* Enable update mask. */ 1006c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez#define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 10073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Enable. */ 10083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPEX_ENABLE (BIT_1|BIT_0) 10093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t iobase_addr; /* I/O Bus Base Address register. */ 10113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t unused_3[10]; /* Gap. */ 10133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox0; 10153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox1; 10163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox2; 10173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox3; 10183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox4; 10193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox5; 10203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox6; 10213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox7; 10223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox8; 10233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox9; 10243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox10; 10253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox11; 10263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox12; 10273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox13; 10283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox14; 10293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox15; 10303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox16; 10313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox17; 10323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox18; 10333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox19; 10343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox20; 10353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox21; 10363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox22; 10373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox23; 10383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox24; 10393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox25; 10403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox26; 10413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox27; 10423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox28; 10433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox29; 10443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox30; 10453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox31; 1046c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez 1047c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez uint32_t iobase_window; 1048b58369273956775c3e8b7bbbe152593d52762099Andrew Vasquez uint32_t iobase_c4; 104905236a050f8e3a20962bad98ad8ceb94bbdb748cAndrew Vasquez uint32_t iobase_c8; 105005236a050f8e3a20962bad98ad8ceb94bbdb748cAndrew Vasquez uint32_t unused_4_1[6]; /* Gap. */ 1051c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez uint32_t iobase_q; 1052c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez uint32_t unused_5[2]; /* Gap. */ 1053c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez uint32_t iobase_select; 1054c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez uint32_t unused_6[2]; /* Gap. */ 1055c3a2f0dfe1cecac76950f340f540c1a887dd2500Andrew Vasquez uint32_t iobase_sdata; 10563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 10573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 105800b6bd25166e2a4bad23c614c10c55993bb2489eAndrew Vasquez/* Trace Control *************************************************************/ 105900b6bd25166e2a4bad23c614c10c55993bb2489eAndrew Vasquez 106000b6bd25166e2a4bad23c614c10c55993bb2489eAndrew Vasquez#define TC_AEN_DISABLE 0 106100b6bd25166e2a4bad23c614c10c55993bb2489eAndrew Vasquez 106200b6bd25166e2a4bad23c614c10c55993bb2489eAndrew Vasquez#define TC_EFT_ENABLE 4 106300b6bd25166e2a4bad23c614c10c55993bb2489eAndrew Vasquez#define TC_EFT_DISABLE 5 106400b6bd25166e2a4bad23c614c10c55993bb2489eAndrew Vasquez 1065df613b96077cee826b14089ae6e75eeabf71faa3Andrew Vasquez#define TC_FCE_ENABLE 8 1066df613b96077cee826b14089ae6e75eeabf71faa3Andrew Vasquez#define TC_FCE_OPTIONS 0 1067df613b96077cee826b14089ae6e75eeabf71faa3Andrew Vasquez#define TC_FCE_DEFAULT_RX_SIZE 2112 1068df613b96077cee826b14089ae6e75eeabf71faa3Andrew Vasquez#define TC_FCE_DEFAULT_TX_SIZE 2112 1069df613b96077cee826b14089ae6e75eeabf71faa3Andrew Vasquez#define TC_FCE_DISABLE 9 1070df613b96077cee826b14089ae6e75eeabf71faa3Andrew Vasquez#define TC_FCE_DISABLE_TRACE BIT_0 1071df613b96077cee826b14089ae6e75eeabf71faa3Andrew Vasquez 10723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* MID Support ***************************************************************/ 10733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1074eb66dc60be5a72bc940458a5adfd400e4d810d49Andrew Vasquez#define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */ 1075eb66dc60be5a72bc940458a5adfd400e4d810d49Andrew Vasquez#define MAX_MULTI_ID_FABRIC 256 /* ... */ 1076eb66dc60be5a72bc940458a5adfd400e4d810d49Andrew Vasquez 1077eb66dc60be5a72bc940458a5adfd400e4d810d49Andrew Vasquez#define for_each_mapped_vp_idx(_ha, _idx) \ 1078eb66dc60be5a72bc940458a5adfd400e4d810d49Andrew Vasquez for (_idx = find_next_bit((_ha)->vp_idx_map, \ 1079eb66dc60be5a72bc940458a5adfd400e4d810d49Andrew Vasquez (_ha)->max_npiv_vports + 1, 1); \ 1080eb66dc60be5a72bc940458a5adfd400e4d810d49Andrew Vasquez _idx <= (_ha)->max_npiv_vports; \ 1081eb66dc60be5a72bc940458a5adfd400e4d810d49Andrew Vasquez _idx = find_next_bit((_ha)->vp_idx_map, \ 1082eb66dc60be5a72bc940458a5adfd400e4d810d49Andrew Vasquez (_ha)->max_npiv_vports + 1, _idx + 1)) \ 10833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct mid_conf_entry_24xx { 10853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 10863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 10883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Enable Hard Loop Id 10893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Acquire Loop ID in LIPA 10903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = ID not Acquired 10913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Enable VP 10923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = Enable Initiator Mode 10933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 5 = Disable Target Mode 10943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6-7 = Reserved 10953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 10963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t options; 10973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t hard_address; 10993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name[WWN_SIZE]; 11013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name[WWN_SIZE]; 11023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 11033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct mid_init_cb_24xx { 11053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez struct init_cb_24xx init_cb; 11063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t count; 11083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t options; 11093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1110eb66dc60be5a72bc940458a5adfd400e4d810d49Andrew Vasquez struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 11113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 11123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct mid_db_entry_24xx { 11153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t status; 11163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MDBS_NON_PARTIC BIT_3 11173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MDBS_ID_ACQUIRED BIT_1 11183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MDBS_ENABLED BIT_0 11193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t options; 11213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t hard_address; 11223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name[WWN_SIZE]; 11243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name[WWN_SIZE]; 11253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; 11273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_1; 11283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 11293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11302c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju/* 11312c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju * Virtual Port Control IOCB 11322c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju */ 11333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */ 11343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct vp_ctrl_entry_24xx { 11353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 11363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 11373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 11383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 11393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 11413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t vp_idx_failed; 11433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t comp_status; /* Completion status. */ 11452c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju#define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */ 11463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */ 11473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */ 11483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t command; 11503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */ 11513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */ 11523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */ 11533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */ 11542c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju#define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */ 11553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t vp_count; 11573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_idx_map[16]; 11592c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t flags; 1160c6852c4c5984fff130a859792d4b26d30c85c54bSeokmann Ju uint16_t id; 11612c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t reserved_4; 1162c6852c4c5984fff130a859792d4b26d30c85c54bSeokmann Ju uint16_t hopct; 1163c6852c4c5984fff130a859792d4b26d30c85c54bSeokmann Ju uint8_t reserved_5[24]; 11643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 11653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11662c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju/* 11672c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju * Modify Virtual Port Configuration IOCB 11682c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju */ 11693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */ 11703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct vp_config_entry_24xx { 11713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 11723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 11732c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint8_t handle_count; 11743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 11753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 11773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11782c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t flags; 11792c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju#define CS_VF_BIND_VPORTS_TO_VF BIT_0 11802c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju#define CS_VF_SET_QOS_OF_VPORTS BIT_1 11812c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju#define CS_VF_SET_HOPS_OF_VPORTS BIT_2 11823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t comp_status; /* Completion status. */ 11843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */ 11853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */ 11863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCT_ERROR 0x03 /* Unknown error. */ 11873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */ 11883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */ 11893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t command; 11912c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju#define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */ 11922c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju#define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */ 11933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_count; 11953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11962c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint8_t vp_index1; 11972c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint8_t vp_index2; 11983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 11993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t options_idx1; 12003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t hard_address_idx1; 12012c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t reserved_vp1; 12023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name_idx1[WWN_SIZE]; 12033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name_idx1[WWN_SIZE]; 12043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 12053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t options_idx2; 12063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t hard_address_idx2; 12072c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t reserved_vp2; 12083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name_idx2[WWN_SIZE]; 12093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name_idx2[WWN_SIZE]; 1210c6852c4c5984fff130a859792d4b26d30c85c54bSeokmann Ju uint16_t id; 12112c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t reserved_4; 1212c6852c4c5984fff130a859792d4b26d30c85c54bSeokmann Ju uint16_t hopct; 1213f9e899ebe502e547fca37f64ebc4b1399880d8f7Shyam Sundar uint8_t reserved_5[2]; 12143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 12153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 12163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */ 12173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct vp_rpt_id_entry_24xx { 12183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 12193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 12203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 12213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 12223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 12233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 12243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 12253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */ 12263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Format 1 -- | VP count |. */ 12273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t vp_idx; /* Format 0 -- Reserved. */ 12283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Format 1 -- VP status and index. */ 12293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 12303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; 12313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t format; 12323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 12333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_idx_map[16]; 12343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 12353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_4[32]; 12363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 12373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 12382c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju#define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */ 12392c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Justruct vf_evfp_entry_24xx { 12402c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint8_t entry_type; /* Entry type. */ 12412c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint8_t entry_count; /* Entry count. */ 12422c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint8_t sys_define; /* System defined. */ 12432c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint8_t entry_status; /* Entry Status. */ 12442c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju 12452c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint32_t handle; /* System handle. */ 12462c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t comp_status; /* Completion status. */ 12472c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t timeout; /* timeout */ 12482c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t adim_tagging_mode; 12492c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju 12502c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t vfport_id; 12512c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint32_t exch_addr; 12522c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju 12532c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t nport_handle; /* N_PORT handle. */ 12542c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint16_t control_flags; 12552c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint32_t io_parameter_0; 12562c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint32_t io_parameter_1; 12572c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint32_t tx_address[2]; /* Data segment 0 address. */ 12582c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint32_t tx_len; /* Data segment 0 length. */ 12592c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint32_t rx_address[2]; /* Data segment 1 address. */ 12602c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju uint32_t rx_len; /* Data segment 1 length. */ 12612c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju}; 12622c3dfe3f6ad8daff5acdb01713e4f2b116e78136Seokmann Ju 12633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* END MID Support ***********************************************************/ 12647d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez 12657d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez/* Flash Description Table ***************************************************/ 12667d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez 12677d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquezstruct qla_fdt_layout { 12687d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t sig[4]; 12697d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint16_t version; 12707d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint16_t len; 12717d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint16_t checksum; 12727d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t unused1[2]; 12737d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t model[16]; 12747d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint16_t man_id; 12757d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint16_t id; 12767d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t flags; 12777d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t erase_cmd; 12787d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t alt_erase_cmd; 12797d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t wrt_enable_cmd; 12807d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t wrt_enable_bits; 12817d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t wrt_sts_reg_cmd; 12827d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t unprotect_sec_cmd; 12837d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t read_man_id_cmd; 12847d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint32_t block_size; 12857d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint32_t alt_block_size; 12867d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint32_t flash_size; 12877d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint32_t wrt_enable_data; 12887d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t read_id_addr_len; 12897d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t wrt_disable_bits; 12907d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t read_dev_id_len; 12917d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t chip_erase_cmd; 12927d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint16_t read_timeout; 12937d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t protect_sec_cmd; 12947d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez uint8_t unused2[65]; 12957d232c745ef2ce141cc9d9538421affa32846fdbAndrew Vasquez}; 12964d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 1297c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez/* Flash Layout Table ********************************************************/ 1298c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez 1299c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquezstruct qla_flt_location { 1300c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez uint8_t sig[4]; 13013a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t start_lo; 13023a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t start_hi; 13033a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t version; 13043a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t unused[5]; 1305c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez uint16_t checksum; 1306c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez}; 1307c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez 1308c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquezstruct qla_flt_header { 1309c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez uint16_t version; 1310c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez uint16_t length; 1311c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez uint16_t checksum; 1312c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez uint16_t unused; 1313c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez}; 1314c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez 1315c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FLT_REG_FW 0x01 1316c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FLT_REG_BOOT_CODE 0x07 1317c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FLT_REG_VPD_0 0x14 1318c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FLT_REG_NVRAM_0 0x15 1319c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FLT_REG_VPD_1 0x16 1320c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FLT_REG_NVRAM_1 0x17 1321c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FLT_REG_FDT 0x1a 1322c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FLT_REG_FLT 0x1c 1323c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FLT_REG_HW_EVENT_0 0x1d 1324c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez#define FLT_REG_HW_EVENT_1 0x1f 1325272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez#define FLT_REG_NPIV_CONF_0 0x29 1326272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez#define FLT_REG_NPIV_CONF_1 0x2a 1327cbc8eb67da11a4972834f61fe4729f4c037a17c9Andrew Vasquez#define FLT_REG_GOLD_FW 0x2f 132809ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FLT_REG_FCP_PRIO_0 0x87 132909ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FLT_REG_FCP_PRIO_1 0x88 13306246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali#define FLT_REG_FCOE_FW 0xA4 13316246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali#define FLT_REG_FCOE_VPD_0 0xA9 13326246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali#define FLT_REG_FCOE_NVRAM_0 0xAA 13336246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali#define FLT_REG_FCOE_VPD_1 0xAB 13346246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali#define FLT_REG_FCOE_NVRAM_1 0xAC 1335c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez 1336c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquezstruct qla_flt_region { 1337c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez uint32_t code; 1338c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez uint32_t size; 1339c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez uint32_t start; 1340c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez uint32_t end; 1341c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez}; 1342c00d8994d91e51aa6b891ad0e877f66cc1011de2Andrew Vasquez 1343272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez/* Flash NPIV Configuration Table ********************************************/ 1344272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez 1345272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquezstruct qla_npiv_header { 1346272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez uint8_t sig[2]; 1347272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez uint16_t version; 1348272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez uint16_t entries; 1349272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez uint16_t unused[4]; 1350272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez uint16_t checksum; 1351272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez}; 1352272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez 1353272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquezstruct qla_npiv_entry { 1354272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez uint16_t flags; 1355272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez uint16_t vf_id; 135673208dfd7ab19f379d73e8a0fbf30f92c203e5e8Anirban Chakraborty uint8_t q_qos; 135773208dfd7ab19f379d73e8a0fbf30f92c203e5e8Anirban Chakraborty uint8_t f_qos; 1358272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez uint16_t unused1; 1359272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez uint8_t port_name[WWN_SIZE]; 1360272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez uint8_t node_name[WWN_SIZE]; 1361272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez}; 1362272976ca186982f7bbc4f22876c53d6c9f7b6e32Andrew Vasquez 13634d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam/* 84XX Support **************************************************************/ 13644d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 13654d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */ 13664d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define A84_PANIC_RECOVERY 0x1 13674d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define A84_OP_LOGIN_COMPLETE 0x2 13684d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define A84_DIAG_LOGIN_COMPLETE 0x3 13694d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define A84_GOLD_LOGIN_COMPLETE 0x4 13704d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 13714d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define MBC_ISP84XX_RESET 0x3a /* Reset. */ 13724d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 13734d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define FSTATE_REMOTE_FC_DOWN BIT_0 13744d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define FSTATE_NSL_LINK_DOWN BIT_1 13754d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define FSTATE_IS_DIAG_FW BIT_2 13764d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define FSTATE_LOGGED_IN BIT_3 13774d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define FSTATE_WAITING_FOR_VERIFY BIT_4 13784d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 13794d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define VERIFY_CHIP_IOCB_TYPE 0x1B 13804d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayamstruct verify_chip_entry_84xx { 13814d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_type; 13824d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_count; 13834d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t sys_defined; 13844d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_status; 13854d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 13864d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t handle; 13874d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 13884d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t options; 13894d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define VCO_DONT_UPDATE_FW BIT_0 13904d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define VCO_FORCE_UPDATE BIT_1 13914d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define VCO_DONT_RESET_UPDATE BIT_2 13924d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define VCO_DIAG_FW BIT_3 13934d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define VCO_END_OF_DATA BIT_14 13944d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define VCO_ENABLE_DSD BIT_15 13954d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 13964d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t reserved_1; 13974d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 13984d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t data_seg_cnt; 13994d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t reserved_2[3]; 14004d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14014d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t fw_ver; 14024d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t exchange_address; 14034d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14044d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t reserved_3[3]; 14054d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t fw_size; 14064d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t fw_seq_size; 14074d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t relative_offset; 14084d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14094d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t dseg_address[2]; 14104d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t dseg_length; 14114d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam}; 14124d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14134d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayamstruct verify_chip_rsp_84xx { 14144d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_type; 14154d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_count; 14164d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t sys_defined; 14174d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_status; 14184d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14194d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t handle; 14204d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14214d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t comp_status; 14224d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define CS_VCS_CHIP_FAILURE 0x3 14234d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define CS_VCS_BAD_EXCHANGE 0x8 14244d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define CS_VCS_SEQ_COMPLETEi 0x40 14254d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14264d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t failure_code; 14274d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define VFC_CHECKSUM_ERROR 0x1 14284d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define VFC_INVALID_LEN 0x2 14294d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define VFC_ALREADY_IN_PROGRESS 0x8 14304d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14314d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t reserved_1[4]; 14324d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14334d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t fw_ver; 14344d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t exchange_address; 14354d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14364d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t reserved_2[6]; 14374d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam}; 14384d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14394d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define ACCESS_CHIP_IOCB_TYPE 0x2B 14404d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayamstruct access_chip_84xx { 14414d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_type; 14424d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_count; 14434d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t sys_defined; 14444d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_status; 14454d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14464d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t handle; 14474d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14484d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t options; 14494d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define ACO_DUMP_MEMORY 0x0 14504d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define ACO_LOAD_MEMORY 0x1 14514d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define ACO_CHANGE_CONFIG_PARAM 0x2 14524d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam#define ACO_REQUEST_INFO 0x3 14534d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14544d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t reserved1; 14554d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14564d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t dseg_count; 14574d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t reserved2[3]; 14584d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14594d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t parameter1; 14604d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t parameter2; 14614d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t parameter3; 14624d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14634d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t reserved3[3]; 14644d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t total_byte_cnt; 14654d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t reserved4; 14664d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14674d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t dseg_address[2]; 14684d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t dseg_length; 14694d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam}; 14704d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14714d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayamstruct access_chip_rsp_84xx { 14724d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_type; 14734d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_count; 14744d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t sys_defined; 14754d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint8_t entry_status; 14764d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14774d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t handle; 14784d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14794d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t comp_status; 14804d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint16_t failure_code; 14814d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t residual_count; 14824d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam 14834d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam uint32_t reserved[12]; 14844d4df1932b6b116aecc81039066fec27f2050762Harihara Kadayam}; 14853a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 14863a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez/* 81XX Support **************************************************************/ 14873a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 14883a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define MBA_DCBX_START 0x8016 14893a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define MBA_DCBX_COMPLETE 0x8030 14903a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define MBA_FCF_CONF_ERR 0x8031 14913a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define MBA_DCBX_PARAM_UPDATE 0x8032 14923a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define MBA_IDC_COMPLETE 0x8100 14933a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define MBA_IDC_NOTIFY 0x8101 14943a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define MBA_IDC_TIME_EXT 0x8102 14953a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 14968a659571eccfde1df9bd057d67be51d1aaa0e2dbAndrew Vasquez#define MBC_IDC_ACK 0x101 14976e181be508cf81fda4407b4689befeb7e4149607Lalit Chandivade#define MBC_RESTART_MPI_FW 0x3d 14981d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio#define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */ 1499ce0423f4a23317d0166addd7d6fcc4a0fa95e751Andrew Vasquez#define MBC_GET_XGMAC_STATS 0x7a 150011bbc1d896637c1d83b11cc3b97ed3d6d2076c63Andrew Vasquez#define MBC_GET_DCBX_PARAMS 0x51 15011d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio 15026246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali/* 15036246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali * ISP83xx mailbox commands 15046246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali */ 15056246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali#define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */ 15066246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali 15071d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio/* Flash access control option field bit definitions */ 15081d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio#define FAC_OPT_FORCE_SEMAPHORE BIT_15 15091d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio#define FAC_OPT_REQUESTOR_ID BIT_14 15101d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio#define FAC_OPT_CMD_SUBCODE 0xff 15111d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio 15121d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio/* Flash access control command subcodes */ 15131d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio#define FAC_OPT_CMD_WRITE_PROTECT 0x00 15141d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio#define FAC_OPT_CMD_WRITE_ENABLE 0x01 15151d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio#define FAC_OPT_CMD_ERASE_SECTOR 0x02 15161d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio#define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03 15171d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio#define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04 15181d2874de809a14e6780246b99a18bbc0fc0a8f2aJoe Carnuccio#define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05 15198a659571eccfde1df9bd057d67be51d1aaa0e2dbAndrew Vasquez 15203a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquezstruct nvram_81xx { 15213a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* NVRAM header. */ 15223a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t id[4]; 15233a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t nvram_version; 15243a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_0; 15253a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 15263a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* Firmware Initialization Control Block. */ 15273a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t version; 15283a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_1; 15293a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t frame_payload_size; 15303a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t execution_throttle; 15313a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t exchange_count; 15323a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_2; 15333a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 15343a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t port_name[WWN_SIZE]; 15353a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t node_name[WWN_SIZE]; 15363a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 15373a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t login_retry_count; 15383a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_3; 15393a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t interrupt_delay_timer; 15403a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t login_timeout; 15413a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 15423a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t firmware_options_1; 15433a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t firmware_options_2; 15443a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t firmware_options_3; 15453a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 15463a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_4[4]; 15473a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 15483a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* Offset 64. */ 15493a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t enode_mac[6]; 15503a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_5[5]; 15513a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 15523a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* Offset 80. */ 15533a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_6[24]; 15543a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 15553a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* Offset 128. */ 1556b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint16_t ex_version; 1557b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint8_t prio_fcf_matching_flags; 1558b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint8_t reserved_6_1[3]; 1559b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint16_t pri_fcf_vlan_id; 1560b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint8_t pri_fcf_fabric_name[8]; 1561b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint16_t reserved_6_2[7]; 1562b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint8_t spma_mac_addr[6]; 1563b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint16_t reserved_6_3[14]; 1564b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez 1565b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez /* Offset 192. */ 1566b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint16_t reserved_7[32]; 15673a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 15683a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* 15693a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 0 = Enable spinup delay 15703a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 1 = Disable BIOS 15713a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 2 = Enable Memory Map BIOS 15723a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 3 = Enable Selectable Boot 15733a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 4 = Disable RISC code load 15743a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 5 = Disable Serdes 15753a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 6 = Opt boot mode 15763a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 7 = Interrupt enable 15773a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * 15783a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 8 = EV Control enable 15793a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 9 = Enable lip reset 15803a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 10 = Enable lip full login 15813a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 11 = Enable target reset 15823a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 12 = Stop firmware 15833a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 13 = Enable nodename option 15843a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 14 = Default WWPN valid 15853a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 15 = Enable alternate WWN 15863a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * 15873a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 16 = CLP LUN string 15883a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 17 = CLP Target string 15893a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 18 = CLP BIOS enable string 15903a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 19 = CLP Serdes string 15913a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 20 = CLP WWPN string 15923a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 21 = CLP WWNN string 15933a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 22 = 15943a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 23 = 15953a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 24 = Keep WWPN 15963a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 25 = Temp WWPN 15973a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 26-31 = 15983a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez */ 15993a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t host_p; 16003a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16013a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t alternate_port_name[WWN_SIZE]; 16023a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t alternate_node_name[WWN_SIZE]; 16033a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16043a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t boot_port_name[WWN_SIZE]; 16053a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t boot_lun_number; 16063a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_8; 16073a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16083a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t alt1_boot_port_name[WWN_SIZE]; 16093a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t alt1_boot_lun_number; 16103a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_9; 16113a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16123a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t alt2_boot_port_name[WWN_SIZE]; 16133a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t alt2_boot_lun_number; 16143a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_10; 16153a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16163a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t alt3_boot_port_name[WWN_SIZE]; 16173a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t alt3_boot_lun_number; 16183a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_11; 16193a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16203a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* 16213a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 0 = Selective Login 16223a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 1 = Alt-Boot Enable 16233a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 2 = Reserved 16243a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 3 = Boot Order List 16253a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 4 = Reserved 16263a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 5 = Selective LUN 16273a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 6 = Reserved 16283a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 7-31 = 16293a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez */ 16303a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t efi_parameters; 16313a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16323a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t reset_delay; 16333a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t reserved_12; 16343a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_13; 16353a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16363a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t boot_id_number; 16373a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_14; 16383a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16393a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t max_luns_per_target; 16403a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_15; 16413a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16423a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t port_down_retry_count; 16433a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t link_down_timeout; 16443a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16453a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* FCode parameters. */ 16463a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t fcode_parameter; 16473a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16483a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_16[3]; 16493a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16503a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* Offset 352. */ 16513a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t reserved_17[4]; 16523a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_18[5]; 16533a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t reserved_19[2]; 16543a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_20[8]; 16553a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16563a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* Offset 384. */ 16573a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t reserved_21[16]; 1658cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar uint16_t reserved_22[3]; 1659cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar 1660cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar /* 1661cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar * BIT 0 = Extended BB credits for LR 1662cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar * BIT 1 = Virtual Fabric Enable 1663cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar * BIT 2 = Enhanced Features Unused 1664cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar * BIT 3-7 = Enhanced Features Reserved 1665cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar */ 1666cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar /* Enhanced Features */ 1667cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar uint8_t enhanced_features; 1668cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar 1669cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar uint8_t reserved_23; 1670cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar uint16_t reserved_24[4]; 16713a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16723a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* Offset 416. */ 1673cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar uint16_t reserved_25[32]; 16743a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16753a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* Offset 480. */ 16763a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t model_name[16]; 16773a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16783a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* Offset 496. */ 16793a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t feature_mask_l; 16803a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t feature_mask_h; 1681cad454b12a23c24fd7f409402cf51434655e76c1Santosh Vernekar uint16_t reserved_26[2]; 16823a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16833a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t subsystem_vendor_id; 16843a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t subsystem_device_id; 16853a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16863a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t checksum; 16873a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez}; 16883a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16893a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez/* 16903a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * ISP Initialization Control Block. 16913a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * Little endian except where noted. 16923a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez */ 16933a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define ICB_VERSION 1 16943a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquezstruct init_cb_81xx { 16953a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t version; 16963a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_1; 16973a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 16983a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t frame_payload_size; 16993a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t execution_throttle; 17003a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t exchange_count; 17013a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17023a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_2; 17033a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17043a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t port_name[WWN_SIZE]; /* Big endian. */ 17053a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t node_name[WWN_SIZE]; /* Big endian. */ 17063a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17073a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t response_q_inpointer; 17083a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t request_q_outpointer; 17093a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17103a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t login_retry_count; 17113a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17123a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t prio_request_q_outpointer; 17133a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17143a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t response_q_length; 17153a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t request_q_length; 17163a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17173a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t reserved_3; 17183a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17193a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t prio_request_q_length; 17203a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17213a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t request_q_address[2]; 17223a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t response_q_address[2]; 17233a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t prio_request_q_address[2]; 17243a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17253a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t reserved_4[8]; 17263a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17273a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t atio_q_inpointer; 17283a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t atio_q_length; 17293a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t atio_q_address[2]; 17303a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17313a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t interrupt_delay_timer; /* 100us increments. */ 17323a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t login_timeout; 17333a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17343a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* 17353a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 0-3 = Reserved 17363a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 4 = Enable Target Mode 17373a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 5 = Disable Initiator Mode 17383a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 6 = Reserved 17393a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 7 = Reserved 17403a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * 17413a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 8-13 = Reserved 17423a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 14 = Node Name Option 17433a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 15-31 = Reserved 17443a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez */ 17453a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t firmware_options_1; 17463a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17473a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* 17483a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 0 = Operation Mode bit 0 17493a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 1 = Operation Mode bit 1 17503a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 2 = Operation Mode bit 2 17513a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 3 = Operation Mode bit 3 17523a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 4-7 = Reserved 17533a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * 17543a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 8 = Enable Class 2 17553a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 9 = Enable ACK0 17563a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 10 = Reserved 17573a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 11 = Enable FC-SP Security 17583a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 12 = FC Tape Enable 17593a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 13 = Reserved 17603a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 14 = Enable Target PRLI Control 17613a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 15-31 = Reserved 17623a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez */ 17633a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t firmware_options_2; 17643a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17653a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez /* 17663a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 0-3 = Reserved 17673a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 4 = FCP RSP Payload bit 0 17683a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 5 = FCP RSP Payload bit 1 17693a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 6 = Enable Receive Out-of-Order data frame handling 17703a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 7 = Reserved 17713a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * 17723a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 8 = Reserved 17733a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 17743a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 10-16 = Reserved 17753a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 17 = Enable multiple FCFs 17763a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 18-20 = MAC addressing mode 17773a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 21-25 = Ethernet data rate 17783a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 26 = Enable ethernet header rx IOCB for ATIO q 17793a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 27 = Enable ethernet header rx IOCB for response q 17803a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 28 = SPMA selection bit 0 17813a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 28 = SPMA selection bit 1 17823a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez * BIT 30-31 = Reserved 17833a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez */ 17843a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint32_t firmware_options_3; 17853a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17863a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t reserved_5[8]; 17873a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17883a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t enode_mac[6]; 17893a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17903a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint8_t reserved_6[10]; 17913a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez}; 17923a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17933a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquezstruct mid_init_cb_81xx { 17943a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez struct init_cb_81xx init_cb; 17953a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17963a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t count; 17973a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez uint16_t options; 17983a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 17993a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 18003a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez}; 18013a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 1802b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquezstruct ex_init_cb_81xx { 1803b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint16_t ex_version; 1804b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint8_t prio_fcf_matching_flags; 1805b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint8_t reserved_1[3]; 1806b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint16_t pri_fcf_vlan_id; 1807b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint8_t pri_fcf_fabric_name[8]; 1808b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint16_t reserved_2[7]; 1809b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint8_t spma_mac_addr[6]; 1810b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez uint16_t reserved_3[14]; 1811b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez}; 1812b64b0e8fd964ce637794d4aaa772db1ae4298ea9Andrew Vasquez 18133a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000 18143a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000 18153a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 181609ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke/* FCP priority config defines *************************************/ 181709ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke/* operations */ 181809ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define QLFC_FCP_PRIO_DISABLE 0x0 181909ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define QLFC_FCP_PRIO_ENABLE 0x1 182009ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define QLFC_FCP_PRIO_GET_CONFIG 0x2 182109ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define QLFC_FCP_PRIO_SET_CONFIG 0x3 182209ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke 182309ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radkestruct qla_fcp_prio_entry { 182409ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint16_t flags; /* Describes parameter(s) in FCP */ 182509ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke /* priority entry that are valid */ 182609ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_ENTRY_VALID 0x1 182709ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_ENTRY_TAG_VALID 0x2 182809ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_ENTRY_SPID_VALID 0x4 182909ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_ENTRY_DPID_VALID 0x8 183009ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_ENTRY_LUNB_VALID 0x10 183109ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_ENTRY_LUNE_VALID 0x20 183209ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_ENTRY_SWWN_VALID 0x40 183309ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_ENTRY_DWWN_VALID 0x80 183409ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint8_t tag; /* Priority value */ 183509ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint8_t reserved; /* Reserved for future use */ 183609ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint32_t src_pid; /* Src port id. high order byte */ 183709ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke /* unused; -1 (wild card) */ 183809ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint32_t dst_pid; /* Src port id. high order byte */ 183909ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke /* unused; -1 (wild card) */ 184009ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint16_t lun_beg; /* 1st lun num of lun range. */ 184109ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke /* -1 (wild card) */ 184209ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint16_t lun_end; /* 2nd lun num of lun range. */ 184309ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke /* -1 (wild card) */ 184409ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */ 184509ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */ 184609ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke}; 184709ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke 184809ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radkestruct qla_fcp_prio_cfg { 184909ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint8_t signature[4]; /* "HQOS" signature of config data */ 185009ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint16_t version; /* 1: Initial version */ 185109ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint16_t length; /* config data size in num bytes */ 185209ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint16_t checksum; /* config data bytes checksum */ 185309ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint16_t num_entries; /* Number of entries */ 185409ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint16_t size_of_entry; /* Size of each entry in num bytes */ 185509ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint8_t attributes; /* enable/disable, persistence */ 185609ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_ATTR_DISABLE 0x0 185709ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_ATTR_ENABLE 0x1 185809ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_ATTR_PERSIST 0x2 185909ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke uint8_t reserved; /* Reserved for future use */ 186009ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_CFG_HDR_SIZE 0x10 186109ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */ 186209ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_CFG_ENTRY_SIZE 0x20 186309ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke}; 186409ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke 186509ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/ 186609ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke 186709ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke/* 25XX Support ****************************************************/ 186809ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FA_FCP_PRIO0_ADDR_25 0x3C000 186909ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke#define FA_FCP_PRIO1_ADDR_25 0x3E000 187009ff701a177b116c6c15b6e501e58fbfb306b424Sarang Radke 18713a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez/* 81XX Flash locations -- occupies second 2MB region. */ 18723a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FA_BOOT_CODE_ADDR_81 0x80000 18733a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FA_RISC_CODE_ADDR_81 0xA0000 18743a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FA_FW_AREA_ADDR_81 0xC0000 18753a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FA_VPD_NVRAM_ADDR_81 0xD0000 18763d79038f92841052aced9aec43c9d9aa864d28abAndrew Vasquez#define FA_VPD0_ADDR_81 0xD0000 18773d79038f92841052aced9aec43c9d9aa864d28abAndrew Vasquez#define FA_VPD1_ADDR_81 0xD0400 18783d79038f92841052aced9aec43c9d9aa864d28abAndrew Vasquez#define FA_NVRAM0_ADDR_81 0xD0080 1879fc3ea9bcb86a1c5126807f747291563e08405944Harish Zunjarrao#define FA_NVRAM1_ADDR_81 0xD0180 18803a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FA_FEATURE_ADDR_81 0xD4000 18813a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FA_FLASH_DESCR_ADDR_81 0xD8000 18823a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FA_FLASH_LAYOUT_ADDR_81 0xD8400 18833a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FA_HW_EVENT0_ADDR_81 0xDC000 18843a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FA_HW_EVENT1_ADDR_81 0xDC400 18853a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FA_NPIV_CONF0_ADDR_81 0xD1000 18863a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez#define FA_NPIV_CONF1_ADDR_81 0xD2000 18873a03eb797ce76ae8868a1497e9e746ad0add1e3bAndrew Vasquez 18886246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali/* 83XX Flash locations -- occupies second 8MB region. */ 18896246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali#define FA_FLASH_LAYOUT_ADDR_83 0xFC400 18906246b8a1d26c7cdb77fd2f3f3578d4db025d5c9eGiridhar Malavali 18913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#endif 1892