qla_fw.h revision ed17c71b5d11327efd40666fd621486f964fae4f
1fa90c54f6d27664cc67691f9e52d9165e0c25ca7Andrew Vasquez/* 2fa90c54f6d27664cc67691f9e52d9165e0c25ca7Andrew Vasquez * QLogic Fibre Channel HBA Driver 3fa90c54f6d27664cc67691f9e52d9165e0c25ca7Andrew Vasquez * Copyright (c) 2003-2005 QLogic Corporation 4fa90c54f6d27664cc67691f9e52d9165e0c25ca7Andrew Vasquez * 5fa90c54f6d27664cc67691f9e52d9165e0c25ca7Andrew Vasquez * See LICENSE.qla2xxx for copyright and licensing details. 6fa90c54f6d27664cc67691f9e52d9165e0c25ca7Andrew Vasquez */ 73d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#ifndef __QLA_FW_H 83d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define __QLA_FW_H 93d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define RISC_SADDRESS 0x100000 113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MBS_CHECKSUM_ERROR 0x4010 123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * Firmware Options. 153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FO1_ENABLE_PUREX BIT_10 173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FO1_DISABLE_LED_CTRL BIT_6 183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FO2_ENABLE_SEL_CLASS2 BIT_5 193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FO3_NO_ABTS_ON_LINKDOWN BIT_14 203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * Port Database structure definition for ISP 24xx. 233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDO_FORCE_ADISC BIT_1 253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDO_FORCE_PLOGI BIT_0 263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PORT_DATABASE_24XX_SIZE 64 293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct port_database_24xx { 303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t flags; 313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_TASK_RETRY_ID BIT_14 323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_FC_TAPE BIT_7 333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_ACK0_CAPABLE BIT_6 343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_FCP2_CONF BIT_5 353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_CLASS_2 BIT_4 363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDF_HARD_ADDR BIT_1 373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t current_login_state; 393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t last_login_state; 403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PLOGI_PENDING 0x03 413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PLOGI_COMPLETE 0x04 423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PRLI_PENDING 0x05 433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PRLI_COMPLETE 0x06 443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PORT_UNAVAILABLE 0x07 453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PRLO_PENDING 0x09 463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_LOGO_PENDING 0x11 473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PDS_PRLI2_PENDING 0x12 483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t hard_address[3]; 503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_1; 513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; 533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sequence_id; 543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t port_timer; 563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t receive_data_size; 603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_2; 613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prli_svc_param_word_0[2]; /* Big endian */ 633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Bits 15-0 of word 0 */ 643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prli_svc_param_word_3[2]; /* Big endian */ 653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Bits 15-0 of word 3 */ 663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name[WWN_SIZE]; 683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name[WWN_SIZE]; 693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_3[24]; 713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct nvram_24xx { 743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* NVRAM header. */ 753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t id[4]; 763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nvram_version; 773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_0; 783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Firmware Initialization Control Block. */ 803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t version; 813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t frame_payload_size; 833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t execution_throttle; 843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t exchange_count; 853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t hard_address; 863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name[WWN_SIZE]; 883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name[WWN_SIZE]; 893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t login_retry_count; 913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t link_down_on_nos; 923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t interrupt_delay_timer; 933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t login_timeout; 943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_1; 963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_2; 973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_3; 983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 56. */ 1003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 1023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Control Enable 1033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1-15 = 1043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 1053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0-7 = Reserved 1063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8-10 = Output Swing 1G 1073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11-13 = Output Emphasis 1G 1083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14-15 = Reserved 1093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 1103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0-7 = Reserved 1113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8-10 = Output Swing 2G 1123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11-13 = Output Emphasis 2G 1133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14-15 = Reserved 1143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 1153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0-7 = Reserved 1163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8-10 = Output Swing 4G 1173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11-13 = Output Emphasis 4G 1183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14-15 = Reserved 1193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 1203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t seriallink_options[4]; 1213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_2[16]; 1233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 96. */ 1253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_3[16]; 1263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* PCIe table entries. */ 1283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_4[16]; 1293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 160. */ 1313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_5[16]; 1323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 192. */ 1343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_6[16]; 1353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 224. */ 1373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_7[16]; 1383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 1403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Enable spinup delay 1413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Disable BIOS 1423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = Enable Memory Map BIOS 1433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Enable Selectable Boot 1443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = Disable RISC code load 1453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 5 = 1463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6 = 1473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 7 = 1483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 1493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8 = 1503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 9 = 1513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 10 = Enable lip full login 1523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11 = Enable target reset 1533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 12 = 1543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 13 = 1553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14 = 1563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 15 = Enable alternate WWN 1573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 1583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 16-31 = 1593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 1603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t host_p; 1613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t alternate_port_name[WWN_SIZE]; 1633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t alternate_node_name[WWN_SIZE]; 1643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t boot_port_name[WWN_SIZE]; 1663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t boot_lun_number; 1673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_8; 1683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t alt1_boot_port_name[WWN_SIZE]; 1703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t alt1_boot_lun_number; 1713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_9; 1723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t alt2_boot_port_name[WWN_SIZE]; 1743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t alt2_boot_lun_number; 1753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_10; 1763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t alt3_boot_port_name[WWN_SIZE]; 1783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t alt3_boot_lun_number; 1793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_11; 1803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 1823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Selective Login 1833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Alt-Boot Enable 1843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = Reserved 1853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Boot Order List 1863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = Reserved 1873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 5 = Selective LUN 1883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6 = Reserved 1893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 7-31 = 1903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 1913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t efi_parameters; 1923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reset_delay; 1943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_12; 1953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_13; 1963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 1973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t boot_id_number; 1983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_14; 1993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t max_luns_per_target; 2013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_15; 2023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t port_down_retry_count; 2043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t link_down_timeout; 2053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* FCode parameters. */ 2073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t fcode_parameter; 2083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_16[3]; 2103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 352. */ 2123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_drv_ver_major; 2133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_drv_ver_submajob; 2143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_drv_ver_minor; 2153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_drv_ver_subminor; 2163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prev_bios_ver_major; 2183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prev_bios_ver_minor; 2193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prev_efi_ver_major; 2213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prev_efi_ver_minor; 2223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prev_fw_ver_major; 2243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_fw_ver_minor; 2253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t prev_fw_ver_subminor; 2263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_17[8]; 2283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 384. */ 2303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_18[16]; 2313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 416. */ 2333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_19[16]; 2343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 448. */ 2363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_20[16]; 2373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 480. */ 2393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t model_name[16]; 2403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_21[2]; 2423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Offset 500. */ 2443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* HW Parameter Block. */ 2453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t pcie_table_sig; 2463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t pcie_table_offset; 2473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t subsystem_vendor_id; 2493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t subsystem_device_id; 2503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t checksum; 2523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 2533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 2553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP Initialization Control Block. 2563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * Little endian except where noted. 2573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 2583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ICB_VERSION 1 2593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct init_cb_24xx { 2603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t version; 2613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 2623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t frame_payload_size; 2643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t execution_throttle; 2653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t exchange_count; 2663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t hard_address; 2683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name[WWN_SIZE]; /* Big endian. */ 2703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name[WWN_SIZE]; /* Big endian. */ 2713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t response_q_inpointer; 2733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t request_q_outpointer; 2743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t login_retry_count; 2763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prio_request_q_outpointer; 2783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t response_q_length; 2803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t request_q_length; 2813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t link_down_timeout; /* Milliseconds. */ 2833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t prio_request_q_length; 2853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t request_q_address[2]; 2873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t response_q_address[2]; 2883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t prio_request_q_address[2]; 2893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_2[8]; 2913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t atio_q_inpointer; 2933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t atio_q_length; 2943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t atio_q_address[2]; 2953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t interrupt_delay_timer; /* 100us increments. */ 2973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t login_timeout; 2983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 2993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 3003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Enable Hard Loop Id 3013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Enable Fairness 3023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = Enable Full-Duplex 3033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Reserved 3043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = Enable Target Mode 3053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 5 = Disable Initiator Mode 3063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6 = Reserved 3073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 7 = Reserved 3083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 3093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8 = Reserved 3103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 9 = Non Participating LIP 3113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 10 = Descending Loop ID Search 3123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11 = Acquire Loop ID in LIPA 3133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 12 = Reserved 3143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 13 = Full Login after LIP 3153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14 = Node Name Option 3163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 15-31 = Reserved 3173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 3183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_1; 3193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 3213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Operation Mode bit 0 3223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Operation Mode bit 1 3233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = Operation Mode bit 2 3243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Operation Mode bit 3 3253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = Connection Options bit 0 3263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 5 = Connection Options bit 1 3273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6 = Connection Options bit 2 3283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 7 = Enable Non part on LIHA failure 3293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 3303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8 = Enable Class 2 3313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 9 = Enable ACK0 3323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 10 = Reserved 3333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11 = Enable FC-SP Security 3343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 12 = FC Tape Enable 3353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 13-31 = Reserved 3363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 3373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_2; 3383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 3403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Reserved 3413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Soft ID only 3423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = Reserved 3433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Reserved 3443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = FCP RSP Payload bit 0 3453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 5 = FCP RSP Payload bit 1 3463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6 = Enable Receive Out-of-Order data frame handling 3473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 7 = Disable Automatic PLOGI on Local Loop 3483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * 3493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 8 = Reserved 3503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 3513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 10 = Reserved 3523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 11 = Reserved 3533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 12 = Reserved 3543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 13 = Data Rate bit 0 3553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 14 = Data Rate bit 1 3563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 15 = Data Rate bit 2 3573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 16-31 = Reserved 3583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 3593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t firmware_options_3; 3603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_3[24]; 3623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 3633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 3653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - command entry structure definition. 3663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 3673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */ 3683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct cmd_type_6 { 3693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 3703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 3713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 3723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 3733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 3753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 3773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t timeout; /* Command timeout. */ 3783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t dseg_count; /* Data segment count. */ 3803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */ 3823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 383661c3f6cc32e1307fc7df724149884c95e98358dAndrew Vasquez struct scsi_lun lun; /* FCP LUN (BE). */ 3843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t control_flags; /* Control flags. */ 3863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CF_DATA_SEG_DESCR_ENABLE BIT_2 3873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CF_READ_DATA BIT_1 3883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CF_WRITE_DATA BIT_0 3893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 3913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 3923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 3943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t byte_count; /* Total byte count. */ 3963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 3973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; /* PortID of destination port. */ 3983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 3993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ 4013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t fcp_data_dseg_len; /* Data segment length. */ 4023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; /* MUST be set to 0. */ 4033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 4043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */ 4063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct cmd_type_7 { 4073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 4083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 4093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 4103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 4113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 4133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 4153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t timeout; /* Command timeout. */ 4163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FW_MAX_TIMEOUT 0x1999 4173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t dseg_count; /* Data segment count. */ 4193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 4203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 421661c3f6cc32e1307fc7df724149884c95e98358dAndrew Vasquez struct scsi_lun lun; /* FCP LUN (BE). */ 4223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t task_mgmt_flags; /* Task management flags. */ 4243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_CLEAR_ACA BIT_14 4253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_TARGET_RESET BIT_13 4263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_LUN_RESET BIT_12 4273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_CLEAR_TASK_SET BIT_10 4283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_ABORT_TASK_SET BIT_9 4293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_READ_DATA BIT_1 4303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TMF_WRITE_DATA BIT_0 4313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t task; 4333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_SIMPLE 0 4343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_HEAD_OF_QUEUE 1 4353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_ORDERED 2 4363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_ACA 4 4373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_UNTAGGED 5 4383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t crn; 4403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ 4423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t byte_count; /* Total byte count. */ 4433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; /* PortID of destination port. */ 4453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 4463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 4483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_0_len; /* Data segment 0 length. */ 4493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 4503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 4523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - status entry structure definition. 4533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 4543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define STATUS_TYPE 0x03 /* Status entry. */ 4553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct sts_entry_24xx { 4563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 4573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 4583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 4593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 4603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 4623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t comp_status; /* Completion status. */ 4643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t ox_id; /* OX_ID used by the firmware. */ 4653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 466ed17c71b5d11327efd40666fd621486f964fae4fRavi Anand uint32_t residual_len; /* FW calc residual transfer length. */ 4673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 4693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t state_flags; /* State flags. */ 4703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define SF_TRANSFERRED_DATA BIT_11 4713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define SF_FCP_RSP_DMA BIT_0 4723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_2; 4743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t scsi_status; /* SCSI status. */ 4753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define SS_CONFIRMATION_REQ BIT_12 4763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rsp_residual_count; /* FCP RSP residual count. */ 4783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t sense_len; /* FCP SENSE length. */ 4803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rsp_data_len; /* FCP response data length. */ 4813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t data[28]; /* FCP response/sense information. */ 4833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 4843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 4863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * Status entry completion status 4873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 4883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */ 4893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */ 4903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */ 4913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */ 4923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */ 4933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 4943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 4953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - marker entry structure definition. 4963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 4973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MARKER_TYPE 0x04 /* Marker entry. */ 4983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct mrk_entry_24xx { 4993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 5003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 5013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t handle_count; /* Handle count. */ 5023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 5033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 5053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 5073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t modifier; /* Modifier (7-0). */ 5093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 5103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MK_SYNC_ID 1 /* Synchronize ID */ 5113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 5123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_1; 5133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_2; 5153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 5163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_3; 5183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t lun[8]; /* FCP LUN (BE). */ 5203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_4[40]; 5213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 5223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 5243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - CT Pass-Through entry structure definition. 5253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 5263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */ 5273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct ct_entry_24xx { 5283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 5293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 5303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System Defined. */ 5313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 5323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 5343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t comp_status; /* Completion status. */ 5363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 5383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t cmd_dsd_count; 5403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 5423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_1; 5433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t timeout; /* Command timeout. */ 5453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_2; 5463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t rsp_dsd_count; 5483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_3[10]; 5503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rsp_byte_count; 5523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t cmd_byte_count; 5533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 5553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_0_len; /* Data segment 0 length. */ 5563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 5573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t dseg_1_len; /* Data segment 1 length. */ 5583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 5593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 5613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - ELS Pass-Through entry structure definition. 5623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 5633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */ 5643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct els_entry_24xx { 5653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 5663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 5673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System Defined. */ 5683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 5693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 5713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 5733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 5753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t tx_dsd_count; 5773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 5793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sof_type; 5803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EST_SOFI3 (1 << 4) 5813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EST_SOFI2 (3 << 4) 5823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rx_xchg_address[2]; /* Receive exchange address. */ 5843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t rx_dsd_count; 5853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t opcode; 5873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_2; 5883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; 5903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_3; 5913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_4; 5933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 5943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t control_flags; /* Control flags. */ 5953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13) 5963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EPD_ELS_COMMAND (0 << 13) 5973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EPD_ELS_ACC (1 << 13) 5983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EPD_ELS_RJT (2 << 13) 5993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define EPD_RX_XCHG (3 << 13) 6003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ECF_CLR_PASSTHRU_PEND BIT_12 6013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ECF_INCL_FRAME_HDR BIT_11 6023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rx_byte_count; 6043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t tx_byte_count; 6053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t tx_address[2]; /* Data segment 0 address. */ 6073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t tx_len; /* Data segment 0 length. */ 6083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rx_address[2]; /* Data segment 1 address. */ 6093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rx_len; /* Data segment 1 length. */ 6103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 6113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 6133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP queue - Mailbox Command entry structure definition. 6143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 6153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MBX_IOCB_TYPE 0x39 6163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct mbx_entry_24xx { 6173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 6183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 6193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t handle_count; /* Handle count. */ 6203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 6213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 6233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mbx[28]; 6253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 6263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */ 6293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct logio_entry_24xx { 6303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 6313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 6323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 6333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 6343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 6363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t comp_status; /* Completion status. */ 6383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */ 6393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 6413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t control_flags; /* Control flags. */ 6433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Modifiers. */ 6443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ 6453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ 6463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ 6473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */ 6483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */ 6493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */ 6503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */ 6513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */ 6523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */ 6533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Commands. */ 6543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */ 6553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_PRLI 0x01 /* PRLI. */ 6563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_PDISC 0x02 /* PDISC. */ 6573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_ADISC 0x03 /* ADISC. */ 6583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_LOGO 0x08 /* LOGO. */ 6593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_PRLO 0x09 /* PRLO. */ 6603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */ 6613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 6633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_1; 6643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; /* PortID of destination port. */ 6663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t rsp_size; /* Response size in 32bit words. */ 6683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t io_parameter[11]; /* General I/O parameters. */ 6703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOLINK 0x01 6713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOIOCB 0x02 6723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOXCB 0x03 6733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_CMD_FAILED 0x04 6743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOFABRIC 0x05 6753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_FW_NOT_READY 0x07 6763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOT_LOGGED_IN 0x09 6773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOPCB 0x0A 6783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_ELS_REJECT 0x18 6803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_CMD_PARAM_ERR 0x19 6813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_PORTID_USED 0x1A 6823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NPORT_USED 0x1B 6833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NONPORT 0x1C 6843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_LOGGED_IN 0x1D 6853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define LSC_SCODE_NOFLOGI_ACC 0x1F 6863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 6873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TSK_MGMT_IOCB_TYPE 0x14 6893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct tsk_mgmt_entry { 6903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 6913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 6923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t handle_count; /* Handle count. */ 6933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 6943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 6963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 6983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 6993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 7003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t delay; /* Activity delay in seconds. */ 7023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t timeout; /* Command timeout. */ 7043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t lun[8]; /* FCP LUN (BE). */ 7063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t control_flags; /* Control Flags. */ 7083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_NOTMCMD_TO_TARGET BIT_31 7093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_LUN_RESET BIT_4 7103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_ABORT_TASK_SET BIT_3 7113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_CLEAR_TASK_SET BIT_2 7123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_TARGET_RESET BIT_1 7133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define TCF_CLEAR_ACA BIT_0 7143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_2[20]; 7163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; /* PortID of destination port. */ 7183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 7193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_3[12]; 7213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 7223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ABORT_IOCB_TYPE 0x33 7243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct abort_entry_24xx { 7253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 7263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 7273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t handle_count; /* Handle count. */ 7283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 7293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 7313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t nport_handle; /* N_PORT handle. */ 7333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* or Completion status. */ 7343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t options; /* Options. */ 7363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ 7373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle_to_abort; /* System handle to abort. */ 7393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_1[32]; 7413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; /* PortID of destination port. */ 7433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_index; 7443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_2[12]; 7463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 7473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* 7493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * ISP I/O Register Set structure definitions. 7503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 7513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct device_reg_24xx { 7523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t flash_addr; /* Flash/NVRAM BIOS address. */ 7533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FARX_DATA_FLAG BIT_31 7543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FARX_ACCESS_FLASH_CONF 0x7FFD0000 7553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FARX_ACCESS_FLASH_DATA 0x7FF00000 7563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FARX_ACCESS_NVRAM_CONF 0x7FFF0000 7573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FARX_ACCESS_NVRAM_DATA 0x7FFE0000 7583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_NVRAM_FUNC0_ADDR 0x80 7603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_NVRAM_FUNC1_ADDR 0x180 7613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7626f6417905cf272337a9762e1f92a1fffa651fcd3Andrew Vasquez#define FA_NVRAM_VPD_SIZE 0x200 7633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_NVRAM_VPD0_ADDR 0x00 7643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_NVRAM_VPD1_ADDR 0x100 7653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 7663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * RISC code begins at offset 512KB 7673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * within flash. Consisting of two 7683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * contiguous RISC code segments. 7693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 7703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_RISC_CODE_ADDR 0x20000 7713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define FA_RISC_CODE_SEGMENTS 2 7723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t flash_data; /* Flash/NVRAM BIOS data. */ 7743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t ctrl_status; /* Control/Status. */ 7763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */ 7773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */ 7783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */ 7793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_FUNCTION BIT_15 /* Function number. */ 7803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* PCI-X Bus Mode. */ 7813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8) 7823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCI_33MHZ (0 << 8) 7833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M1_66MHZ (1 << 8) 7843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M1_100MHZ (2 << 8) 7853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M1_133MHZ (3 << 8) 7863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M2_66MHZ (5 << 8) 7873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M2_100MHZ (6 << 8) 7883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCIX_M2_133MHZ (7 << 8) 7893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define PBM_PCI_66MHZ (8 << 8) 7903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Max Write Burst byte count. */ 7913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4) 7923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MWB_512_BYTES (0 << 4) 7933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MWB_1024_BYTES (1 << 4) 7943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MWB_2048_BYTES (2 << 4) 7953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MWB_4096_BYTES (3 << 4) 7963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 7973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */ 7983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */ 7993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ 8003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t ictrl; /* Interrupt control. */ 8023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */ 8033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t istatus; /* Interrupt status. */ 8053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define ISRX_RISC_INT BIT_3 /* RISC interrupt. */ 8063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t unused_1[2]; /* Gap. */ 8083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Request Queue. */ 8103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t req_q_in; /* In-Pointer. */ 8113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t req_q_out; /* Out-Pointer. */ 8123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Response Queue. */ 8133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rsp_q_in; /* In-Pointer. */ 8143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t rsp_q_out; /* Out-Pointer. */ 8153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Priority Request Queue. */ 8163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t preq_q_in; /* In-Pointer. */ 8173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t preq_q_out; /* Out-Pointer. */ 8183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t unused_2[2]; /* Gap. */ 8203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* ATIO Queue. */ 8223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t atio_q_in; /* In-Pointer. */ 8233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t atio_q_out; /* Out-Pointer. */ 8243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t host_status; 8263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ 8273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ 8283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t hccr; /* Host command & control register. */ 8303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* HCCR statuses. */ 8313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ 8323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 8333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_RISC_PAUSE BIT_4 /* RISC Pause mode bit. */ 8343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* HCCR commands. */ 8353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* NOOP. */ 8363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_NOOP 0x00000000 8373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Set RISC Reset. */ 8383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_SET_RISC_RESET 0x10000000 8393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Clear RISC Reset. */ 8403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_CLR_RISC_RESET 0x20000000 8413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Set RISC Pause. */ 8423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_SET_RISC_PAUSE 0x30000000 8433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Releases RISC Pause. */ 8443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_REL_RISC_PAUSE 0x40000000 8453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Set HOST to RISC interrupt. */ 8463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_SET_HOST_INT 0x50000000 8473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Clear HOST to RISC interrupt. */ 8483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_CLR_HOST_INT 0x60000000 8493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Clear RISC to PCI interrupt. */ 8503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define HCCRX_CLR_RISC_INT 0xA0000000 8513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t gpiod; /* GPIO Data register. */ 8533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* LED update mask. */ 8543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) 8553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Data update mask. */ 8563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) 8573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* LED control mask. */ 8583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) 8593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* LED bit values. Color names as 8603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * referenced in fw spec. 8613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 8623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_LED_YELLOW_ON BIT_2 8633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_LED_GREEN_ON BIT_3 8643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_LED_AMBER_ON BIT_4 8653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Data in/out. */ 8663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPDX_DATA_INOUT (BIT_1|BIT_0) 8673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t gpioe; /* GPIO Enable register. */ 8693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Enable update mask. */ 8703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) 8713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Enable. */ 8723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define GPEX_ENABLE (BIT_1|BIT_0) 8733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t iobase_addr; /* I/O Bus Base Address register. */ 8753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t unused_3[10]; /* Gap. */ 8773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 8783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox0; 8793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox1; 8803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox2; 8813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox3; 8823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox4; 8833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox5; 8843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox6; 8853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox7; 8863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox8; 8873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox9; 8883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox10; 8893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox11; 8903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox12; 8913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox13; 8923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox14; 8933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox15; 8943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox16; 8953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox17; 8963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox18; 8973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox19; 8983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox20; 8993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox21; 9003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox22; 9013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox23; 9023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox24; 9033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox25; 9043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox26; 9053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox27; 9063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox28; 9073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox29; 9083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox30; 9093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t mailbox31; 9103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 9113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* MID Support ***************************************************************/ 9133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MAX_MID_VPS 125 9153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct mid_conf_entry_24xx { 9173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 9183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* 9203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 0 = Enable Hard Loop Id 9213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 1 = Acquire Loop ID in LIPA 9223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 2 = ID not Acquired 9233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 3 = Enable VP 9243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 4 = Enable Initiator Mode 9253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 5 = Disable Target Mode 9263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez * BIT 6-7 = Reserved 9273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez */ 9283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t options; 9293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t hard_address; 9313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name[WWN_SIZE]; 9333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name[WWN_SIZE]; 9343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 9353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct mid_init_cb_24xx { 9373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez struct init_cb_24xx init_cb; 9383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t count; 9403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t options; 9413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez struct mid_conf_entry_24xx entries[MAX_MID_VPS]; 9433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 9443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct mid_db_entry_24xx { 9473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t status; 9483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MDBS_NON_PARTIC BIT_3 9493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MDBS_ID_ACQUIRED BIT_1 9503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define MDBS_ENABLED BIT_0 9513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t options; 9533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t hard_address; 9543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name[WWN_SIZE]; 9563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name[WWN_SIZE]; 9573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; 9593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_1; 9603d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 9613d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9623d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct mid_db_24xx { 9633d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez struct mid_db_entry_24xx entries[MAX_MID_VPS]; 9643d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 9653d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9663d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */ 9673d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct vp_ctrl_entry_24xx { 9683d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 9693d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 9703d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 9713d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 9723d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9733d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 9743d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9753d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t vp_idx_failed; 9763d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9773d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t comp_status; /* Completion status. */ 9783d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */ 9793d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */ 9803d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9813d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t command; 9823d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */ 9833d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */ 9843d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */ 9853d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */ 9863d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9873d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t vp_count; 9883d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9893d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_idx_map[16]; 9903d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9913d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_4[32]; 9923d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 9933d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 9943d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */ 9953d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct vp_config_entry_24xx { 9963d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 9973d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 9983d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 9993d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 10003d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10013d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 10023d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10033d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_1; 10043d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10053d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t comp_status; /* Completion status. */ 10063d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */ 10073d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */ 10083d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCT_ERROR 0x03 /* Unknown error. */ 10093d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */ 10103d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */ 10113d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10123d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t command; 10133d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VCT_COMMAND_MOD_VPS 0x00 /* Enable VPs. */ 10143d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VCT_COMMAND_MOD_ENABLE_VPS 0x08 /* Disable VPs. */ 10153d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10163d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_count; 10173d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10183d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_idx1; 10193d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_idx2; 10203d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10213d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t options_idx1; 10223d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t hard_address_idx1; 10233d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_2; 10243d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name_idx1[WWN_SIZE]; 10253d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name_idx1[WWN_SIZE]; 10263d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10273d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t options_idx2; 10283d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t hard_address_idx2; 10293d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t reserved_3; 10303d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_name_idx2[WWN_SIZE]; 10313d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t node_name_idx2[WWN_SIZE]; 10323d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10333d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_4[8]; 10343d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 10353d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10363d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */ 10373d71644cf952fd1157a13173237258422ba3c569Andrew Vasquezstruct vp_rpt_id_entry_24xx { 10383d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_type; /* Entry type. */ 10393d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_count; /* Entry count. */ 10403d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t sys_define; /* System defined. */ 10413d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t entry_status; /* Entry Status. */ 10423d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10433d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint32_t handle; /* System handle. */ 10443d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10453d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */ 10463d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Format 1 -- | VP count |. */ 10473d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint16_t vp_idx; /* Format 0 -- Reserved. */ 10483d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez /* Format 1 -- VP status and index. */ 10493d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10503d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t port_id[3]; 10513d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t format; 10523d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10533d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t vp_idx_map[16]; 10543d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10553d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez uint8_t reserved_4[32]; 10563d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez}; 10573d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez 10583d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez/* END MID Support ***********************************************************/ 10593d71644cf952fd1157a13173237258422ba3c569Andrew Vasquez#endif 1060