qla_nx.c revision 9ba56b95a588906a65664a9299a9f8ac1a0f6a91
1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2011 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7#include "qla_def.h" 8#include <linux/delay.h> 9#include <linux/pci.h> 10#include <linux/ratelimit.h> 11#include <linux/vmalloc.h> 12#include <scsi/scsi_tcq.h> 13 14#define MASK(n) ((1ULL<<(n))-1) 15#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16 ((addr >> 25) & 0x3ff)) 17#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18 ((addr >> 25) & 0x3ff)) 19#define MS_WIN(addr) (addr & 0x0ffc0000) 20#define QLA82XX_PCI_MN_2M (0) 21#define QLA82XX_PCI_MS_2M (0x80000) 22#define QLA82XX_PCI_OCM0_2M (0xc0000) 23#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24#define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25#define BLOCK_PROTECT_BITS 0x0F 26 27/* CRB window related */ 28#define CRB_BLK(off) ((off >> 20) & 0x3f) 29#define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30#define CRB_WINDOW_2M (0x130060) 31#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32#define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33 ((off) & 0xf0000)) 34#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35#define CRB_INDIRECT_2M (0x1e0000UL) 36 37#define MAX_CRB_XFORM 60 38static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39int qla82xx_crb_table_initialized; 40 41#define qla82xx_crb_addr_transform(name) \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44 45static void qla82xx_crb_addr_transform_setup(void) 46{ 47 qla82xx_crb_addr_transform(XDMA); 48 qla82xx_crb_addr_transform(TIMR); 49 qla82xx_crb_addr_transform(SRE); 50 qla82xx_crb_addr_transform(SQN3); 51 qla82xx_crb_addr_transform(SQN2); 52 qla82xx_crb_addr_transform(SQN1); 53 qla82xx_crb_addr_transform(SQN0); 54 qla82xx_crb_addr_transform(SQS3); 55 qla82xx_crb_addr_transform(SQS2); 56 qla82xx_crb_addr_transform(SQS1); 57 qla82xx_crb_addr_transform(SQS0); 58 qla82xx_crb_addr_transform(RPMX7); 59 qla82xx_crb_addr_transform(RPMX6); 60 qla82xx_crb_addr_transform(RPMX5); 61 qla82xx_crb_addr_transform(RPMX4); 62 qla82xx_crb_addr_transform(RPMX3); 63 qla82xx_crb_addr_transform(RPMX2); 64 qla82xx_crb_addr_transform(RPMX1); 65 qla82xx_crb_addr_transform(RPMX0); 66 qla82xx_crb_addr_transform(ROMUSB); 67 qla82xx_crb_addr_transform(SN); 68 qla82xx_crb_addr_transform(QMN); 69 qla82xx_crb_addr_transform(QMS); 70 qla82xx_crb_addr_transform(PGNI); 71 qla82xx_crb_addr_transform(PGND); 72 qla82xx_crb_addr_transform(PGN3); 73 qla82xx_crb_addr_transform(PGN2); 74 qla82xx_crb_addr_transform(PGN1); 75 qla82xx_crb_addr_transform(PGN0); 76 qla82xx_crb_addr_transform(PGSI); 77 qla82xx_crb_addr_transform(PGSD); 78 qla82xx_crb_addr_transform(PGS3); 79 qla82xx_crb_addr_transform(PGS2); 80 qla82xx_crb_addr_transform(PGS1); 81 qla82xx_crb_addr_transform(PGS0); 82 qla82xx_crb_addr_transform(PS); 83 qla82xx_crb_addr_transform(PH); 84 qla82xx_crb_addr_transform(NIU); 85 qla82xx_crb_addr_transform(I2Q); 86 qla82xx_crb_addr_transform(EG); 87 qla82xx_crb_addr_transform(MN); 88 qla82xx_crb_addr_transform(MS); 89 qla82xx_crb_addr_transform(CAS2); 90 qla82xx_crb_addr_transform(CAS1); 91 qla82xx_crb_addr_transform(CAS0); 92 qla82xx_crb_addr_transform(CAM); 93 qla82xx_crb_addr_transform(C2C1); 94 qla82xx_crb_addr_transform(C2C0); 95 qla82xx_crb_addr_transform(SMB); 96 qla82xx_crb_addr_transform(OCM0); 97 /* 98 * Used only in P3 just define it for P2 also. 99 */ 100 qla82xx_crb_addr_transform(I2C0); 101 102 qla82xx_crb_table_initialized = 1; 103} 104 105struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106 {{{0, 0, 0, 0} } }, 107 {{{1, 0x0100000, 0x0102000, 0x120000}, 108 {1, 0x0110000, 0x0120000, 0x130000}, 109 {1, 0x0120000, 0x0122000, 0x124000}, 110 {1, 0x0130000, 0x0132000, 0x126000}, 111 {1, 0x0140000, 0x0142000, 0x128000}, 112 {1, 0x0150000, 0x0152000, 0x12a000}, 113 {1, 0x0160000, 0x0170000, 0x110000}, 114 {1, 0x0170000, 0x0172000, 0x12e000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {1, 0x01e0000, 0x01e0800, 0x122000}, 122 {0, 0x0000000, 0x0000000, 0x000000} } } , 123 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124 {{{0, 0, 0, 0} } }, 125 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129 {{{1, 0x0800000, 0x0802000, 0x170000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145 {{{1, 0x0900000, 0x0902000, 0x174000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {0, 0x0000000, 0x0000000, 0x000000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204 {{{0, 0, 0, 0} } }, 205 {{{0, 0, 0, 0} } }, 206 {{{0, 0, 0, 0} } }, 207 {{{0, 0, 0, 0} } }, 208 {{{0, 0, 0, 0} } }, 209 {{{0, 0, 0, 0} } }, 210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213 {{{0} } }, 214 {{{1, 0x2100000, 0x2102000, 0x120000}, 215 {1, 0x2110000, 0x2120000, 0x130000}, 216 {1, 0x2120000, 0x2122000, 0x124000}, 217 {1, 0x2130000, 0x2132000, 0x126000}, 218 {1, 0x2140000, 0x2142000, 0x128000}, 219 {1, 0x2150000, 0x2152000, 0x12a000}, 220 {1, 0x2160000, 0x2170000, 0x110000}, 221 {1, 0x2170000, 0x2172000, 0x12e000}, 222 {0, 0x0000000, 0x0000000, 0x000000}, 223 {0, 0x0000000, 0x0000000, 0x000000}, 224 {0, 0x0000000, 0x0000000, 0x000000}, 225 {0, 0x0000000, 0x0000000, 0x000000}, 226 {0, 0x0000000, 0x0000000, 0x000000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000} } }, 230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231 {{{0} } }, 232 {{{0} } }, 233 {{{0} } }, 234 {{{0} } }, 235 {{{0} } }, 236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248 {{{0} } }, 249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255 {{{0} } }, 256 {{{0} } }, 257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260}; 261 262/* 263 * top 12 bits of crb internal address (hub, agent) 264 */ 265unsigned qla82xx_crb_hub_agt[64] = { 266 0, 267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270 0, 271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293 0, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296 0, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301 0, 302 0, 303 0, 304 0, 305 0, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307 0, 308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318 0, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327 0, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329 0, 330}; 331 332/* Device states */ 333char *q_dev_state[] = { 334 "Unknown", 335 "Cold", 336 "Initializing", 337 "Ready", 338 "Need Reset", 339 "Need Quiescent", 340 "Failed", 341 "Quiescent", 342}; 343 344char *qdev_state(uint32_t dev_state) 345{ 346 return q_dev_state[dev_state]; 347} 348 349/* 350 * In: 'off' is offset from CRB space in 128M pci map 351 * Out: 'off' is 2M pci map addr 352 * side effect: lock crb window 353 */ 354static void 355qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356{ 357 u32 win_read; 358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359 360 ha->crb_win = CRB_HI(*off); 361 writel(ha->crb_win, 362 (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363 364 /* Read back value to make sure write has gone through before trying 365 * to use it. 366 */ 367 win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 368 if (win_read != ha->crb_win) { 369 ql_dbg(ql_dbg_p3p, vha, 0xb000, 370 "%s: Written crbwin (0x%x) " 371 "!= Read crbwin (0x%x), off=0x%lx.\n", 372 __func__, ha->crb_win, win_read, *off); 373 } 374 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 375} 376 377static inline unsigned long 378qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 379{ 380 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 381 /* See if we are currently pointing to the region we want to use next */ 382 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 383 /* No need to change window. PCIX and PCIEregs are in both 384 * regs are in both windows. 385 */ 386 return off; 387 } 388 389 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 390 /* We are in first CRB window */ 391 if (ha->curr_window != 0) 392 WARN_ON(1); 393 return off; 394 } 395 396 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 397 /* We are in second CRB window */ 398 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 399 400 if (ha->curr_window != 1) 401 return off; 402 403 /* We are in the QM or direct access 404 * register region - do nothing 405 */ 406 if ((off >= QLA82XX_PCI_DIRECT_CRB) && 407 (off < QLA82XX_PCI_CAMQM_MAX)) 408 return off; 409 } 410 /* strange address given */ 411 ql_dbg(ql_dbg_p3p, vha, 0xb001, 412 "%s: Warning: unm_nic_pci_set_crbwindow " 413 "called with an unknown address(%llx).\n", 414 QLA2XXX_DRIVER_NAME, off); 415 return off; 416} 417 418static int 419qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 420{ 421 struct crb_128M_2M_sub_block_map *m; 422 423 if (*off >= QLA82XX_CRB_MAX) 424 return -1; 425 426 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 427 *off = (*off - QLA82XX_PCI_CAMQM) + 428 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 429 return 0; 430 } 431 432 if (*off < QLA82XX_PCI_CRBSPACE) 433 return -1; 434 435 *off -= QLA82XX_PCI_CRBSPACE; 436 437 /* Try direct map */ 438 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 439 440 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 441 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 442 return 0; 443 } 444 /* Not in direct map, use crb window */ 445 return 1; 446} 447 448#define CRB_WIN_LOCK_TIMEOUT 100000000 449static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 450{ 451 int done = 0, timeout = 0; 452 453 while (!done) { 454 /* acquire semaphore3 from PCI HW block */ 455 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 456 if (done == 1) 457 break; 458 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 459 return -1; 460 timeout++; 461 } 462 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 463 return 0; 464} 465 466int 467qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 468{ 469 unsigned long flags = 0; 470 int rv; 471 472 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 473 474 BUG_ON(rv == -1); 475 476 if (rv == 1) { 477 write_lock_irqsave(&ha->hw_lock, flags); 478 qla82xx_crb_win_lock(ha); 479 qla82xx_pci_set_crbwindow_2M(ha, &off); 480 } 481 482 writel(data, (void __iomem *)off); 483 484 if (rv == 1) { 485 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 486 write_unlock_irqrestore(&ha->hw_lock, flags); 487 } 488 return 0; 489} 490 491int 492qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 493{ 494 unsigned long flags = 0; 495 int rv; 496 u32 data; 497 498 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 499 500 BUG_ON(rv == -1); 501 502 if (rv == 1) { 503 write_lock_irqsave(&ha->hw_lock, flags); 504 qla82xx_crb_win_lock(ha); 505 qla82xx_pci_set_crbwindow_2M(ha, &off); 506 } 507 data = RD_REG_DWORD((void __iomem *)off); 508 509 if (rv == 1) { 510 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 511 write_unlock_irqrestore(&ha->hw_lock, flags); 512 } 513 return data; 514} 515 516#define IDC_LOCK_TIMEOUT 100000000 517int qla82xx_idc_lock(struct qla_hw_data *ha) 518{ 519 int i; 520 int done = 0, timeout = 0; 521 522 while (!done) { 523 /* acquire semaphore5 from PCI HW block */ 524 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 525 if (done == 1) 526 break; 527 if (timeout >= IDC_LOCK_TIMEOUT) 528 return -1; 529 530 timeout++; 531 532 /* Yield CPU */ 533 if (!in_interrupt()) 534 schedule(); 535 else { 536 for (i = 0; i < 20; i++) 537 cpu_relax(); 538 } 539 } 540 541 return 0; 542} 543 544void qla82xx_idc_unlock(struct qla_hw_data *ha) 545{ 546 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 547} 548 549/* PCI Windowing for DDR regions. */ 550#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 551 (((addr) <= (high)) && ((addr) >= (low))) 552/* 553 * check memory access boundary. 554 * used by test agent. support ddr access only for now 555 */ 556static unsigned long 557qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 558 unsigned long long addr, int size) 559{ 560 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 561 QLA82XX_ADDR_DDR_NET_MAX) || 562 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 563 QLA82XX_ADDR_DDR_NET_MAX) || 564 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 565 return 0; 566 else 567 return 1; 568} 569 570int qla82xx_pci_set_window_warning_count; 571 572static unsigned long 573qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 574{ 575 int window; 576 u32 win_read; 577 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 578 579 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 580 QLA82XX_ADDR_DDR_NET_MAX)) { 581 /* DDR network side */ 582 window = MN_WIN(addr); 583 ha->ddr_mn_window = window; 584 qla82xx_wr_32(ha, 585 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 586 win_read = qla82xx_rd_32(ha, 587 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 588 if ((win_read << 17) != window) { 589 ql_dbg(ql_dbg_p3p, vha, 0xb003, 590 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 591 __func__, window, win_read); 592 } 593 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 594 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 595 QLA82XX_ADDR_OCM0_MAX)) { 596 unsigned int temp1; 597 if ((addr & 0x00ff800) == 0xff800) { 598 ql_log(ql_log_warn, vha, 0xb004, 599 "%s: QM access not handled.\n", __func__); 600 addr = -1UL; 601 } 602 window = OCM_WIN(addr); 603 ha->ddr_mn_window = window; 604 qla82xx_wr_32(ha, 605 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 606 win_read = qla82xx_rd_32(ha, 607 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 608 temp1 = ((window & 0x1FF) << 7) | 609 ((window & 0x0FFFE0000) >> 17); 610 if (win_read != temp1) { 611 ql_log(ql_log_warn, vha, 0xb005, 612 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 613 __func__, temp1, win_read); 614 } 615 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 616 617 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 618 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 619 /* QDR network side */ 620 window = MS_WIN(addr); 621 ha->qdr_sn_window = window; 622 qla82xx_wr_32(ha, 623 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 624 win_read = qla82xx_rd_32(ha, 625 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 626 if (win_read != window) { 627 ql_log(ql_log_warn, vha, 0xb006, 628 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 629 __func__, window, win_read); 630 } 631 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 632 } else { 633 /* 634 * peg gdb frequently accesses memory that doesn't exist, 635 * this limits the chit chat so debugging isn't slowed down. 636 */ 637 if ((qla82xx_pci_set_window_warning_count++ < 8) || 638 (qla82xx_pci_set_window_warning_count%64 == 0)) { 639 ql_log(ql_log_warn, vha, 0xb007, 640 "%s: Warning:%s Unknown address range!.\n", 641 __func__, QLA2XXX_DRIVER_NAME); 642 } 643 addr = -1UL; 644 } 645 return addr; 646} 647 648/* check if address is in the same windows as the previous access */ 649static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 650 unsigned long long addr) 651{ 652 int window; 653 unsigned long long qdr_max; 654 655 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 656 657 /* DDR network side */ 658 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 659 QLA82XX_ADDR_DDR_NET_MAX)) 660 BUG(); 661 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 662 QLA82XX_ADDR_OCM0_MAX)) 663 return 1; 664 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 665 QLA82XX_ADDR_OCM1_MAX)) 666 return 1; 667 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 668 /* QDR network side */ 669 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 670 if (ha->qdr_sn_window == window) 671 return 1; 672 } 673 return 0; 674} 675 676static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 677 u64 off, void *data, int size) 678{ 679 unsigned long flags; 680 void *addr = NULL; 681 int ret = 0; 682 u64 start; 683 uint8_t *mem_ptr = NULL; 684 unsigned long mem_base; 685 unsigned long mem_page; 686 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 687 688 write_lock_irqsave(&ha->hw_lock, flags); 689 690 /* 691 * If attempting to access unknown address or straddle hw windows, 692 * do not access. 693 */ 694 start = qla82xx_pci_set_window(ha, off); 695 if ((start == -1UL) || 696 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 697 write_unlock_irqrestore(&ha->hw_lock, flags); 698 ql_log(ql_log_fatal, vha, 0xb008, 699 "%s out of bound pci memory " 700 "access, offset is 0x%llx.\n", 701 QLA2XXX_DRIVER_NAME, off); 702 return -1; 703 } 704 705 write_unlock_irqrestore(&ha->hw_lock, flags); 706 mem_base = pci_resource_start(ha->pdev, 0); 707 mem_page = start & PAGE_MASK; 708 /* Map two pages whenever user tries to access addresses in two 709 * consecutive pages. 710 */ 711 if (mem_page != ((start + size - 1) & PAGE_MASK)) 712 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 713 else 714 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 715 if (mem_ptr == 0UL) { 716 *(u8 *)data = 0; 717 return -1; 718 } 719 addr = mem_ptr; 720 addr += start & (PAGE_SIZE - 1); 721 write_lock_irqsave(&ha->hw_lock, flags); 722 723 switch (size) { 724 case 1: 725 *(u8 *)data = readb(addr); 726 break; 727 case 2: 728 *(u16 *)data = readw(addr); 729 break; 730 case 4: 731 *(u32 *)data = readl(addr); 732 break; 733 case 8: 734 *(u64 *)data = readq(addr); 735 break; 736 default: 737 ret = -1; 738 break; 739 } 740 write_unlock_irqrestore(&ha->hw_lock, flags); 741 742 if (mem_ptr) 743 iounmap(mem_ptr); 744 return ret; 745} 746 747static int 748qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 749 u64 off, void *data, int size) 750{ 751 unsigned long flags; 752 void *addr = NULL; 753 int ret = 0; 754 u64 start; 755 uint8_t *mem_ptr = NULL; 756 unsigned long mem_base; 757 unsigned long mem_page; 758 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 759 760 write_lock_irqsave(&ha->hw_lock, flags); 761 762 /* 763 * If attempting to access unknown address or straddle hw windows, 764 * do not access. 765 */ 766 start = qla82xx_pci_set_window(ha, off); 767 if ((start == -1UL) || 768 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 769 write_unlock_irqrestore(&ha->hw_lock, flags); 770 ql_log(ql_log_fatal, vha, 0xb009, 771 "%s out of bount memory " 772 "access, offset is 0x%llx.\n", 773 QLA2XXX_DRIVER_NAME, off); 774 return -1; 775 } 776 777 write_unlock_irqrestore(&ha->hw_lock, flags); 778 mem_base = pci_resource_start(ha->pdev, 0); 779 mem_page = start & PAGE_MASK; 780 /* Map two pages whenever user tries to access addresses in two 781 * consecutive pages. 782 */ 783 if (mem_page != ((start + size - 1) & PAGE_MASK)) 784 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 785 else 786 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 787 if (mem_ptr == 0UL) 788 return -1; 789 790 addr = mem_ptr; 791 addr += start & (PAGE_SIZE - 1); 792 write_lock_irqsave(&ha->hw_lock, flags); 793 794 switch (size) { 795 case 1: 796 writeb(*(u8 *)data, addr); 797 break; 798 case 2: 799 writew(*(u16 *)data, addr); 800 break; 801 case 4: 802 writel(*(u32 *)data, addr); 803 break; 804 case 8: 805 writeq(*(u64 *)data, addr); 806 break; 807 default: 808 ret = -1; 809 break; 810 } 811 write_unlock_irqrestore(&ha->hw_lock, flags); 812 if (mem_ptr) 813 iounmap(mem_ptr); 814 return ret; 815} 816 817#define MTU_FUDGE_FACTOR 100 818static unsigned long 819qla82xx_decode_crb_addr(unsigned long addr) 820{ 821 int i; 822 unsigned long base_addr, offset, pci_base; 823 824 if (!qla82xx_crb_table_initialized) 825 qla82xx_crb_addr_transform_setup(); 826 827 pci_base = ADDR_ERROR; 828 base_addr = addr & 0xfff00000; 829 offset = addr & 0x000fffff; 830 831 for (i = 0; i < MAX_CRB_XFORM; i++) { 832 if (crb_addr_xform[i] == base_addr) { 833 pci_base = i << 20; 834 break; 835 } 836 } 837 if (pci_base == ADDR_ERROR) 838 return pci_base; 839 return pci_base + offset; 840} 841 842static long rom_max_timeout = 100; 843static long qla82xx_rom_lock_timeout = 100; 844 845static int 846qla82xx_rom_lock(struct qla_hw_data *ha) 847{ 848 int done = 0, timeout = 0; 849 850 while (!done) { 851 /* acquire semaphore2 from PCI HW block */ 852 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 853 if (done == 1) 854 break; 855 if (timeout >= qla82xx_rom_lock_timeout) 856 return -1; 857 timeout++; 858 } 859 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 860 return 0; 861} 862 863static void 864qla82xx_rom_unlock(struct qla_hw_data *ha) 865{ 866 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 867} 868 869static int 870qla82xx_wait_rom_busy(struct qla_hw_data *ha) 871{ 872 long timeout = 0; 873 long done = 0 ; 874 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 875 876 while (done == 0) { 877 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 878 done &= 4; 879 timeout++; 880 if (timeout >= rom_max_timeout) { 881 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 882 "%s: Timeout reached waiting for rom busy.\n", 883 QLA2XXX_DRIVER_NAME); 884 return -1; 885 } 886 } 887 return 0; 888} 889 890static int 891qla82xx_wait_rom_done(struct qla_hw_data *ha) 892{ 893 long timeout = 0; 894 long done = 0 ; 895 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 896 897 while (done == 0) { 898 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 899 done &= 2; 900 timeout++; 901 if (timeout >= rom_max_timeout) { 902 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 903 "%s: Timeout reached waiting for rom done.\n", 904 QLA2XXX_DRIVER_NAME); 905 return -1; 906 } 907 } 908 return 0; 909} 910 911static int 912qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 913{ 914 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 915 916 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 917 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 918 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 919 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 920 qla82xx_wait_rom_busy(ha); 921 if (qla82xx_wait_rom_done(ha)) { 922 ql_log(ql_log_fatal, vha, 0x00ba, 923 "Error waiting for rom done.\n"); 924 return -1; 925 } 926 /* Reset abyte_cnt and dummy_byte_cnt */ 927 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 928 udelay(10); 929 cond_resched(); 930 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 931 *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 932 return 0; 933} 934 935static int 936qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 937{ 938 int ret, loops = 0; 939 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 940 941 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 942 udelay(100); 943 schedule(); 944 loops++; 945 } 946 if (loops >= 50000) { 947 ql_log(ql_log_fatal, vha, 0x00b9, 948 "Failed to aquire SEM2 lock.\n"); 949 return -1; 950 } 951 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 952 qla82xx_rom_unlock(ha); 953 return ret; 954} 955 956static int 957qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 958{ 959 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 960 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 961 qla82xx_wait_rom_busy(ha); 962 if (qla82xx_wait_rom_done(ha)) { 963 ql_log(ql_log_warn, vha, 0xb00c, 964 "Error waiting for rom done.\n"); 965 return -1; 966 } 967 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 968 return 0; 969} 970 971static int 972qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 973{ 974 long timeout = 0; 975 uint32_t done = 1 ; 976 uint32_t val; 977 int ret = 0; 978 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 979 980 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 981 while ((done != 0) && (ret == 0)) { 982 ret = qla82xx_read_status_reg(ha, &val); 983 done = val & 1; 984 timeout++; 985 udelay(10); 986 cond_resched(); 987 if (timeout >= 50000) { 988 ql_log(ql_log_warn, vha, 0xb00d, 989 "Timeout reached waiting for write finish.\n"); 990 return -1; 991 } 992 } 993 return ret; 994} 995 996static int 997qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 998{ 999 uint32_t val; 1000 qla82xx_wait_rom_busy(ha); 1001 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1002 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1003 qla82xx_wait_rom_busy(ha); 1004 if (qla82xx_wait_rom_done(ha)) 1005 return -1; 1006 if (qla82xx_read_status_reg(ha, &val) != 0) 1007 return -1; 1008 if ((val & 2) != 2) 1009 return -1; 1010 return 0; 1011} 1012 1013static int 1014qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1015{ 1016 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1017 if (qla82xx_flash_set_write_enable(ha)) 1018 return -1; 1019 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1020 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1021 if (qla82xx_wait_rom_done(ha)) { 1022 ql_log(ql_log_warn, vha, 0xb00e, 1023 "Error waiting for rom done.\n"); 1024 return -1; 1025 } 1026 return qla82xx_flash_wait_write_finish(ha); 1027} 1028 1029static int 1030qla82xx_write_disable_flash(struct qla_hw_data *ha) 1031{ 1032 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1033 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1034 if (qla82xx_wait_rom_done(ha)) { 1035 ql_log(ql_log_warn, vha, 0xb00f, 1036 "Error waiting for rom done.\n"); 1037 return -1; 1038 } 1039 return 0; 1040} 1041 1042static int 1043ql82xx_rom_lock_d(struct qla_hw_data *ha) 1044{ 1045 int loops = 0; 1046 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1047 1048 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1049 udelay(100); 1050 cond_resched(); 1051 loops++; 1052 } 1053 if (loops >= 50000) { 1054 ql_log(ql_log_warn, vha, 0xb010, 1055 "ROM lock failed.\n"); 1056 return -1; 1057 } 1058 return 0; 1059} 1060 1061static int 1062qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1063 uint32_t data) 1064{ 1065 int ret = 0; 1066 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1067 1068 ret = ql82xx_rom_lock_d(ha); 1069 if (ret < 0) { 1070 ql_log(ql_log_warn, vha, 0xb011, 1071 "ROM lock failed.\n"); 1072 return ret; 1073 } 1074 1075 if (qla82xx_flash_set_write_enable(ha)) 1076 goto done_write; 1077 1078 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1079 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1080 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1081 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1082 qla82xx_wait_rom_busy(ha); 1083 if (qla82xx_wait_rom_done(ha)) { 1084 ql_log(ql_log_warn, vha, 0xb012, 1085 "Error waiting for rom done.\n"); 1086 ret = -1; 1087 goto done_write; 1088 } 1089 1090 ret = qla82xx_flash_wait_write_finish(ha); 1091 1092done_write: 1093 qla82xx_rom_unlock(ha); 1094 return ret; 1095} 1096 1097/* This routine does CRB initialize sequence 1098 * to put the ISP into operational state 1099 */ 1100static int 1101qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1102{ 1103 int addr, val; 1104 int i ; 1105 struct crb_addr_pair *buf; 1106 unsigned long off; 1107 unsigned offset, n; 1108 struct qla_hw_data *ha = vha->hw; 1109 1110 struct crb_addr_pair { 1111 long addr; 1112 long data; 1113 }; 1114 1115 /* Halt all the indiviual PEGs and other blocks of the ISP */ 1116 qla82xx_rom_lock(ha); 1117 1118 /* disable all I2Q */ 1119 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1120 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1121 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1122 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1123 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1124 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1125 1126 /* disable all niu interrupts */ 1127 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1128 /* disable xge rx/tx */ 1129 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1130 /* disable xg1 rx/tx */ 1131 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1132 /* disable sideband mac */ 1133 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1134 /* disable ap0 mac */ 1135 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1136 /* disable ap1 mac */ 1137 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1138 1139 /* halt sre */ 1140 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1141 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1142 1143 /* halt epg */ 1144 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1145 1146 /* halt timers */ 1147 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1148 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1149 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1150 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1151 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1152 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1153 1154 /* halt pegs */ 1155 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1156 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1157 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1158 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1159 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1160 msleep(20); 1161 1162 /* big hammer */ 1163 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1164 /* don't reset CAM block on reset */ 1165 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1166 else 1167 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1168 qla82xx_rom_unlock(ha); 1169 1170 /* Read the signature value from the flash. 1171 * Offset 0: Contain signature (0xcafecafe) 1172 * Offset 4: Offset and number of addr/value pairs 1173 * that present in CRB initialize sequence 1174 */ 1175 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1176 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1177 ql_log(ql_log_fatal, vha, 0x006e, 1178 "Error Reading crb_init area: n: %08x.\n", n); 1179 return -1; 1180 } 1181 1182 /* Offset in flash = lower 16 bits 1183 * Number of enteries = upper 16 bits 1184 */ 1185 offset = n & 0xffffU; 1186 n = (n >> 16) & 0xffffU; 1187 1188 /* number of addr/value pair should not exceed 1024 enteries */ 1189 if (n >= 1024) { 1190 ql_log(ql_log_fatal, vha, 0x0071, 1191 "Card flash not initialized:n=0x%x.\n", n); 1192 return -1; 1193 } 1194 1195 ql_log(ql_log_info, vha, 0x0072, 1196 "%d CRB init values found in ROM.\n", n); 1197 1198 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1199 if (buf == NULL) { 1200 ql_log(ql_log_fatal, vha, 0x010c, 1201 "Unable to allocate memory.\n"); 1202 return -1; 1203 } 1204 1205 for (i = 0; i < n; i++) { 1206 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1207 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1208 kfree(buf); 1209 return -1; 1210 } 1211 1212 buf[i].addr = addr; 1213 buf[i].data = val; 1214 } 1215 1216 for (i = 0; i < n; i++) { 1217 /* Translate internal CRB initialization 1218 * address to PCI bus address 1219 */ 1220 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1221 QLA82XX_PCI_CRBSPACE; 1222 /* Not all CRB addr/value pair to be written, 1223 * some of them are skipped 1224 */ 1225 1226 /* skipping cold reboot MAGIC */ 1227 if (off == QLA82XX_CAM_RAM(0x1fc)) 1228 continue; 1229 1230 /* do not reset PCI */ 1231 if (off == (ROMUSB_GLB + 0xbc)) 1232 continue; 1233 1234 /* skip core clock, so that firmware can increase the clock */ 1235 if (off == (ROMUSB_GLB + 0xc8)) 1236 continue; 1237 1238 /* skip the function enable register */ 1239 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1240 continue; 1241 1242 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1243 continue; 1244 1245 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1246 continue; 1247 1248 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1249 continue; 1250 1251 if (off == ADDR_ERROR) { 1252 ql_log(ql_log_fatal, vha, 0x0116, 1253 "Unknow addr: 0x%08lx.\n", buf[i].addr); 1254 continue; 1255 } 1256 1257 qla82xx_wr_32(ha, off, buf[i].data); 1258 1259 /* ISP requires much bigger delay to settle down, 1260 * else crb_window returns 0xffffffff 1261 */ 1262 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1263 msleep(1000); 1264 1265 /* ISP requires millisec delay between 1266 * successive CRB register updation 1267 */ 1268 msleep(1); 1269 } 1270 1271 kfree(buf); 1272 1273 /* Resetting the data and instruction cache */ 1274 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1275 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1276 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1277 1278 /* Clear all protocol processing engines */ 1279 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1280 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1281 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1282 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1283 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1284 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1285 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1286 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1287 return 0; 1288} 1289 1290static int 1291qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1292 u64 off, void *data, int size) 1293{ 1294 int i, j, ret = 0, loop, sz[2], off0; 1295 int scale, shift_amount, startword; 1296 uint32_t temp; 1297 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1298 1299 /* 1300 * If not MN, go check for MS or invalid. 1301 */ 1302 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1303 mem_crb = QLA82XX_CRB_QDR_NET; 1304 else { 1305 mem_crb = QLA82XX_CRB_DDR_NET; 1306 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1307 return qla82xx_pci_mem_write_direct(ha, 1308 off, data, size); 1309 } 1310 1311 off0 = off & 0x7; 1312 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1313 sz[1] = size - sz[0]; 1314 1315 off8 = off & 0xfffffff0; 1316 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1317 shift_amount = 4; 1318 scale = 2; 1319 startword = (off & 0xf)/8; 1320 1321 for (i = 0; i < loop; i++) { 1322 if (qla82xx_pci_mem_read_2M(ha, off8 + 1323 (i << shift_amount), &word[i * scale], 8)) 1324 return -1; 1325 } 1326 1327 switch (size) { 1328 case 1: 1329 tmpw = *((uint8_t *)data); 1330 break; 1331 case 2: 1332 tmpw = *((uint16_t *)data); 1333 break; 1334 case 4: 1335 tmpw = *((uint32_t *)data); 1336 break; 1337 case 8: 1338 default: 1339 tmpw = *((uint64_t *)data); 1340 break; 1341 } 1342 1343 if (sz[0] == 8) { 1344 word[startword] = tmpw; 1345 } else { 1346 word[startword] &= 1347 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1348 word[startword] |= tmpw << (off0 * 8); 1349 } 1350 if (sz[1] != 0) { 1351 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1352 word[startword+1] |= tmpw >> (sz[0] * 8); 1353 } 1354 1355 for (i = 0; i < loop; i++) { 1356 temp = off8 + (i << shift_amount); 1357 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1358 temp = 0; 1359 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1360 temp = word[i * scale] & 0xffffffff; 1361 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1362 temp = (word[i * scale] >> 32) & 0xffffffff; 1363 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1364 temp = word[i*scale + 1] & 0xffffffff; 1365 qla82xx_wr_32(ha, mem_crb + 1366 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1367 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1368 qla82xx_wr_32(ha, mem_crb + 1369 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1370 1371 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1372 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1373 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1374 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1375 1376 for (j = 0; j < MAX_CTL_CHECK; j++) { 1377 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1378 if ((temp & MIU_TA_CTL_BUSY) == 0) 1379 break; 1380 } 1381 1382 if (j >= MAX_CTL_CHECK) { 1383 if (printk_ratelimit()) 1384 dev_err(&ha->pdev->dev, 1385 "failed to write through agent.\n"); 1386 ret = -1; 1387 break; 1388 } 1389 } 1390 1391 return ret; 1392} 1393 1394static int 1395qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1396{ 1397 int i; 1398 long size = 0; 1399 long flashaddr = ha->flt_region_bootload << 2; 1400 long memaddr = BOOTLD_START; 1401 u64 data; 1402 u32 high, low; 1403 size = (IMAGE_START - BOOTLD_START) / 8; 1404 1405 for (i = 0; i < size; i++) { 1406 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1407 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1408 return -1; 1409 } 1410 data = ((u64)high << 32) | low ; 1411 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1412 flashaddr += 8; 1413 memaddr += 8; 1414 1415 if (i % 0x1000 == 0) 1416 msleep(1); 1417 } 1418 udelay(100); 1419 read_lock(&ha->hw_lock); 1420 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1421 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1422 read_unlock(&ha->hw_lock); 1423 return 0; 1424} 1425 1426int 1427qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1428 u64 off, void *data, int size) 1429{ 1430 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1431 int shift_amount; 1432 uint32_t temp; 1433 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1434 1435 /* 1436 * If not MN, go check for MS or invalid. 1437 */ 1438 1439 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1440 mem_crb = QLA82XX_CRB_QDR_NET; 1441 else { 1442 mem_crb = QLA82XX_CRB_DDR_NET; 1443 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1444 return qla82xx_pci_mem_read_direct(ha, 1445 off, data, size); 1446 } 1447 1448 off8 = off & 0xfffffff0; 1449 off0[0] = off & 0xf; 1450 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1451 shift_amount = 4; 1452 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1453 off0[1] = 0; 1454 sz[1] = size - sz[0]; 1455 1456 for (i = 0; i < loop; i++) { 1457 temp = off8 + (i << shift_amount); 1458 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1459 temp = 0; 1460 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1461 temp = MIU_TA_CTL_ENABLE; 1462 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1463 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1464 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1465 1466 for (j = 0; j < MAX_CTL_CHECK; j++) { 1467 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1468 if ((temp & MIU_TA_CTL_BUSY) == 0) 1469 break; 1470 } 1471 1472 if (j >= MAX_CTL_CHECK) { 1473 if (printk_ratelimit()) 1474 dev_err(&ha->pdev->dev, 1475 "failed to read through agent.\n"); 1476 break; 1477 } 1478 1479 start = off0[i] >> 2; 1480 end = (off0[i] + sz[i] - 1) >> 2; 1481 for (k = start; k <= end; k++) { 1482 temp = qla82xx_rd_32(ha, 1483 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1484 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1485 } 1486 } 1487 1488 if (j >= MAX_CTL_CHECK) 1489 return -1; 1490 1491 if ((off0[0] & 7) == 0) { 1492 val = word[0]; 1493 } else { 1494 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1495 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1496 } 1497 1498 switch (size) { 1499 case 1: 1500 *(uint8_t *)data = val; 1501 break; 1502 case 2: 1503 *(uint16_t *)data = val; 1504 break; 1505 case 4: 1506 *(uint32_t *)data = val; 1507 break; 1508 case 8: 1509 *(uint64_t *)data = val; 1510 break; 1511 } 1512 return 0; 1513} 1514 1515 1516static struct qla82xx_uri_table_desc * 1517qla82xx_get_table_desc(const u8 *unirom, int section) 1518{ 1519 uint32_t i; 1520 struct qla82xx_uri_table_desc *directory = 1521 (struct qla82xx_uri_table_desc *)&unirom[0]; 1522 __le32 offset; 1523 __le32 tab_type; 1524 __le32 entries = cpu_to_le32(directory->num_entries); 1525 1526 for (i = 0; i < entries; i++) { 1527 offset = cpu_to_le32(directory->findex) + 1528 (i * cpu_to_le32(directory->entry_size)); 1529 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 1530 1531 if (tab_type == section) 1532 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1533 } 1534 1535 return NULL; 1536} 1537 1538static struct qla82xx_uri_data_desc * 1539qla82xx_get_data_desc(struct qla_hw_data *ha, 1540 u32 section, u32 idx_offset) 1541{ 1542 const u8 *unirom = ha->hablob->fw->data; 1543 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 1544 struct qla82xx_uri_table_desc *tab_desc = NULL; 1545 __le32 offset; 1546 1547 tab_desc = qla82xx_get_table_desc(unirom, section); 1548 if (!tab_desc) 1549 return NULL; 1550 1551 offset = cpu_to_le32(tab_desc->findex) + 1552 (cpu_to_le32(tab_desc->entry_size) * idx); 1553 1554 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1555} 1556 1557static u8 * 1558qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1559{ 1560 u32 offset = BOOTLD_START; 1561 struct qla82xx_uri_data_desc *uri_desc = NULL; 1562 1563 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1564 uri_desc = qla82xx_get_data_desc(ha, 1565 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1566 if (uri_desc) 1567 offset = cpu_to_le32(uri_desc->findex); 1568 } 1569 1570 return (u8 *)&ha->hablob->fw->data[offset]; 1571} 1572 1573static __le32 1574qla82xx_get_fw_size(struct qla_hw_data *ha) 1575{ 1576 struct qla82xx_uri_data_desc *uri_desc = NULL; 1577 1578 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1579 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1580 QLA82XX_URI_FIRMWARE_IDX_OFF); 1581 if (uri_desc) 1582 return cpu_to_le32(uri_desc->size); 1583 } 1584 1585 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1586} 1587 1588static u8 * 1589qla82xx_get_fw_offs(struct qla_hw_data *ha) 1590{ 1591 u32 offset = IMAGE_START; 1592 struct qla82xx_uri_data_desc *uri_desc = NULL; 1593 1594 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1595 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1596 QLA82XX_URI_FIRMWARE_IDX_OFF); 1597 if (uri_desc) 1598 offset = cpu_to_le32(uri_desc->findex); 1599 } 1600 1601 return (u8 *)&ha->hablob->fw->data[offset]; 1602} 1603 1604/* PCI related functions */ 1605char * 1606qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) 1607{ 1608 int pcie_reg; 1609 struct qla_hw_data *ha = vha->hw; 1610 char lwstr[6]; 1611 uint16_t lnk; 1612 1613 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1614 pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); 1615 ha->link_width = (lnk >> 4) & 0x3f; 1616 1617 strcpy(str, "PCIe ("); 1618 strcat(str, "2.5Gb/s "); 1619 snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); 1620 strcat(str, lwstr); 1621 return str; 1622} 1623 1624int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1625{ 1626 unsigned long val = 0; 1627 u32 control; 1628 1629 switch (region) { 1630 case 0: 1631 val = 0; 1632 break; 1633 case 1: 1634 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1635 val = control + QLA82XX_MSIX_TBL_SPACE; 1636 break; 1637 } 1638 return val; 1639} 1640 1641 1642int 1643qla82xx_iospace_config(struct qla_hw_data *ha) 1644{ 1645 uint32_t len = 0; 1646 1647 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1648 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1649 "Failed to reserver selected regions.\n"); 1650 goto iospace_error_exit; 1651 } 1652 1653 /* Use MMIO operations for all accesses. */ 1654 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1655 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1656 "Region #0 not an MMIO resource, aborting.\n"); 1657 goto iospace_error_exit; 1658 } 1659 1660 len = pci_resource_len(ha->pdev, 0); 1661 ha->nx_pcibase = 1662 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1663 if (!ha->nx_pcibase) { 1664 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1665 "Cannot remap pcibase MMIO, aborting.\n"); 1666 pci_release_regions(ha->pdev); 1667 goto iospace_error_exit; 1668 } 1669 1670 /* Mapping of IO base pointer */ 1671 ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1672 0xbc000 + (ha->pdev->devfn << 11)); 1673 1674 if (!ql2xdbwr) { 1675 ha->nxdb_wr_ptr = 1676 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1677 (ha->pdev->devfn << 12)), 4); 1678 if (!ha->nxdb_wr_ptr) { 1679 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1680 "Cannot remap MMIO, aborting.\n"); 1681 pci_release_regions(ha->pdev); 1682 goto iospace_error_exit; 1683 } 1684 1685 /* Mapping of IO base pointer, 1686 * door bell read and write pointer 1687 */ 1688 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1689 (ha->pdev->devfn * 8); 1690 } else { 1691 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1692 QLA82XX_CAMRAM_DB1 : 1693 QLA82XX_CAMRAM_DB2); 1694 } 1695 1696 ha->max_req_queues = ha->max_rsp_queues = 1; 1697 ha->msix_count = ha->max_rsp_queues + 1; 1698 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1699 "nx_pci_base=%p iobase=%p " 1700 "max_req_queues=%d msix_count=%d.\n", 1701 (void *)ha->nx_pcibase, ha->iobase, 1702 ha->max_req_queues, ha->msix_count); 1703 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1704 "nx_pci_base=%p iobase=%p " 1705 "max_req_queues=%d msix_count=%d.\n", 1706 (void *)ha->nx_pcibase, ha->iobase, 1707 ha->max_req_queues, ha->msix_count); 1708 return 0; 1709 1710iospace_error_exit: 1711 return -ENOMEM; 1712} 1713 1714/* GS related functions */ 1715 1716/* Initialization related functions */ 1717 1718/** 1719 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1720 * @ha: HA context 1721 * 1722 * Returns 0 on success. 1723*/ 1724int 1725qla82xx_pci_config(scsi_qla_host_t *vha) 1726{ 1727 struct qla_hw_data *ha = vha->hw; 1728 int ret; 1729 1730 pci_set_master(ha->pdev); 1731 ret = pci_set_mwi(ha->pdev); 1732 ha->chip_revision = ha->pdev->revision; 1733 ql_dbg(ql_dbg_init, vha, 0x0043, 1734 "Chip revision:%d.\n", 1735 ha->chip_revision); 1736 return 0; 1737} 1738 1739/** 1740 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1741 * @ha: HA context 1742 * 1743 * Returns 0 on success. 1744 */ 1745void 1746qla82xx_reset_chip(scsi_qla_host_t *vha) 1747{ 1748 struct qla_hw_data *ha = vha->hw; 1749 ha->isp_ops->disable_intrs(ha); 1750} 1751 1752void qla82xx_config_rings(struct scsi_qla_host *vha) 1753{ 1754 struct qla_hw_data *ha = vha->hw; 1755 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1756 struct init_cb_81xx *icb; 1757 struct req_que *req = ha->req_q_map[0]; 1758 struct rsp_que *rsp = ha->rsp_q_map[0]; 1759 1760 /* Setup ring parameters in initialization control block. */ 1761 icb = (struct init_cb_81xx *)ha->init_cb; 1762 icb->request_q_outpointer = __constant_cpu_to_le16(0); 1763 icb->response_q_inpointer = __constant_cpu_to_le16(0); 1764 icb->request_q_length = cpu_to_le16(req->length); 1765 icb->response_q_length = cpu_to_le16(rsp->length); 1766 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1767 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1768 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1769 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1770 1771 WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1772 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1773 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1774} 1775 1776void qla82xx_reset_adapter(struct scsi_qla_host *vha) 1777{ 1778 struct qla_hw_data *ha = vha->hw; 1779 vha->flags.online = 0; 1780 qla2x00_try_to_stop_firmware(vha); 1781 ha->isp_ops->disable_intrs(ha); 1782} 1783 1784static int 1785qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1786{ 1787 u64 *ptr64; 1788 u32 i, flashaddr, size; 1789 __le64 data; 1790 1791 size = (IMAGE_START - BOOTLD_START) / 8; 1792 1793 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1794 flashaddr = BOOTLD_START; 1795 1796 for (i = 0; i < size; i++) { 1797 data = cpu_to_le64(ptr64[i]); 1798 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1799 return -EIO; 1800 flashaddr += 8; 1801 } 1802 1803 flashaddr = FLASH_ADDR_START; 1804 size = (__force u32)qla82xx_get_fw_size(ha) / 8; 1805 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1806 1807 for (i = 0; i < size; i++) { 1808 data = cpu_to_le64(ptr64[i]); 1809 1810 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1811 return -EIO; 1812 flashaddr += 8; 1813 } 1814 udelay(100); 1815 1816 /* Write a magic value to CAMRAM register 1817 * at a specified offset to indicate 1818 * that all data is written and 1819 * ready for firmware to initialize. 1820 */ 1821 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1822 1823 read_lock(&ha->hw_lock); 1824 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1825 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1826 read_unlock(&ha->hw_lock); 1827 return 0; 1828} 1829 1830static int 1831qla82xx_set_product_offset(struct qla_hw_data *ha) 1832{ 1833 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1834 const uint8_t *unirom = ha->hablob->fw->data; 1835 uint32_t i; 1836 __le32 entries; 1837 __le32 flags, file_chiprev, offset; 1838 uint8_t chiprev = ha->chip_revision; 1839 /* Hardcoding mn_present flag for P3P */ 1840 int mn_present = 0; 1841 uint32_t flagbit; 1842 1843 ptab_desc = qla82xx_get_table_desc(unirom, 1844 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1845 if (!ptab_desc) 1846 return -1; 1847 1848 entries = cpu_to_le32(ptab_desc->num_entries); 1849 1850 for (i = 0; i < entries; i++) { 1851 offset = cpu_to_le32(ptab_desc->findex) + 1852 (i * cpu_to_le32(ptab_desc->entry_size)); 1853 flags = cpu_to_le32(*((int *)&unirom[offset] + 1854 QLA82XX_URI_FLAGS_OFF)); 1855 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 1856 QLA82XX_URI_CHIP_REV_OFF)); 1857 1858 flagbit = mn_present ? 1 : 2; 1859 1860 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1861 ha->file_prd_off = offset; 1862 return 0; 1863 } 1864 } 1865 return -1; 1866} 1867 1868int 1869qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1870{ 1871 __le32 val; 1872 uint32_t min_size; 1873 struct qla_hw_data *ha = vha->hw; 1874 const struct firmware *fw = ha->hablob->fw; 1875 1876 ha->fw_type = fw_type; 1877 1878 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1879 if (qla82xx_set_product_offset(ha)) 1880 return -EINVAL; 1881 1882 min_size = QLA82XX_URI_FW_MIN_SIZE; 1883 } else { 1884 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1885 if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 1886 return -EINVAL; 1887 1888 min_size = QLA82XX_FW_MIN_SIZE; 1889 } 1890 1891 if (fw->size < min_size) 1892 return -EINVAL; 1893 return 0; 1894} 1895 1896static int 1897qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1898{ 1899 u32 val = 0; 1900 int retries = 60; 1901 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1902 1903 do { 1904 read_lock(&ha->hw_lock); 1905 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1906 read_unlock(&ha->hw_lock); 1907 1908 switch (val) { 1909 case PHAN_INITIALIZE_COMPLETE: 1910 case PHAN_INITIALIZE_ACK: 1911 return QLA_SUCCESS; 1912 case PHAN_INITIALIZE_FAILED: 1913 break; 1914 default: 1915 break; 1916 } 1917 ql_log(ql_log_info, vha, 0x00a8, 1918 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1919 val, retries); 1920 1921 msleep(500); 1922 1923 } while (--retries); 1924 1925 ql_log(ql_log_fatal, vha, 0x00a9, 1926 "Cmd Peg initialization failed: 0x%x.\n", val); 1927 1928 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1929 read_lock(&ha->hw_lock); 1930 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1931 read_unlock(&ha->hw_lock); 1932 return QLA_FUNCTION_FAILED; 1933} 1934 1935static int 1936qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1937{ 1938 u32 val = 0; 1939 int retries = 60; 1940 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1941 1942 do { 1943 read_lock(&ha->hw_lock); 1944 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1945 read_unlock(&ha->hw_lock); 1946 1947 switch (val) { 1948 case PHAN_INITIALIZE_COMPLETE: 1949 case PHAN_INITIALIZE_ACK: 1950 return QLA_SUCCESS; 1951 case PHAN_INITIALIZE_FAILED: 1952 break; 1953 default: 1954 break; 1955 } 1956 ql_log(ql_log_info, vha, 0x00ab, 1957 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1958 val, retries); 1959 1960 msleep(500); 1961 1962 } while (--retries); 1963 1964 ql_log(ql_log_fatal, vha, 0x00ac, 1965 "Rcv Peg initializatin failed: 0x%x.\n", val); 1966 read_lock(&ha->hw_lock); 1967 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1968 read_unlock(&ha->hw_lock); 1969 return QLA_FUNCTION_FAILED; 1970} 1971 1972/* ISR related functions */ 1973uint32_t qla82xx_isr_int_target_mask_enable[8] = { 1974 ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, 1975 ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, 1976 ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, 1977 ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 1978}; 1979 1980uint32_t qla82xx_isr_int_target_status[8] = { 1981 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, 1982 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, 1983 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, 1984 ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 1985}; 1986 1987static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1988 QLA82XX_LEGACY_INTR_CONFIG; 1989 1990/* 1991 * qla82xx_mbx_completion() - Process mailbox command completions. 1992 * @ha: SCSI driver HA context 1993 * @mb0: Mailbox0 register 1994 */ 1995static void 1996qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 1997{ 1998 uint16_t cnt; 1999 uint16_t __iomem *wptr; 2000 struct qla_hw_data *ha = vha->hw; 2001 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 2002 wptr = (uint16_t __iomem *)®->mailbox_out[1]; 2003 2004 /* Load return mailbox registers. */ 2005 ha->flags.mbox_int = 1; 2006 ha->mailbox_out[0] = mb0; 2007 2008 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2009 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 2010 wptr++; 2011 } 2012 2013 if (!ha->mcp) 2014 ql_dbg(ql_dbg_async, vha, 0x5053, 2015 "MBX pointer ERROR.\n"); 2016} 2017 2018/* 2019 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2020 * @irq: 2021 * @dev_id: SCSI driver HA context 2022 * @regs: 2023 * 2024 * Called by system whenever the host adapter generates an interrupt. 2025 * 2026 * Returns handled flag. 2027 */ 2028irqreturn_t 2029qla82xx_intr_handler(int irq, void *dev_id) 2030{ 2031 scsi_qla_host_t *vha; 2032 struct qla_hw_data *ha; 2033 struct rsp_que *rsp; 2034 struct device_reg_82xx __iomem *reg; 2035 int status = 0, status1 = 0; 2036 unsigned long flags; 2037 unsigned long iter; 2038 uint32_t stat = 0; 2039 uint16_t mb[4]; 2040 2041 rsp = (struct rsp_que *) dev_id; 2042 if (!rsp) { 2043 printk(KERN_INFO 2044 "%s(): NULL response queue pointer.\n", __func__); 2045 return IRQ_NONE; 2046 } 2047 ha = rsp->hw; 2048 2049 if (!ha->flags.msi_enabled) { 2050 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2051 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2052 return IRQ_NONE; 2053 2054 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2055 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2056 return IRQ_NONE; 2057 } 2058 2059 /* clear the interrupt */ 2060 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2061 2062 /* read twice to ensure write is flushed */ 2063 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2064 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2065 2066 reg = &ha->iobase->isp82; 2067 2068 spin_lock_irqsave(&ha->hardware_lock, flags); 2069 vha = pci_get_drvdata(ha->pdev); 2070 for (iter = 1; iter--; ) { 2071 2072 if (RD_REG_DWORD(®->host_int)) { 2073 stat = RD_REG_DWORD(®->host_status); 2074 2075 switch (stat & 0xff) { 2076 case 0x1: 2077 case 0x2: 2078 case 0x10: 2079 case 0x11: 2080 qla82xx_mbx_completion(vha, MSW(stat)); 2081 status |= MBX_INTERRUPT; 2082 break; 2083 case 0x12: 2084 mb[0] = MSW(stat); 2085 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2086 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2087 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2088 qla2x00_async_event(vha, rsp, mb); 2089 break; 2090 case 0x13: 2091 qla24xx_process_response_queue(vha, rsp); 2092 break; 2093 default: 2094 ql_dbg(ql_dbg_async, vha, 0x5054, 2095 "Unrecognized interrupt type (%d).\n", 2096 stat & 0xff); 2097 break; 2098 } 2099 } 2100 WRT_REG_DWORD(®->host_int, 0); 2101 } 2102 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2103 if (!ha->flags.msi_enabled) 2104 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2105 2106#ifdef QL_DEBUG_LEVEL_17 2107 if (!irq && ha->flags.eeh_busy) 2108 ql_log(ql_log_warn, vha, 0x503d, 2109 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2110 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2111#endif 2112 2113 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2114 (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2115 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2116 complete(&ha->mbx_intr_comp); 2117 } 2118 return IRQ_HANDLED; 2119} 2120 2121irqreturn_t 2122qla82xx_msix_default(int irq, void *dev_id) 2123{ 2124 scsi_qla_host_t *vha; 2125 struct qla_hw_data *ha; 2126 struct rsp_que *rsp; 2127 struct device_reg_82xx __iomem *reg; 2128 int status = 0; 2129 unsigned long flags; 2130 uint32_t stat = 0; 2131 uint16_t mb[4]; 2132 2133 rsp = (struct rsp_que *) dev_id; 2134 if (!rsp) { 2135 printk(KERN_INFO 2136 "%s(): NULL response queue pointer.\n", __func__); 2137 return IRQ_NONE; 2138 } 2139 ha = rsp->hw; 2140 2141 reg = &ha->iobase->isp82; 2142 2143 spin_lock_irqsave(&ha->hardware_lock, flags); 2144 vha = pci_get_drvdata(ha->pdev); 2145 do { 2146 if (RD_REG_DWORD(®->host_int)) { 2147 stat = RD_REG_DWORD(®->host_status); 2148 2149 switch (stat & 0xff) { 2150 case 0x1: 2151 case 0x2: 2152 case 0x10: 2153 case 0x11: 2154 qla82xx_mbx_completion(vha, MSW(stat)); 2155 status |= MBX_INTERRUPT; 2156 break; 2157 case 0x12: 2158 mb[0] = MSW(stat); 2159 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2160 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2161 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2162 qla2x00_async_event(vha, rsp, mb); 2163 break; 2164 case 0x13: 2165 qla24xx_process_response_queue(vha, rsp); 2166 break; 2167 default: 2168 ql_dbg(ql_dbg_async, vha, 0x5041, 2169 "Unrecognized interrupt type (%d).\n", 2170 stat & 0xff); 2171 break; 2172 } 2173 } 2174 WRT_REG_DWORD(®->host_int, 0); 2175 } while (0); 2176 2177 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2178 2179#ifdef QL_DEBUG_LEVEL_17 2180 if (!irq && ha->flags.eeh_busy) 2181 ql_log(ql_log_warn, vha, 0x5044, 2182 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2183 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2184#endif 2185 2186 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2187 (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2188 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2189 complete(&ha->mbx_intr_comp); 2190 } 2191 return IRQ_HANDLED; 2192} 2193 2194irqreturn_t 2195qla82xx_msix_rsp_q(int irq, void *dev_id) 2196{ 2197 scsi_qla_host_t *vha; 2198 struct qla_hw_data *ha; 2199 struct rsp_que *rsp; 2200 struct device_reg_82xx __iomem *reg; 2201 unsigned long flags; 2202 2203 rsp = (struct rsp_que *) dev_id; 2204 if (!rsp) { 2205 printk(KERN_INFO 2206 "%s(): NULL response queue pointer.\n", __func__); 2207 return IRQ_NONE; 2208 } 2209 2210 ha = rsp->hw; 2211 reg = &ha->iobase->isp82; 2212 spin_lock_irqsave(&ha->hardware_lock, flags); 2213 vha = pci_get_drvdata(ha->pdev); 2214 qla24xx_process_response_queue(vha, rsp); 2215 WRT_REG_DWORD(®->host_int, 0); 2216 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2217 return IRQ_HANDLED; 2218} 2219 2220void 2221qla82xx_poll(int irq, void *dev_id) 2222{ 2223 scsi_qla_host_t *vha; 2224 struct qla_hw_data *ha; 2225 struct rsp_que *rsp; 2226 struct device_reg_82xx __iomem *reg; 2227 int status = 0; 2228 uint32_t stat; 2229 uint16_t mb[4]; 2230 unsigned long flags; 2231 2232 rsp = (struct rsp_que *) dev_id; 2233 if (!rsp) { 2234 printk(KERN_INFO 2235 "%s(): NULL response queue pointer.\n", __func__); 2236 return; 2237 } 2238 ha = rsp->hw; 2239 2240 reg = &ha->iobase->isp82; 2241 spin_lock_irqsave(&ha->hardware_lock, flags); 2242 vha = pci_get_drvdata(ha->pdev); 2243 2244 if (RD_REG_DWORD(®->host_int)) { 2245 stat = RD_REG_DWORD(®->host_status); 2246 switch (stat & 0xff) { 2247 case 0x1: 2248 case 0x2: 2249 case 0x10: 2250 case 0x11: 2251 qla82xx_mbx_completion(vha, MSW(stat)); 2252 status |= MBX_INTERRUPT; 2253 break; 2254 case 0x12: 2255 mb[0] = MSW(stat); 2256 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2257 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2258 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2259 qla2x00_async_event(vha, rsp, mb); 2260 break; 2261 case 0x13: 2262 qla24xx_process_response_queue(vha, rsp); 2263 break; 2264 default: 2265 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2266 "Unrecognized interrupt type (%d).\n", 2267 stat * 0xff); 2268 break; 2269 } 2270 } 2271 WRT_REG_DWORD(®->host_int, 0); 2272 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2273} 2274 2275void 2276qla82xx_enable_intrs(struct qla_hw_data *ha) 2277{ 2278 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2279 qla82xx_mbx_intr_enable(vha); 2280 spin_lock_irq(&ha->hardware_lock); 2281 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2282 spin_unlock_irq(&ha->hardware_lock); 2283 ha->interrupts_on = 1; 2284} 2285 2286void 2287qla82xx_disable_intrs(struct qla_hw_data *ha) 2288{ 2289 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2290 qla82xx_mbx_intr_disable(vha); 2291 spin_lock_irq(&ha->hardware_lock); 2292 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2293 spin_unlock_irq(&ha->hardware_lock); 2294 ha->interrupts_on = 0; 2295} 2296 2297void qla82xx_init_flags(struct qla_hw_data *ha) 2298{ 2299 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2300 2301 /* ISP 8021 initializations */ 2302 rwlock_init(&ha->hw_lock); 2303 ha->qdr_sn_window = -1; 2304 ha->ddr_mn_window = -1; 2305 ha->curr_window = 255; 2306 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2307 nx_legacy_intr = &legacy_intr[ha->portnum]; 2308 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2309 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2310 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2311 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2312} 2313 2314inline void 2315qla82xx_set_drv_active(scsi_qla_host_t *vha) 2316{ 2317 uint32_t drv_active; 2318 struct qla_hw_data *ha = vha->hw; 2319 2320 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2321 2322 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2323 if (drv_active == 0xffffffff) { 2324 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2325 QLA82XX_DRV_NOT_ACTIVE); 2326 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2327 } 2328 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2329 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2330} 2331 2332inline void 2333qla82xx_clear_drv_active(struct qla_hw_data *ha) 2334{ 2335 uint32_t drv_active; 2336 2337 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2338 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2339 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2340} 2341 2342static inline int 2343qla82xx_need_reset(struct qla_hw_data *ha) 2344{ 2345 uint32_t drv_state; 2346 int rval; 2347 2348 if (ha->flags.isp82xx_reset_owner) 2349 return 1; 2350 else { 2351 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2352 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2353 return rval; 2354 } 2355} 2356 2357static inline void 2358qla82xx_set_rst_ready(struct qla_hw_data *ha) 2359{ 2360 uint32_t drv_state; 2361 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2362 2363 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2364 2365 /* If reset value is all FF's, initialize DRV_STATE */ 2366 if (drv_state == 0xffffffff) { 2367 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2368 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2369 } 2370 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2371 ql_dbg(ql_dbg_init, vha, 0x00bb, 2372 "drv_state = 0x%08x.\n", drv_state); 2373 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2374} 2375 2376static inline void 2377qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2378{ 2379 uint32_t drv_state; 2380 2381 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2382 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2383 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2384} 2385 2386static inline void 2387qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2388{ 2389 uint32_t qsnt_state; 2390 2391 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2392 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2393 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2394} 2395 2396void 2397qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2398{ 2399 struct qla_hw_data *ha = vha->hw; 2400 uint32_t qsnt_state; 2401 2402 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2403 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2404 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2405} 2406 2407static int 2408qla82xx_load_fw(scsi_qla_host_t *vha) 2409{ 2410 int rst; 2411 struct fw_blob *blob; 2412 struct qla_hw_data *ha = vha->hw; 2413 2414 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2415 ql_log(ql_log_fatal, vha, 0x009f, 2416 "Error during CRB initialization.\n"); 2417 return QLA_FUNCTION_FAILED; 2418 } 2419 udelay(500); 2420 2421 /* Bring QM and CAMRAM out of reset */ 2422 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2423 rst &= ~((1 << 28) | (1 << 24)); 2424 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2425 2426 /* 2427 * FW Load priority: 2428 * 1) Operational firmware residing in flash. 2429 * 2) Firmware via request-firmware interface (.bin file). 2430 */ 2431 if (ql2xfwloadbin == 2) 2432 goto try_blob_fw; 2433 2434 ql_log(ql_log_info, vha, 0x00a0, 2435 "Attempting to load firmware from flash.\n"); 2436 2437 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2438 ql_log(ql_log_info, vha, 0x00a1, 2439 "Firmware loaded successully from flash.\n"); 2440 return QLA_SUCCESS; 2441 } else { 2442 ql_log(ql_log_warn, vha, 0x0108, 2443 "Firmware load from flash failed.\n"); 2444 } 2445 2446try_blob_fw: 2447 ql_log(ql_log_info, vha, 0x00a2, 2448 "Attempting to load firmware from blob.\n"); 2449 2450 /* Load firmware blob. */ 2451 blob = ha->hablob = qla2x00_request_firmware(vha); 2452 if (!blob) { 2453 ql_log(ql_log_fatal, vha, 0x00a3, 2454 "Firmware image not preset.\n"); 2455 goto fw_load_failed; 2456 } 2457 2458 /* Validating firmware blob */ 2459 if (qla82xx_validate_firmware_blob(vha, 2460 QLA82XX_FLASH_ROMIMAGE)) { 2461 /* Fallback to URI format */ 2462 if (qla82xx_validate_firmware_blob(vha, 2463 QLA82XX_UNIFIED_ROMIMAGE)) { 2464 ql_log(ql_log_fatal, vha, 0x00a4, 2465 "No valid firmware image found.\n"); 2466 return QLA_FUNCTION_FAILED; 2467 } 2468 } 2469 2470 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2471 ql_log(ql_log_info, vha, 0x00a5, 2472 "Firmware loaded successfully from binary blob.\n"); 2473 return QLA_SUCCESS; 2474 } else { 2475 ql_log(ql_log_fatal, vha, 0x00a6, 2476 "Firmware load failed for binary blob.\n"); 2477 blob->fw = NULL; 2478 blob = NULL; 2479 goto fw_load_failed; 2480 } 2481 return QLA_SUCCESS; 2482 2483fw_load_failed: 2484 return QLA_FUNCTION_FAILED; 2485} 2486 2487int 2488qla82xx_start_firmware(scsi_qla_host_t *vha) 2489{ 2490 int pcie_cap; 2491 uint16_t lnk; 2492 struct qla_hw_data *ha = vha->hw; 2493 2494 /* scrub dma mask expansion register */ 2495 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2496 2497 /* Put both the PEG CMD and RCV PEG to default state 2498 * of 0 before resetting the hardware 2499 */ 2500 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2501 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2502 2503 /* Overwrite stale initialization register values */ 2504 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2505 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2506 2507 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2508 ql_log(ql_log_fatal, vha, 0x00a7, 2509 "Error trying to start fw.\n"); 2510 return QLA_FUNCTION_FAILED; 2511 } 2512 2513 /* Handshake with the card before we register the devices. */ 2514 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2515 ql_log(ql_log_fatal, vha, 0x00aa, 2516 "Error during card handshake.\n"); 2517 return QLA_FUNCTION_FAILED; 2518 } 2519 2520 /* Negotiated Link width */ 2521 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 2522 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 2523 ha->link_width = (lnk >> 4) & 0x3f; 2524 2525 /* Synchronize with Receive peg */ 2526 return qla82xx_check_rcvpeg_state(ha); 2527} 2528 2529static uint32_t * 2530qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2531 uint32_t length) 2532{ 2533 uint32_t i; 2534 uint32_t val; 2535 struct qla_hw_data *ha = vha->hw; 2536 2537 /* Dword reads to flash. */ 2538 for (i = 0; i < length/4; i++, faddr += 4) { 2539 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2540 ql_log(ql_log_warn, vha, 0x0106, 2541 "Do ROM fast read failed.\n"); 2542 goto done_read; 2543 } 2544 dwptr[i] = __constant_cpu_to_le32(val); 2545 } 2546done_read: 2547 return dwptr; 2548} 2549 2550static int 2551qla82xx_unprotect_flash(struct qla_hw_data *ha) 2552{ 2553 int ret; 2554 uint32_t val; 2555 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2556 2557 ret = ql82xx_rom_lock_d(ha); 2558 if (ret < 0) { 2559 ql_log(ql_log_warn, vha, 0xb014, 2560 "ROM Lock failed.\n"); 2561 return ret; 2562 } 2563 2564 ret = qla82xx_read_status_reg(ha, &val); 2565 if (ret < 0) 2566 goto done_unprotect; 2567 2568 val &= ~(BLOCK_PROTECT_BITS << 2); 2569 ret = qla82xx_write_status_reg(ha, val); 2570 if (ret < 0) { 2571 val |= (BLOCK_PROTECT_BITS << 2); 2572 qla82xx_write_status_reg(ha, val); 2573 } 2574 2575 if (qla82xx_write_disable_flash(ha) != 0) 2576 ql_log(ql_log_warn, vha, 0xb015, 2577 "Write disable failed.\n"); 2578 2579done_unprotect: 2580 qla82xx_rom_unlock(ha); 2581 return ret; 2582} 2583 2584static int 2585qla82xx_protect_flash(struct qla_hw_data *ha) 2586{ 2587 int ret; 2588 uint32_t val; 2589 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2590 2591 ret = ql82xx_rom_lock_d(ha); 2592 if (ret < 0) { 2593 ql_log(ql_log_warn, vha, 0xb016, 2594 "ROM Lock failed.\n"); 2595 return ret; 2596 } 2597 2598 ret = qla82xx_read_status_reg(ha, &val); 2599 if (ret < 0) 2600 goto done_protect; 2601 2602 val |= (BLOCK_PROTECT_BITS << 2); 2603 /* LOCK all sectors */ 2604 ret = qla82xx_write_status_reg(ha, val); 2605 if (ret < 0) 2606 ql_log(ql_log_warn, vha, 0xb017, 2607 "Write status register failed.\n"); 2608 2609 if (qla82xx_write_disable_flash(ha) != 0) 2610 ql_log(ql_log_warn, vha, 0xb018, 2611 "Write disable failed.\n"); 2612done_protect: 2613 qla82xx_rom_unlock(ha); 2614 return ret; 2615} 2616 2617static int 2618qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2619{ 2620 int ret = 0; 2621 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2622 2623 ret = ql82xx_rom_lock_d(ha); 2624 if (ret < 0) { 2625 ql_log(ql_log_warn, vha, 0xb019, 2626 "ROM Lock failed.\n"); 2627 return ret; 2628 } 2629 2630 qla82xx_flash_set_write_enable(ha); 2631 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2632 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2633 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2634 2635 if (qla82xx_wait_rom_done(ha)) { 2636 ql_log(ql_log_warn, vha, 0xb01a, 2637 "Error waiting for rom done.\n"); 2638 ret = -1; 2639 goto done; 2640 } 2641 ret = qla82xx_flash_wait_write_finish(ha); 2642done: 2643 qla82xx_rom_unlock(ha); 2644 return ret; 2645} 2646 2647/* 2648 * Address and length are byte address 2649 */ 2650uint8_t * 2651qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2652 uint32_t offset, uint32_t length) 2653{ 2654 scsi_block_requests(vha->host); 2655 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2656 scsi_unblock_requests(vha->host); 2657 return buf; 2658} 2659 2660static int 2661qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2662 uint32_t faddr, uint32_t dwords) 2663{ 2664 int ret; 2665 uint32_t liter; 2666 uint32_t sec_mask, rest_addr; 2667 dma_addr_t optrom_dma; 2668 void *optrom = NULL; 2669 int page_mode = 0; 2670 struct qla_hw_data *ha = vha->hw; 2671 2672 ret = -1; 2673 2674 /* Prepare burst-capable write on supported ISPs. */ 2675 if (page_mode && !(faddr & 0xfff) && 2676 dwords > OPTROM_BURST_DWORDS) { 2677 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2678 &optrom_dma, GFP_KERNEL); 2679 if (!optrom) { 2680 ql_log(ql_log_warn, vha, 0xb01b, 2681 "Unable to allocate memory " 2682 "for optron burst write (%x KB).\n", 2683 OPTROM_BURST_SIZE / 1024); 2684 } 2685 } 2686 2687 rest_addr = ha->fdt_block_size - 1; 2688 sec_mask = ~rest_addr; 2689 2690 ret = qla82xx_unprotect_flash(ha); 2691 if (ret) { 2692 ql_log(ql_log_warn, vha, 0xb01c, 2693 "Unable to unprotect flash for update.\n"); 2694 goto write_done; 2695 } 2696 2697 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2698 /* Are we at the beginning of a sector? */ 2699 if ((faddr & rest_addr) == 0) { 2700 2701 ret = qla82xx_erase_sector(ha, faddr); 2702 if (ret) { 2703 ql_log(ql_log_warn, vha, 0xb01d, 2704 "Unable to erase sector: address=%x.\n", 2705 faddr); 2706 break; 2707 } 2708 } 2709 2710 /* Go with burst-write. */ 2711 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2712 /* Copy data to DMA'ble buffer. */ 2713 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2714 2715 ret = qla2x00_load_ram(vha, optrom_dma, 2716 (ha->flash_data_off | faddr), 2717 OPTROM_BURST_DWORDS); 2718 if (ret != QLA_SUCCESS) { 2719 ql_log(ql_log_warn, vha, 0xb01e, 2720 "Unable to burst-write optrom segment " 2721 "(%x/%x/%llx).\n", ret, 2722 (ha->flash_data_off | faddr), 2723 (unsigned long long)optrom_dma); 2724 ql_log(ql_log_warn, vha, 0xb01f, 2725 "Reverting to slow-write.\n"); 2726 2727 dma_free_coherent(&ha->pdev->dev, 2728 OPTROM_BURST_SIZE, optrom, optrom_dma); 2729 optrom = NULL; 2730 } else { 2731 liter += OPTROM_BURST_DWORDS - 1; 2732 faddr += OPTROM_BURST_DWORDS - 1; 2733 dwptr += OPTROM_BURST_DWORDS - 1; 2734 continue; 2735 } 2736 } 2737 2738 ret = qla82xx_write_flash_dword(ha, faddr, 2739 cpu_to_le32(*dwptr)); 2740 if (ret) { 2741 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2742 "Unable to program flash address=%x data=%x.\n", 2743 faddr, *dwptr); 2744 break; 2745 } 2746 } 2747 2748 ret = qla82xx_protect_flash(ha); 2749 if (ret) 2750 ql_log(ql_log_warn, vha, 0xb021, 2751 "Unable to protect flash after update.\n"); 2752write_done: 2753 if (optrom) 2754 dma_free_coherent(&ha->pdev->dev, 2755 OPTROM_BURST_SIZE, optrom, optrom_dma); 2756 return ret; 2757} 2758 2759int 2760qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2761 uint32_t offset, uint32_t length) 2762{ 2763 int rval; 2764 2765 /* Suspend HBA. */ 2766 scsi_block_requests(vha->host); 2767 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2768 length >> 2); 2769 scsi_unblock_requests(vha->host); 2770 2771 /* Convert return ISP82xx to generic */ 2772 if (rval) 2773 rval = QLA_FUNCTION_FAILED; 2774 else 2775 rval = QLA_SUCCESS; 2776 return rval; 2777} 2778 2779void 2780qla82xx_start_iocbs(scsi_qla_host_t *vha) 2781{ 2782 struct qla_hw_data *ha = vha->hw; 2783 struct req_que *req = ha->req_q_map[0]; 2784 struct device_reg_82xx __iomem *reg; 2785 uint32_t dbval; 2786 2787 /* Adjust ring index. */ 2788 req->ring_index++; 2789 if (req->ring_index == req->length) { 2790 req->ring_index = 0; 2791 req->ring_ptr = req->ring; 2792 } else 2793 req->ring_ptr++; 2794 2795 reg = &ha->iobase->isp82; 2796 dbval = 0x04 | (ha->portnum << 5); 2797 2798 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2799 if (ql2xdbwr) 2800 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2801 else { 2802 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2803 wmb(); 2804 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 2805 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 2806 dbval); 2807 wmb(); 2808 } 2809 } 2810} 2811 2812void qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2813{ 2814 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2815 2816 if (qla82xx_rom_lock(ha)) 2817 /* Someone else is holding the lock. */ 2818 ql_log(ql_log_info, vha, 0xb022, 2819 "Resetting rom_lock.\n"); 2820 2821 /* 2822 * Either we got the lock, or someone 2823 * else died while holding it. 2824 * In either case, unlock. 2825 */ 2826 qla82xx_rom_unlock(ha); 2827} 2828 2829/* 2830 * qla82xx_device_bootstrap 2831 * Initialize device, set DEV_READY, start fw 2832 * 2833 * Note: 2834 * IDC lock must be held upon entry 2835 * 2836 * Return: 2837 * Success : 0 2838 * Failed : 1 2839 */ 2840static int 2841qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2842{ 2843 int rval = QLA_SUCCESS; 2844 int i, timeout; 2845 uint32_t old_count, count; 2846 struct qla_hw_data *ha = vha->hw; 2847 int need_reset = 0, peg_stuck = 1; 2848 2849 need_reset = qla82xx_need_reset(ha); 2850 2851 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2852 2853 for (i = 0; i < 10; i++) { 2854 timeout = msleep_interruptible(200); 2855 if (timeout) { 2856 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2857 QLA82XX_DEV_FAILED); 2858 return QLA_FUNCTION_FAILED; 2859 } 2860 2861 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2862 if (count != old_count) 2863 peg_stuck = 0; 2864 } 2865 2866 if (need_reset) { 2867 /* We are trying to perform a recovery here. */ 2868 if (peg_stuck) 2869 qla82xx_rom_lock_recovery(ha); 2870 goto dev_initialize; 2871 } else { 2872 /* Start of day for this ha context. */ 2873 if (peg_stuck) { 2874 /* Either we are the first or recovery in progress. */ 2875 qla82xx_rom_lock_recovery(ha); 2876 goto dev_initialize; 2877 } else 2878 /* Firmware already running. */ 2879 goto dev_ready; 2880 } 2881 2882 return rval; 2883 2884dev_initialize: 2885 /* set to DEV_INITIALIZING */ 2886 ql_log(ql_log_info, vha, 0x009e, 2887 "HW State: INITIALIZING.\n"); 2888 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 2889 2890 /* Driver that sets device state to initializating sets IDC version */ 2891 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 2892 2893 qla82xx_idc_unlock(ha); 2894 rval = qla82xx_start_firmware(vha); 2895 qla82xx_idc_lock(ha); 2896 2897 if (rval != QLA_SUCCESS) { 2898 ql_log(ql_log_fatal, vha, 0x00ad, 2899 "HW State: FAILED.\n"); 2900 qla82xx_clear_drv_active(ha); 2901 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 2902 return rval; 2903 } 2904 2905dev_ready: 2906 ql_log(ql_log_info, vha, 0x00ae, 2907 "HW State: READY.\n"); 2908 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 2909 2910 return QLA_SUCCESS; 2911} 2912 2913/* 2914* qla82xx_need_qsnt_handler 2915* Code to start quiescence sequence 2916* 2917* Note: 2918* IDC lock must be held upon entry 2919* 2920* Return: void 2921*/ 2922 2923static void 2924qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2925{ 2926 struct qla_hw_data *ha = vha->hw; 2927 uint32_t dev_state, drv_state, drv_active; 2928 unsigned long reset_timeout; 2929 2930 if (vha->flags.online) { 2931 /*Block any further I/O and wait for pending cmnds to complete*/ 2932 qla82xx_quiescent_state_cleanup(vha); 2933 } 2934 2935 /* Set the quiescence ready bit */ 2936 qla82xx_set_qsnt_ready(ha); 2937 2938 /*wait for 30 secs for other functions to ack */ 2939 reset_timeout = jiffies + (30 * HZ); 2940 2941 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2942 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2943 /* Its 2 that is written when qsnt is acked, moving one bit */ 2944 drv_active = drv_active << 0x01; 2945 2946 while (drv_state != drv_active) { 2947 2948 if (time_after_eq(jiffies, reset_timeout)) { 2949 /* quiescence timeout, other functions didn't ack 2950 * changing the state to DEV_READY 2951 */ 2952 ql_log(ql_log_info, vha, 0xb023, 2953 "%s : QUIESCENT TIMEOUT.\n", QLA2XXX_DRIVER_NAME); 2954 ql_log(ql_log_info, vha, 0xb024, 2955 "DRV_ACTIVE:%d DRV_STATE:%d.\n", 2956 drv_active, drv_state); 2957 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2958 QLA82XX_DEV_READY); 2959 ql_log(ql_log_info, vha, 0xb025, 2960 "HW State: DEV_READY.\n"); 2961 qla82xx_idc_unlock(ha); 2962 qla2x00_perform_loop_resync(vha); 2963 qla82xx_idc_lock(ha); 2964 2965 qla82xx_clear_qsnt_ready(vha); 2966 return; 2967 } 2968 2969 qla82xx_idc_unlock(ha); 2970 msleep(1000); 2971 qla82xx_idc_lock(ha); 2972 2973 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2974 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2975 drv_active = drv_active << 0x01; 2976 } 2977 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2978 /* everyone acked so set the state to DEV_QUIESCENCE */ 2979 if (dev_state == QLA82XX_DEV_NEED_QUIESCENT) { 2980 ql_log(ql_log_info, vha, 0xb026, 2981 "HW State: DEV_QUIESCENT.\n"); 2982 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_QUIESCENT); 2983 } 2984} 2985 2986/* 2987* qla82xx_wait_for_state_change 2988* Wait for device state to change from given current state 2989* 2990* Note: 2991* IDC lock must not be held upon entry 2992* 2993* Return: 2994* Changed device state. 2995*/ 2996uint32_t 2997qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 2998{ 2999 struct qla_hw_data *ha = vha->hw; 3000 uint32_t dev_state; 3001 3002 do { 3003 msleep(1000); 3004 qla82xx_idc_lock(ha); 3005 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3006 qla82xx_idc_unlock(ha); 3007 } while (dev_state == curr_state); 3008 3009 return dev_state; 3010} 3011 3012static void 3013qla82xx_dev_failed_handler(scsi_qla_host_t *vha) 3014{ 3015 struct qla_hw_data *ha = vha->hw; 3016 3017 /* Disable the board */ 3018 ql_log(ql_log_fatal, vha, 0x00b8, 3019 "Disabling the board.\n"); 3020 3021 qla82xx_idc_lock(ha); 3022 qla82xx_clear_drv_active(ha); 3023 qla82xx_idc_unlock(ha); 3024 3025 /* Set DEV_FAILED flag to disable timer */ 3026 vha->device_flags |= DFLG_DEV_FAILED; 3027 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3028 qla2x00_mark_all_devices_lost(vha, 0); 3029 vha->flags.online = 0; 3030 vha->flags.init_done = 0; 3031} 3032 3033/* 3034 * qla82xx_need_reset_handler 3035 * Code to start reset sequence 3036 * 3037 * Note: 3038 * IDC lock must be held upon entry 3039 * 3040 * Return: 3041 * Success : 0 3042 * Failed : 1 3043 */ 3044static void 3045qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3046{ 3047 uint32_t dev_state, drv_state, drv_active; 3048 uint32_t active_mask = 0; 3049 unsigned long reset_timeout; 3050 struct qla_hw_data *ha = vha->hw; 3051 struct req_que *req = ha->req_q_map[0]; 3052 3053 if (vha->flags.online) { 3054 qla82xx_idc_unlock(ha); 3055 qla2x00_abort_isp_cleanup(vha); 3056 ha->isp_ops->get_flash_version(vha, req->ring); 3057 ha->isp_ops->nvram_config(vha); 3058 qla82xx_idc_lock(ha); 3059 } 3060 3061 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3062 if (!ha->flags.isp82xx_reset_owner) { 3063 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3064 "reset_acknowledged by 0x%x\n", ha->portnum); 3065 qla82xx_set_rst_ready(ha); 3066 } else { 3067 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3068 drv_active &= active_mask; 3069 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3070 "active_mask: 0x%08x\n", active_mask); 3071 } 3072 3073 /* wait for 10 seconds for reset ack from all functions */ 3074 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3075 3076 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3077 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3078 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3079 3080 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3081 "drv_state: 0x%08x, drv_active: 0x%08x, " 3082 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3083 drv_state, drv_active, dev_state, active_mask); 3084 3085 while (drv_state != drv_active && 3086 dev_state != QLA82XX_DEV_INITIALIZING) { 3087 if (time_after_eq(jiffies, reset_timeout)) { 3088 ql_log(ql_log_warn, vha, 0x00b5, 3089 "Reset timeout.\n"); 3090 break; 3091 } 3092 qla82xx_idc_unlock(ha); 3093 msleep(1000); 3094 qla82xx_idc_lock(ha); 3095 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3096 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3097 if (ha->flags.isp82xx_reset_owner) 3098 drv_active &= active_mask; 3099 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3100 } 3101 3102 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3103 "drv_state: 0x%08x, drv_active: 0x%08x, " 3104 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3105 drv_state, drv_active, dev_state, active_mask); 3106 3107 ql_log(ql_log_info, vha, 0x00b6, 3108 "Device state is 0x%x = %s.\n", 3109 dev_state, 3110 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3111 3112 /* Force to DEV_COLD unless someone else is starting a reset */ 3113 if (dev_state != QLA82XX_DEV_INITIALIZING && 3114 dev_state != QLA82XX_DEV_COLD) { 3115 ql_log(ql_log_info, vha, 0x00b7, 3116 "HW State: COLD/RE-INIT.\n"); 3117 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 3118 if (ql2xmdenable) { 3119 if (qla82xx_md_collect(vha)) 3120 ql_log(ql_log_warn, vha, 0xb02c, 3121 "Not able to collect minidump.\n"); 3122 } else 3123 ql_log(ql_log_warn, vha, 0xb04f, 3124 "Minidump disabled.\n"); 3125 } 3126} 3127 3128int 3129qla82xx_check_md_needed(scsi_qla_host_t *vha) 3130{ 3131 struct qla_hw_data *ha = vha->hw; 3132 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3133 int rval = QLA_SUCCESS; 3134 3135 fw_major_version = ha->fw_major_version; 3136 fw_minor_version = ha->fw_minor_version; 3137 fw_subminor_version = ha->fw_subminor_version; 3138 3139 rval = qla2x00_get_fw_version(vha); 3140 if (rval != QLA_SUCCESS) 3141 return rval; 3142 3143 if (ql2xmdenable) { 3144 if (!ha->fw_dumped) { 3145 if (fw_major_version != ha->fw_major_version || 3146 fw_minor_version != ha->fw_minor_version || 3147 fw_subminor_version != ha->fw_subminor_version) { 3148 ql_log(ql_log_info, vha, 0xb02d, 3149 "Firmware version differs " 3150 "Previous version: %d:%d:%d - " 3151 "New version: %d:%d:%d\n", 3152 ha->fw_major_version, 3153 ha->fw_minor_version, 3154 ha->fw_subminor_version, 3155 fw_major_version, fw_minor_version, 3156 fw_subminor_version); 3157 /* Release MiniDump resources */ 3158 qla82xx_md_free(vha); 3159 /* ALlocate MiniDump resources */ 3160 qla82xx_md_prep(vha); 3161 } 3162 } else 3163 ql_log(ql_log_info, vha, 0xb02e, 3164 "Firmware dump available to retrieve\n"); 3165 } 3166 return rval; 3167} 3168 3169 3170int 3171qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3172{ 3173 uint32_t fw_heartbeat_counter; 3174 int status = 0; 3175 3176 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3177 QLA82XX_PEG_ALIVE_COUNTER); 3178 /* all 0xff, assume AER/EEH in progress, ignore */ 3179 if (fw_heartbeat_counter == 0xffffffff) { 3180 ql_dbg(ql_dbg_timer, vha, 0x6003, 3181 "FW heartbeat counter is 0xffffffff, " 3182 "returning status=%d.\n", status); 3183 return status; 3184 } 3185 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3186 vha->seconds_since_last_heartbeat++; 3187 /* FW not alive after 2 seconds */ 3188 if (vha->seconds_since_last_heartbeat == 2) { 3189 vha->seconds_since_last_heartbeat = 0; 3190 status = 1; 3191 } 3192 } else 3193 vha->seconds_since_last_heartbeat = 0; 3194 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3195 if (status) 3196 ql_dbg(ql_dbg_timer, vha, 0x6004, 3197 "Returning status=%d.\n", status); 3198 return status; 3199} 3200 3201/* 3202 * qla82xx_device_state_handler 3203 * Main state handler 3204 * 3205 * Note: 3206 * IDC lock must be held upon entry 3207 * 3208 * Return: 3209 * Success : 0 3210 * Failed : 1 3211 */ 3212int 3213qla82xx_device_state_handler(scsi_qla_host_t *vha) 3214{ 3215 uint32_t dev_state; 3216 uint32_t old_dev_state; 3217 int rval = QLA_SUCCESS; 3218 unsigned long dev_init_timeout; 3219 struct qla_hw_data *ha = vha->hw; 3220 int loopcount = 0; 3221 3222 qla82xx_idc_lock(ha); 3223 if (!vha->flags.init_done) 3224 qla82xx_set_drv_active(vha); 3225 3226 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3227 old_dev_state = dev_state; 3228 ql_log(ql_log_info, vha, 0x009b, 3229 "Device state is 0x%x = %s.\n", 3230 dev_state, 3231 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3232 3233 /* wait for 30 seconds for device to go ready */ 3234 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3235 3236 while (1) { 3237 3238 if (time_after_eq(jiffies, dev_init_timeout)) { 3239 ql_log(ql_log_fatal, vha, 0x009c, 3240 "Device init failed.\n"); 3241 rval = QLA_FUNCTION_FAILED; 3242 break; 3243 } 3244 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3245 if (old_dev_state != dev_state) { 3246 loopcount = 0; 3247 old_dev_state = dev_state; 3248 } 3249 if (loopcount < 5) { 3250 ql_log(ql_log_info, vha, 0x009d, 3251 "Device state is 0x%x = %s.\n", 3252 dev_state, 3253 dev_state < MAX_STATES ? qdev_state(dev_state) : 3254 "Unknown"); 3255 } 3256 3257 switch (dev_state) { 3258 case QLA82XX_DEV_READY: 3259 ha->flags.isp82xx_reset_owner = 0; 3260 goto exit; 3261 case QLA82XX_DEV_COLD: 3262 rval = qla82xx_device_bootstrap(vha); 3263 break; 3264 case QLA82XX_DEV_INITIALIZING: 3265 qla82xx_idc_unlock(ha); 3266 msleep(1000); 3267 qla82xx_idc_lock(ha); 3268 break; 3269 case QLA82XX_DEV_NEED_RESET: 3270 if (!ql2xdontresethba) 3271 qla82xx_need_reset_handler(vha); 3272 else { 3273 qla82xx_idc_unlock(ha); 3274 msleep(1000); 3275 qla82xx_idc_lock(ha); 3276 } 3277 dev_init_timeout = jiffies + 3278 (ha->nx_dev_init_timeout * HZ); 3279 break; 3280 case QLA82XX_DEV_NEED_QUIESCENT: 3281 qla82xx_need_qsnt_handler(vha); 3282 /* Reset timeout value after quiescence handler */ 3283 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3284 * HZ); 3285 break; 3286 case QLA82XX_DEV_QUIESCENT: 3287 /* Owner will exit and other will wait for the state 3288 * to get changed 3289 */ 3290 if (ha->flags.quiesce_owner) 3291 goto exit; 3292 3293 qla82xx_idc_unlock(ha); 3294 msleep(1000); 3295 qla82xx_idc_lock(ha); 3296 3297 /* Reset timeout value after quiescence handler */ 3298 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3299 * HZ); 3300 break; 3301 case QLA82XX_DEV_FAILED: 3302 qla82xx_dev_failed_handler(vha); 3303 rval = QLA_FUNCTION_FAILED; 3304 goto exit; 3305 default: 3306 qla82xx_idc_unlock(ha); 3307 msleep(1000); 3308 qla82xx_idc_lock(ha); 3309 } 3310 loopcount++; 3311 } 3312exit: 3313 qla82xx_idc_unlock(ha); 3314 return rval; 3315} 3316 3317void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3318{ 3319 struct qla_hw_data *ha = vha->hw; 3320 3321 if (ha->flags.mbox_busy) { 3322 ha->flags.mbox_int = 1; 3323 ha->flags.mbox_busy = 0; 3324 ql_log(ql_log_warn, vha, 0x6010, 3325 "Doing premature completion of mbx command.\n"); 3326 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3327 complete(&ha->mbx_intr_comp); 3328 } 3329} 3330 3331void qla82xx_watchdog(scsi_qla_host_t *vha) 3332{ 3333 uint32_t dev_state, halt_status; 3334 struct qla_hw_data *ha = vha->hw; 3335 3336 /* don't poll if reset is going on */ 3337 if (!ha->flags.isp82xx_reset_hdlr_active) { 3338 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3339 if (dev_state == QLA82XX_DEV_NEED_RESET && 3340 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3341 ql_log(ql_log_warn, vha, 0x6001, 3342 "Adapter reset needed.\n"); 3343 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3344 qla2xxx_wake_dpc(vha); 3345 } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT && 3346 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3347 ql_log(ql_log_warn, vha, 0x6002, 3348 "Quiescent needed.\n"); 3349 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3350 qla2xxx_wake_dpc(vha); 3351 } else { 3352 if (qla82xx_check_fw_alive(vha)) { 3353 ql_dbg(ql_dbg_timer, vha, 0x6011, 3354 "disabling pause transmit on port 0 & 1.\n"); 3355 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3356 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3357 halt_status = qla82xx_rd_32(ha, 3358 QLA82XX_PEG_HALT_STATUS1); 3359 ql_log(ql_log_info, vha, 0x6005, 3360 "dumping hw/fw registers:.\n " 3361 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3362 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3363 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3364 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3365 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3366 qla82xx_rd_32(ha, 3367 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3368 qla82xx_rd_32(ha, 3369 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3370 qla82xx_rd_32(ha, 3371 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3372 qla82xx_rd_32(ha, 3373 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3374 qla82xx_rd_32(ha, 3375 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3376 if (((halt_status & 0x1fffff00) >> 8) == 0x67) 3377 ql_log(ql_log_warn, vha, 0xb052, 3378 "Firmware aborted with " 3379 "error code 0x00006700. Device is " 3380 "being reset.\n"); 3381 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3382 set_bit(ISP_UNRECOVERABLE, 3383 &vha->dpc_flags); 3384 } else { 3385 ql_log(ql_log_info, vha, 0x6006, 3386 "Detect abort needed.\n"); 3387 set_bit(ISP_ABORT_NEEDED, 3388 &vha->dpc_flags); 3389 } 3390 qla2xxx_wake_dpc(vha); 3391 ha->flags.isp82xx_fw_hung = 1; 3392 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3393 qla82xx_clear_pending_mbx(vha); 3394 } 3395 } 3396 } 3397} 3398 3399int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3400{ 3401 int rval; 3402 rval = qla82xx_device_state_handler(vha); 3403 return rval; 3404} 3405 3406void 3407qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3408{ 3409 struct qla_hw_data *ha = vha->hw; 3410 uint32_t dev_state; 3411 3412 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3413 if (dev_state == QLA82XX_DEV_READY) { 3414 ql_log(ql_log_info, vha, 0xb02f, 3415 "HW State: NEED RESET\n"); 3416 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3417 QLA82XX_DEV_NEED_RESET); 3418 ha->flags.isp82xx_reset_owner = 1; 3419 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3420 "reset_owner is 0x%x\n", ha->portnum); 3421 } else 3422 ql_log(ql_log_info, vha, 0xb031, 3423 "Device state is 0x%x = %s.\n", 3424 dev_state, 3425 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3426} 3427 3428/* 3429 * qla82xx_abort_isp 3430 * Resets ISP and aborts all outstanding commands. 3431 * 3432 * Input: 3433 * ha = adapter block pointer. 3434 * 3435 * Returns: 3436 * 0 = success 3437 */ 3438int 3439qla82xx_abort_isp(scsi_qla_host_t *vha) 3440{ 3441 int rval; 3442 struct qla_hw_data *ha = vha->hw; 3443 3444 if (vha->device_flags & DFLG_DEV_FAILED) { 3445 ql_log(ql_log_warn, vha, 0x8024, 3446 "Device in failed state, exiting.\n"); 3447 return QLA_SUCCESS; 3448 } 3449 ha->flags.isp82xx_reset_hdlr_active = 1; 3450 3451 qla82xx_idc_lock(ha); 3452 qla82xx_set_reset_owner(vha); 3453 qla82xx_idc_unlock(ha); 3454 3455 rval = qla82xx_device_state_handler(vha); 3456 3457 qla82xx_idc_lock(ha); 3458 qla82xx_clear_rst_ready(ha); 3459 qla82xx_idc_unlock(ha); 3460 3461 if (rval == QLA_SUCCESS) { 3462 ha->flags.isp82xx_fw_hung = 0; 3463 ha->flags.isp82xx_reset_hdlr_active = 0; 3464 qla82xx_restart_isp(vha); 3465 } 3466 3467 if (rval) { 3468 vha->flags.online = 1; 3469 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3470 if (ha->isp_abort_cnt == 0) { 3471 ql_log(ql_log_warn, vha, 0x8027, 3472 "ISP error recover failed - board " 3473 "disabled.\n"); 3474 /* 3475 * The next call disables the board 3476 * completely. 3477 */ 3478 ha->isp_ops->reset_adapter(vha); 3479 vha->flags.online = 0; 3480 clear_bit(ISP_ABORT_RETRY, 3481 &vha->dpc_flags); 3482 rval = QLA_SUCCESS; 3483 } else { /* schedule another ISP abort */ 3484 ha->isp_abort_cnt--; 3485 ql_log(ql_log_warn, vha, 0x8036, 3486 "ISP abort - retry remaining %d.\n", 3487 ha->isp_abort_cnt); 3488 rval = QLA_FUNCTION_FAILED; 3489 } 3490 } else { 3491 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3492 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3493 "ISP error recovery - retrying (%d) more times.\n", 3494 ha->isp_abort_cnt); 3495 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3496 rval = QLA_FUNCTION_FAILED; 3497 } 3498 } 3499 return rval; 3500} 3501 3502/* 3503 * qla82xx_fcoe_ctx_reset 3504 * Perform a quick reset and aborts all outstanding commands. 3505 * This will only perform an FCoE context reset and avoids a full blown 3506 * chip reset. 3507 * 3508 * Input: 3509 * ha = adapter block pointer. 3510 * is_reset_path = flag for identifying the reset path. 3511 * 3512 * Returns: 3513 * 0 = success 3514 */ 3515int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3516{ 3517 int rval = QLA_FUNCTION_FAILED; 3518 3519 if (vha->flags.online) { 3520 /* Abort all outstanding commands, so as to be requeued later */ 3521 qla2x00_abort_isp_cleanup(vha); 3522 } 3523 3524 /* Stop currently executing firmware. 3525 * This will destroy existing FCoE context at the F/W end. 3526 */ 3527 qla2x00_try_to_stop_firmware(vha); 3528 3529 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3530 rval = qla82xx_restart_isp(vha); 3531 3532 return rval; 3533} 3534 3535/* 3536 * qla2x00_wait_for_fcoe_ctx_reset 3537 * Wait till the FCoE context is reset. 3538 * 3539 * Note: 3540 * Does context switching here. 3541 * Release SPIN_LOCK (if any) before calling this routine. 3542 * 3543 * Return: 3544 * Success (fcoe_ctx reset is done) : 0 3545 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3546 */ 3547int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3548{ 3549 int status = QLA_FUNCTION_FAILED; 3550 unsigned long wait_reset; 3551 3552 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3553 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3554 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3555 && time_before(jiffies, wait_reset)) { 3556 3557 set_current_state(TASK_UNINTERRUPTIBLE); 3558 schedule_timeout(HZ); 3559 3560 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3561 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3562 status = QLA_SUCCESS; 3563 break; 3564 } 3565 } 3566 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3567 "%s: status=%d.\n", __func__, status); 3568 3569 return status; 3570} 3571 3572void 3573qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3574{ 3575 int i; 3576 unsigned long flags; 3577 struct qla_hw_data *ha = vha->hw; 3578 3579 /* Check if 82XX firmware is alive or not 3580 * We may have arrived here from NEED_RESET 3581 * detection only 3582 */ 3583 if (!ha->flags.isp82xx_fw_hung) { 3584 for (i = 0; i < 2; i++) { 3585 msleep(1000); 3586 if (qla82xx_check_fw_alive(vha)) { 3587 ha->flags.isp82xx_fw_hung = 1; 3588 qla82xx_clear_pending_mbx(vha); 3589 break; 3590 } 3591 } 3592 } 3593 ql_dbg(ql_dbg_init, vha, 0x00b0, 3594 "Entered %s fw_hung=%d.\n", 3595 __func__, ha->flags.isp82xx_fw_hung); 3596 3597 /* Abort all commands gracefully if fw NOT hung */ 3598 if (!ha->flags.isp82xx_fw_hung) { 3599 int cnt, que; 3600 srb_t *sp; 3601 struct req_que *req; 3602 3603 spin_lock_irqsave(&ha->hardware_lock, flags); 3604 for (que = 0; que < ha->max_req_queues; que++) { 3605 req = ha->req_q_map[que]; 3606 if (!req) 3607 continue; 3608 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 3609 sp = req->outstanding_cmds[cnt]; 3610 if (sp) { 3611 if (!sp->u.scmd.ctx || 3612 (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 3613 spin_unlock_irqrestore( 3614 &ha->hardware_lock, flags); 3615 if (ha->isp_ops->abort_command(sp)) { 3616 ql_log(ql_log_info, vha, 3617 0x00b1, 3618 "mbx abort failed.\n"); 3619 } else { 3620 ql_log(ql_log_info, vha, 3621 0x00b2, 3622 "mbx abort success.\n"); 3623 } 3624 spin_lock_irqsave(&ha->hardware_lock, flags); 3625 } 3626 } 3627 } 3628 } 3629 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3630 3631 /* Wait for pending cmds (physical and virtual) to complete */ 3632 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3633 WAIT_HOST) == QLA_SUCCESS) { 3634 ql_dbg(ql_dbg_init, vha, 0x00b3, 3635 "Done wait for " 3636 "pending commands.\n"); 3637 } 3638 } 3639} 3640 3641/* Minidump related functions */ 3642int 3643qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 3644{ 3645 uint32_t off_value, rval = 0; 3646 3647 WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase), 3648 (off & 0xFFFF0000)); 3649 3650 /* Read back value to make sure write has gone through */ 3651 RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 3652 off_value = (off & 0x0000FFFF); 3653 3654 if (flag) 3655 WRT_REG_DWORD((void *) 3656 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 3657 data); 3658 else 3659 rval = RD_REG_DWORD((void *) 3660 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 3661 3662 return rval; 3663} 3664 3665static int 3666qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3667 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3668{ 3669 struct qla_hw_data *ha = vha->hw; 3670 struct qla82xx_md_entry_crb *crb_entry; 3671 uint32_t read_value, opcode, poll_time; 3672 uint32_t addr, index, crb_addr; 3673 unsigned long wtime; 3674 struct qla82xx_md_template_hdr *tmplt_hdr; 3675 uint32_t rval = QLA_SUCCESS; 3676 int i; 3677 3678 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3679 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3680 crb_addr = crb_entry->addr; 3681 3682 for (i = 0; i < crb_entry->op_count; i++) { 3683 opcode = crb_entry->crb_ctrl.opcode; 3684 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3685 qla82xx_md_rw_32(ha, crb_addr, 3686 crb_entry->value_1, 1); 3687 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3688 } 3689 3690 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3691 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3692 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3693 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3694 } 3695 3696 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3697 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3698 read_value &= crb_entry->value_2; 3699 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3700 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3701 read_value |= crb_entry->value_3; 3702 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3703 } 3704 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3705 } 3706 3707 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3708 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3709 read_value |= crb_entry->value_3; 3710 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3711 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3712 } 3713 3714 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3715 poll_time = crb_entry->crb_strd.poll_timeout; 3716 wtime = jiffies + poll_time; 3717 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3718 3719 do { 3720 if ((read_value & crb_entry->value_2) 3721 == crb_entry->value_1) 3722 break; 3723 else if (time_after_eq(jiffies, wtime)) { 3724 /* capturing dump failed */ 3725 rval = QLA_FUNCTION_FAILED; 3726 break; 3727 } else 3728 read_value = qla82xx_md_rw_32(ha, 3729 crb_addr, 0, 0); 3730 } while (1); 3731 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3732 } 3733 3734 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3735 if (crb_entry->crb_strd.state_index_a) { 3736 index = crb_entry->crb_strd.state_index_a; 3737 addr = tmplt_hdr->saved_state_array[index]; 3738 } else 3739 addr = crb_addr; 3740 3741 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3742 index = crb_entry->crb_ctrl.state_index_v; 3743 tmplt_hdr->saved_state_array[index] = read_value; 3744 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3745 } 3746 3747 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3748 if (crb_entry->crb_strd.state_index_a) { 3749 index = crb_entry->crb_strd.state_index_a; 3750 addr = tmplt_hdr->saved_state_array[index]; 3751 } else 3752 addr = crb_addr; 3753 3754 if (crb_entry->crb_ctrl.state_index_v) { 3755 index = crb_entry->crb_ctrl.state_index_v; 3756 read_value = 3757 tmplt_hdr->saved_state_array[index]; 3758 } else 3759 read_value = crb_entry->value_1; 3760 3761 qla82xx_md_rw_32(ha, addr, read_value, 1); 3762 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3763 } 3764 3765 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3766 index = crb_entry->crb_ctrl.state_index_v; 3767 read_value = tmplt_hdr->saved_state_array[index]; 3768 read_value <<= crb_entry->crb_ctrl.shl; 3769 read_value >>= crb_entry->crb_ctrl.shr; 3770 if (crb_entry->value_2) 3771 read_value &= crb_entry->value_2; 3772 read_value |= crb_entry->value_3; 3773 read_value += crb_entry->value_1; 3774 tmplt_hdr->saved_state_array[index] = read_value; 3775 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3776 } 3777 crb_addr += crb_entry->crb_strd.addr_stride; 3778 } 3779 return rval; 3780} 3781 3782static void 3783qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3784 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3785{ 3786 struct qla_hw_data *ha = vha->hw; 3787 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3788 struct qla82xx_md_entry_rdocm *ocm_hdr; 3789 uint32_t *data_ptr = *d_ptr; 3790 3791 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3792 r_addr = ocm_hdr->read_addr; 3793 r_stride = ocm_hdr->read_addr_stride; 3794 loop_cnt = ocm_hdr->op_count; 3795 3796 for (i = 0; i < loop_cnt; i++) { 3797 r_value = RD_REG_DWORD((void *)(r_addr + ha->nx_pcibase)); 3798 *data_ptr++ = cpu_to_le32(r_value); 3799 r_addr += r_stride; 3800 } 3801 *d_ptr = data_ptr; 3802} 3803 3804static void 3805qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3806 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3807{ 3808 struct qla_hw_data *ha = vha->hw; 3809 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3810 struct qla82xx_md_entry_mux *mux_hdr; 3811 uint32_t *data_ptr = *d_ptr; 3812 3813 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3814 r_addr = mux_hdr->read_addr; 3815 s_addr = mux_hdr->select_addr; 3816 s_stride = mux_hdr->select_value_stride; 3817 s_value = mux_hdr->select_value; 3818 loop_cnt = mux_hdr->op_count; 3819 3820 for (i = 0; i < loop_cnt; i++) { 3821 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3822 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3823 *data_ptr++ = cpu_to_le32(s_value); 3824 *data_ptr++ = cpu_to_le32(r_value); 3825 s_value += s_stride; 3826 } 3827 *d_ptr = data_ptr; 3828} 3829 3830static void 3831qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3832 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3833{ 3834 struct qla_hw_data *ha = vha->hw; 3835 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3836 struct qla82xx_md_entry_crb *crb_hdr; 3837 uint32_t *data_ptr = *d_ptr; 3838 3839 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3840 r_addr = crb_hdr->addr; 3841 r_stride = crb_hdr->crb_strd.addr_stride; 3842 loop_cnt = crb_hdr->op_count; 3843 3844 for (i = 0; i < loop_cnt; i++) { 3845 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3846 *data_ptr++ = cpu_to_le32(r_addr); 3847 *data_ptr++ = cpu_to_le32(r_value); 3848 r_addr += r_stride; 3849 } 3850 *d_ptr = data_ptr; 3851} 3852 3853static int 3854qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3855 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3856{ 3857 struct qla_hw_data *ha = vha->hw; 3858 uint32_t addr, r_addr, c_addr, t_r_addr; 3859 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3860 unsigned long p_wait, w_time, p_mask; 3861 uint32_t c_value_w, c_value_r; 3862 struct qla82xx_md_entry_cache *cache_hdr; 3863 int rval = QLA_FUNCTION_FAILED; 3864 uint32_t *data_ptr = *d_ptr; 3865 3866 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3867 loop_count = cache_hdr->op_count; 3868 r_addr = cache_hdr->read_addr; 3869 c_addr = cache_hdr->control_addr; 3870 c_value_w = cache_hdr->cache_ctrl.write_value; 3871 3872 t_r_addr = cache_hdr->tag_reg_addr; 3873 t_value = cache_hdr->addr_ctrl.init_tag_value; 3874 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3875 p_wait = cache_hdr->cache_ctrl.poll_wait; 3876 p_mask = cache_hdr->cache_ctrl.poll_mask; 3877 3878 for (i = 0; i < loop_count; i++) { 3879 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3880 if (c_value_w) 3881 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3882 3883 if (p_mask) { 3884 w_time = jiffies + p_wait; 3885 do { 3886 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3887 if ((c_value_r & p_mask) == 0) 3888 break; 3889 else if (time_after_eq(jiffies, w_time)) { 3890 /* capturing dump failed */ 3891 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3892 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3893 "w_time: 0x%lx\n", 3894 c_value_r, p_mask, w_time); 3895 return rval; 3896 } 3897 } while (1); 3898 } 3899 3900 addr = r_addr; 3901 for (k = 0; k < r_cnt; k++) { 3902 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3903 *data_ptr++ = cpu_to_le32(r_value); 3904 addr += cache_hdr->read_ctrl.read_addr_stride; 3905 } 3906 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3907 } 3908 *d_ptr = data_ptr; 3909 return QLA_SUCCESS; 3910} 3911 3912static void 3913qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3914 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3915{ 3916 struct qla_hw_data *ha = vha->hw; 3917 uint32_t addr, r_addr, c_addr, t_r_addr; 3918 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3919 uint32_t c_value_w; 3920 struct qla82xx_md_entry_cache *cache_hdr; 3921 uint32_t *data_ptr = *d_ptr; 3922 3923 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3924 loop_count = cache_hdr->op_count; 3925 r_addr = cache_hdr->read_addr; 3926 c_addr = cache_hdr->control_addr; 3927 c_value_w = cache_hdr->cache_ctrl.write_value; 3928 3929 t_r_addr = cache_hdr->tag_reg_addr; 3930 t_value = cache_hdr->addr_ctrl.init_tag_value; 3931 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3932 3933 for (i = 0; i < loop_count; i++) { 3934 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3935 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3936 addr = r_addr; 3937 for (k = 0; k < r_cnt; k++) { 3938 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3939 *data_ptr++ = cpu_to_le32(r_value); 3940 addr += cache_hdr->read_ctrl.read_addr_stride; 3941 } 3942 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3943 } 3944 *d_ptr = data_ptr; 3945} 3946 3947static void 3948qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 3949 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3950{ 3951 struct qla_hw_data *ha = vha->hw; 3952 uint32_t s_addr, r_addr; 3953 uint32_t r_stride, r_value, r_cnt, qid = 0; 3954 uint32_t i, k, loop_cnt; 3955 struct qla82xx_md_entry_queue *q_hdr; 3956 uint32_t *data_ptr = *d_ptr; 3957 3958 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 3959 s_addr = q_hdr->select_addr; 3960 r_cnt = q_hdr->rd_strd.read_addr_cnt; 3961 r_stride = q_hdr->rd_strd.read_addr_stride; 3962 loop_cnt = q_hdr->op_count; 3963 3964 for (i = 0; i < loop_cnt; i++) { 3965 qla82xx_md_rw_32(ha, s_addr, qid, 1); 3966 r_addr = q_hdr->read_addr; 3967 for (k = 0; k < r_cnt; k++) { 3968 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3969 *data_ptr++ = cpu_to_le32(r_value); 3970 r_addr += r_stride; 3971 } 3972 qid += q_hdr->q_strd.queue_id_stride; 3973 } 3974 *d_ptr = data_ptr; 3975} 3976 3977static void 3978qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 3979 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3980{ 3981 struct qla_hw_data *ha = vha->hw; 3982 uint32_t r_addr, r_value; 3983 uint32_t i, loop_cnt; 3984 struct qla82xx_md_entry_rdrom *rom_hdr; 3985 uint32_t *data_ptr = *d_ptr; 3986 3987 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 3988 r_addr = rom_hdr->read_addr; 3989 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 3990 3991 for (i = 0; i < loop_cnt; i++) { 3992 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 3993 (r_addr & 0xFFFF0000), 1); 3994 r_value = qla82xx_md_rw_32(ha, 3995 MD_DIRECT_ROM_READ_BASE + 3996 (r_addr & 0x0000FFFF), 0, 0); 3997 *data_ptr++ = cpu_to_le32(r_value); 3998 r_addr += sizeof(uint32_t); 3999 } 4000 *d_ptr = data_ptr; 4001} 4002 4003static int 4004qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4005 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4006{ 4007 struct qla_hw_data *ha = vha->hw; 4008 uint32_t r_addr, r_value, r_data; 4009 uint32_t i, j, loop_cnt; 4010 struct qla82xx_md_entry_rdmem *m_hdr; 4011 unsigned long flags; 4012 int rval = QLA_FUNCTION_FAILED; 4013 uint32_t *data_ptr = *d_ptr; 4014 4015 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4016 r_addr = m_hdr->read_addr; 4017 loop_cnt = m_hdr->read_data_size/16; 4018 4019 if (r_addr & 0xf) { 4020 ql_log(ql_log_warn, vha, 0xb033, 4021 "Read addr 0x%x not 16 bytes alligned\n", r_addr); 4022 return rval; 4023 } 4024 4025 if (m_hdr->read_data_size % 16) { 4026 ql_log(ql_log_warn, vha, 0xb034, 4027 "Read data[0x%x] not multiple of 16 bytes\n", 4028 m_hdr->read_data_size); 4029 return rval; 4030 } 4031 4032 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4033 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4034 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4035 4036 write_lock_irqsave(&ha->hw_lock, flags); 4037 for (i = 0; i < loop_cnt; i++) { 4038 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4039 r_value = 0; 4040 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4041 r_value = MIU_TA_CTL_ENABLE; 4042 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4043 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4044 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4045 4046 for (j = 0; j < MAX_CTL_CHECK; j++) { 4047 r_value = qla82xx_md_rw_32(ha, 4048 MD_MIU_TEST_AGT_CTRL, 0, 0); 4049 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4050 break; 4051 } 4052 4053 if (j >= MAX_CTL_CHECK) { 4054 printk_ratelimited(KERN_ERR 4055 "failed to read through agent\n"); 4056 write_unlock_irqrestore(&ha->hw_lock, flags); 4057 return rval; 4058 } 4059 4060 for (j = 0; j < 4; j++) { 4061 r_data = qla82xx_md_rw_32(ha, 4062 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4063 *data_ptr++ = cpu_to_le32(r_data); 4064 } 4065 r_addr += 16; 4066 } 4067 write_unlock_irqrestore(&ha->hw_lock, flags); 4068 *d_ptr = data_ptr; 4069 return QLA_SUCCESS; 4070} 4071 4072static int 4073qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4074{ 4075 struct qla_hw_data *ha = vha->hw; 4076 uint64_t chksum = 0; 4077 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4078 int count = ha->md_template_size/sizeof(uint32_t); 4079 4080 while (count-- > 0) 4081 chksum += *d_ptr++; 4082 while (chksum >> 32) 4083 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4084 return ~chksum; 4085} 4086 4087static void 4088qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4089 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4090{ 4091 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4092 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4093 "Skipping entry[%d]: " 4094 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4095 index, entry_hdr->entry_type, 4096 entry_hdr->d_ctrl.entry_capture_mask); 4097} 4098 4099int 4100qla82xx_md_collect(scsi_qla_host_t *vha) 4101{ 4102 struct qla_hw_data *ha = vha->hw; 4103 int no_entry_hdr = 0; 4104 qla82xx_md_entry_hdr_t *entry_hdr; 4105 struct qla82xx_md_template_hdr *tmplt_hdr; 4106 uint32_t *data_ptr; 4107 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4108 int i = 0, rval = QLA_FUNCTION_FAILED; 4109 4110 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4111 data_ptr = (uint32_t *)ha->md_dump; 4112 4113 if (ha->fw_dumped) { 4114 ql_log(ql_log_info, vha, 0xb037, 4115 "Firmware dump available to retrive\n"); 4116 goto md_failed; 4117 } 4118 4119 ha->fw_dumped = 0; 4120 4121 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4122 ql_log(ql_log_warn, vha, 0xb038, 4123 "Memory not allocated for minidump capture\n"); 4124 goto md_failed; 4125 } 4126 4127 if (qla82xx_validate_template_chksum(vha)) { 4128 ql_log(ql_log_info, vha, 0xb039, 4129 "Template checksum validation error\n"); 4130 goto md_failed; 4131 } 4132 4133 no_entry_hdr = tmplt_hdr->num_of_entries; 4134 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4135 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4136 4137 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4138 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4139 4140 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4141 4142 /* Validate whether required debug level is set */ 4143 if ((f_capture_mask & 0x3) != 0x3) { 4144 ql_log(ql_log_warn, vha, 0xb03c, 4145 "Minimum required capture mask[0x%x] level not set\n", 4146 f_capture_mask); 4147 goto md_failed; 4148 } 4149 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4150 4151 tmplt_hdr->driver_info[0] = vha->host_no; 4152 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4153 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4154 QLA_DRIVER_BETA_VER; 4155 4156 total_data_size = ha->md_dump_size; 4157 4158 ql_dbg(ql_log_info, vha, 0xb03d, 4159 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4160 4161 /* Check whether template obtained is valid */ 4162 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4163 ql_log(ql_log_warn, vha, 0xb04e, 4164 "Bad template header entry type: 0x%x obtained\n", 4165 tmplt_hdr->entry_type); 4166 goto md_failed; 4167 } 4168 4169 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4170 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4171 4172 /* Walk through the entry headers */ 4173 for (i = 0; i < no_entry_hdr; i++) { 4174 4175 if (data_collected > total_data_size) { 4176 ql_log(ql_log_warn, vha, 0xb03e, 4177 "More MiniDump data collected: [0x%x]\n", 4178 data_collected); 4179 goto md_failed; 4180 } 4181 4182 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4183 ql2xmdcapmask)) { 4184 entry_hdr->d_ctrl.driver_flags |= 4185 QLA82XX_DBG_SKIPPED_FLAG; 4186 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4187 "Skipping entry[%d]: " 4188 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4189 i, entry_hdr->entry_type, 4190 entry_hdr->d_ctrl.entry_capture_mask); 4191 goto skip_nxt_entry; 4192 } 4193 4194 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4195 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4196 "entry_type: 0x%x, captrue_mask: 0x%x\n", 4197 __func__, i, data_ptr, entry_hdr, 4198 entry_hdr->entry_type, 4199 entry_hdr->d_ctrl.entry_capture_mask); 4200 4201 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4202 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4203 data_collected, (ha->md_dump_size - data_collected)); 4204 4205 /* Decode the entry type and take 4206 * required action to capture debug data */ 4207 switch (entry_hdr->entry_type) { 4208 case QLA82XX_RDEND: 4209 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4210 break; 4211 case QLA82XX_CNTRL: 4212 rval = qla82xx_minidump_process_control(vha, 4213 entry_hdr, &data_ptr); 4214 if (rval != QLA_SUCCESS) { 4215 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4216 goto md_failed; 4217 } 4218 break; 4219 case QLA82XX_RDCRB: 4220 qla82xx_minidump_process_rdcrb(vha, 4221 entry_hdr, &data_ptr); 4222 break; 4223 case QLA82XX_RDMEM: 4224 rval = qla82xx_minidump_process_rdmem(vha, 4225 entry_hdr, &data_ptr); 4226 if (rval != QLA_SUCCESS) { 4227 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4228 goto md_failed; 4229 } 4230 break; 4231 case QLA82XX_BOARD: 4232 case QLA82XX_RDROM: 4233 qla82xx_minidump_process_rdrom(vha, 4234 entry_hdr, &data_ptr); 4235 break; 4236 case QLA82XX_L2DTG: 4237 case QLA82XX_L2ITG: 4238 case QLA82XX_L2DAT: 4239 case QLA82XX_L2INS: 4240 rval = qla82xx_minidump_process_l2tag(vha, 4241 entry_hdr, &data_ptr); 4242 if (rval != QLA_SUCCESS) { 4243 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4244 goto md_failed; 4245 } 4246 break; 4247 case QLA82XX_L1DAT: 4248 case QLA82XX_L1INS: 4249 qla82xx_minidump_process_l1cache(vha, 4250 entry_hdr, &data_ptr); 4251 break; 4252 case QLA82XX_RDOCM: 4253 qla82xx_minidump_process_rdocm(vha, 4254 entry_hdr, &data_ptr); 4255 break; 4256 case QLA82XX_RDMUX: 4257 qla82xx_minidump_process_rdmux(vha, 4258 entry_hdr, &data_ptr); 4259 break; 4260 case QLA82XX_QUEUE: 4261 qla82xx_minidump_process_queue(vha, 4262 entry_hdr, &data_ptr); 4263 break; 4264 case QLA82XX_RDNOP: 4265 default: 4266 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4267 break; 4268 } 4269 4270 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4271 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4272 4273 data_collected = (uint8_t *)data_ptr - 4274 (uint8_t *)ha->md_dump; 4275skip_nxt_entry: 4276 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4277 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4278 } 4279 4280 if (data_collected != total_data_size) { 4281 ql_dbg(ql_log_warn, vha, 0xb043, 4282 "MiniDump data mismatch: Data collected: [0x%x]," 4283 "total_data_size:[0x%x]\n", 4284 data_collected, total_data_size); 4285 goto md_failed; 4286 } 4287 4288 ql_log(ql_log_info, vha, 0xb044, 4289 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4290 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4291 ha->fw_dumped = 1; 4292 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4293 4294md_failed: 4295 return rval; 4296} 4297 4298int 4299qla82xx_md_alloc(scsi_qla_host_t *vha) 4300{ 4301 struct qla_hw_data *ha = vha->hw; 4302 int i, k; 4303 struct qla82xx_md_template_hdr *tmplt_hdr; 4304 4305 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4306 4307 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4308 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4309 ql_log(ql_log_info, vha, 0xb045, 4310 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4311 ql2xmdcapmask); 4312 } 4313 4314 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4315 if (i & ql2xmdcapmask) 4316 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4317 } 4318 4319 if (ha->md_dump) { 4320 ql_log(ql_log_warn, vha, 0xb046, 4321 "Firmware dump previously allocated.\n"); 4322 return 1; 4323 } 4324 4325 ha->md_dump = vmalloc(ha->md_dump_size); 4326 if (ha->md_dump == NULL) { 4327 ql_log(ql_log_warn, vha, 0xb047, 4328 "Unable to allocate memory for Minidump size " 4329 "(0x%x).\n", ha->md_dump_size); 4330 return 1; 4331 } 4332 return 0; 4333} 4334 4335void 4336qla82xx_md_free(scsi_qla_host_t *vha) 4337{ 4338 struct qla_hw_data *ha = vha->hw; 4339 4340 /* Release the template header allocated */ 4341 if (ha->md_tmplt_hdr) { 4342 ql_log(ql_log_info, vha, 0xb048, 4343 "Free MiniDump template: %p, size (%d KB)\n", 4344 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4345 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4346 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4347 ha->md_tmplt_hdr = 0; 4348 } 4349 4350 /* Release the template data buffer allocated */ 4351 if (ha->md_dump) { 4352 ql_log(ql_log_info, vha, 0xb049, 4353 "Free MiniDump memory: %p, size (%d KB)\n", 4354 ha->md_dump, ha->md_dump_size / 1024); 4355 vfree(ha->md_dump); 4356 ha->md_dump_size = 0; 4357 ha->md_dump = 0; 4358 } 4359} 4360 4361void 4362qla82xx_md_prep(scsi_qla_host_t *vha) 4363{ 4364 struct qla_hw_data *ha = vha->hw; 4365 int rval; 4366 4367 /* Get Minidump template size */ 4368 rval = qla82xx_md_get_template_size(vha); 4369 if (rval == QLA_SUCCESS) { 4370 ql_log(ql_log_info, vha, 0xb04a, 4371 "MiniDump Template size obtained (%d KB)\n", 4372 ha->md_template_size / 1024); 4373 4374 /* Get Minidump template */ 4375 rval = qla82xx_md_get_template(vha); 4376 if (rval == QLA_SUCCESS) { 4377 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4378 "MiniDump Template obtained\n"); 4379 4380 /* Allocate memory for minidump */ 4381 rval = qla82xx_md_alloc(vha); 4382 if (rval == QLA_SUCCESS) 4383 ql_log(ql_log_info, vha, 0xb04c, 4384 "MiniDump memory allocated (%d KB)\n", 4385 ha->md_dump_size / 1024); 4386 else { 4387 ql_log(ql_log_info, vha, 0xb04d, 4388 "Free MiniDump template: %p, size: (%d KB)\n", 4389 ha->md_tmplt_hdr, 4390 ha->md_template_size / 1024); 4391 dma_free_coherent(&ha->pdev->dev, 4392 ha->md_template_size, 4393 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4394 ha->md_tmplt_hdr = 0; 4395 } 4396 4397 } 4398 } 4399} 4400 4401int 4402qla82xx_beacon_on(struct scsi_qla_host *vha) 4403{ 4404 4405 int rval; 4406 struct qla_hw_data *ha = vha->hw; 4407 qla82xx_idc_lock(ha); 4408 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4409 4410 if (rval) { 4411 ql_log(ql_log_warn, vha, 0xb050, 4412 "mbx set led config failed in %s\n", __func__); 4413 goto exit; 4414 } 4415 ha->beacon_blink_led = 1; 4416exit: 4417 qla82xx_idc_unlock(ha); 4418 return rval; 4419} 4420 4421int 4422qla82xx_beacon_off(struct scsi_qla_host *vha) 4423{ 4424 4425 int rval; 4426 struct qla_hw_data *ha = vha->hw; 4427 qla82xx_idc_lock(ha); 4428 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4429 4430 if (rval) { 4431 ql_log(ql_log_warn, vha, 0xb051, 4432 "mbx set led config failed in %s\n", __func__); 4433 goto exit; 4434 } 4435 ha->beacon_blink_led = 0; 4436exit: 4437 qla82xx_idc_unlock(ha); 4438 return rval; 4439} 4440