qla_nx.c revision cfb0919c12a33132f75fb91971bbd8bdd44ebb90
1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2011 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7#include "qla_def.h" 8#include <linux/delay.h> 9#include <linux/pci.h> 10#include <linux/ratelimit.h> 11#include <linux/vmalloc.h> 12#include <scsi/scsi_tcq.h> 13 14#define MASK(n) ((1ULL<<(n))-1) 15#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16 ((addr >> 25) & 0x3ff)) 17#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18 ((addr >> 25) & 0x3ff)) 19#define MS_WIN(addr) (addr & 0x0ffc0000) 20#define QLA82XX_PCI_MN_2M (0) 21#define QLA82XX_PCI_MS_2M (0x80000) 22#define QLA82XX_PCI_OCM0_2M (0xc0000) 23#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24#define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25#define BLOCK_PROTECT_BITS 0x0F 26 27/* CRB window related */ 28#define CRB_BLK(off) ((off >> 20) & 0x3f) 29#define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30#define CRB_WINDOW_2M (0x130060) 31#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32#define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33 ((off) & 0xf0000)) 34#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35#define CRB_INDIRECT_2M (0x1e0000UL) 36 37#define MAX_CRB_XFORM 60 38static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39int qla82xx_crb_table_initialized; 40 41#define qla82xx_crb_addr_transform(name) \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44 45static void qla82xx_crb_addr_transform_setup(void) 46{ 47 qla82xx_crb_addr_transform(XDMA); 48 qla82xx_crb_addr_transform(TIMR); 49 qla82xx_crb_addr_transform(SRE); 50 qla82xx_crb_addr_transform(SQN3); 51 qla82xx_crb_addr_transform(SQN2); 52 qla82xx_crb_addr_transform(SQN1); 53 qla82xx_crb_addr_transform(SQN0); 54 qla82xx_crb_addr_transform(SQS3); 55 qla82xx_crb_addr_transform(SQS2); 56 qla82xx_crb_addr_transform(SQS1); 57 qla82xx_crb_addr_transform(SQS0); 58 qla82xx_crb_addr_transform(RPMX7); 59 qla82xx_crb_addr_transform(RPMX6); 60 qla82xx_crb_addr_transform(RPMX5); 61 qla82xx_crb_addr_transform(RPMX4); 62 qla82xx_crb_addr_transform(RPMX3); 63 qla82xx_crb_addr_transform(RPMX2); 64 qla82xx_crb_addr_transform(RPMX1); 65 qla82xx_crb_addr_transform(RPMX0); 66 qla82xx_crb_addr_transform(ROMUSB); 67 qla82xx_crb_addr_transform(SN); 68 qla82xx_crb_addr_transform(QMN); 69 qla82xx_crb_addr_transform(QMS); 70 qla82xx_crb_addr_transform(PGNI); 71 qla82xx_crb_addr_transform(PGND); 72 qla82xx_crb_addr_transform(PGN3); 73 qla82xx_crb_addr_transform(PGN2); 74 qla82xx_crb_addr_transform(PGN1); 75 qla82xx_crb_addr_transform(PGN0); 76 qla82xx_crb_addr_transform(PGSI); 77 qla82xx_crb_addr_transform(PGSD); 78 qla82xx_crb_addr_transform(PGS3); 79 qla82xx_crb_addr_transform(PGS2); 80 qla82xx_crb_addr_transform(PGS1); 81 qla82xx_crb_addr_transform(PGS0); 82 qla82xx_crb_addr_transform(PS); 83 qla82xx_crb_addr_transform(PH); 84 qla82xx_crb_addr_transform(NIU); 85 qla82xx_crb_addr_transform(I2Q); 86 qla82xx_crb_addr_transform(EG); 87 qla82xx_crb_addr_transform(MN); 88 qla82xx_crb_addr_transform(MS); 89 qla82xx_crb_addr_transform(CAS2); 90 qla82xx_crb_addr_transform(CAS1); 91 qla82xx_crb_addr_transform(CAS0); 92 qla82xx_crb_addr_transform(CAM); 93 qla82xx_crb_addr_transform(C2C1); 94 qla82xx_crb_addr_transform(C2C0); 95 qla82xx_crb_addr_transform(SMB); 96 qla82xx_crb_addr_transform(OCM0); 97 /* 98 * Used only in P3 just define it for P2 also. 99 */ 100 qla82xx_crb_addr_transform(I2C0); 101 102 qla82xx_crb_table_initialized = 1; 103} 104 105struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106 {{{0, 0, 0, 0} } }, 107 {{{1, 0x0100000, 0x0102000, 0x120000}, 108 {1, 0x0110000, 0x0120000, 0x130000}, 109 {1, 0x0120000, 0x0122000, 0x124000}, 110 {1, 0x0130000, 0x0132000, 0x126000}, 111 {1, 0x0140000, 0x0142000, 0x128000}, 112 {1, 0x0150000, 0x0152000, 0x12a000}, 113 {1, 0x0160000, 0x0170000, 0x110000}, 114 {1, 0x0170000, 0x0172000, 0x12e000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {1, 0x01e0000, 0x01e0800, 0x122000}, 122 {0, 0x0000000, 0x0000000, 0x000000} } } , 123 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124 {{{0, 0, 0, 0} } }, 125 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129 {{{1, 0x0800000, 0x0802000, 0x170000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145 {{{1, 0x0900000, 0x0902000, 0x174000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {0, 0x0000000, 0x0000000, 0x000000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204 {{{0, 0, 0, 0} } }, 205 {{{0, 0, 0, 0} } }, 206 {{{0, 0, 0, 0} } }, 207 {{{0, 0, 0, 0} } }, 208 {{{0, 0, 0, 0} } }, 209 {{{0, 0, 0, 0} } }, 210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213 {{{0} } }, 214 {{{1, 0x2100000, 0x2102000, 0x120000}, 215 {1, 0x2110000, 0x2120000, 0x130000}, 216 {1, 0x2120000, 0x2122000, 0x124000}, 217 {1, 0x2130000, 0x2132000, 0x126000}, 218 {1, 0x2140000, 0x2142000, 0x128000}, 219 {1, 0x2150000, 0x2152000, 0x12a000}, 220 {1, 0x2160000, 0x2170000, 0x110000}, 221 {1, 0x2170000, 0x2172000, 0x12e000}, 222 {0, 0x0000000, 0x0000000, 0x000000}, 223 {0, 0x0000000, 0x0000000, 0x000000}, 224 {0, 0x0000000, 0x0000000, 0x000000}, 225 {0, 0x0000000, 0x0000000, 0x000000}, 226 {0, 0x0000000, 0x0000000, 0x000000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000} } }, 230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231 {{{0} } }, 232 {{{0} } }, 233 {{{0} } }, 234 {{{0} } }, 235 {{{0} } }, 236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248 {{{0} } }, 249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255 {{{0} } }, 256 {{{0} } }, 257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260}; 261 262/* 263 * top 12 bits of crb internal address (hub, agent) 264 */ 265unsigned qla82xx_crb_hub_agt[64] = { 266 0, 267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270 0, 271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293 0, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296 0, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301 0, 302 0, 303 0, 304 0, 305 0, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307 0, 308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318 0, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327 0, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329 0, 330}; 331 332/* Device states */ 333char *q_dev_state[] = { 334 "Unknown", 335 "Cold", 336 "Initializing", 337 "Ready", 338 "Need Reset", 339 "Need Quiescent", 340 "Failed", 341 "Quiescent", 342}; 343 344char *qdev_state(uint32_t dev_state) 345{ 346 return q_dev_state[dev_state]; 347} 348 349/* 350 * In: 'off' is offset from CRB space in 128M pci map 351 * Out: 'off' is 2M pci map addr 352 * side effect: lock crb window 353 */ 354static void 355qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356{ 357 u32 win_read; 358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359 360 ha->crb_win = CRB_HI(*off); 361 writel(ha->crb_win, 362 (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363 364 /* Read back value to make sure write has gone through before trying 365 * to use it. 366 */ 367 win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 368 if (win_read != ha->crb_win) { 369 ql_dbg(ql_dbg_p3p, vha, 0xb000, 370 "%s: Written crbwin (0x%x) " 371 "!= Read crbwin (0x%x), off=0x%lx.\n", 372 __func__, ha->crb_win, win_read, *off); 373 } 374 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 375} 376 377static inline unsigned long 378qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 379{ 380 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 381 /* See if we are currently pointing to the region we want to use next */ 382 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 383 /* No need to change window. PCIX and PCIEregs are in both 384 * regs are in both windows. 385 */ 386 return off; 387 } 388 389 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 390 /* We are in first CRB window */ 391 if (ha->curr_window != 0) 392 WARN_ON(1); 393 return off; 394 } 395 396 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 397 /* We are in second CRB window */ 398 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 399 400 if (ha->curr_window != 1) 401 return off; 402 403 /* We are in the QM or direct access 404 * register region - do nothing 405 */ 406 if ((off >= QLA82XX_PCI_DIRECT_CRB) && 407 (off < QLA82XX_PCI_CAMQM_MAX)) 408 return off; 409 } 410 /* strange address given */ 411 ql_dbg(ql_dbg_p3p, vha, 0xb001, 412 "%s: Warning: unm_nic_pci_set_crbwindow " 413 "called with an unknown address(%llx).\n", 414 QLA2XXX_DRIVER_NAME, off); 415 return off; 416} 417 418static int 419qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 420{ 421 struct crb_128M_2M_sub_block_map *m; 422 423 if (*off >= QLA82XX_CRB_MAX) 424 return -1; 425 426 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 427 *off = (*off - QLA82XX_PCI_CAMQM) + 428 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 429 return 0; 430 } 431 432 if (*off < QLA82XX_PCI_CRBSPACE) 433 return -1; 434 435 *off -= QLA82XX_PCI_CRBSPACE; 436 437 /* Try direct map */ 438 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 439 440 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 441 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 442 return 0; 443 } 444 /* Not in direct map, use crb window */ 445 return 1; 446} 447 448#define CRB_WIN_LOCK_TIMEOUT 100000000 449static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 450{ 451 int done = 0, timeout = 0; 452 453 while (!done) { 454 /* acquire semaphore3 from PCI HW block */ 455 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 456 if (done == 1) 457 break; 458 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 459 return -1; 460 timeout++; 461 } 462 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 463 return 0; 464} 465 466int 467qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 468{ 469 unsigned long flags = 0; 470 int rv; 471 472 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 473 474 BUG_ON(rv == -1); 475 476 if (rv == 1) { 477 write_lock_irqsave(&ha->hw_lock, flags); 478 qla82xx_crb_win_lock(ha); 479 qla82xx_pci_set_crbwindow_2M(ha, &off); 480 } 481 482 writel(data, (void __iomem *)off); 483 484 if (rv == 1) { 485 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 486 write_unlock_irqrestore(&ha->hw_lock, flags); 487 } 488 return 0; 489} 490 491int 492qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 493{ 494 unsigned long flags = 0; 495 int rv; 496 u32 data; 497 498 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 499 500 BUG_ON(rv == -1); 501 502 if (rv == 1) { 503 write_lock_irqsave(&ha->hw_lock, flags); 504 qla82xx_crb_win_lock(ha); 505 qla82xx_pci_set_crbwindow_2M(ha, &off); 506 } 507 data = RD_REG_DWORD((void __iomem *)off); 508 509 if (rv == 1) { 510 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 511 write_unlock_irqrestore(&ha->hw_lock, flags); 512 } 513 return data; 514} 515 516#define IDC_LOCK_TIMEOUT 100000000 517int qla82xx_idc_lock(struct qla_hw_data *ha) 518{ 519 int i; 520 int done = 0, timeout = 0; 521 522 while (!done) { 523 /* acquire semaphore5 from PCI HW block */ 524 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 525 if (done == 1) 526 break; 527 if (timeout >= IDC_LOCK_TIMEOUT) 528 return -1; 529 530 timeout++; 531 532 /* Yield CPU */ 533 if (!in_interrupt()) 534 schedule(); 535 else { 536 for (i = 0; i < 20; i++) 537 cpu_relax(); 538 } 539 } 540 541 return 0; 542} 543 544void qla82xx_idc_unlock(struct qla_hw_data *ha) 545{ 546 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 547} 548 549/* PCI Windowing for DDR regions. */ 550#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 551 (((addr) <= (high)) && ((addr) >= (low))) 552/* 553 * check memory access boundary. 554 * used by test agent. support ddr access only for now 555 */ 556static unsigned long 557qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 558 unsigned long long addr, int size) 559{ 560 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 561 QLA82XX_ADDR_DDR_NET_MAX) || 562 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 563 QLA82XX_ADDR_DDR_NET_MAX) || 564 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 565 return 0; 566 else 567 return 1; 568} 569 570int qla82xx_pci_set_window_warning_count; 571 572static unsigned long 573qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 574{ 575 int window; 576 u32 win_read; 577 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 578 579 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 580 QLA82XX_ADDR_DDR_NET_MAX)) { 581 /* DDR network side */ 582 window = MN_WIN(addr); 583 ha->ddr_mn_window = window; 584 qla82xx_wr_32(ha, 585 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 586 win_read = qla82xx_rd_32(ha, 587 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 588 if ((win_read << 17) != window) { 589 ql_dbg(ql_dbg_p3p, vha, 0xb003, 590 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 591 __func__, window, win_read); 592 } 593 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 594 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 595 QLA82XX_ADDR_OCM0_MAX)) { 596 unsigned int temp1; 597 if ((addr & 0x00ff800) == 0xff800) { 598 ql_log(ql_log_warn, vha, 0xb004, 599 "%s: QM access not handled.\n", __func__); 600 addr = -1UL; 601 } 602 window = OCM_WIN(addr); 603 ha->ddr_mn_window = window; 604 qla82xx_wr_32(ha, 605 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 606 win_read = qla82xx_rd_32(ha, 607 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 608 temp1 = ((window & 0x1FF) << 7) | 609 ((window & 0x0FFFE0000) >> 17); 610 if (win_read != temp1) { 611 ql_log(ql_log_warn, vha, 0xb005, 612 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 613 __func__, temp1, win_read); 614 } 615 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 616 617 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 618 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 619 /* QDR network side */ 620 window = MS_WIN(addr); 621 ha->qdr_sn_window = window; 622 qla82xx_wr_32(ha, 623 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 624 win_read = qla82xx_rd_32(ha, 625 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 626 if (win_read != window) { 627 ql_log(ql_log_warn, vha, 0xb006, 628 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 629 __func__, window, win_read); 630 } 631 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 632 } else { 633 /* 634 * peg gdb frequently accesses memory that doesn't exist, 635 * this limits the chit chat so debugging isn't slowed down. 636 */ 637 if ((qla82xx_pci_set_window_warning_count++ < 8) || 638 (qla82xx_pci_set_window_warning_count%64 == 0)) { 639 ql_log(ql_log_warn, vha, 0xb007, 640 "%s: Warning:%s Unknown address range!.\n", 641 __func__, QLA2XXX_DRIVER_NAME); 642 } 643 addr = -1UL; 644 } 645 return addr; 646} 647 648/* check if address is in the same windows as the previous access */ 649static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 650 unsigned long long addr) 651{ 652 int window; 653 unsigned long long qdr_max; 654 655 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 656 657 /* DDR network side */ 658 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 659 QLA82XX_ADDR_DDR_NET_MAX)) 660 BUG(); 661 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 662 QLA82XX_ADDR_OCM0_MAX)) 663 return 1; 664 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 665 QLA82XX_ADDR_OCM1_MAX)) 666 return 1; 667 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 668 /* QDR network side */ 669 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 670 if (ha->qdr_sn_window == window) 671 return 1; 672 } 673 return 0; 674} 675 676static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 677 u64 off, void *data, int size) 678{ 679 unsigned long flags; 680 void *addr = NULL; 681 int ret = 0; 682 u64 start; 683 uint8_t *mem_ptr = NULL; 684 unsigned long mem_base; 685 unsigned long mem_page; 686 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 687 688 write_lock_irqsave(&ha->hw_lock, flags); 689 690 /* 691 * If attempting to access unknown address or straddle hw windows, 692 * do not access. 693 */ 694 start = qla82xx_pci_set_window(ha, off); 695 if ((start == -1UL) || 696 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 697 write_unlock_irqrestore(&ha->hw_lock, flags); 698 ql_log(ql_log_fatal, vha, 0xb008, 699 "%s out of bound pci memory " 700 "access, offset is 0x%llx.\n", 701 QLA2XXX_DRIVER_NAME, off); 702 return -1; 703 } 704 705 write_unlock_irqrestore(&ha->hw_lock, flags); 706 mem_base = pci_resource_start(ha->pdev, 0); 707 mem_page = start & PAGE_MASK; 708 /* Map two pages whenever user tries to access addresses in two 709 * consecutive pages. 710 */ 711 if (mem_page != ((start + size - 1) & PAGE_MASK)) 712 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 713 else 714 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 715 if (mem_ptr == 0UL) { 716 *(u8 *)data = 0; 717 return -1; 718 } 719 addr = mem_ptr; 720 addr += start & (PAGE_SIZE - 1); 721 write_lock_irqsave(&ha->hw_lock, flags); 722 723 switch (size) { 724 case 1: 725 *(u8 *)data = readb(addr); 726 break; 727 case 2: 728 *(u16 *)data = readw(addr); 729 break; 730 case 4: 731 *(u32 *)data = readl(addr); 732 break; 733 case 8: 734 *(u64 *)data = readq(addr); 735 break; 736 default: 737 ret = -1; 738 break; 739 } 740 write_unlock_irqrestore(&ha->hw_lock, flags); 741 742 if (mem_ptr) 743 iounmap(mem_ptr); 744 return ret; 745} 746 747static int 748qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 749 u64 off, void *data, int size) 750{ 751 unsigned long flags; 752 void *addr = NULL; 753 int ret = 0; 754 u64 start; 755 uint8_t *mem_ptr = NULL; 756 unsigned long mem_base; 757 unsigned long mem_page; 758 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 759 760 write_lock_irqsave(&ha->hw_lock, flags); 761 762 /* 763 * If attempting to access unknown address or straddle hw windows, 764 * do not access. 765 */ 766 start = qla82xx_pci_set_window(ha, off); 767 if ((start == -1UL) || 768 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 769 write_unlock_irqrestore(&ha->hw_lock, flags); 770 ql_log(ql_log_fatal, vha, 0xb009, 771 "%s out of bount memory " 772 "access, offset is 0x%llx.\n", 773 QLA2XXX_DRIVER_NAME, off); 774 return -1; 775 } 776 777 write_unlock_irqrestore(&ha->hw_lock, flags); 778 mem_base = pci_resource_start(ha->pdev, 0); 779 mem_page = start & PAGE_MASK; 780 /* Map two pages whenever user tries to access addresses in two 781 * consecutive pages. 782 */ 783 if (mem_page != ((start + size - 1) & PAGE_MASK)) 784 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 785 else 786 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 787 if (mem_ptr == 0UL) 788 return -1; 789 790 addr = mem_ptr; 791 addr += start & (PAGE_SIZE - 1); 792 write_lock_irqsave(&ha->hw_lock, flags); 793 794 switch (size) { 795 case 1: 796 writeb(*(u8 *)data, addr); 797 break; 798 case 2: 799 writew(*(u16 *)data, addr); 800 break; 801 case 4: 802 writel(*(u32 *)data, addr); 803 break; 804 case 8: 805 writeq(*(u64 *)data, addr); 806 break; 807 default: 808 ret = -1; 809 break; 810 } 811 write_unlock_irqrestore(&ha->hw_lock, flags); 812 if (mem_ptr) 813 iounmap(mem_ptr); 814 return ret; 815} 816 817#define MTU_FUDGE_FACTOR 100 818static unsigned long 819qla82xx_decode_crb_addr(unsigned long addr) 820{ 821 int i; 822 unsigned long base_addr, offset, pci_base; 823 824 if (!qla82xx_crb_table_initialized) 825 qla82xx_crb_addr_transform_setup(); 826 827 pci_base = ADDR_ERROR; 828 base_addr = addr & 0xfff00000; 829 offset = addr & 0x000fffff; 830 831 for (i = 0; i < MAX_CRB_XFORM; i++) { 832 if (crb_addr_xform[i] == base_addr) { 833 pci_base = i << 20; 834 break; 835 } 836 } 837 if (pci_base == ADDR_ERROR) 838 return pci_base; 839 return pci_base + offset; 840} 841 842static long rom_max_timeout = 100; 843static long qla82xx_rom_lock_timeout = 100; 844 845static int 846qla82xx_rom_lock(struct qla_hw_data *ha) 847{ 848 int done = 0, timeout = 0; 849 850 while (!done) { 851 /* acquire semaphore2 from PCI HW block */ 852 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 853 if (done == 1) 854 break; 855 if (timeout >= qla82xx_rom_lock_timeout) 856 return -1; 857 timeout++; 858 } 859 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 860 return 0; 861} 862 863static void 864qla82xx_rom_unlock(struct qla_hw_data *ha) 865{ 866 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 867} 868 869static int 870qla82xx_wait_rom_busy(struct qla_hw_data *ha) 871{ 872 long timeout = 0; 873 long done = 0 ; 874 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 875 876 while (done == 0) { 877 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 878 done &= 4; 879 timeout++; 880 if (timeout >= rom_max_timeout) { 881 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 882 "%s: Timeout reached waiting for rom busy.\n", 883 QLA2XXX_DRIVER_NAME); 884 return -1; 885 } 886 } 887 return 0; 888} 889 890static int 891qla82xx_wait_rom_done(struct qla_hw_data *ha) 892{ 893 long timeout = 0; 894 long done = 0 ; 895 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 896 897 while (done == 0) { 898 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 899 done &= 2; 900 timeout++; 901 if (timeout >= rom_max_timeout) { 902 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 903 "%s: Timeout reached waiting for rom done.\n", 904 QLA2XXX_DRIVER_NAME); 905 return -1; 906 } 907 } 908 return 0; 909} 910 911static int 912qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 913{ 914 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 915 916 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 917 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 918 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 919 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 920 qla82xx_wait_rom_busy(ha); 921 if (qla82xx_wait_rom_done(ha)) { 922 ql_log(ql_log_fatal, vha, 0x00ba, 923 "Error waiting for rom done.\n"); 924 return -1; 925 } 926 /* Reset abyte_cnt and dummy_byte_cnt */ 927 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 928 udelay(10); 929 cond_resched(); 930 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 931 *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 932 return 0; 933} 934 935static int 936qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 937{ 938 int ret, loops = 0; 939 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 940 941 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 942 udelay(100); 943 schedule(); 944 loops++; 945 } 946 if (loops >= 50000) { 947 ql_log(ql_log_fatal, vha, 0x00b9, 948 "Failed to aquire SEM2 lock.\n"); 949 return -1; 950 } 951 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 952 qla82xx_rom_unlock(ha); 953 return ret; 954} 955 956static int 957qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 958{ 959 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 960 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 961 qla82xx_wait_rom_busy(ha); 962 if (qla82xx_wait_rom_done(ha)) { 963 ql_log(ql_log_warn, vha, 0xb00c, 964 "Error waiting for rom done.\n"); 965 return -1; 966 } 967 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 968 return 0; 969} 970 971static int 972qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 973{ 974 long timeout = 0; 975 uint32_t done = 1 ; 976 uint32_t val; 977 int ret = 0; 978 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 979 980 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 981 while ((done != 0) && (ret == 0)) { 982 ret = qla82xx_read_status_reg(ha, &val); 983 done = val & 1; 984 timeout++; 985 udelay(10); 986 cond_resched(); 987 if (timeout >= 50000) { 988 ql_log(ql_log_warn, vha, 0xb00d, 989 "Timeout reached waiting for write finish.\n"); 990 return -1; 991 } 992 } 993 return ret; 994} 995 996static int 997qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 998{ 999 uint32_t val; 1000 qla82xx_wait_rom_busy(ha); 1001 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1002 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1003 qla82xx_wait_rom_busy(ha); 1004 if (qla82xx_wait_rom_done(ha)) 1005 return -1; 1006 if (qla82xx_read_status_reg(ha, &val) != 0) 1007 return -1; 1008 if ((val & 2) != 2) 1009 return -1; 1010 return 0; 1011} 1012 1013static int 1014qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1015{ 1016 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1017 if (qla82xx_flash_set_write_enable(ha)) 1018 return -1; 1019 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1020 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1021 if (qla82xx_wait_rom_done(ha)) { 1022 ql_log(ql_log_warn, vha, 0xb00e, 1023 "Error waiting for rom done.\n"); 1024 return -1; 1025 } 1026 return qla82xx_flash_wait_write_finish(ha); 1027} 1028 1029static int 1030qla82xx_write_disable_flash(struct qla_hw_data *ha) 1031{ 1032 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1033 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1034 if (qla82xx_wait_rom_done(ha)) { 1035 ql_log(ql_log_warn, vha, 0xb00f, 1036 "Error waiting for rom done.\n"); 1037 return -1; 1038 } 1039 return 0; 1040} 1041 1042static int 1043ql82xx_rom_lock_d(struct qla_hw_data *ha) 1044{ 1045 int loops = 0; 1046 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1047 1048 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1049 udelay(100); 1050 cond_resched(); 1051 loops++; 1052 } 1053 if (loops >= 50000) { 1054 ql_log(ql_log_warn, vha, 0xb010, 1055 "ROM lock failed.\n"); 1056 return -1; 1057 } 1058 return 0;; 1059} 1060 1061static int 1062qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1063 uint32_t data) 1064{ 1065 int ret = 0; 1066 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1067 1068 ret = ql82xx_rom_lock_d(ha); 1069 if (ret < 0) { 1070 ql_log(ql_log_warn, vha, 0xb011, 1071 "ROM lock failed.\n"); 1072 return ret; 1073 } 1074 1075 if (qla82xx_flash_set_write_enable(ha)) 1076 goto done_write; 1077 1078 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1079 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1080 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1081 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1082 qla82xx_wait_rom_busy(ha); 1083 if (qla82xx_wait_rom_done(ha)) { 1084 ql_log(ql_log_warn, vha, 0xb012, 1085 "Error waiting for rom done.\n"); 1086 ret = -1; 1087 goto done_write; 1088 } 1089 1090 ret = qla82xx_flash_wait_write_finish(ha); 1091 1092done_write: 1093 qla82xx_rom_unlock(ha); 1094 return ret; 1095} 1096 1097/* This routine does CRB initialize sequence 1098 * to put the ISP into operational state 1099 */ 1100static int 1101qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1102{ 1103 int addr, val; 1104 int i ; 1105 struct crb_addr_pair *buf; 1106 unsigned long off; 1107 unsigned offset, n; 1108 struct qla_hw_data *ha = vha->hw; 1109 1110 struct crb_addr_pair { 1111 long addr; 1112 long data; 1113 }; 1114 1115 /* Halt all the indiviual PEGs and other blocks of the ISP */ 1116 qla82xx_rom_lock(ha); 1117 1118 /* disable all I2Q */ 1119 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1120 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1121 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1122 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1123 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1124 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1125 1126 /* disable all niu interrupts */ 1127 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1128 /* disable xge rx/tx */ 1129 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1130 /* disable xg1 rx/tx */ 1131 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1132 /* disable sideband mac */ 1133 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1134 /* disable ap0 mac */ 1135 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1136 /* disable ap1 mac */ 1137 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1138 1139 /* halt sre */ 1140 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1141 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1142 1143 /* halt epg */ 1144 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1145 1146 /* halt timers */ 1147 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1148 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1149 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1150 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1151 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1152 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1153 1154 /* halt pegs */ 1155 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1156 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1157 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1158 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1159 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1160 msleep(20); 1161 1162 /* big hammer */ 1163 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1164 /* don't reset CAM block on reset */ 1165 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1166 else 1167 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1168 1169 /* reset ms */ 1170 val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1171 val |= (1 << 1); 1172 qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1173 msleep(20); 1174 1175 /* unreset ms */ 1176 val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1177 val &= ~(1 << 1); 1178 qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1179 msleep(20); 1180 1181 qla82xx_rom_unlock(ha); 1182 1183 /* Read the signature value from the flash. 1184 * Offset 0: Contain signature (0xcafecafe) 1185 * Offset 4: Offset and number of addr/value pairs 1186 * that present in CRB initialize sequence 1187 */ 1188 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1189 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1190 ql_log(ql_log_fatal, vha, 0x006e, 1191 "Error Reading crb_init area: n: %08x.\n", n); 1192 return -1; 1193 } 1194 1195 /* Offset in flash = lower 16 bits 1196 * Number of enteries = upper 16 bits 1197 */ 1198 offset = n & 0xffffU; 1199 n = (n >> 16) & 0xffffU; 1200 1201 /* number of addr/value pair should not exceed 1024 enteries */ 1202 if (n >= 1024) { 1203 ql_log(ql_log_fatal, vha, 0x0071, 1204 "Card flash not initialized:n=0x%x.\n", n); 1205 return -1; 1206 } 1207 1208 ql_log(ql_log_info, vha, 0x0072, 1209 "%d CRB init values found in ROM.\n", n); 1210 1211 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1212 if (buf == NULL) { 1213 ql_log(ql_log_fatal, vha, 0x010c, 1214 "Unable to allocate memory.\n"); 1215 return -1; 1216 } 1217 1218 for (i = 0; i < n; i++) { 1219 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1220 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1221 kfree(buf); 1222 return -1; 1223 } 1224 1225 buf[i].addr = addr; 1226 buf[i].data = val; 1227 } 1228 1229 for (i = 0; i < n; i++) { 1230 /* Translate internal CRB initialization 1231 * address to PCI bus address 1232 */ 1233 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1234 QLA82XX_PCI_CRBSPACE; 1235 /* Not all CRB addr/value pair to be written, 1236 * some of them are skipped 1237 */ 1238 1239 /* skipping cold reboot MAGIC */ 1240 if (off == QLA82XX_CAM_RAM(0x1fc)) 1241 continue; 1242 1243 /* do not reset PCI */ 1244 if (off == (ROMUSB_GLB + 0xbc)) 1245 continue; 1246 1247 /* skip core clock, so that firmware can increase the clock */ 1248 if (off == (ROMUSB_GLB + 0xc8)) 1249 continue; 1250 1251 /* skip the function enable register */ 1252 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1253 continue; 1254 1255 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1256 continue; 1257 1258 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1259 continue; 1260 1261 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1262 continue; 1263 1264 if (off == ADDR_ERROR) { 1265 ql_log(ql_log_fatal, vha, 0x0116, 1266 "Unknow addr: 0x%08lx.\n", buf[i].addr); 1267 continue; 1268 } 1269 1270 qla82xx_wr_32(ha, off, buf[i].data); 1271 1272 /* ISP requires much bigger delay to settle down, 1273 * else crb_window returns 0xffffffff 1274 */ 1275 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1276 msleep(1000); 1277 1278 /* ISP requires millisec delay between 1279 * successive CRB register updation 1280 */ 1281 msleep(1); 1282 } 1283 1284 kfree(buf); 1285 1286 /* Resetting the data and instruction cache */ 1287 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1288 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1289 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1290 1291 /* Clear all protocol processing engines */ 1292 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1293 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1294 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1295 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1296 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1297 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1298 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1299 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1300 return 0; 1301} 1302 1303static int 1304qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1305 u64 off, void *data, int size) 1306{ 1307 int i, j, ret = 0, loop, sz[2], off0; 1308 int scale, shift_amount, startword; 1309 uint32_t temp; 1310 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1311 1312 /* 1313 * If not MN, go check for MS or invalid. 1314 */ 1315 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1316 mem_crb = QLA82XX_CRB_QDR_NET; 1317 else { 1318 mem_crb = QLA82XX_CRB_DDR_NET; 1319 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1320 return qla82xx_pci_mem_write_direct(ha, 1321 off, data, size); 1322 } 1323 1324 off0 = off & 0x7; 1325 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1326 sz[1] = size - sz[0]; 1327 1328 off8 = off & 0xfffffff0; 1329 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1330 shift_amount = 4; 1331 scale = 2; 1332 startword = (off & 0xf)/8; 1333 1334 for (i = 0; i < loop; i++) { 1335 if (qla82xx_pci_mem_read_2M(ha, off8 + 1336 (i << shift_amount), &word[i * scale], 8)) 1337 return -1; 1338 } 1339 1340 switch (size) { 1341 case 1: 1342 tmpw = *((uint8_t *)data); 1343 break; 1344 case 2: 1345 tmpw = *((uint16_t *)data); 1346 break; 1347 case 4: 1348 tmpw = *((uint32_t *)data); 1349 break; 1350 case 8: 1351 default: 1352 tmpw = *((uint64_t *)data); 1353 break; 1354 } 1355 1356 if (sz[0] == 8) { 1357 word[startword] = tmpw; 1358 } else { 1359 word[startword] &= 1360 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1361 word[startword] |= tmpw << (off0 * 8); 1362 } 1363 if (sz[1] != 0) { 1364 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1365 word[startword+1] |= tmpw >> (sz[0] * 8); 1366 } 1367 1368 for (i = 0; i < loop; i++) { 1369 temp = off8 + (i << shift_amount); 1370 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1371 temp = 0; 1372 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1373 temp = word[i * scale] & 0xffffffff; 1374 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1375 temp = (word[i * scale] >> 32) & 0xffffffff; 1376 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1377 temp = word[i*scale + 1] & 0xffffffff; 1378 qla82xx_wr_32(ha, mem_crb + 1379 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1380 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1381 qla82xx_wr_32(ha, mem_crb + 1382 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1383 1384 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1385 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1386 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1387 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1388 1389 for (j = 0; j < MAX_CTL_CHECK; j++) { 1390 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1391 if ((temp & MIU_TA_CTL_BUSY) == 0) 1392 break; 1393 } 1394 1395 if (j >= MAX_CTL_CHECK) { 1396 if (printk_ratelimit()) 1397 dev_err(&ha->pdev->dev, 1398 "failed to write through agent.\n"); 1399 ret = -1; 1400 break; 1401 } 1402 } 1403 1404 return ret; 1405} 1406 1407static int 1408qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1409{ 1410 int i; 1411 long size = 0; 1412 long flashaddr = ha->flt_region_bootload << 2; 1413 long memaddr = BOOTLD_START; 1414 u64 data; 1415 u32 high, low; 1416 size = (IMAGE_START - BOOTLD_START) / 8; 1417 1418 for (i = 0; i < size; i++) { 1419 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1420 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1421 return -1; 1422 } 1423 data = ((u64)high << 32) | low ; 1424 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1425 flashaddr += 8; 1426 memaddr += 8; 1427 1428 if (i % 0x1000 == 0) 1429 msleep(1); 1430 } 1431 udelay(100); 1432 read_lock(&ha->hw_lock); 1433 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1434 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1435 read_unlock(&ha->hw_lock); 1436 return 0; 1437} 1438 1439int 1440qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1441 u64 off, void *data, int size) 1442{ 1443 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1444 int shift_amount; 1445 uint32_t temp; 1446 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1447 1448 /* 1449 * If not MN, go check for MS or invalid. 1450 */ 1451 1452 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1453 mem_crb = QLA82XX_CRB_QDR_NET; 1454 else { 1455 mem_crb = QLA82XX_CRB_DDR_NET; 1456 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1457 return qla82xx_pci_mem_read_direct(ha, 1458 off, data, size); 1459 } 1460 1461 off8 = off & 0xfffffff0; 1462 off0[0] = off & 0xf; 1463 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1464 shift_amount = 4; 1465 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1466 off0[1] = 0; 1467 sz[1] = size - sz[0]; 1468 1469 for (i = 0; i < loop; i++) { 1470 temp = off8 + (i << shift_amount); 1471 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1472 temp = 0; 1473 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1474 temp = MIU_TA_CTL_ENABLE; 1475 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1476 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1477 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1478 1479 for (j = 0; j < MAX_CTL_CHECK; j++) { 1480 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1481 if ((temp & MIU_TA_CTL_BUSY) == 0) 1482 break; 1483 } 1484 1485 if (j >= MAX_CTL_CHECK) { 1486 if (printk_ratelimit()) 1487 dev_err(&ha->pdev->dev, 1488 "failed to read through agent.\n"); 1489 break; 1490 } 1491 1492 start = off0[i] >> 2; 1493 end = (off0[i] + sz[i] - 1) >> 2; 1494 for (k = start; k <= end; k++) { 1495 temp = qla82xx_rd_32(ha, 1496 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1497 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1498 } 1499 } 1500 1501 if (j >= MAX_CTL_CHECK) 1502 return -1; 1503 1504 if ((off0[0] & 7) == 0) { 1505 val = word[0]; 1506 } else { 1507 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1508 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1509 } 1510 1511 switch (size) { 1512 case 1: 1513 *(uint8_t *)data = val; 1514 break; 1515 case 2: 1516 *(uint16_t *)data = val; 1517 break; 1518 case 4: 1519 *(uint32_t *)data = val; 1520 break; 1521 case 8: 1522 *(uint64_t *)data = val; 1523 break; 1524 } 1525 return 0; 1526} 1527 1528 1529static struct qla82xx_uri_table_desc * 1530qla82xx_get_table_desc(const u8 *unirom, int section) 1531{ 1532 uint32_t i; 1533 struct qla82xx_uri_table_desc *directory = 1534 (struct qla82xx_uri_table_desc *)&unirom[0]; 1535 __le32 offset; 1536 __le32 tab_type; 1537 __le32 entries = cpu_to_le32(directory->num_entries); 1538 1539 for (i = 0; i < entries; i++) { 1540 offset = cpu_to_le32(directory->findex) + 1541 (i * cpu_to_le32(directory->entry_size)); 1542 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 1543 1544 if (tab_type == section) 1545 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1546 } 1547 1548 return NULL; 1549} 1550 1551static struct qla82xx_uri_data_desc * 1552qla82xx_get_data_desc(struct qla_hw_data *ha, 1553 u32 section, u32 idx_offset) 1554{ 1555 const u8 *unirom = ha->hablob->fw->data; 1556 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 1557 struct qla82xx_uri_table_desc *tab_desc = NULL; 1558 __le32 offset; 1559 1560 tab_desc = qla82xx_get_table_desc(unirom, section); 1561 if (!tab_desc) 1562 return NULL; 1563 1564 offset = cpu_to_le32(tab_desc->findex) + 1565 (cpu_to_le32(tab_desc->entry_size) * idx); 1566 1567 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1568} 1569 1570static u8 * 1571qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1572{ 1573 u32 offset = BOOTLD_START; 1574 struct qla82xx_uri_data_desc *uri_desc = NULL; 1575 1576 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1577 uri_desc = qla82xx_get_data_desc(ha, 1578 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1579 if (uri_desc) 1580 offset = cpu_to_le32(uri_desc->findex); 1581 } 1582 1583 return (u8 *)&ha->hablob->fw->data[offset]; 1584} 1585 1586static __le32 1587qla82xx_get_fw_size(struct qla_hw_data *ha) 1588{ 1589 struct qla82xx_uri_data_desc *uri_desc = NULL; 1590 1591 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1592 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1593 QLA82XX_URI_FIRMWARE_IDX_OFF); 1594 if (uri_desc) 1595 return cpu_to_le32(uri_desc->size); 1596 } 1597 1598 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1599} 1600 1601static u8 * 1602qla82xx_get_fw_offs(struct qla_hw_data *ha) 1603{ 1604 u32 offset = IMAGE_START; 1605 struct qla82xx_uri_data_desc *uri_desc = NULL; 1606 1607 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1608 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1609 QLA82XX_URI_FIRMWARE_IDX_OFF); 1610 if (uri_desc) 1611 offset = cpu_to_le32(uri_desc->findex); 1612 } 1613 1614 return (u8 *)&ha->hablob->fw->data[offset]; 1615} 1616 1617/* PCI related functions */ 1618char * 1619qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) 1620{ 1621 int pcie_reg; 1622 struct qla_hw_data *ha = vha->hw; 1623 char lwstr[6]; 1624 uint16_t lnk; 1625 1626 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1627 pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); 1628 ha->link_width = (lnk >> 4) & 0x3f; 1629 1630 strcpy(str, "PCIe ("); 1631 strcat(str, "2.5Gb/s "); 1632 snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); 1633 strcat(str, lwstr); 1634 return str; 1635} 1636 1637int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1638{ 1639 unsigned long val = 0; 1640 u32 control; 1641 1642 switch (region) { 1643 case 0: 1644 val = 0; 1645 break; 1646 case 1: 1647 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1648 val = control + QLA82XX_MSIX_TBL_SPACE; 1649 break; 1650 } 1651 return val; 1652} 1653 1654 1655int 1656qla82xx_iospace_config(struct qla_hw_data *ha) 1657{ 1658 uint32_t len = 0; 1659 1660 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1661 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1662 "Failed to reserver selected regions.\n"); 1663 goto iospace_error_exit; 1664 } 1665 1666 /* Use MMIO operations for all accesses. */ 1667 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1668 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1669 "Region #0 not an MMIO resource, aborting.\n"); 1670 goto iospace_error_exit; 1671 } 1672 1673 len = pci_resource_len(ha->pdev, 0); 1674 ha->nx_pcibase = 1675 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1676 if (!ha->nx_pcibase) { 1677 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1678 "Cannot remap pcibase MMIO, aborting.\n"); 1679 pci_release_regions(ha->pdev); 1680 goto iospace_error_exit; 1681 } 1682 1683 /* Mapping of IO base pointer */ 1684 ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1685 0xbc000 + (ha->pdev->devfn << 11)); 1686 1687 if (!ql2xdbwr) { 1688 ha->nxdb_wr_ptr = 1689 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1690 (ha->pdev->devfn << 12)), 4); 1691 if (!ha->nxdb_wr_ptr) { 1692 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1693 "Cannot remap MMIO, aborting.\n"); 1694 pci_release_regions(ha->pdev); 1695 goto iospace_error_exit; 1696 } 1697 1698 /* Mapping of IO base pointer, 1699 * door bell read and write pointer 1700 */ 1701 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1702 (ha->pdev->devfn * 8); 1703 } else { 1704 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1705 QLA82XX_CAMRAM_DB1 : 1706 QLA82XX_CAMRAM_DB2); 1707 } 1708 1709 ha->max_req_queues = ha->max_rsp_queues = 1; 1710 ha->msix_count = ha->max_rsp_queues + 1; 1711 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1712 "nx_pci_base=%p iobase=%p " 1713 "max_req_queues=%d msix_count=%d.\n", 1714 (void *)ha->nx_pcibase, ha->iobase, 1715 ha->max_req_queues, ha->msix_count); 1716 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1717 "nx_pci_base=%p iobase=%p " 1718 "max_req_queues=%d msix_count=%d.\n", 1719 (void *)ha->nx_pcibase, ha->iobase, 1720 ha->max_req_queues, ha->msix_count); 1721 return 0; 1722 1723iospace_error_exit: 1724 return -ENOMEM; 1725} 1726 1727/* GS related functions */ 1728 1729/* Initialization related functions */ 1730 1731/** 1732 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1733 * @ha: HA context 1734 * 1735 * Returns 0 on success. 1736*/ 1737int 1738qla82xx_pci_config(scsi_qla_host_t *vha) 1739{ 1740 struct qla_hw_data *ha = vha->hw; 1741 int ret; 1742 1743 pci_set_master(ha->pdev); 1744 ret = pci_set_mwi(ha->pdev); 1745 ha->chip_revision = ha->pdev->revision; 1746 ql_dbg(ql_dbg_init, vha, 0x0043, 1747 "Chip revision:%d.\n", 1748 ha->chip_revision); 1749 return 0; 1750} 1751 1752/** 1753 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1754 * @ha: HA context 1755 * 1756 * Returns 0 on success. 1757 */ 1758void 1759qla82xx_reset_chip(scsi_qla_host_t *vha) 1760{ 1761 struct qla_hw_data *ha = vha->hw; 1762 ha->isp_ops->disable_intrs(ha); 1763} 1764 1765void qla82xx_config_rings(struct scsi_qla_host *vha) 1766{ 1767 struct qla_hw_data *ha = vha->hw; 1768 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1769 struct init_cb_81xx *icb; 1770 struct req_que *req = ha->req_q_map[0]; 1771 struct rsp_que *rsp = ha->rsp_q_map[0]; 1772 1773 /* Setup ring parameters in initialization control block. */ 1774 icb = (struct init_cb_81xx *)ha->init_cb; 1775 icb->request_q_outpointer = __constant_cpu_to_le16(0); 1776 icb->response_q_inpointer = __constant_cpu_to_le16(0); 1777 icb->request_q_length = cpu_to_le16(req->length); 1778 icb->response_q_length = cpu_to_le16(rsp->length); 1779 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1780 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1781 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1782 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1783 1784 WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1785 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1786 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1787} 1788 1789void qla82xx_reset_adapter(struct scsi_qla_host *vha) 1790{ 1791 struct qla_hw_data *ha = vha->hw; 1792 vha->flags.online = 0; 1793 qla2x00_try_to_stop_firmware(vha); 1794 ha->isp_ops->disable_intrs(ha); 1795} 1796 1797static int 1798qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1799{ 1800 u64 *ptr64; 1801 u32 i, flashaddr, size; 1802 __le64 data; 1803 1804 size = (IMAGE_START - BOOTLD_START) / 8; 1805 1806 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1807 flashaddr = BOOTLD_START; 1808 1809 for (i = 0; i < size; i++) { 1810 data = cpu_to_le64(ptr64[i]); 1811 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1812 return -EIO; 1813 flashaddr += 8; 1814 } 1815 1816 flashaddr = FLASH_ADDR_START; 1817 size = (__force u32)qla82xx_get_fw_size(ha) / 8; 1818 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1819 1820 for (i = 0; i < size; i++) { 1821 data = cpu_to_le64(ptr64[i]); 1822 1823 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1824 return -EIO; 1825 flashaddr += 8; 1826 } 1827 udelay(100); 1828 1829 /* Write a magic value to CAMRAM register 1830 * at a specified offset to indicate 1831 * that all data is written and 1832 * ready for firmware to initialize. 1833 */ 1834 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1835 1836 read_lock(&ha->hw_lock); 1837 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1838 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1839 read_unlock(&ha->hw_lock); 1840 return 0; 1841} 1842 1843static int 1844qla82xx_set_product_offset(struct qla_hw_data *ha) 1845{ 1846 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1847 const uint8_t *unirom = ha->hablob->fw->data; 1848 uint32_t i; 1849 __le32 entries; 1850 __le32 flags, file_chiprev, offset; 1851 uint8_t chiprev = ha->chip_revision; 1852 /* Hardcoding mn_present flag for P3P */ 1853 int mn_present = 0; 1854 uint32_t flagbit; 1855 1856 ptab_desc = qla82xx_get_table_desc(unirom, 1857 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1858 if (!ptab_desc) 1859 return -1; 1860 1861 entries = cpu_to_le32(ptab_desc->num_entries); 1862 1863 for (i = 0; i < entries; i++) { 1864 offset = cpu_to_le32(ptab_desc->findex) + 1865 (i * cpu_to_le32(ptab_desc->entry_size)); 1866 flags = cpu_to_le32(*((int *)&unirom[offset] + 1867 QLA82XX_URI_FLAGS_OFF)); 1868 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 1869 QLA82XX_URI_CHIP_REV_OFF)); 1870 1871 flagbit = mn_present ? 1 : 2; 1872 1873 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1874 ha->file_prd_off = offset; 1875 return 0; 1876 } 1877 } 1878 return -1; 1879} 1880 1881int 1882qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1883{ 1884 __le32 val; 1885 uint32_t min_size; 1886 struct qla_hw_data *ha = vha->hw; 1887 const struct firmware *fw = ha->hablob->fw; 1888 1889 ha->fw_type = fw_type; 1890 1891 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1892 if (qla82xx_set_product_offset(ha)) 1893 return -EINVAL; 1894 1895 min_size = QLA82XX_URI_FW_MIN_SIZE; 1896 } else { 1897 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1898 if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 1899 return -EINVAL; 1900 1901 min_size = QLA82XX_FW_MIN_SIZE; 1902 } 1903 1904 if (fw->size < min_size) 1905 return -EINVAL; 1906 return 0; 1907} 1908 1909static int 1910qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1911{ 1912 u32 val = 0; 1913 int retries = 60; 1914 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1915 1916 do { 1917 read_lock(&ha->hw_lock); 1918 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1919 read_unlock(&ha->hw_lock); 1920 1921 switch (val) { 1922 case PHAN_INITIALIZE_COMPLETE: 1923 case PHAN_INITIALIZE_ACK: 1924 return QLA_SUCCESS; 1925 case PHAN_INITIALIZE_FAILED: 1926 break; 1927 default: 1928 break; 1929 } 1930 ql_log(ql_log_info, vha, 0x00a8, 1931 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1932 val, retries); 1933 1934 msleep(500); 1935 1936 } while (--retries); 1937 1938 ql_log(ql_log_fatal, vha, 0x00a9, 1939 "Cmd Peg initialization failed: 0x%x.\n", val); 1940 1941 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1942 read_lock(&ha->hw_lock); 1943 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1944 read_unlock(&ha->hw_lock); 1945 return QLA_FUNCTION_FAILED; 1946} 1947 1948static int 1949qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1950{ 1951 u32 val = 0; 1952 int retries = 60; 1953 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1954 1955 do { 1956 read_lock(&ha->hw_lock); 1957 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1958 read_unlock(&ha->hw_lock); 1959 1960 switch (val) { 1961 case PHAN_INITIALIZE_COMPLETE: 1962 case PHAN_INITIALIZE_ACK: 1963 return QLA_SUCCESS; 1964 case PHAN_INITIALIZE_FAILED: 1965 break; 1966 default: 1967 break; 1968 } 1969 ql_log(ql_log_info, vha, 0x00ab, 1970 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1971 val, retries); 1972 1973 msleep(500); 1974 1975 } while (--retries); 1976 1977 ql_log(ql_log_fatal, vha, 0x00ac, 1978 "Rcv Peg initializatin failed: 0x%x.\n", val); 1979 read_lock(&ha->hw_lock); 1980 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1981 read_unlock(&ha->hw_lock); 1982 return QLA_FUNCTION_FAILED; 1983} 1984 1985/* ISR related functions */ 1986uint32_t qla82xx_isr_int_target_mask_enable[8] = { 1987 ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, 1988 ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, 1989 ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, 1990 ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 1991}; 1992 1993uint32_t qla82xx_isr_int_target_status[8] = { 1994 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, 1995 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, 1996 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, 1997 ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 1998}; 1999 2000static struct qla82xx_legacy_intr_set legacy_intr[] = \ 2001 QLA82XX_LEGACY_INTR_CONFIG; 2002 2003/* 2004 * qla82xx_mbx_completion() - Process mailbox command completions. 2005 * @ha: SCSI driver HA context 2006 * @mb0: Mailbox0 register 2007 */ 2008static void 2009qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 2010{ 2011 uint16_t cnt; 2012 uint16_t __iomem *wptr; 2013 struct qla_hw_data *ha = vha->hw; 2014 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 2015 wptr = (uint16_t __iomem *)®->mailbox_out[1]; 2016 2017 /* Load return mailbox registers. */ 2018 ha->flags.mbox_int = 1; 2019 ha->mailbox_out[0] = mb0; 2020 2021 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2022 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 2023 wptr++; 2024 } 2025 2026 if (!ha->mcp) 2027 ql_dbg(ql_dbg_async, vha, 0x5053, 2028 "MBX pointer ERROR.\n"); 2029} 2030 2031/* 2032 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2033 * @irq: 2034 * @dev_id: SCSI driver HA context 2035 * @regs: 2036 * 2037 * Called by system whenever the host adapter generates an interrupt. 2038 * 2039 * Returns handled flag. 2040 */ 2041irqreturn_t 2042qla82xx_intr_handler(int irq, void *dev_id) 2043{ 2044 scsi_qla_host_t *vha; 2045 struct qla_hw_data *ha; 2046 struct rsp_que *rsp; 2047 struct device_reg_82xx __iomem *reg; 2048 int status = 0, status1 = 0; 2049 unsigned long flags; 2050 unsigned long iter; 2051 uint32_t stat = 0; 2052 uint16_t mb[4]; 2053 2054 rsp = (struct rsp_que *) dev_id; 2055 if (!rsp) { 2056 printk(KERN_INFO 2057 "%s(): NULL response queue pointer.\n", __func__); 2058 return IRQ_NONE; 2059 } 2060 ha = rsp->hw; 2061 2062 if (!ha->flags.msi_enabled) { 2063 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2064 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2065 return IRQ_NONE; 2066 2067 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2068 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2069 return IRQ_NONE; 2070 } 2071 2072 /* clear the interrupt */ 2073 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2074 2075 /* read twice to ensure write is flushed */ 2076 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2077 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2078 2079 reg = &ha->iobase->isp82; 2080 2081 spin_lock_irqsave(&ha->hardware_lock, flags); 2082 vha = pci_get_drvdata(ha->pdev); 2083 for (iter = 1; iter--; ) { 2084 2085 if (RD_REG_DWORD(®->host_int)) { 2086 stat = RD_REG_DWORD(®->host_status); 2087 2088 switch (stat & 0xff) { 2089 case 0x1: 2090 case 0x2: 2091 case 0x10: 2092 case 0x11: 2093 qla82xx_mbx_completion(vha, MSW(stat)); 2094 status |= MBX_INTERRUPT; 2095 break; 2096 case 0x12: 2097 mb[0] = MSW(stat); 2098 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2099 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2100 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2101 qla2x00_async_event(vha, rsp, mb); 2102 break; 2103 case 0x13: 2104 qla24xx_process_response_queue(vha, rsp); 2105 break; 2106 default: 2107 ql_dbg(ql_dbg_async, vha, 0x5054, 2108 "Unrecognized interrupt type (%d).\n", 2109 stat & 0xff); 2110 break; 2111 } 2112 } 2113 WRT_REG_DWORD(®->host_int, 0); 2114 } 2115 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2116 if (!ha->flags.msi_enabled) 2117 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2118 2119#ifdef QL_DEBUG_LEVEL_17 2120 if (!irq && ha->flags.eeh_busy) 2121 ql_log(ql_log_warn, vha, 0x503d, 2122 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2123 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2124#endif 2125 2126 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2127 (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2128 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2129 complete(&ha->mbx_intr_comp); 2130 } 2131 return IRQ_HANDLED; 2132} 2133 2134irqreturn_t 2135qla82xx_msix_default(int irq, void *dev_id) 2136{ 2137 scsi_qla_host_t *vha; 2138 struct qla_hw_data *ha; 2139 struct rsp_que *rsp; 2140 struct device_reg_82xx __iomem *reg; 2141 int status = 0; 2142 unsigned long flags; 2143 uint32_t stat = 0; 2144 uint16_t mb[4]; 2145 2146 rsp = (struct rsp_que *) dev_id; 2147 if (!rsp) { 2148 printk(KERN_INFO 2149 "%s(): NULL response queue pointer.\n", __func__); 2150 return IRQ_NONE; 2151 } 2152 ha = rsp->hw; 2153 2154 reg = &ha->iobase->isp82; 2155 2156 spin_lock_irqsave(&ha->hardware_lock, flags); 2157 vha = pci_get_drvdata(ha->pdev); 2158 do { 2159 if (RD_REG_DWORD(®->host_int)) { 2160 stat = RD_REG_DWORD(®->host_status); 2161 2162 switch (stat & 0xff) { 2163 case 0x1: 2164 case 0x2: 2165 case 0x10: 2166 case 0x11: 2167 qla82xx_mbx_completion(vha, MSW(stat)); 2168 status |= MBX_INTERRUPT; 2169 break; 2170 case 0x12: 2171 mb[0] = MSW(stat); 2172 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2173 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2174 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2175 qla2x00_async_event(vha, rsp, mb); 2176 break; 2177 case 0x13: 2178 qla24xx_process_response_queue(vha, rsp); 2179 break; 2180 default: 2181 ql_dbg(ql_dbg_async, vha, 0x5041, 2182 "Unrecognized interrupt type (%d).\n", 2183 stat & 0xff); 2184 break; 2185 } 2186 } 2187 WRT_REG_DWORD(®->host_int, 0); 2188 } while (0); 2189 2190 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2191 2192#ifdef QL_DEBUG_LEVEL_17 2193 if (!irq && ha->flags.eeh_busy) 2194 ql_log(ql_log_warn, vha, 0x5044, 2195 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2196 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2197#endif 2198 2199 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2200 (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2201 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2202 complete(&ha->mbx_intr_comp); 2203 } 2204 return IRQ_HANDLED; 2205} 2206 2207irqreturn_t 2208qla82xx_msix_rsp_q(int irq, void *dev_id) 2209{ 2210 scsi_qla_host_t *vha; 2211 struct qla_hw_data *ha; 2212 struct rsp_que *rsp; 2213 struct device_reg_82xx __iomem *reg; 2214 unsigned long flags; 2215 2216 rsp = (struct rsp_que *) dev_id; 2217 if (!rsp) { 2218 printk(KERN_INFO 2219 "%s(): NULL response queue pointer.\n", __func__); 2220 return IRQ_NONE; 2221 } 2222 2223 ha = rsp->hw; 2224 reg = &ha->iobase->isp82; 2225 spin_lock_irqsave(&ha->hardware_lock, flags); 2226 vha = pci_get_drvdata(ha->pdev); 2227 qla24xx_process_response_queue(vha, rsp); 2228 WRT_REG_DWORD(®->host_int, 0); 2229 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2230 return IRQ_HANDLED; 2231} 2232 2233void 2234qla82xx_poll(int irq, void *dev_id) 2235{ 2236 scsi_qla_host_t *vha; 2237 struct qla_hw_data *ha; 2238 struct rsp_que *rsp; 2239 struct device_reg_82xx __iomem *reg; 2240 int status = 0; 2241 uint32_t stat; 2242 uint16_t mb[4]; 2243 unsigned long flags; 2244 2245 rsp = (struct rsp_que *) dev_id; 2246 if (!rsp) { 2247 printk(KERN_INFO 2248 "%s(): NULL response queue pointer.\n", __func__); 2249 return; 2250 } 2251 ha = rsp->hw; 2252 2253 reg = &ha->iobase->isp82; 2254 spin_lock_irqsave(&ha->hardware_lock, flags); 2255 vha = pci_get_drvdata(ha->pdev); 2256 2257 if (RD_REG_DWORD(®->host_int)) { 2258 stat = RD_REG_DWORD(®->host_status); 2259 switch (stat & 0xff) { 2260 case 0x1: 2261 case 0x2: 2262 case 0x10: 2263 case 0x11: 2264 qla82xx_mbx_completion(vha, MSW(stat)); 2265 status |= MBX_INTERRUPT; 2266 break; 2267 case 0x12: 2268 mb[0] = MSW(stat); 2269 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2270 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2271 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2272 qla2x00_async_event(vha, rsp, mb); 2273 break; 2274 case 0x13: 2275 qla24xx_process_response_queue(vha, rsp); 2276 break; 2277 default: 2278 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2279 "Unrecognized interrupt type (%d).\n", 2280 stat * 0xff); 2281 break; 2282 } 2283 } 2284 WRT_REG_DWORD(®->host_int, 0); 2285 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2286} 2287 2288void 2289qla82xx_enable_intrs(struct qla_hw_data *ha) 2290{ 2291 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2292 qla82xx_mbx_intr_enable(vha); 2293 spin_lock_irq(&ha->hardware_lock); 2294 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2295 spin_unlock_irq(&ha->hardware_lock); 2296 ha->interrupts_on = 1; 2297} 2298 2299void 2300qla82xx_disable_intrs(struct qla_hw_data *ha) 2301{ 2302 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2303 qla82xx_mbx_intr_disable(vha); 2304 spin_lock_irq(&ha->hardware_lock); 2305 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2306 spin_unlock_irq(&ha->hardware_lock); 2307 ha->interrupts_on = 0; 2308} 2309 2310void qla82xx_init_flags(struct qla_hw_data *ha) 2311{ 2312 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2313 2314 /* ISP 8021 initializations */ 2315 rwlock_init(&ha->hw_lock); 2316 ha->qdr_sn_window = -1; 2317 ha->ddr_mn_window = -1; 2318 ha->curr_window = 255; 2319 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2320 nx_legacy_intr = &legacy_intr[ha->portnum]; 2321 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2322 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2323 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2324 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2325} 2326 2327inline void 2328qla82xx_set_drv_active(scsi_qla_host_t *vha) 2329{ 2330 uint32_t drv_active; 2331 struct qla_hw_data *ha = vha->hw; 2332 2333 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2334 2335 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2336 if (drv_active == 0xffffffff) { 2337 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2338 QLA82XX_DRV_NOT_ACTIVE); 2339 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2340 } 2341 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2342 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2343} 2344 2345inline void 2346qla82xx_clear_drv_active(struct qla_hw_data *ha) 2347{ 2348 uint32_t drv_active; 2349 2350 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2351 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2352 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2353} 2354 2355static inline int 2356qla82xx_need_reset(struct qla_hw_data *ha) 2357{ 2358 uint32_t drv_state; 2359 int rval; 2360 2361 if (ha->flags.isp82xx_reset_owner) 2362 return 1; 2363 else { 2364 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2365 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2366 return rval; 2367 } 2368} 2369 2370static inline void 2371qla82xx_set_rst_ready(struct qla_hw_data *ha) 2372{ 2373 uint32_t drv_state; 2374 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2375 2376 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2377 2378 /* If reset value is all FF's, initialize DRV_STATE */ 2379 if (drv_state == 0xffffffff) { 2380 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2381 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2382 } 2383 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2384 ql_dbg(ql_dbg_init, vha, 0x00bb, 2385 "drv_state = 0x%08x.\n", drv_state); 2386 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2387} 2388 2389static inline void 2390qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2391{ 2392 uint32_t drv_state; 2393 2394 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2395 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2396 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2397} 2398 2399static inline void 2400qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2401{ 2402 uint32_t qsnt_state; 2403 2404 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2405 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2406 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2407} 2408 2409void 2410qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2411{ 2412 struct qla_hw_data *ha = vha->hw; 2413 uint32_t qsnt_state; 2414 2415 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2416 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2417 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2418} 2419 2420static int 2421qla82xx_load_fw(scsi_qla_host_t *vha) 2422{ 2423 int rst; 2424 struct fw_blob *blob; 2425 struct qla_hw_data *ha = vha->hw; 2426 2427 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2428 ql_log(ql_log_fatal, vha, 0x009f, 2429 "Error during CRB initialization.\n"); 2430 return QLA_FUNCTION_FAILED; 2431 } 2432 udelay(500); 2433 2434 /* Bring QM and CAMRAM out of reset */ 2435 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2436 rst &= ~((1 << 28) | (1 << 24)); 2437 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2438 2439 /* 2440 * FW Load priority: 2441 * 1) Operational firmware residing in flash. 2442 * 2) Firmware via request-firmware interface (.bin file). 2443 */ 2444 if (ql2xfwloadbin == 2) 2445 goto try_blob_fw; 2446 2447 ql_log(ql_log_info, vha, 0x00a0, 2448 "Attempting to load firmware from flash.\n"); 2449 2450 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2451 ql_log(ql_log_info, vha, 0x00a1, 2452 "Firmware loaded successully from flash.\n"); 2453 return QLA_SUCCESS; 2454 } else { 2455 ql_log(ql_log_warn, vha, 0x0108, 2456 "Firmware load from flash failed.\n"); 2457 } 2458 2459try_blob_fw: 2460 ql_log(ql_log_info, vha, 0x00a2, 2461 "Attempting to load firmware from blob.\n"); 2462 2463 /* Load firmware blob. */ 2464 blob = ha->hablob = qla2x00_request_firmware(vha); 2465 if (!blob) { 2466 ql_log(ql_log_fatal, vha, 0x00a3, 2467 "Firmware image not preset.\n"); 2468 goto fw_load_failed; 2469 } 2470 2471 /* Validating firmware blob */ 2472 if (qla82xx_validate_firmware_blob(vha, 2473 QLA82XX_FLASH_ROMIMAGE)) { 2474 /* Fallback to URI format */ 2475 if (qla82xx_validate_firmware_blob(vha, 2476 QLA82XX_UNIFIED_ROMIMAGE)) { 2477 ql_log(ql_log_fatal, vha, 0x00a4, 2478 "No valid firmware image found.\n"); 2479 return QLA_FUNCTION_FAILED; 2480 } 2481 } 2482 2483 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2484 ql_log(ql_log_info, vha, 0x00a5, 2485 "Firmware loaded successfully from binary blob.\n"); 2486 return QLA_SUCCESS; 2487 } else { 2488 ql_log(ql_log_fatal, vha, 0x00a6, 2489 "Firmware load failed for binary blob.\n"); 2490 blob->fw = NULL; 2491 blob = NULL; 2492 goto fw_load_failed; 2493 } 2494 return QLA_SUCCESS; 2495 2496fw_load_failed: 2497 return QLA_FUNCTION_FAILED; 2498} 2499 2500int 2501qla82xx_start_firmware(scsi_qla_host_t *vha) 2502{ 2503 int pcie_cap; 2504 uint16_t lnk; 2505 struct qla_hw_data *ha = vha->hw; 2506 2507 /* scrub dma mask expansion register */ 2508 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2509 2510 /* Put both the PEG CMD and RCV PEG to default state 2511 * of 0 before resetting the hardware 2512 */ 2513 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2514 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2515 2516 /* Overwrite stale initialization register values */ 2517 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2518 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2519 2520 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2521 ql_log(ql_log_fatal, vha, 0x00a7, 2522 "Error trying to start fw.\n"); 2523 return QLA_FUNCTION_FAILED; 2524 } 2525 2526 /* Handshake with the card before we register the devices. */ 2527 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2528 ql_log(ql_log_fatal, vha, 0x00aa, 2529 "Error during card handshake.\n"); 2530 return QLA_FUNCTION_FAILED; 2531 } 2532 2533 /* Negotiated Link width */ 2534 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 2535 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 2536 ha->link_width = (lnk >> 4) & 0x3f; 2537 2538 /* Synchronize with Receive peg */ 2539 return qla82xx_check_rcvpeg_state(ha); 2540} 2541 2542static inline int 2543qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt, 2544 uint16_t tot_dsds) 2545{ 2546 uint32_t *cur_dsd = NULL; 2547 scsi_qla_host_t *vha; 2548 struct qla_hw_data *ha; 2549 struct scsi_cmnd *cmd; 2550 struct scatterlist *cur_seg; 2551 uint32_t *dsd_seg; 2552 void *next_dsd; 2553 uint8_t avail_dsds; 2554 uint8_t first_iocb = 1; 2555 uint32_t dsd_list_len; 2556 struct dsd_dma *dsd_ptr; 2557 struct ct6_dsd *ctx; 2558 2559 cmd = sp->cmd; 2560 2561 /* Update entry type to indicate Command Type 3 IOCB */ 2562 *((uint32_t *)(&cmd_pkt->entry_type)) = 2563 __constant_cpu_to_le32(COMMAND_TYPE_6); 2564 2565 /* No data transfer */ 2566 if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { 2567 cmd_pkt->byte_count = __constant_cpu_to_le32(0); 2568 return 0; 2569 } 2570 2571 vha = sp->fcport->vha; 2572 ha = vha->hw; 2573 2574 /* Set transfer direction */ 2575 if (cmd->sc_data_direction == DMA_TO_DEVICE) { 2576 cmd_pkt->control_flags = 2577 __constant_cpu_to_le16(CF_WRITE_DATA); 2578 ha->qla_stats.output_bytes += scsi_bufflen(cmd); 2579 } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) { 2580 cmd_pkt->control_flags = 2581 __constant_cpu_to_le16(CF_READ_DATA); 2582 ha->qla_stats.input_bytes += scsi_bufflen(cmd); 2583 } 2584 2585 cur_seg = scsi_sglist(cmd); 2586 ctx = sp->ctx; 2587 2588 while (tot_dsds) { 2589 avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ? 2590 QLA_DSDS_PER_IOCB : tot_dsds; 2591 tot_dsds -= avail_dsds; 2592 dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE; 2593 2594 dsd_ptr = list_first_entry(&ha->gbl_dsd_list, 2595 struct dsd_dma, list); 2596 next_dsd = dsd_ptr->dsd_addr; 2597 list_del(&dsd_ptr->list); 2598 ha->gbl_dsd_avail--; 2599 list_add_tail(&dsd_ptr->list, &ctx->dsd_list); 2600 ctx->dsd_use_cnt++; 2601 ha->gbl_dsd_inuse++; 2602 2603 if (first_iocb) { 2604 first_iocb = 0; 2605 dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address; 2606 *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2607 *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 2608 cmd_pkt->fcp_data_dseg_len = cpu_to_le32(dsd_list_len); 2609 } else { 2610 *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); 2611 *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); 2612 *cur_dsd++ = cpu_to_le32(dsd_list_len); 2613 } 2614 cur_dsd = (uint32_t *)next_dsd; 2615 while (avail_dsds) { 2616 dma_addr_t sle_dma; 2617 2618 sle_dma = sg_dma_address(cur_seg); 2619 *cur_dsd++ = cpu_to_le32(LSD(sle_dma)); 2620 *cur_dsd++ = cpu_to_le32(MSD(sle_dma)); 2621 *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg)); 2622 cur_seg = sg_next(cur_seg); 2623 avail_dsds--; 2624 } 2625 } 2626 2627 /* Null termination */ 2628 *cur_dsd++ = 0; 2629 *cur_dsd++ = 0; 2630 *cur_dsd++ = 0; 2631 cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE; 2632 return 0; 2633} 2634 2635/* 2636 * qla82xx_calc_dsd_lists() - Determine number of DSD list required 2637 * for Command Type 6. 2638 * 2639 * @dsds: number of data segment decriptors needed 2640 * 2641 * Returns the number of dsd list needed to store @dsds. 2642 */ 2643inline uint16_t 2644qla82xx_calc_dsd_lists(uint16_t dsds) 2645{ 2646 uint16_t dsd_lists = 0; 2647 2648 dsd_lists = (dsds/QLA_DSDS_PER_IOCB); 2649 if (dsds % QLA_DSDS_PER_IOCB) 2650 dsd_lists++; 2651 return dsd_lists; 2652} 2653 2654/* 2655 * qla82xx_start_scsi() - Send a SCSI command to the ISP 2656 * @sp: command to send to the ISP 2657 * 2658 * Returns non-zero if a failure occurred, else zero. 2659 */ 2660int 2661qla82xx_start_scsi(srb_t *sp) 2662{ 2663 int ret, nseg; 2664 unsigned long flags; 2665 struct scsi_cmnd *cmd; 2666 uint32_t *clr_ptr; 2667 uint32_t index; 2668 uint32_t handle; 2669 uint16_t cnt; 2670 uint16_t req_cnt; 2671 uint16_t tot_dsds; 2672 struct device_reg_82xx __iomem *reg; 2673 uint32_t dbval; 2674 uint32_t *fcp_dl; 2675 uint8_t additional_cdb_len; 2676 struct ct6_dsd *ctx; 2677 struct scsi_qla_host *vha = sp->fcport->vha; 2678 struct qla_hw_data *ha = vha->hw; 2679 struct req_que *req = NULL; 2680 struct rsp_que *rsp = NULL; 2681 char tag[2]; 2682 2683 /* Setup device pointers. */ 2684 ret = 0; 2685 reg = &ha->iobase->isp82; 2686 cmd = sp->cmd; 2687 req = vha->req; 2688 rsp = ha->rsp_q_map[0]; 2689 2690 /* So we know we haven't pci_map'ed anything yet */ 2691 tot_dsds = 0; 2692 2693 dbval = 0x04 | (ha->portnum << 5); 2694 2695 /* Send marker if required */ 2696 if (vha->marker_needed != 0) { 2697 if (qla2x00_marker(vha, req, 2698 rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS) { 2699 ql_log(ql_log_warn, vha, 0x300c, 2700 "qla2x00_marker failed for cmd=%p.\n", cmd); 2701 return QLA_FUNCTION_FAILED; 2702 } 2703 vha->marker_needed = 0; 2704 } 2705 2706 /* Acquire ring specific lock */ 2707 spin_lock_irqsave(&ha->hardware_lock, flags); 2708 2709 /* Check for room in outstanding command list. */ 2710 handle = req->current_outstanding_cmd; 2711 for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) { 2712 handle++; 2713 if (handle == MAX_OUTSTANDING_COMMANDS) 2714 handle = 1; 2715 if (!req->outstanding_cmds[handle]) 2716 break; 2717 } 2718 if (index == MAX_OUTSTANDING_COMMANDS) 2719 goto queuing_error; 2720 2721 /* Map the sg table so we have an accurate count of sg entries needed */ 2722 if (scsi_sg_count(cmd)) { 2723 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd), 2724 scsi_sg_count(cmd), cmd->sc_data_direction); 2725 if (unlikely(!nseg)) 2726 goto queuing_error; 2727 } else 2728 nseg = 0; 2729 2730 tot_dsds = nseg; 2731 2732 if (tot_dsds > ql2xshiftctondsd) { 2733 struct cmd_type_6 *cmd_pkt; 2734 uint16_t more_dsd_lists = 0; 2735 struct dsd_dma *dsd_ptr; 2736 uint16_t i; 2737 2738 more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds); 2739 if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN) { 2740 ql_dbg(ql_dbg_io, vha, 0x300d, 2741 "Num of DSD list %d is than %d for cmd=%p.\n", 2742 more_dsd_lists + ha->gbl_dsd_inuse, NUM_DSD_CHAIN, 2743 cmd); 2744 goto queuing_error; 2745 } 2746 2747 if (more_dsd_lists <= ha->gbl_dsd_avail) 2748 goto sufficient_dsds; 2749 else 2750 more_dsd_lists -= ha->gbl_dsd_avail; 2751 2752 for (i = 0; i < more_dsd_lists; i++) { 2753 dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC); 2754 if (!dsd_ptr) { 2755 ql_log(ql_log_fatal, vha, 0x300e, 2756 "Failed to allocate memory for dsd_dma " 2757 "for cmd=%p.\n", cmd); 2758 goto queuing_error; 2759 } 2760 2761 dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool, 2762 GFP_ATOMIC, &dsd_ptr->dsd_list_dma); 2763 if (!dsd_ptr->dsd_addr) { 2764 kfree(dsd_ptr); 2765 ql_log(ql_log_fatal, vha, 0x300f, 2766 "Failed to allocate memory for dsd_addr " 2767 "for cmd=%p.\n", cmd); 2768 goto queuing_error; 2769 } 2770 list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list); 2771 ha->gbl_dsd_avail++; 2772 } 2773 2774sufficient_dsds: 2775 req_cnt = 1; 2776 2777 if (req->cnt < (req_cnt + 2)) { 2778 cnt = (uint16_t)RD_REG_DWORD_RELAXED( 2779 ®->req_q_out[0]); 2780 if (req->ring_index < cnt) 2781 req->cnt = cnt - req->ring_index; 2782 else 2783 req->cnt = req->length - 2784 (req->ring_index - cnt); 2785 } 2786 2787 if (req->cnt < (req_cnt + 2)) 2788 goto queuing_error; 2789 2790 ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC); 2791 if (!sp->ctx) { 2792 ql_log(ql_log_fatal, vha, 0x3010, 2793 "Failed to allocate ctx for cmd=%p.\n", cmd); 2794 goto queuing_error; 2795 } 2796 memset(ctx, 0, sizeof(struct ct6_dsd)); 2797 ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool, 2798 GFP_ATOMIC, &ctx->fcp_cmnd_dma); 2799 if (!ctx->fcp_cmnd) { 2800 ql_log(ql_log_fatal, vha, 0x3011, 2801 "Failed to allocate fcp_cmnd for cmd=%p.\n", cmd); 2802 goto queuing_error_fcp_cmnd; 2803 } 2804 2805 /* Initialize the DSD list and dma handle */ 2806 INIT_LIST_HEAD(&ctx->dsd_list); 2807 ctx->dsd_use_cnt = 0; 2808 2809 if (cmd->cmd_len > 16) { 2810 additional_cdb_len = cmd->cmd_len - 16; 2811 if ((cmd->cmd_len % 4) != 0) { 2812 /* SCSI command bigger than 16 bytes must be 2813 * multiple of 4 2814 */ 2815 ql_log(ql_log_warn, vha, 0x3012, 2816 "scsi cmd len %d not multiple of 4 " 2817 "for cmd=%p.\n", cmd->cmd_len, cmd); 2818 goto queuing_error_fcp_cmnd; 2819 } 2820 ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4; 2821 } else { 2822 additional_cdb_len = 0; 2823 ctx->fcp_cmnd_len = 12 + 16 + 4; 2824 } 2825 2826 cmd_pkt = (struct cmd_type_6 *)req->ring_ptr; 2827 cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 2828 2829 /* Zero out remaining portion of packet. */ 2830 /* tagged queuing modifier -- default is TSK_SIMPLE (0). */ 2831 clr_ptr = (uint32_t *)cmd_pkt + 2; 2832 memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 2833 cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 2834 2835 /* Set NPORT-ID and LUN number*/ 2836 cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 2837 cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 2838 cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 2839 cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 2840 cmd_pkt->vp_index = sp->fcport->vp_idx; 2841 2842 /* Build IOCB segments */ 2843 if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds)) 2844 goto queuing_error_fcp_cmnd; 2845 2846 int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 2847 host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun)); 2848 2849 /* build FCP_CMND IU */ 2850 memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd)); 2851 int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun); 2852 ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len; 2853 2854 if (cmd->sc_data_direction == DMA_TO_DEVICE) 2855 ctx->fcp_cmnd->additional_cdb_len |= 1; 2856 else if (cmd->sc_data_direction == DMA_FROM_DEVICE) 2857 ctx->fcp_cmnd->additional_cdb_len |= 2; 2858 2859 /* 2860 * Update tagged queuing modifier -- default is TSK_SIMPLE (0). 2861 */ 2862 if (scsi_populate_tag_msg(cmd, tag)) { 2863 switch (tag[0]) { 2864 case HEAD_OF_QUEUE_TAG: 2865 ctx->fcp_cmnd->task_attribute = 2866 TSK_HEAD_OF_QUEUE; 2867 break; 2868 case ORDERED_QUEUE_TAG: 2869 ctx->fcp_cmnd->task_attribute = 2870 TSK_ORDERED; 2871 break; 2872 } 2873 } 2874 2875 memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len); 2876 2877 fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 + 2878 additional_cdb_len); 2879 *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd)); 2880 2881 cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len); 2882 cmd_pkt->fcp_cmnd_dseg_address[0] = 2883 cpu_to_le32(LSD(ctx->fcp_cmnd_dma)); 2884 cmd_pkt->fcp_cmnd_dseg_address[1] = 2885 cpu_to_le32(MSD(ctx->fcp_cmnd_dma)); 2886 2887 sp->flags |= SRB_FCP_CMND_DMA_VALID; 2888 cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 2889 /* Set total data segment count. */ 2890 cmd_pkt->entry_count = (uint8_t)req_cnt; 2891 /* Specify response queue number where 2892 * completion should happen 2893 */ 2894 cmd_pkt->entry_status = (uint8_t) rsp->id; 2895 } else { 2896 struct cmd_type_7 *cmd_pkt; 2897 req_cnt = qla24xx_calc_iocbs(vha, tot_dsds); 2898 if (req->cnt < (req_cnt + 2)) { 2899 cnt = (uint16_t)RD_REG_DWORD_RELAXED( 2900 ®->req_q_out[0]); 2901 if (req->ring_index < cnt) 2902 req->cnt = cnt - req->ring_index; 2903 else 2904 req->cnt = req->length - 2905 (req->ring_index - cnt); 2906 } 2907 if (req->cnt < (req_cnt + 2)) 2908 goto queuing_error; 2909 2910 cmd_pkt = (struct cmd_type_7 *)req->ring_ptr; 2911 cmd_pkt->handle = MAKE_HANDLE(req->id, handle); 2912 2913 /* Zero out remaining portion of packet. */ 2914 /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/ 2915 clr_ptr = (uint32_t *)cmd_pkt + 2; 2916 memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); 2917 cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); 2918 2919 /* Set NPORT-ID and LUN number*/ 2920 cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); 2921 cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; 2922 cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; 2923 cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; 2924 cmd_pkt->vp_index = sp->fcport->vp_idx; 2925 2926 int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); 2927 host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, 2928 sizeof(cmd_pkt->lun)); 2929 2930 /* 2931 * Update tagged queuing modifier -- default is TSK_SIMPLE (0). 2932 */ 2933 if (scsi_populate_tag_msg(cmd, tag)) { 2934 switch (tag[0]) { 2935 case HEAD_OF_QUEUE_TAG: 2936 cmd_pkt->task = TSK_HEAD_OF_QUEUE; 2937 break; 2938 case ORDERED_QUEUE_TAG: 2939 cmd_pkt->task = TSK_ORDERED; 2940 break; 2941 } 2942 } 2943 2944 /* Load SCSI command packet. */ 2945 memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len); 2946 host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb)); 2947 2948 cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 2949 2950 /* Build IOCB segments */ 2951 qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds); 2952 2953 /* Set total data segment count. */ 2954 cmd_pkt->entry_count = (uint8_t)req_cnt; 2955 /* Specify response queue number where 2956 * completion should happen. 2957 */ 2958 cmd_pkt->entry_status = (uint8_t) rsp->id; 2959 2960 } 2961 /* Build command packet. */ 2962 req->current_outstanding_cmd = handle; 2963 req->outstanding_cmds[handle] = sp; 2964 sp->handle = handle; 2965 sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle; 2966 req->cnt -= req_cnt; 2967 wmb(); 2968 2969 /* Adjust ring index. */ 2970 req->ring_index++; 2971 if (req->ring_index == req->length) { 2972 req->ring_index = 0; 2973 req->ring_ptr = req->ring; 2974 } else 2975 req->ring_ptr++; 2976 2977 sp->flags |= SRB_DMA_VALID; 2978 2979 /* Set chip new ring index. */ 2980 /* write, read and verify logic */ 2981 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2982 if (ql2xdbwr) 2983 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2984 else { 2985 WRT_REG_DWORD( 2986 (unsigned long __iomem *)ha->nxdb_wr_ptr, 2987 dbval); 2988 wmb(); 2989 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 2990 WRT_REG_DWORD( 2991 (unsigned long __iomem *)ha->nxdb_wr_ptr, 2992 dbval); 2993 wmb(); 2994 } 2995 } 2996 2997 /* Manage unprocessed RIO/ZIO commands in response queue. */ 2998 if (vha->flags.process_response_queue && 2999 rsp->ring_ptr->signature != RESPONSE_PROCESSED) 3000 qla24xx_process_response_queue(vha, rsp); 3001 3002 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3003 return QLA_SUCCESS; 3004 3005queuing_error_fcp_cmnd: 3006 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma); 3007queuing_error: 3008 if (tot_dsds) 3009 scsi_dma_unmap(cmd); 3010 3011 if (sp->ctx) { 3012 mempool_free(sp->ctx, ha->ctx_mempool); 3013 sp->ctx = NULL; 3014 } 3015 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3016 3017 return QLA_FUNCTION_FAILED; 3018} 3019 3020static uint32_t * 3021qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 3022 uint32_t length) 3023{ 3024 uint32_t i; 3025 uint32_t val; 3026 struct qla_hw_data *ha = vha->hw; 3027 3028 /* Dword reads to flash. */ 3029 for (i = 0; i < length/4; i++, faddr += 4) { 3030 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 3031 ql_log(ql_log_warn, vha, 0x0106, 3032 "Do ROM fast read failed.\n"); 3033 goto done_read; 3034 } 3035 dwptr[i] = __constant_cpu_to_le32(val); 3036 } 3037done_read: 3038 return dwptr; 3039} 3040 3041static int 3042qla82xx_unprotect_flash(struct qla_hw_data *ha) 3043{ 3044 int ret; 3045 uint32_t val; 3046 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 3047 3048 ret = ql82xx_rom_lock_d(ha); 3049 if (ret < 0) { 3050 ql_log(ql_log_warn, vha, 0xb014, 3051 "ROM Lock failed.\n"); 3052 return ret; 3053 } 3054 3055 ret = qla82xx_read_status_reg(ha, &val); 3056 if (ret < 0) 3057 goto done_unprotect; 3058 3059 val &= ~(BLOCK_PROTECT_BITS << 2); 3060 ret = qla82xx_write_status_reg(ha, val); 3061 if (ret < 0) { 3062 val |= (BLOCK_PROTECT_BITS << 2); 3063 qla82xx_write_status_reg(ha, val); 3064 } 3065 3066 if (qla82xx_write_disable_flash(ha) != 0) 3067 ql_log(ql_log_warn, vha, 0xb015, 3068 "Write disable failed.\n"); 3069 3070done_unprotect: 3071 qla82xx_rom_unlock(ha); 3072 return ret; 3073} 3074 3075static int 3076qla82xx_protect_flash(struct qla_hw_data *ha) 3077{ 3078 int ret; 3079 uint32_t val; 3080 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 3081 3082 ret = ql82xx_rom_lock_d(ha); 3083 if (ret < 0) { 3084 ql_log(ql_log_warn, vha, 0xb016, 3085 "ROM Lock failed.\n"); 3086 return ret; 3087 } 3088 3089 ret = qla82xx_read_status_reg(ha, &val); 3090 if (ret < 0) 3091 goto done_protect; 3092 3093 val |= (BLOCK_PROTECT_BITS << 2); 3094 /* LOCK all sectors */ 3095 ret = qla82xx_write_status_reg(ha, val); 3096 if (ret < 0) 3097 ql_log(ql_log_warn, vha, 0xb017, 3098 "Write status register failed.\n"); 3099 3100 if (qla82xx_write_disable_flash(ha) != 0) 3101 ql_log(ql_log_warn, vha, 0xb018, 3102 "Write disable failed.\n"); 3103done_protect: 3104 qla82xx_rom_unlock(ha); 3105 return ret; 3106} 3107 3108static int 3109qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 3110{ 3111 int ret = 0; 3112 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 3113 3114 ret = ql82xx_rom_lock_d(ha); 3115 if (ret < 0) { 3116 ql_log(ql_log_warn, vha, 0xb019, 3117 "ROM Lock failed.\n"); 3118 return ret; 3119 } 3120 3121 qla82xx_flash_set_write_enable(ha); 3122 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 3123 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 3124 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 3125 3126 if (qla82xx_wait_rom_done(ha)) { 3127 ql_log(ql_log_warn, vha, 0xb01a, 3128 "Error waiting for rom done.\n"); 3129 ret = -1; 3130 goto done; 3131 } 3132 ret = qla82xx_flash_wait_write_finish(ha); 3133done: 3134 qla82xx_rom_unlock(ha); 3135 return ret; 3136} 3137 3138/* 3139 * Address and length are byte address 3140 */ 3141uint8_t * 3142qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3143 uint32_t offset, uint32_t length) 3144{ 3145 scsi_block_requests(vha->host); 3146 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 3147 scsi_unblock_requests(vha->host); 3148 return buf; 3149} 3150 3151static int 3152qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 3153 uint32_t faddr, uint32_t dwords) 3154{ 3155 int ret; 3156 uint32_t liter; 3157 uint32_t sec_mask, rest_addr; 3158 dma_addr_t optrom_dma; 3159 void *optrom = NULL; 3160 int page_mode = 0; 3161 struct qla_hw_data *ha = vha->hw; 3162 3163 ret = -1; 3164 3165 /* Prepare burst-capable write on supported ISPs. */ 3166 if (page_mode && !(faddr & 0xfff) && 3167 dwords > OPTROM_BURST_DWORDS) { 3168 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3169 &optrom_dma, GFP_KERNEL); 3170 if (!optrom) { 3171 ql_log(ql_log_warn, vha, 0xb01b, 3172 "Unable to allocate memory " 3173 "for optron burst write (%x KB).\n", 3174 OPTROM_BURST_SIZE / 1024); 3175 } 3176 } 3177 3178 rest_addr = ha->fdt_block_size - 1; 3179 sec_mask = ~rest_addr; 3180 3181 ret = qla82xx_unprotect_flash(ha); 3182 if (ret) { 3183 ql_log(ql_log_warn, vha, 0xb01c, 3184 "Unable to unprotect flash for update.\n"); 3185 goto write_done; 3186 } 3187 3188 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 3189 /* Are we at the beginning of a sector? */ 3190 if ((faddr & rest_addr) == 0) { 3191 3192 ret = qla82xx_erase_sector(ha, faddr); 3193 if (ret) { 3194 ql_log(ql_log_warn, vha, 0xb01d, 3195 "Unable to erase sector: address=%x.\n", 3196 faddr); 3197 break; 3198 } 3199 } 3200 3201 /* Go with burst-write. */ 3202 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 3203 /* Copy data to DMA'ble buffer. */ 3204 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 3205 3206 ret = qla2x00_load_ram(vha, optrom_dma, 3207 (ha->flash_data_off | faddr), 3208 OPTROM_BURST_DWORDS); 3209 if (ret != QLA_SUCCESS) { 3210 ql_log(ql_log_warn, vha, 0xb01e, 3211 "Unable to burst-write optrom segment " 3212 "(%x/%x/%llx).\n", ret, 3213 (ha->flash_data_off | faddr), 3214 (unsigned long long)optrom_dma); 3215 ql_log(ql_log_warn, vha, 0xb01f, 3216 "Reverting to slow-write.\n"); 3217 3218 dma_free_coherent(&ha->pdev->dev, 3219 OPTROM_BURST_SIZE, optrom, optrom_dma); 3220 optrom = NULL; 3221 } else { 3222 liter += OPTROM_BURST_DWORDS - 1; 3223 faddr += OPTROM_BURST_DWORDS - 1; 3224 dwptr += OPTROM_BURST_DWORDS - 1; 3225 continue; 3226 } 3227 } 3228 3229 ret = qla82xx_write_flash_dword(ha, faddr, 3230 cpu_to_le32(*dwptr)); 3231 if (ret) { 3232 ql_dbg(ql_dbg_p3p, vha, 0xb020, 3233 "Unable to program flash address=%x data=%x.\n", 3234 faddr, *dwptr); 3235 break; 3236 } 3237 } 3238 3239 ret = qla82xx_protect_flash(ha); 3240 if (ret) 3241 ql_log(ql_log_warn, vha, 0xb021, 3242 "Unable to protect flash after update.\n"); 3243write_done: 3244 if (optrom) 3245 dma_free_coherent(&ha->pdev->dev, 3246 OPTROM_BURST_SIZE, optrom, optrom_dma); 3247 return ret; 3248} 3249 3250int 3251qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3252 uint32_t offset, uint32_t length) 3253{ 3254 int rval; 3255 3256 /* Suspend HBA. */ 3257 scsi_block_requests(vha->host); 3258 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 3259 length >> 2); 3260 scsi_unblock_requests(vha->host); 3261 3262 /* Convert return ISP82xx to generic */ 3263 if (rval) 3264 rval = QLA_FUNCTION_FAILED; 3265 else 3266 rval = QLA_SUCCESS; 3267 return rval; 3268} 3269 3270void 3271qla82xx_start_iocbs(srb_t *sp) 3272{ 3273 struct qla_hw_data *ha = sp->fcport->vha->hw; 3274 struct req_que *req = ha->req_q_map[0]; 3275 struct device_reg_82xx __iomem *reg; 3276 uint32_t dbval; 3277 3278 /* Adjust ring index. */ 3279 req->ring_index++; 3280 if (req->ring_index == req->length) { 3281 req->ring_index = 0; 3282 req->ring_ptr = req->ring; 3283 } else 3284 req->ring_ptr++; 3285 3286 reg = &ha->iobase->isp82; 3287 dbval = 0x04 | (ha->portnum << 5); 3288 3289 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 3290 if (ql2xdbwr) 3291 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 3292 else { 3293 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 3294 wmb(); 3295 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 3296 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 3297 dbval); 3298 wmb(); 3299 } 3300 } 3301} 3302 3303void qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 3304{ 3305 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 3306 3307 if (qla82xx_rom_lock(ha)) 3308 /* Someone else is holding the lock. */ 3309 ql_log(ql_log_info, vha, 0xb022, 3310 "Resetting rom_lock.\n"); 3311 3312 /* 3313 * Either we got the lock, or someone 3314 * else died while holding it. 3315 * In either case, unlock. 3316 */ 3317 qla82xx_rom_unlock(ha); 3318} 3319 3320/* 3321 * qla82xx_device_bootstrap 3322 * Initialize device, set DEV_READY, start fw 3323 * 3324 * Note: 3325 * IDC lock must be held upon entry 3326 * 3327 * Return: 3328 * Success : 0 3329 * Failed : 1 3330 */ 3331static int 3332qla82xx_device_bootstrap(scsi_qla_host_t *vha) 3333{ 3334 int rval = QLA_SUCCESS; 3335 int i, timeout; 3336 uint32_t old_count, count; 3337 struct qla_hw_data *ha = vha->hw; 3338 int need_reset = 0, peg_stuck = 1; 3339 3340 need_reset = qla82xx_need_reset(ha); 3341 3342 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3343 3344 for (i = 0; i < 10; i++) { 3345 timeout = msleep_interruptible(200); 3346 if (timeout) { 3347 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3348 QLA82XX_DEV_FAILED); 3349 return QLA_FUNCTION_FAILED; 3350 } 3351 3352 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 3353 if (count != old_count) 3354 peg_stuck = 0; 3355 } 3356 3357 if (need_reset) { 3358 /* We are trying to perform a recovery here. */ 3359 if (peg_stuck) 3360 qla82xx_rom_lock_recovery(ha); 3361 goto dev_initialize; 3362 } else { 3363 /* Start of day for this ha context. */ 3364 if (peg_stuck) { 3365 /* Either we are the first or recovery in progress. */ 3366 qla82xx_rom_lock_recovery(ha); 3367 goto dev_initialize; 3368 } else 3369 /* Firmware already running. */ 3370 goto dev_ready; 3371 } 3372 3373 return rval; 3374 3375dev_initialize: 3376 /* set to DEV_INITIALIZING */ 3377 ql_log(ql_log_info, vha, 0x009e, 3378 "HW State: INITIALIZING.\n"); 3379 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 3380 3381 /* Driver that sets device state to initializating sets IDC version */ 3382 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 3383 3384 qla82xx_idc_unlock(ha); 3385 rval = qla82xx_start_firmware(vha); 3386 qla82xx_idc_lock(ha); 3387 3388 if (rval != QLA_SUCCESS) { 3389 ql_log(ql_log_fatal, vha, 0x00ad, 3390 "HW State: FAILED.\n"); 3391 qla82xx_clear_drv_active(ha); 3392 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 3393 return rval; 3394 } 3395 3396dev_ready: 3397 ql_log(ql_log_info, vha, 0x00ae, 3398 "HW State: READY.\n"); 3399 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 3400 3401 return QLA_SUCCESS; 3402} 3403 3404/* 3405* qla82xx_need_qsnt_handler 3406* Code to start quiescence sequence 3407* 3408* Note: 3409* IDC lock must be held upon entry 3410* 3411* Return: void 3412*/ 3413 3414static void 3415qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 3416{ 3417 struct qla_hw_data *ha = vha->hw; 3418 uint32_t dev_state, drv_state, drv_active; 3419 unsigned long reset_timeout; 3420 3421 if (vha->flags.online) { 3422 /*Block any further I/O and wait for pending cmnds to complete*/ 3423 qla82xx_quiescent_state_cleanup(vha); 3424 } 3425 3426 /* Set the quiescence ready bit */ 3427 qla82xx_set_qsnt_ready(ha); 3428 3429 /*wait for 30 secs for other functions to ack */ 3430 reset_timeout = jiffies + (30 * HZ); 3431 3432 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3433 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3434 /* Its 2 that is written when qsnt is acked, moving one bit */ 3435 drv_active = drv_active << 0x01; 3436 3437 while (drv_state != drv_active) { 3438 3439 if (time_after_eq(jiffies, reset_timeout)) { 3440 /* quiescence timeout, other functions didn't ack 3441 * changing the state to DEV_READY 3442 */ 3443 ql_log(ql_log_info, vha, 0xb023, 3444 "%s : QUIESCENT TIMEOUT.\n", QLA2XXX_DRIVER_NAME); 3445 ql_log(ql_log_info, vha, 0xb024, 3446 "DRV_ACTIVE:%d DRV_STATE:%d.\n", 3447 drv_active, drv_state); 3448 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3449 QLA82XX_DEV_READY); 3450 ql_log(ql_log_info, vha, 0xb025, 3451 "HW State: DEV_READY.\n"); 3452 qla82xx_idc_unlock(ha); 3453 qla2x00_perform_loop_resync(vha); 3454 qla82xx_idc_lock(ha); 3455 3456 qla82xx_clear_qsnt_ready(vha); 3457 return; 3458 } 3459 3460 qla82xx_idc_unlock(ha); 3461 msleep(1000); 3462 qla82xx_idc_lock(ha); 3463 3464 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3465 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3466 drv_active = drv_active << 0x01; 3467 } 3468 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3469 /* everyone acked so set the state to DEV_QUIESCENCE */ 3470 if (dev_state == QLA82XX_DEV_NEED_QUIESCENT) { 3471 ql_log(ql_log_info, vha, 0xb026, 3472 "HW State: DEV_QUIESCENT.\n"); 3473 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_QUIESCENT); 3474 } 3475} 3476 3477/* 3478* qla82xx_wait_for_state_change 3479* Wait for device state to change from given current state 3480* 3481* Note: 3482* IDC lock must not be held upon entry 3483* 3484* Return: 3485* Changed device state. 3486*/ 3487uint32_t 3488qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 3489{ 3490 struct qla_hw_data *ha = vha->hw; 3491 uint32_t dev_state; 3492 3493 do { 3494 msleep(1000); 3495 qla82xx_idc_lock(ha); 3496 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3497 qla82xx_idc_unlock(ha); 3498 } while (dev_state == curr_state); 3499 3500 return dev_state; 3501} 3502 3503static void 3504qla82xx_dev_failed_handler(scsi_qla_host_t *vha) 3505{ 3506 struct qla_hw_data *ha = vha->hw; 3507 3508 /* Disable the board */ 3509 ql_log(ql_log_fatal, vha, 0x00b8, 3510 "Disabling the board.\n"); 3511 3512 qla82xx_idc_lock(ha); 3513 qla82xx_clear_drv_active(ha); 3514 qla82xx_idc_unlock(ha); 3515 3516 /* Set DEV_FAILED flag to disable timer */ 3517 vha->device_flags |= DFLG_DEV_FAILED; 3518 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3519 qla2x00_mark_all_devices_lost(vha, 0); 3520 vha->flags.online = 0; 3521 vha->flags.init_done = 0; 3522} 3523 3524/* 3525 * qla82xx_need_reset_handler 3526 * Code to start reset sequence 3527 * 3528 * Note: 3529 * IDC lock must be held upon entry 3530 * 3531 * Return: 3532 * Success : 0 3533 * Failed : 1 3534 */ 3535static void 3536qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3537{ 3538 uint32_t dev_state, drv_state, drv_active; 3539 uint32_t active_mask = 0; 3540 unsigned long reset_timeout; 3541 struct qla_hw_data *ha = vha->hw; 3542 struct req_que *req = ha->req_q_map[0]; 3543 3544 if (vha->flags.online) { 3545 qla82xx_idc_unlock(ha); 3546 qla2x00_abort_isp_cleanup(vha); 3547 ha->isp_ops->get_flash_version(vha, req->ring); 3548 ha->isp_ops->nvram_config(vha); 3549 qla82xx_idc_lock(ha); 3550 } 3551 3552 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3553 if (!ha->flags.isp82xx_reset_owner) { 3554 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3555 "reset_acknowledged by 0x%x\n", ha->portnum); 3556 qla82xx_set_rst_ready(ha); 3557 } else { 3558 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3559 drv_active &= active_mask; 3560 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3561 "active_mask: 0x%08x\n", active_mask); 3562 } 3563 3564 /* wait for 10 seconds for reset ack from all functions */ 3565 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3566 3567 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3568 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3569 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3570 3571 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3572 "drv_state: 0x%08x, drv_active: 0x%08x, " 3573 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3574 drv_state, drv_active, dev_state, active_mask); 3575 3576 while (drv_state != drv_active && 3577 dev_state != QLA82XX_DEV_INITIALIZING) { 3578 if (time_after_eq(jiffies, reset_timeout)) { 3579 ql_log(ql_log_warn, vha, 0x00b5, 3580 "Reset timeout.\n"); 3581 break; 3582 } 3583 qla82xx_idc_unlock(ha); 3584 msleep(1000); 3585 qla82xx_idc_lock(ha); 3586 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3587 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3588 if (ha->flags.isp82xx_reset_owner) 3589 drv_active &= active_mask; 3590 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3591 } 3592 3593 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3594 "drv_state: 0x%08x, drv_active: 0x%08x, " 3595 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3596 drv_state, drv_active, dev_state, active_mask); 3597 3598 ql_log(ql_log_info, vha, 0x00b6, 3599 "Device state is 0x%x = %s.\n", 3600 dev_state, 3601 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3602 3603 /* Force to DEV_COLD unless someone else is starting a reset */ 3604 if (dev_state != QLA82XX_DEV_INITIALIZING && 3605 dev_state != QLA82XX_DEV_COLD) { 3606 ql_log(ql_log_info, vha, 0x00b7, 3607 "HW State: COLD/RE-INIT.\n"); 3608 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 3609 if (ql2xmdenable) { 3610 if (qla82xx_md_collect(vha)) 3611 ql_log(ql_log_warn, vha, 0xb02c, 3612 "Not able to collect minidump.\n"); 3613 } else 3614 ql_log(ql_log_warn, vha, 0xb04f, 3615 "Minidump disabled.\n"); 3616 } 3617} 3618 3619int 3620qla82xx_check_md_needed(scsi_qla_host_t *vha) 3621{ 3622 struct qla_hw_data *ha = vha->hw; 3623 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3624 int rval = QLA_SUCCESS; 3625 3626 fw_major_version = ha->fw_major_version; 3627 fw_minor_version = ha->fw_minor_version; 3628 fw_subminor_version = ha->fw_subminor_version; 3629 3630 rval = qla2x00_get_fw_version(vha, &ha->fw_major_version, 3631 &ha->fw_minor_version, &ha->fw_subminor_version, 3632 &ha->fw_attributes, &ha->fw_memory_size, 3633 ha->mpi_version, &ha->mpi_capabilities, 3634 ha->phy_version); 3635 3636 if (rval != QLA_SUCCESS) 3637 return rval; 3638 3639 if (ql2xmdenable) { 3640 if (!ha->fw_dumped) { 3641 if (fw_major_version != ha->fw_major_version || 3642 fw_minor_version != ha->fw_minor_version || 3643 fw_subminor_version != ha->fw_subminor_version) { 3644 3645 ql_log(ql_log_info, vha, 0xb02d, 3646 "Firmware version differs " 3647 "Previous version: %d:%d:%d - " 3648 "New version: %d:%d:%d\n", 3649 ha->fw_major_version, 3650 ha->fw_minor_version, 3651 ha->fw_subminor_version, 3652 fw_major_version, fw_minor_version, 3653 fw_subminor_version); 3654 /* Release MiniDump resources */ 3655 qla82xx_md_free(vha); 3656 /* ALlocate MiniDump resources */ 3657 qla82xx_md_prep(vha); 3658 } else 3659 ql_log(ql_log_info, vha, 0xb02e, 3660 "Firmware dump available to retrieve\n"); 3661 } 3662 } 3663 return rval; 3664} 3665 3666 3667int 3668qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3669{ 3670 uint32_t fw_heartbeat_counter; 3671 int status = 0; 3672 3673 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3674 QLA82XX_PEG_ALIVE_COUNTER); 3675 /* all 0xff, assume AER/EEH in progress, ignore */ 3676 if (fw_heartbeat_counter == 0xffffffff) { 3677 ql_dbg(ql_dbg_timer, vha, 0x6003, 3678 "FW heartbeat counter is 0xffffffff, " 3679 "returning status=%d.\n", status); 3680 return status; 3681 } 3682 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3683 vha->seconds_since_last_heartbeat++; 3684 /* FW not alive after 2 seconds */ 3685 if (vha->seconds_since_last_heartbeat == 2) { 3686 vha->seconds_since_last_heartbeat = 0; 3687 status = 1; 3688 } 3689 } else 3690 vha->seconds_since_last_heartbeat = 0; 3691 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3692 if (status) 3693 ql_dbg(ql_dbg_timer, vha, 0x6004, 3694 "Returning status=%d.\n", status); 3695 return status; 3696} 3697 3698/* 3699 * qla82xx_device_state_handler 3700 * Main state handler 3701 * 3702 * Note: 3703 * IDC lock must be held upon entry 3704 * 3705 * Return: 3706 * Success : 0 3707 * Failed : 1 3708 */ 3709int 3710qla82xx_device_state_handler(scsi_qla_host_t *vha) 3711{ 3712 uint32_t dev_state; 3713 uint32_t old_dev_state; 3714 int rval = QLA_SUCCESS; 3715 unsigned long dev_init_timeout; 3716 struct qla_hw_data *ha = vha->hw; 3717 int loopcount = 0; 3718 3719 qla82xx_idc_lock(ha); 3720 if (!vha->flags.init_done) 3721 qla82xx_set_drv_active(vha); 3722 3723 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3724 old_dev_state = dev_state; 3725 ql_log(ql_log_info, vha, 0x009b, 3726 "Device state is 0x%x = %s.\n", 3727 dev_state, 3728 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3729 3730 /* wait for 30 seconds for device to go ready */ 3731 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3732 3733 while (1) { 3734 3735 if (time_after_eq(jiffies, dev_init_timeout)) { 3736 ql_log(ql_log_fatal, vha, 0x009c, 3737 "Device init failed.\n"); 3738 rval = QLA_FUNCTION_FAILED; 3739 break; 3740 } 3741 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3742 if (old_dev_state != dev_state) { 3743 loopcount = 0; 3744 old_dev_state = dev_state; 3745 } 3746 if (loopcount < 5) { 3747 ql_log(ql_log_info, vha, 0x009d, 3748 "Device state is 0x%x = %s.\n", 3749 dev_state, 3750 dev_state < MAX_STATES ? qdev_state(dev_state) : 3751 "Unknown"); 3752 } 3753 3754 switch (dev_state) { 3755 case QLA82XX_DEV_READY: 3756 qla82xx_check_md_needed(vha); 3757 ha->flags.isp82xx_reset_owner = 0; 3758 goto exit; 3759 case QLA82XX_DEV_COLD: 3760 rval = qla82xx_device_bootstrap(vha); 3761 break; 3762 case QLA82XX_DEV_INITIALIZING: 3763 qla82xx_idc_unlock(ha); 3764 msleep(1000); 3765 qla82xx_idc_lock(ha); 3766 break; 3767 case QLA82XX_DEV_NEED_RESET: 3768 if (!ql2xdontresethba) 3769 qla82xx_need_reset_handler(vha); 3770 else { 3771 qla82xx_idc_unlock(ha); 3772 msleep(1000); 3773 qla82xx_idc_lock(ha); 3774 } 3775 dev_init_timeout = jiffies + 3776 (ha->nx_dev_init_timeout * HZ); 3777 break; 3778 case QLA82XX_DEV_NEED_QUIESCENT: 3779 qla82xx_need_qsnt_handler(vha); 3780 /* Reset timeout value after quiescence handler */ 3781 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3782 * HZ); 3783 break; 3784 case QLA82XX_DEV_QUIESCENT: 3785 /* Owner will exit and other will wait for the state 3786 * to get changed 3787 */ 3788 if (ha->flags.quiesce_owner) 3789 goto exit; 3790 3791 qla82xx_idc_unlock(ha); 3792 msleep(1000); 3793 qla82xx_idc_lock(ha); 3794 3795 /* Reset timeout value after quiescence handler */ 3796 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3797 * HZ); 3798 break; 3799 case QLA82XX_DEV_FAILED: 3800 qla82xx_dev_failed_handler(vha); 3801 rval = QLA_FUNCTION_FAILED; 3802 goto exit; 3803 default: 3804 qla82xx_idc_unlock(ha); 3805 msleep(1000); 3806 qla82xx_idc_lock(ha); 3807 } 3808 loopcount++; 3809 } 3810exit: 3811 qla82xx_idc_unlock(ha); 3812 return rval; 3813} 3814 3815void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3816{ 3817 struct qla_hw_data *ha = vha->hw; 3818 3819 if (ha->flags.mbox_busy) { 3820 ha->flags.mbox_int = 1; 3821 ha->flags.mbox_busy = 0; 3822 ql_log(ql_log_warn, vha, 0x6010, 3823 "Doing premature completion of mbx command.\n"); 3824 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3825 complete(&ha->mbx_intr_comp); 3826 } 3827} 3828 3829void qla82xx_watchdog(scsi_qla_host_t *vha) 3830{ 3831 uint32_t dev_state, halt_status; 3832 struct qla_hw_data *ha = vha->hw; 3833 3834 /* don't poll if reset is going on */ 3835 if (!ha->flags.isp82xx_reset_hdlr_active) { 3836 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3837 if (dev_state == QLA82XX_DEV_NEED_RESET && 3838 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3839 ql_log(ql_log_warn, vha, 0x6001, 3840 "Adapter reset needed.\n"); 3841 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3842 qla2xxx_wake_dpc(vha); 3843 } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT && 3844 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3845 ql_log(ql_log_warn, vha, 0x6002, 3846 "Quiescent needed.\n"); 3847 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3848 qla2xxx_wake_dpc(vha); 3849 } else { 3850 if (qla82xx_check_fw_alive(vha)) { 3851 ql_dbg(ql_dbg_timer, vha, 0x6011, 3852 "disabling pause transmit on port 0 & 1.\n"); 3853 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3854 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3855 halt_status = qla82xx_rd_32(ha, 3856 QLA82XX_PEG_HALT_STATUS1); 3857 ql_log(ql_log_info, vha, 0x6005, 3858 "dumping hw/fw registers:.\n " 3859 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3860 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3861 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3862 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3863 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3864 qla82xx_rd_32(ha, 3865 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3866 qla82xx_rd_32(ha, 3867 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3868 qla82xx_rd_32(ha, 3869 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3870 qla82xx_rd_32(ha, 3871 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3872 qla82xx_rd_32(ha, 3873 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3874 if (LSW(MSB(halt_status)) == 0x67) 3875 ql_log(ql_log_warn, vha, 0xb052, 3876 "Firmware aborted with " 3877 "error code 0x00006700. Device is " 3878 "being reset.\n"); 3879 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3880 set_bit(ISP_UNRECOVERABLE, 3881 &vha->dpc_flags); 3882 } else { 3883 ql_log(ql_log_info, vha, 0x6006, 3884 "Detect abort needed.\n"); 3885 set_bit(ISP_ABORT_NEEDED, 3886 &vha->dpc_flags); 3887 } 3888 qla2xxx_wake_dpc(vha); 3889 ha->flags.isp82xx_fw_hung = 1; 3890 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3891 qla82xx_clear_pending_mbx(vha); 3892 } 3893 } 3894 } 3895} 3896 3897int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3898{ 3899 int rval; 3900 rval = qla82xx_device_state_handler(vha); 3901 return rval; 3902} 3903 3904void 3905qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3906{ 3907 struct qla_hw_data *ha = vha->hw; 3908 uint32_t dev_state; 3909 3910 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3911 if (dev_state == QLA82XX_DEV_READY) { 3912 ql_log(ql_log_info, vha, 0xb02f, 3913 "HW State: NEED RESET\n"); 3914 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3915 QLA82XX_DEV_NEED_RESET); 3916 ha->flags.isp82xx_reset_owner = 1; 3917 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3918 "reset_owner is 0x%x\n", ha->portnum); 3919 } else 3920 ql_log(ql_log_info, vha, 0xb031, 3921 "Device state is 0x%x = %s.\n", 3922 dev_state, 3923 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3924} 3925 3926/* 3927 * qla82xx_abort_isp 3928 * Resets ISP and aborts all outstanding commands. 3929 * 3930 * Input: 3931 * ha = adapter block pointer. 3932 * 3933 * Returns: 3934 * 0 = success 3935 */ 3936int 3937qla82xx_abort_isp(scsi_qla_host_t *vha) 3938{ 3939 int rval; 3940 struct qla_hw_data *ha = vha->hw; 3941 3942 if (vha->device_flags & DFLG_DEV_FAILED) { 3943 ql_log(ql_log_warn, vha, 0x8024, 3944 "Device in failed state, exiting.\n"); 3945 return QLA_SUCCESS; 3946 } 3947 ha->flags.isp82xx_reset_hdlr_active = 1; 3948 3949 qla82xx_idc_lock(ha); 3950 qla82xx_set_reset_owner(vha); 3951 qla82xx_idc_unlock(ha); 3952 3953 rval = qla82xx_device_state_handler(vha); 3954 3955 qla82xx_idc_lock(ha); 3956 qla82xx_clear_rst_ready(ha); 3957 qla82xx_idc_unlock(ha); 3958 3959 if (rval == QLA_SUCCESS) { 3960 ha->flags.isp82xx_fw_hung = 0; 3961 ha->flags.isp82xx_reset_hdlr_active = 0; 3962 qla82xx_restart_isp(vha); 3963 } 3964 3965 if (rval) { 3966 vha->flags.online = 1; 3967 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3968 if (ha->isp_abort_cnt == 0) { 3969 ql_log(ql_log_warn, vha, 0x8027, 3970 "ISP error recover failed - board " 3971 "disabled.\n"); 3972 /* 3973 * The next call disables the board 3974 * completely. 3975 */ 3976 ha->isp_ops->reset_adapter(vha); 3977 vha->flags.online = 0; 3978 clear_bit(ISP_ABORT_RETRY, 3979 &vha->dpc_flags); 3980 rval = QLA_SUCCESS; 3981 } else { /* schedule another ISP abort */ 3982 ha->isp_abort_cnt--; 3983 ql_log(ql_log_warn, vha, 0x8036, 3984 "ISP abort - retry remaining %d.\n", 3985 ha->isp_abort_cnt); 3986 rval = QLA_FUNCTION_FAILED; 3987 } 3988 } else { 3989 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3990 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3991 "ISP error recovery - retrying (%d) more times.\n", 3992 ha->isp_abort_cnt); 3993 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3994 rval = QLA_FUNCTION_FAILED; 3995 } 3996 } 3997 return rval; 3998} 3999 4000/* 4001 * qla82xx_fcoe_ctx_reset 4002 * Perform a quick reset and aborts all outstanding commands. 4003 * This will only perform an FCoE context reset and avoids a full blown 4004 * chip reset. 4005 * 4006 * Input: 4007 * ha = adapter block pointer. 4008 * is_reset_path = flag for identifying the reset path. 4009 * 4010 * Returns: 4011 * 0 = success 4012 */ 4013int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 4014{ 4015 int rval = QLA_FUNCTION_FAILED; 4016 4017 if (vha->flags.online) { 4018 /* Abort all outstanding commands, so as to be requeued later */ 4019 qla2x00_abort_isp_cleanup(vha); 4020 } 4021 4022 /* Stop currently executing firmware. 4023 * This will destroy existing FCoE context at the F/W end. 4024 */ 4025 qla2x00_try_to_stop_firmware(vha); 4026 4027 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 4028 rval = qla82xx_restart_isp(vha); 4029 4030 return rval; 4031} 4032 4033/* 4034 * qla2x00_wait_for_fcoe_ctx_reset 4035 * Wait till the FCoE context is reset. 4036 * 4037 * Note: 4038 * Does context switching here. 4039 * Release SPIN_LOCK (if any) before calling this routine. 4040 * 4041 * Return: 4042 * Success (fcoe_ctx reset is done) : 0 4043 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 4044 */ 4045int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 4046{ 4047 int status = QLA_FUNCTION_FAILED; 4048 unsigned long wait_reset; 4049 4050 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 4051 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 4052 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 4053 && time_before(jiffies, wait_reset)) { 4054 4055 set_current_state(TASK_UNINTERRUPTIBLE); 4056 schedule_timeout(HZ); 4057 4058 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 4059 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 4060 status = QLA_SUCCESS; 4061 break; 4062 } 4063 } 4064 ql_dbg(ql_dbg_p3p, vha, 0xb027, 4065 "%s: status=%d.\n", __func__, status); 4066 4067 return status; 4068} 4069 4070void 4071qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 4072{ 4073 int i; 4074 unsigned long flags; 4075 struct qla_hw_data *ha = vha->hw; 4076 4077 /* Check if 82XX firmware is alive or not 4078 * We may have arrived here from NEED_RESET 4079 * detection only 4080 */ 4081 if (!ha->flags.isp82xx_fw_hung) { 4082 for (i = 0; i < 2; i++) { 4083 msleep(1000); 4084 if (qla82xx_check_fw_alive(vha)) { 4085 ha->flags.isp82xx_fw_hung = 1; 4086 qla82xx_clear_pending_mbx(vha); 4087 break; 4088 } 4089 } 4090 } 4091 ql_dbg(ql_dbg_init, vha, 0x00b0, 4092 "Entered %s fw_hung=%d.\n", 4093 __func__, ha->flags.isp82xx_fw_hung); 4094 4095 /* Abort all commands gracefully if fw NOT hung */ 4096 if (!ha->flags.isp82xx_fw_hung) { 4097 int cnt, que; 4098 srb_t *sp; 4099 struct req_que *req; 4100 4101 spin_lock_irqsave(&ha->hardware_lock, flags); 4102 for (que = 0; que < ha->max_req_queues; que++) { 4103 req = ha->req_q_map[que]; 4104 if (!req) 4105 continue; 4106 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 4107 sp = req->outstanding_cmds[cnt]; 4108 if (sp) { 4109 if (!sp->ctx || 4110 (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 4111 spin_unlock_irqrestore( 4112 &ha->hardware_lock, flags); 4113 if (ha->isp_ops->abort_command(sp)) { 4114 ql_log(ql_log_info, vha, 4115 0x00b1, 4116 "mbx abort failed.\n"); 4117 } else { 4118 ql_log(ql_log_info, vha, 4119 0x00b2, 4120 "mbx abort success.\n"); 4121 } 4122 spin_lock_irqsave(&ha->hardware_lock, flags); 4123 } 4124 } 4125 } 4126 } 4127 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4128 4129 /* Wait for pending cmds (physical and virtual) to complete */ 4130 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 4131 WAIT_HOST) == QLA_SUCCESS) { 4132 ql_dbg(ql_dbg_init, vha, 0x00b3, 4133 "Done wait for " 4134 "pending commands.\n"); 4135 } 4136 } 4137} 4138 4139/* Minidump related functions */ 4140int 4141qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 4142{ 4143 uint32_t off_value, rval = 0; 4144 4145 WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase), 4146 (off & 0xFFFF0000)); 4147 4148 /* Read back value to make sure write has gone through */ 4149 RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 4150 off_value = (off & 0x0000FFFF); 4151 4152 if (flag) 4153 WRT_REG_DWORD((void *) 4154 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 4155 data); 4156 else 4157 rval = RD_REG_DWORD((void *) 4158 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 4159 4160 return rval; 4161} 4162 4163static int 4164qla82xx_minidump_process_control(scsi_qla_host_t *vha, 4165 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4166{ 4167 struct qla_hw_data *ha = vha->hw; 4168 struct qla82xx_md_entry_crb *crb_entry; 4169 uint32_t read_value, opcode, poll_time; 4170 uint32_t addr, index, crb_addr; 4171 unsigned long wtime; 4172 struct qla82xx_md_template_hdr *tmplt_hdr; 4173 uint32_t rval = QLA_SUCCESS; 4174 int i; 4175 4176 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4177 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 4178 crb_addr = crb_entry->addr; 4179 4180 for (i = 0; i < crb_entry->op_count; i++) { 4181 opcode = crb_entry->crb_ctrl.opcode; 4182 if (opcode & QLA82XX_DBG_OPCODE_WR) { 4183 qla82xx_md_rw_32(ha, crb_addr, 4184 crb_entry->value_1, 1); 4185 opcode &= ~QLA82XX_DBG_OPCODE_WR; 4186 } 4187 4188 if (opcode & QLA82XX_DBG_OPCODE_RW) { 4189 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 4190 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 4191 opcode &= ~QLA82XX_DBG_OPCODE_RW; 4192 } 4193 4194 if (opcode & QLA82XX_DBG_OPCODE_AND) { 4195 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 4196 read_value &= crb_entry->value_2; 4197 opcode &= ~QLA82XX_DBG_OPCODE_AND; 4198 if (opcode & QLA82XX_DBG_OPCODE_OR) { 4199 read_value |= crb_entry->value_3; 4200 opcode &= ~QLA82XX_DBG_OPCODE_OR; 4201 } 4202 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 4203 } 4204 4205 if (opcode & QLA82XX_DBG_OPCODE_OR) { 4206 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 4207 read_value |= crb_entry->value_3; 4208 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 4209 opcode &= ~QLA82XX_DBG_OPCODE_OR; 4210 } 4211 4212 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 4213 poll_time = crb_entry->crb_strd.poll_timeout; 4214 wtime = jiffies + poll_time; 4215 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 4216 4217 do { 4218 if ((read_value & crb_entry->value_2) 4219 == crb_entry->value_1) 4220 break; 4221 else if (time_after_eq(jiffies, wtime)) { 4222 /* capturing dump failed */ 4223 rval = QLA_FUNCTION_FAILED; 4224 break; 4225 } else 4226 read_value = qla82xx_md_rw_32(ha, 4227 crb_addr, 0, 0); 4228 } while (1); 4229 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 4230 } 4231 4232 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 4233 if (crb_entry->crb_strd.state_index_a) { 4234 index = crb_entry->crb_strd.state_index_a; 4235 addr = tmplt_hdr->saved_state_array[index]; 4236 } else 4237 addr = crb_addr; 4238 4239 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 4240 index = crb_entry->crb_ctrl.state_index_v; 4241 tmplt_hdr->saved_state_array[index] = read_value; 4242 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 4243 } 4244 4245 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 4246 if (crb_entry->crb_strd.state_index_a) { 4247 index = crb_entry->crb_strd.state_index_a; 4248 addr = tmplt_hdr->saved_state_array[index]; 4249 } else 4250 addr = crb_addr; 4251 4252 if (crb_entry->crb_ctrl.state_index_v) { 4253 index = crb_entry->crb_ctrl.state_index_v; 4254 read_value = 4255 tmplt_hdr->saved_state_array[index]; 4256 } else 4257 read_value = crb_entry->value_1; 4258 4259 qla82xx_md_rw_32(ha, addr, read_value, 1); 4260 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 4261 } 4262 4263 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 4264 index = crb_entry->crb_ctrl.state_index_v; 4265 read_value = tmplt_hdr->saved_state_array[index]; 4266 read_value <<= crb_entry->crb_ctrl.shl; 4267 read_value >>= crb_entry->crb_ctrl.shr; 4268 if (crb_entry->value_2) 4269 read_value &= crb_entry->value_2; 4270 read_value |= crb_entry->value_3; 4271 read_value += crb_entry->value_1; 4272 tmplt_hdr->saved_state_array[index] = read_value; 4273 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 4274 } 4275 crb_addr += crb_entry->crb_strd.addr_stride; 4276 } 4277 return rval; 4278} 4279 4280static void 4281qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 4282 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4283{ 4284 struct qla_hw_data *ha = vha->hw; 4285 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 4286 struct qla82xx_md_entry_rdocm *ocm_hdr; 4287 uint32_t *data_ptr = *d_ptr; 4288 4289 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 4290 r_addr = ocm_hdr->read_addr; 4291 r_stride = ocm_hdr->read_addr_stride; 4292 loop_cnt = ocm_hdr->op_count; 4293 4294 for (i = 0; i < loop_cnt; i++) { 4295 r_value = RD_REG_DWORD((void *)(r_addr + ha->nx_pcibase)); 4296 *data_ptr++ = cpu_to_le32(r_value); 4297 r_addr += r_stride; 4298 } 4299 *d_ptr = data_ptr; 4300} 4301 4302static void 4303qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 4304 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4305{ 4306 struct qla_hw_data *ha = vha->hw; 4307 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 4308 struct qla82xx_md_entry_mux *mux_hdr; 4309 uint32_t *data_ptr = *d_ptr; 4310 4311 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 4312 r_addr = mux_hdr->read_addr; 4313 s_addr = mux_hdr->select_addr; 4314 s_stride = mux_hdr->select_value_stride; 4315 s_value = mux_hdr->select_value; 4316 loop_cnt = mux_hdr->op_count; 4317 4318 for (i = 0; i < loop_cnt; i++) { 4319 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 4320 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 4321 *data_ptr++ = cpu_to_le32(s_value); 4322 *data_ptr++ = cpu_to_le32(r_value); 4323 s_value += s_stride; 4324 } 4325 *d_ptr = data_ptr; 4326} 4327 4328static void 4329qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 4330 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4331{ 4332 struct qla_hw_data *ha = vha->hw; 4333 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 4334 struct qla82xx_md_entry_crb *crb_hdr; 4335 uint32_t *data_ptr = *d_ptr; 4336 4337 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 4338 r_addr = crb_hdr->addr; 4339 r_stride = crb_hdr->crb_strd.addr_stride; 4340 loop_cnt = crb_hdr->op_count; 4341 4342 for (i = 0; i < loop_cnt; i++) { 4343 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 4344 *data_ptr++ = cpu_to_le32(r_addr); 4345 *data_ptr++ = cpu_to_le32(r_value); 4346 r_addr += r_stride; 4347 } 4348 *d_ptr = data_ptr; 4349} 4350 4351static int 4352qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 4353 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4354{ 4355 struct qla_hw_data *ha = vha->hw; 4356 uint32_t addr, r_addr, c_addr, t_r_addr; 4357 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 4358 unsigned long p_wait, w_time, p_mask; 4359 uint32_t c_value_w, c_value_r; 4360 struct qla82xx_md_entry_cache *cache_hdr; 4361 int rval = QLA_FUNCTION_FAILED; 4362 uint32_t *data_ptr = *d_ptr; 4363 4364 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 4365 loop_count = cache_hdr->op_count; 4366 r_addr = cache_hdr->read_addr; 4367 c_addr = cache_hdr->control_addr; 4368 c_value_w = cache_hdr->cache_ctrl.write_value; 4369 4370 t_r_addr = cache_hdr->tag_reg_addr; 4371 t_value = cache_hdr->addr_ctrl.init_tag_value; 4372 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 4373 p_wait = cache_hdr->cache_ctrl.poll_wait; 4374 p_mask = cache_hdr->cache_ctrl.poll_mask; 4375 4376 for (i = 0; i < loop_count; i++) { 4377 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 4378 if (c_value_w) 4379 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 4380 4381 if (p_mask) { 4382 w_time = jiffies + p_wait; 4383 do { 4384 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 4385 if ((c_value_r & p_mask) == 0) 4386 break; 4387 else if (time_after_eq(jiffies, w_time)) { 4388 /* capturing dump failed */ 4389 ql_dbg(ql_dbg_p3p, vha, 0xb032, 4390 "c_value_r: 0x%x, poll_mask: 0x%lx, " 4391 "w_time: 0x%lx\n", 4392 c_value_r, p_mask, w_time); 4393 return rval; 4394 } 4395 } while (1); 4396 } 4397 4398 addr = r_addr; 4399 for (k = 0; k < r_cnt; k++) { 4400 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 4401 *data_ptr++ = cpu_to_le32(r_value); 4402 addr += cache_hdr->read_ctrl.read_addr_stride; 4403 } 4404 t_value += cache_hdr->addr_ctrl.tag_value_stride; 4405 } 4406 *d_ptr = data_ptr; 4407 return QLA_SUCCESS; 4408} 4409 4410static void 4411qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 4412 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4413{ 4414 struct qla_hw_data *ha = vha->hw; 4415 uint32_t addr, r_addr, c_addr, t_r_addr; 4416 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 4417 uint32_t c_value_w; 4418 struct qla82xx_md_entry_cache *cache_hdr; 4419 uint32_t *data_ptr = *d_ptr; 4420 4421 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 4422 loop_count = cache_hdr->op_count; 4423 r_addr = cache_hdr->read_addr; 4424 c_addr = cache_hdr->control_addr; 4425 c_value_w = cache_hdr->cache_ctrl.write_value; 4426 4427 t_r_addr = cache_hdr->tag_reg_addr; 4428 t_value = cache_hdr->addr_ctrl.init_tag_value; 4429 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 4430 4431 for (i = 0; i < loop_count; i++) { 4432 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 4433 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 4434 addr = r_addr; 4435 for (k = 0; k < r_cnt; k++) { 4436 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 4437 *data_ptr++ = cpu_to_le32(r_value); 4438 addr += cache_hdr->read_ctrl.read_addr_stride; 4439 } 4440 t_value += cache_hdr->addr_ctrl.tag_value_stride; 4441 } 4442 *d_ptr = data_ptr; 4443} 4444 4445static void 4446qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 4447 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4448{ 4449 struct qla_hw_data *ha = vha->hw; 4450 uint32_t s_addr, r_addr; 4451 uint32_t r_stride, r_value, r_cnt, qid = 0; 4452 uint32_t i, k, loop_cnt; 4453 struct qla82xx_md_entry_queue *q_hdr; 4454 uint32_t *data_ptr = *d_ptr; 4455 4456 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 4457 s_addr = q_hdr->select_addr; 4458 r_cnt = q_hdr->rd_strd.read_addr_cnt; 4459 r_stride = q_hdr->rd_strd.read_addr_stride; 4460 loop_cnt = q_hdr->op_count; 4461 4462 for (i = 0; i < loop_cnt; i++) { 4463 qla82xx_md_rw_32(ha, s_addr, qid, 1); 4464 r_addr = q_hdr->read_addr; 4465 for (k = 0; k < r_cnt; k++) { 4466 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 4467 *data_ptr++ = cpu_to_le32(r_value); 4468 r_addr += r_stride; 4469 } 4470 qid += q_hdr->q_strd.queue_id_stride; 4471 } 4472 *d_ptr = data_ptr; 4473} 4474 4475static void 4476qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 4477 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4478{ 4479 struct qla_hw_data *ha = vha->hw; 4480 uint32_t r_addr, r_value; 4481 uint32_t i, loop_cnt; 4482 struct qla82xx_md_entry_rdrom *rom_hdr; 4483 uint32_t *data_ptr = *d_ptr; 4484 4485 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 4486 r_addr = rom_hdr->read_addr; 4487 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 4488 4489 for (i = 0; i < loop_cnt; i++) { 4490 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 4491 (r_addr & 0xFFFF0000), 1); 4492 r_value = qla82xx_md_rw_32(ha, 4493 MD_DIRECT_ROM_READ_BASE + 4494 (r_addr & 0x0000FFFF), 0, 0); 4495 *data_ptr++ = cpu_to_le32(r_value); 4496 r_addr += sizeof(uint32_t); 4497 } 4498 *d_ptr = data_ptr; 4499} 4500 4501static int 4502qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 4503 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 4504{ 4505 struct qla_hw_data *ha = vha->hw; 4506 uint32_t r_addr, r_value, r_data; 4507 uint32_t i, j, loop_cnt; 4508 struct qla82xx_md_entry_rdmem *m_hdr; 4509 unsigned long flags; 4510 int rval = QLA_FUNCTION_FAILED; 4511 uint32_t *data_ptr = *d_ptr; 4512 4513 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4514 r_addr = m_hdr->read_addr; 4515 loop_cnt = m_hdr->read_data_size/16; 4516 4517 if (r_addr & 0xf) { 4518 ql_log(ql_log_warn, vha, 0xb033, 4519 "Read addr 0x%x not 16 bytes alligned\n", r_addr); 4520 return rval; 4521 } 4522 4523 if (m_hdr->read_data_size % 16) { 4524 ql_log(ql_log_warn, vha, 0xb034, 4525 "Read data[0x%x] not multiple of 16 bytes\n", 4526 m_hdr->read_data_size); 4527 return rval; 4528 } 4529 4530 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4531 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4532 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4533 4534 write_lock_irqsave(&ha->hw_lock, flags); 4535 for (i = 0; i < loop_cnt; i++) { 4536 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4537 r_value = 0; 4538 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4539 r_value = MIU_TA_CTL_ENABLE; 4540 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4541 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4542 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4543 4544 for (j = 0; j < MAX_CTL_CHECK; j++) { 4545 r_value = qla82xx_md_rw_32(ha, 4546 MD_MIU_TEST_AGT_CTRL, 0, 0); 4547 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4548 break; 4549 } 4550 4551 if (j >= MAX_CTL_CHECK) { 4552 printk_ratelimited(KERN_ERR 4553 "failed to read through agent\n"); 4554 write_unlock_irqrestore(&ha->hw_lock, flags); 4555 return rval; 4556 } 4557 4558 for (j = 0; j < 4; j++) { 4559 r_data = qla82xx_md_rw_32(ha, 4560 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4561 *data_ptr++ = cpu_to_le32(r_data); 4562 } 4563 r_addr += 16; 4564 } 4565 write_unlock_irqrestore(&ha->hw_lock, flags); 4566 *d_ptr = data_ptr; 4567 return QLA_SUCCESS; 4568} 4569 4570static int 4571qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4572{ 4573 struct qla_hw_data *ha = vha->hw; 4574 uint64_t chksum = 0; 4575 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4576 int count = ha->md_template_size/sizeof(uint32_t); 4577 4578 while (count-- > 0) 4579 chksum += *d_ptr++; 4580 while (chksum >> 32) 4581 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4582 return ~chksum; 4583} 4584 4585static void 4586qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4587 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4588{ 4589 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4590 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4591 "Skipping entry[%d]: " 4592 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4593 index, entry_hdr->entry_type, 4594 entry_hdr->d_ctrl.entry_capture_mask); 4595} 4596 4597int 4598qla82xx_md_collect(scsi_qla_host_t *vha) 4599{ 4600 struct qla_hw_data *ha = vha->hw; 4601 int no_entry_hdr = 0; 4602 qla82xx_md_entry_hdr_t *entry_hdr; 4603 struct qla82xx_md_template_hdr *tmplt_hdr; 4604 uint32_t *data_ptr; 4605 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4606 int i = 0, rval = QLA_FUNCTION_FAILED; 4607 4608 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4609 data_ptr = (uint32_t *)ha->md_dump; 4610 4611 if (ha->fw_dumped) { 4612 ql_log(ql_log_info, vha, 0xb037, 4613 "Firmware dump available to retrive\n"); 4614 goto md_failed; 4615 } 4616 4617 ha->fw_dumped = 0; 4618 4619 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4620 ql_log(ql_log_warn, vha, 0xb038, 4621 "Memory not allocated for minidump capture\n"); 4622 goto md_failed; 4623 } 4624 4625 if (qla82xx_validate_template_chksum(vha)) { 4626 ql_log(ql_log_info, vha, 0xb039, 4627 "Template checksum validation error\n"); 4628 goto md_failed; 4629 } 4630 4631 no_entry_hdr = tmplt_hdr->num_of_entries; 4632 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4633 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4634 4635 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4636 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4637 4638 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4639 4640 /* Validate whether required debug level is set */ 4641 if ((f_capture_mask & 0x3) != 0x3) { 4642 ql_log(ql_log_warn, vha, 0xb03c, 4643 "Minimum required capture mask[0x%x] level not set\n", 4644 f_capture_mask); 4645 goto md_failed; 4646 } 4647 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4648 4649 tmplt_hdr->driver_info[0] = vha->host_no; 4650 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4651 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4652 QLA_DRIVER_BETA_VER; 4653 4654 total_data_size = ha->md_dump_size; 4655 4656 ql_dbg(ql_log_info, vha, 0xb03d, 4657 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4658 4659 /* Check whether template obtained is valid */ 4660 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4661 ql_log(ql_log_warn, vha, 0xb04e, 4662 "Bad template header entry type: 0x%x obtained\n", 4663 tmplt_hdr->entry_type); 4664 goto md_failed; 4665 } 4666 4667 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4668 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4669 4670 /* Walk through the entry headers */ 4671 for (i = 0; i < no_entry_hdr; i++) { 4672 4673 if (data_collected > total_data_size) { 4674 ql_log(ql_log_warn, vha, 0xb03e, 4675 "More MiniDump data collected: [0x%x]\n", 4676 data_collected); 4677 goto md_failed; 4678 } 4679 4680 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4681 ql2xmdcapmask)) { 4682 entry_hdr->d_ctrl.driver_flags |= 4683 QLA82XX_DBG_SKIPPED_FLAG; 4684 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4685 "Skipping entry[%d]: " 4686 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4687 i, entry_hdr->entry_type, 4688 entry_hdr->d_ctrl.entry_capture_mask); 4689 goto skip_nxt_entry; 4690 } 4691 4692 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4693 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4694 "entry_type: 0x%x, captrue_mask: 0x%x\n", 4695 __func__, i, data_ptr, entry_hdr, 4696 entry_hdr->entry_type, 4697 entry_hdr->d_ctrl.entry_capture_mask); 4698 4699 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4700 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4701 data_collected, (ha->md_dump_size - data_collected)); 4702 4703 /* Decode the entry type and take 4704 * required action to capture debug data */ 4705 switch (entry_hdr->entry_type) { 4706 case QLA82XX_RDEND: 4707 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4708 break; 4709 case QLA82XX_CNTRL: 4710 rval = qla82xx_minidump_process_control(vha, 4711 entry_hdr, &data_ptr); 4712 if (rval != QLA_SUCCESS) { 4713 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4714 goto md_failed; 4715 } 4716 break; 4717 case QLA82XX_RDCRB: 4718 qla82xx_minidump_process_rdcrb(vha, 4719 entry_hdr, &data_ptr); 4720 break; 4721 case QLA82XX_RDMEM: 4722 rval = qla82xx_minidump_process_rdmem(vha, 4723 entry_hdr, &data_ptr); 4724 if (rval != QLA_SUCCESS) { 4725 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4726 goto md_failed; 4727 } 4728 break; 4729 case QLA82XX_BOARD: 4730 case QLA82XX_RDROM: 4731 qla82xx_minidump_process_rdrom(vha, 4732 entry_hdr, &data_ptr); 4733 break; 4734 case QLA82XX_L2DTG: 4735 case QLA82XX_L2ITG: 4736 case QLA82XX_L2DAT: 4737 case QLA82XX_L2INS: 4738 rval = qla82xx_minidump_process_l2tag(vha, 4739 entry_hdr, &data_ptr); 4740 if (rval != QLA_SUCCESS) { 4741 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4742 goto md_failed; 4743 } 4744 break; 4745 case QLA82XX_L1DAT: 4746 case QLA82XX_L1INS: 4747 qla82xx_minidump_process_l1cache(vha, 4748 entry_hdr, &data_ptr); 4749 break; 4750 case QLA82XX_RDOCM: 4751 qla82xx_minidump_process_rdocm(vha, 4752 entry_hdr, &data_ptr); 4753 break; 4754 case QLA82XX_RDMUX: 4755 qla82xx_minidump_process_rdmux(vha, 4756 entry_hdr, &data_ptr); 4757 break; 4758 case QLA82XX_QUEUE: 4759 qla82xx_minidump_process_queue(vha, 4760 entry_hdr, &data_ptr); 4761 break; 4762 case QLA82XX_RDNOP: 4763 default: 4764 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4765 break; 4766 } 4767 4768 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4769 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4770 4771 data_collected = (uint8_t *)data_ptr - 4772 (uint8_t *)ha->md_dump; 4773skip_nxt_entry: 4774 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4775 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4776 } 4777 4778 if (data_collected != total_data_size) { 4779 ql_dbg(ql_log_warn, vha, 0xb043, 4780 "MiniDump data mismatch: Data collected: [0x%x]," 4781 "total_data_size:[0x%x]\n", 4782 data_collected, total_data_size); 4783 goto md_failed; 4784 } 4785 4786 ql_log(ql_log_info, vha, 0xb044, 4787 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4788 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4789 ha->fw_dumped = 1; 4790 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4791 4792md_failed: 4793 return rval; 4794} 4795 4796int 4797qla82xx_md_alloc(scsi_qla_host_t *vha) 4798{ 4799 struct qla_hw_data *ha = vha->hw; 4800 int i, k; 4801 struct qla82xx_md_template_hdr *tmplt_hdr; 4802 4803 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4804 4805 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4806 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4807 ql_log(ql_log_info, vha, 0xb045, 4808 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4809 ql2xmdcapmask); 4810 } 4811 4812 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4813 if (i & ql2xmdcapmask) 4814 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4815 } 4816 4817 if (ha->md_dump) { 4818 ql_log(ql_log_warn, vha, 0xb046, 4819 "Firmware dump previously allocated.\n"); 4820 return 1; 4821 } 4822 4823 ha->md_dump = vmalloc(ha->md_dump_size); 4824 if (ha->md_dump == NULL) { 4825 ql_log(ql_log_warn, vha, 0xb047, 4826 "Unable to allocate memory for Minidump size " 4827 "(0x%x).\n", ha->md_dump_size); 4828 return 1; 4829 } 4830 return 0; 4831} 4832 4833void 4834qla82xx_md_free(scsi_qla_host_t *vha) 4835{ 4836 struct qla_hw_data *ha = vha->hw; 4837 4838 /* Release the template header allocated */ 4839 if (ha->md_tmplt_hdr) { 4840 ql_log(ql_log_info, vha, 0xb048, 4841 "Free MiniDump template: %p, size (%d KB)\n", 4842 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4843 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4844 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4845 ha->md_tmplt_hdr = 0; 4846 } 4847 4848 /* Release the template data buffer allocated */ 4849 if (ha->md_dump) { 4850 ql_log(ql_log_info, vha, 0xb049, 4851 "Free MiniDump memory: %p, size (%d KB)\n", 4852 ha->md_dump, ha->md_dump_size / 1024); 4853 vfree(ha->md_dump); 4854 ha->md_dump_size = 0; 4855 ha->md_dump = 0; 4856 } 4857} 4858 4859void 4860qla82xx_md_prep(scsi_qla_host_t *vha) 4861{ 4862 struct qla_hw_data *ha = vha->hw; 4863 int rval; 4864 4865 /* Get Minidump template size */ 4866 rval = qla82xx_md_get_template_size(vha); 4867 if (rval == QLA_SUCCESS) { 4868 ql_log(ql_log_info, vha, 0xb04a, 4869 "MiniDump Template size obtained (%d KB)\n", 4870 ha->md_template_size / 1024); 4871 4872 /* Get Minidump template */ 4873 rval = qla82xx_md_get_template(vha); 4874 if (rval == QLA_SUCCESS) { 4875 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4876 "MiniDump Template obtained\n"); 4877 4878 /* Allocate memory for minidump */ 4879 rval = qla82xx_md_alloc(vha); 4880 if (rval == QLA_SUCCESS) 4881 ql_log(ql_log_info, vha, 0xb04c, 4882 "MiniDump memory allocated (%d KB)\n", 4883 ha->md_dump_size / 1024); 4884 else { 4885 ql_log(ql_log_info, vha, 0xb04d, 4886 "Free MiniDump template: %p, size: (%d KB)\n", 4887 ha->md_tmplt_hdr, 4888 ha->md_template_size / 1024); 4889 dma_free_coherent(&ha->pdev->dev, 4890 ha->md_template_size, 4891 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4892 ha->md_tmplt_hdr = 0; 4893 } 4894 4895 } 4896 } 4897} 4898 4899int 4900qla82xx_beacon_on(struct scsi_qla_host *vha) 4901{ 4902 4903 int rval; 4904 struct qla_hw_data *ha = vha->hw; 4905 qla82xx_idc_lock(ha); 4906 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4907 4908 if (rval) { 4909 ql_log(ql_log_warn, vha, 0xb050, 4910 "mbx set led config failed in %s\n", __func__); 4911 goto exit; 4912 } 4913 ha->beacon_blink_led = 1; 4914exit: 4915 qla82xx_idc_unlock(ha); 4916 return rval; 4917} 4918 4919int 4920qla82xx_beacon_off(struct scsi_qla_host *vha) 4921{ 4922 4923 int rval; 4924 struct qla_hw_data *ha = vha->hw; 4925 qla82xx_idc_lock(ha); 4926 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4927 4928 if (rval) { 4929 ql_log(ql_log_warn, vha, 0xb051, 4930 "mbx set led config failed in %s\n", __func__); 4931 goto exit; 4932 } 4933 ha->beacon_blink_led = 0; 4934exit: 4935 qla82xx_idc_unlock(ha); 4936 return rval; 4937} 4938