qla_nx.c revision f4e1648a4f4acc964cefc51c1637aad0dca6c517
1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2011 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7#include "qla_def.h" 8#include <linux/delay.h> 9#include <linux/pci.h> 10#include <linux/ratelimit.h> 11#include <linux/vmalloc.h> 12#include <scsi/scsi_tcq.h> 13 14#define MASK(n) ((1ULL<<(n))-1) 15#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ 16 ((addr >> 25) & 0x3ff)) 17#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ 18 ((addr >> 25) & 0x3ff)) 19#define MS_WIN(addr) (addr & 0x0ffc0000) 20#define QLA82XX_PCI_MN_2M (0) 21#define QLA82XX_PCI_MS_2M (0x80000) 22#define QLA82XX_PCI_OCM0_2M (0xc0000) 23#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24#define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25#define BLOCK_PROTECT_BITS 0x0F 26 27/* CRB window related */ 28#define CRB_BLK(off) ((off >> 20) & 0x3f) 29#define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30#define CRB_WINDOW_2M (0x130060) 31#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32#define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33 ((off) & 0xf0000)) 34#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35#define CRB_INDIRECT_2M (0x1e0000UL) 36 37#define MAX_CRB_XFORM 60 38static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 39int qla82xx_crb_table_initialized; 40 41#define qla82xx_crb_addr_transform(name) \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 44 45static void qla82xx_crb_addr_transform_setup(void) 46{ 47 qla82xx_crb_addr_transform(XDMA); 48 qla82xx_crb_addr_transform(TIMR); 49 qla82xx_crb_addr_transform(SRE); 50 qla82xx_crb_addr_transform(SQN3); 51 qla82xx_crb_addr_transform(SQN2); 52 qla82xx_crb_addr_transform(SQN1); 53 qla82xx_crb_addr_transform(SQN0); 54 qla82xx_crb_addr_transform(SQS3); 55 qla82xx_crb_addr_transform(SQS2); 56 qla82xx_crb_addr_transform(SQS1); 57 qla82xx_crb_addr_transform(SQS0); 58 qla82xx_crb_addr_transform(RPMX7); 59 qla82xx_crb_addr_transform(RPMX6); 60 qla82xx_crb_addr_transform(RPMX5); 61 qla82xx_crb_addr_transform(RPMX4); 62 qla82xx_crb_addr_transform(RPMX3); 63 qla82xx_crb_addr_transform(RPMX2); 64 qla82xx_crb_addr_transform(RPMX1); 65 qla82xx_crb_addr_transform(RPMX0); 66 qla82xx_crb_addr_transform(ROMUSB); 67 qla82xx_crb_addr_transform(SN); 68 qla82xx_crb_addr_transform(QMN); 69 qla82xx_crb_addr_transform(QMS); 70 qla82xx_crb_addr_transform(PGNI); 71 qla82xx_crb_addr_transform(PGND); 72 qla82xx_crb_addr_transform(PGN3); 73 qla82xx_crb_addr_transform(PGN2); 74 qla82xx_crb_addr_transform(PGN1); 75 qla82xx_crb_addr_transform(PGN0); 76 qla82xx_crb_addr_transform(PGSI); 77 qla82xx_crb_addr_transform(PGSD); 78 qla82xx_crb_addr_transform(PGS3); 79 qla82xx_crb_addr_transform(PGS2); 80 qla82xx_crb_addr_transform(PGS1); 81 qla82xx_crb_addr_transform(PGS0); 82 qla82xx_crb_addr_transform(PS); 83 qla82xx_crb_addr_transform(PH); 84 qla82xx_crb_addr_transform(NIU); 85 qla82xx_crb_addr_transform(I2Q); 86 qla82xx_crb_addr_transform(EG); 87 qla82xx_crb_addr_transform(MN); 88 qla82xx_crb_addr_transform(MS); 89 qla82xx_crb_addr_transform(CAS2); 90 qla82xx_crb_addr_transform(CAS1); 91 qla82xx_crb_addr_transform(CAS0); 92 qla82xx_crb_addr_transform(CAM); 93 qla82xx_crb_addr_transform(C2C1); 94 qla82xx_crb_addr_transform(C2C0); 95 qla82xx_crb_addr_transform(SMB); 96 qla82xx_crb_addr_transform(OCM0); 97 /* 98 * Used only in P3 just define it for P2 also. 99 */ 100 qla82xx_crb_addr_transform(I2C0); 101 102 qla82xx_crb_table_initialized = 1; 103} 104 105struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 106 {{{0, 0, 0, 0} } }, 107 {{{1, 0x0100000, 0x0102000, 0x120000}, 108 {1, 0x0110000, 0x0120000, 0x130000}, 109 {1, 0x0120000, 0x0122000, 0x124000}, 110 {1, 0x0130000, 0x0132000, 0x126000}, 111 {1, 0x0140000, 0x0142000, 0x128000}, 112 {1, 0x0150000, 0x0152000, 0x12a000}, 113 {1, 0x0160000, 0x0170000, 0x110000}, 114 {1, 0x0170000, 0x0172000, 0x12e000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {1, 0x01e0000, 0x01e0800, 0x122000}, 122 {0, 0x0000000, 0x0000000, 0x000000} } } , 123 {{{1, 0x0200000, 0x0210000, 0x180000} } }, 124 {{{0, 0, 0, 0} } }, 125 {{{1, 0x0400000, 0x0401000, 0x169000} } }, 126 {{{1, 0x0500000, 0x0510000, 0x140000} } }, 127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, 128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, 129 {{{1, 0x0800000, 0x0802000, 0x170000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 145 {{{1, 0x0900000, 0x0902000, 0x174000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 161 {{{0, 0x0a00000, 0x0a02000, 0x178000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 177 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {0, 0x0000000, 0x0000000, 0x000000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, 194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, 195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, 196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, 197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, 198 {{{1, 0x1100000, 0x1101000, 0x160000} } }, 199 {{{1, 0x1200000, 0x1201000, 0x161000} } }, 200 {{{1, 0x1300000, 0x1301000, 0x162000} } }, 201 {{{1, 0x1400000, 0x1401000, 0x163000} } }, 202 {{{1, 0x1500000, 0x1501000, 0x165000} } }, 203 {{{1, 0x1600000, 0x1601000, 0x166000} } }, 204 {{{0, 0, 0, 0} } }, 205 {{{0, 0, 0, 0} } }, 206 {{{0, 0, 0, 0} } }, 207 {{{0, 0, 0, 0} } }, 208 {{{0, 0, 0, 0} } }, 209 {{{0, 0, 0, 0} } }, 210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, 211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, 212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, 213 {{{0} } }, 214 {{{1, 0x2100000, 0x2102000, 0x120000}, 215 {1, 0x2110000, 0x2120000, 0x130000}, 216 {1, 0x2120000, 0x2122000, 0x124000}, 217 {1, 0x2130000, 0x2132000, 0x126000}, 218 {1, 0x2140000, 0x2142000, 0x128000}, 219 {1, 0x2150000, 0x2152000, 0x12a000}, 220 {1, 0x2160000, 0x2170000, 0x110000}, 221 {1, 0x2170000, 0x2172000, 0x12e000}, 222 {0, 0x0000000, 0x0000000, 0x000000}, 223 {0, 0x0000000, 0x0000000, 0x000000}, 224 {0, 0x0000000, 0x0000000, 0x000000}, 225 {0, 0x0000000, 0x0000000, 0x000000}, 226 {0, 0x0000000, 0x0000000, 0x000000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000} } }, 230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, 231 {{{0} } }, 232 {{{0} } }, 233 {{{0} } }, 234 {{{0} } }, 235 {{{0} } }, 236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, 237 {{{1, 0x2900000, 0x2901000, 0x16b000} } }, 238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, 239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, 240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, 241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, 242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, 243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, 244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, 245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, 246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, 247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, 248 {{{0} } }, 249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, 250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, 251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, 252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, 253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, 254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, 255 {{{0} } }, 256 {{{0} } }, 257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, 258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, 259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } 260}; 261 262/* 263 * top 12 bits of crb internal address (hub, agent) 264 */ 265unsigned qla82xx_crb_hub_agt[64] = { 266 0, 267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 270 0, 271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 293 0, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 296 0, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 301 0, 302 0, 303 0, 304 0, 305 0, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 307 0, 308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 318 0, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 327 0, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 329 0, 330}; 331 332/* Device states */ 333char *q_dev_state[] = { 334 "Unknown", 335 "Cold", 336 "Initializing", 337 "Ready", 338 "Need Reset", 339 "Need Quiescent", 340 "Failed", 341 "Quiescent", 342}; 343 344char *qdev_state(uint32_t dev_state) 345{ 346 return q_dev_state[dev_state]; 347} 348 349/* 350 * In: 'off' is offset from CRB space in 128M pci map 351 * Out: 'off' is 2M pci map addr 352 * side effect: lock crb window 353 */ 354static void 355qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 356{ 357 u32 win_read; 358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359 360 ha->crb_win = CRB_HI(*off); 361 writel(ha->crb_win, 362 (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363 364 /* Read back value to make sure write has gone through before trying 365 * to use it. 366 */ 367 win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 368 if (win_read != ha->crb_win) { 369 ql_dbg(ql_dbg_p3p, vha, 0xb000, 370 "%s: Written crbwin (0x%x) " 371 "!= Read crbwin (0x%x), off=0x%lx.\n", 372 __func__, ha->crb_win, win_read, *off); 373 } 374 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 375} 376 377static inline unsigned long 378qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) 379{ 380 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 381 /* See if we are currently pointing to the region we want to use next */ 382 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { 383 /* No need to change window. PCIX and PCIEregs are in both 384 * regs are in both windows. 385 */ 386 return off; 387 } 388 389 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { 390 /* We are in first CRB window */ 391 if (ha->curr_window != 0) 392 WARN_ON(1); 393 return off; 394 } 395 396 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { 397 /* We are in second CRB window */ 398 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; 399 400 if (ha->curr_window != 1) 401 return off; 402 403 /* We are in the QM or direct access 404 * register region - do nothing 405 */ 406 if ((off >= QLA82XX_PCI_DIRECT_CRB) && 407 (off < QLA82XX_PCI_CAMQM_MAX)) 408 return off; 409 } 410 /* strange address given */ 411 ql_dbg(ql_dbg_p3p, vha, 0xb001, 412 "%s: Warning: unm_nic_pci_set_crbwindow " 413 "called with an unknown address(%llx).\n", 414 QLA2XXX_DRIVER_NAME, off); 415 return off; 416} 417 418static int 419qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 420{ 421 struct crb_128M_2M_sub_block_map *m; 422 423 if (*off >= QLA82XX_CRB_MAX) 424 return -1; 425 426 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 427 *off = (*off - QLA82XX_PCI_CAMQM) + 428 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 429 return 0; 430 } 431 432 if (*off < QLA82XX_PCI_CRBSPACE) 433 return -1; 434 435 *off -= QLA82XX_PCI_CRBSPACE; 436 437 /* Try direct map */ 438 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 439 440 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 441 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 442 return 0; 443 } 444 /* Not in direct map, use crb window */ 445 return 1; 446} 447 448#define CRB_WIN_LOCK_TIMEOUT 100000000 449static int qla82xx_crb_win_lock(struct qla_hw_data *ha) 450{ 451 int done = 0, timeout = 0; 452 453 while (!done) { 454 /* acquire semaphore3 from PCI HW block */ 455 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 456 if (done == 1) 457 break; 458 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 459 return -1; 460 timeout++; 461 } 462 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); 463 return 0; 464} 465 466int 467qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 468{ 469 unsigned long flags = 0; 470 int rv; 471 472 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 473 474 BUG_ON(rv == -1); 475 476 if (rv == 1) { 477 write_lock_irqsave(&ha->hw_lock, flags); 478 qla82xx_crb_win_lock(ha); 479 qla82xx_pci_set_crbwindow_2M(ha, &off); 480 } 481 482 writel(data, (void __iomem *)off); 483 484 if (rv == 1) { 485 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 486 write_unlock_irqrestore(&ha->hw_lock, flags); 487 } 488 return 0; 489} 490 491int 492qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 493{ 494 unsigned long flags = 0; 495 int rv; 496 u32 data; 497 498 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 499 500 BUG_ON(rv == -1); 501 502 if (rv == 1) { 503 write_lock_irqsave(&ha->hw_lock, flags); 504 qla82xx_crb_win_lock(ha); 505 qla82xx_pci_set_crbwindow_2M(ha, &off); 506 } 507 data = RD_REG_DWORD((void __iomem *)off); 508 509 if (rv == 1) { 510 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 511 write_unlock_irqrestore(&ha->hw_lock, flags); 512 } 513 return data; 514} 515 516#define IDC_LOCK_TIMEOUT 100000000 517int qla82xx_idc_lock(struct qla_hw_data *ha) 518{ 519 int i; 520 int done = 0, timeout = 0; 521 522 while (!done) { 523 /* acquire semaphore5 from PCI HW block */ 524 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 525 if (done == 1) 526 break; 527 if (timeout >= IDC_LOCK_TIMEOUT) 528 return -1; 529 530 timeout++; 531 532 /* Yield CPU */ 533 if (!in_interrupt()) 534 schedule(); 535 else { 536 for (i = 0; i < 20; i++) 537 cpu_relax(); 538 } 539 } 540 541 return 0; 542} 543 544void qla82xx_idc_unlock(struct qla_hw_data *ha) 545{ 546 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 547} 548 549/* PCI Windowing for DDR regions. */ 550#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 551 (((addr) <= (high)) && ((addr) >= (low))) 552/* 553 * check memory access boundary. 554 * used by test agent. support ddr access only for now 555 */ 556static unsigned long 557qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, 558 unsigned long long addr, int size) 559{ 560 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 561 QLA82XX_ADDR_DDR_NET_MAX) || 562 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, 563 QLA82XX_ADDR_DDR_NET_MAX) || 564 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) 565 return 0; 566 else 567 return 1; 568} 569 570int qla82xx_pci_set_window_warning_count; 571 572static unsigned long 573qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 574{ 575 int window; 576 u32 win_read; 577 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 578 579 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 580 QLA82XX_ADDR_DDR_NET_MAX)) { 581 /* DDR network side */ 582 window = MN_WIN(addr); 583 ha->ddr_mn_window = window; 584 qla82xx_wr_32(ha, 585 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 586 win_read = qla82xx_rd_32(ha, 587 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 588 if ((win_read << 17) != window) { 589 ql_dbg(ql_dbg_p3p, vha, 0xb003, 590 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", 591 __func__, window, win_read); 592 } 593 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 594 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 595 QLA82XX_ADDR_OCM0_MAX)) { 596 unsigned int temp1; 597 if ((addr & 0x00ff800) == 0xff800) { 598 ql_log(ql_log_warn, vha, 0xb004, 599 "%s: QM access not handled.\n", __func__); 600 addr = -1UL; 601 } 602 window = OCM_WIN(addr); 603 ha->ddr_mn_window = window; 604 qla82xx_wr_32(ha, 605 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); 606 win_read = qla82xx_rd_32(ha, 607 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); 608 temp1 = ((window & 0x1FF) << 7) | 609 ((window & 0x0FFFE0000) >> 17); 610 if (win_read != temp1) { 611 ql_log(ql_log_warn, vha, 0xb005, 612 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", 613 __func__, temp1, win_read); 614 } 615 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 616 617 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 618 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 619 /* QDR network side */ 620 window = MS_WIN(addr); 621 ha->qdr_sn_window = window; 622 qla82xx_wr_32(ha, 623 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); 624 win_read = qla82xx_rd_32(ha, 625 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 626 if (win_read != window) { 627 ql_log(ql_log_warn, vha, 0xb006, 628 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", 629 __func__, window, win_read); 630 } 631 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 632 } else { 633 /* 634 * peg gdb frequently accesses memory that doesn't exist, 635 * this limits the chit chat so debugging isn't slowed down. 636 */ 637 if ((qla82xx_pci_set_window_warning_count++ < 8) || 638 (qla82xx_pci_set_window_warning_count%64 == 0)) { 639 ql_log(ql_log_warn, vha, 0xb007, 640 "%s: Warning:%s Unknown address range!.\n", 641 __func__, QLA2XXX_DRIVER_NAME); 642 } 643 addr = -1UL; 644 } 645 return addr; 646} 647 648/* check if address is in the same windows as the previous access */ 649static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, 650 unsigned long long addr) 651{ 652 int window; 653 unsigned long long qdr_max; 654 655 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 656 657 /* DDR network side */ 658 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 659 QLA82XX_ADDR_DDR_NET_MAX)) 660 BUG(); 661 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 662 QLA82XX_ADDR_OCM0_MAX)) 663 return 1; 664 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 665 QLA82XX_ADDR_OCM1_MAX)) 666 return 1; 667 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { 668 /* QDR network side */ 669 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 670 if (ha->qdr_sn_window == window) 671 return 1; 672 } 673 return 0; 674} 675 676static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, 677 u64 off, void *data, int size) 678{ 679 unsigned long flags; 680 void *addr = NULL; 681 int ret = 0; 682 u64 start; 683 uint8_t *mem_ptr = NULL; 684 unsigned long mem_base; 685 unsigned long mem_page; 686 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 687 688 write_lock_irqsave(&ha->hw_lock, flags); 689 690 /* 691 * If attempting to access unknown address or straddle hw windows, 692 * do not access. 693 */ 694 start = qla82xx_pci_set_window(ha, off); 695 if ((start == -1UL) || 696 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 697 write_unlock_irqrestore(&ha->hw_lock, flags); 698 ql_log(ql_log_fatal, vha, 0xb008, 699 "%s out of bound pci memory " 700 "access, offset is 0x%llx.\n", 701 QLA2XXX_DRIVER_NAME, off); 702 return -1; 703 } 704 705 write_unlock_irqrestore(&ha->hw_lock, flags); 706 mem_base = pci_resource_start(ha->pdev, 0); 707 mem_page = start & PAGE_MASK; 708 /* Map two pages whenever user tries to access addresses in two 709 * consecutive pages. 710 */ 711 if (mem_page != ((start + size - 1) & PAGE_MASK)) 712 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 713 else 714 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 715 if (mem_ptr == 0UL) { 716 *(u8 *)data = 0; 717 return -1; 718 } 719 addr = mem_ptr; 720 addr += start & (PAGE_SIZE - 1); 721 write_lock_irqsave(&ha->hw_lock, flags); 722 723 switch (size) { 724 case 1: 725 *(u8 *)data = readb(addr); 726 break; 727 case 2: 728 *(u16 *)data = readw(addr); 729 break; 730 case 4: 731 *(u32 *)data = readl(addr); 732 break; 733 case 8: 734 *(u64 *)data = readq(addr); 735 break; 736 default: 737 ret = -1; 738 break; 739 } 740 write_unlock_irqrestore(&ha->hw_lock, flags); 741 742 if (mem_ptr) 743 iounmap(mem_ptr); 744 return ret; 745} 746 747static int 748qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, 749 u64 off, void *data, int size) 750{ 751 unsigned long flags; 752 void *addr = NULL; 753 int ret = 0; 754 u64 start; 755 uint8_t *mem_ptr = NULL; 756 unsigned long mem_base; 757 unsigned long mem_page; 758 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 759 760 write_lock_irqsave(&ha->hw_lock, flags); 761 762 /* 763 * If attempting to access unknown address or straddle hw windows, 764 * do not access. 765 */ 766 start = qla82xx_pci_set_window(ha, off); 767 if ((start == -1UL) || 768 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 769 write_unlock_irqrestore(&ha->hw_lock, flags); 770 ql_log(ql_log_fatal, vha, 0xb009, 771 "%s out of bount memory " 772 "access, offset is 0x%llx.\n", 773 QLA2XXX_DRIVER_NAME, off); 774 return -1; 775 } 776 777 write_unlock_irqrestore(&ha->hw_lock, flags); 778 mem_base = pci_resource_start(ha->pdev, 0); 779 mem_page = start & PAGE_MASK; 780 /* Map two pages whenever user tries to access addresses in two 781 * consecutive pages. 782 */ 783 if (mem_page != ((start + size - 1) & PAGE_MASK)) 784 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 785 else 786 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 787 if (mem_ptr == 0UL) 788 return -1; 789 790 addr = mem_ptr; 791 addr += start & (PAGE_SIZE - 1); 792 write_lock_irqsave(&ha->hw_lock, flags); 793 794 switch (size) { 795 case 1: 796 writeb(*(u8 *)data, addr); 797 break; 798 case 2: 799 writew(*(u16 *)data, addr); 800 break; 801 case 4: 802 writel(*(u32 *)data, addr); 803 break; 804 case 8: 805 writeq(*(u64 *)data, addr); 806 break; 807 default: 808 ret = -1; 809 break; 810 } 811 write_unlock_irqrestore(&ha->hw_lock, flags); 812 if (mem_ptr) 813 iounmap(mem_ptr); 814 return ret; 815} 816 817#define MTU_FUDGE_FACTOR 100 818static unsigned long 819qla82xx_decode_crb_addr(unsigned long addr) 820{ 821 int i; 822 unsigned long base_addr, offset, pci_base; 823 824 if (!qla82xx_crb_table_initialized) 825 qla82xx_crb_addr_transform_setup(); 826 827 pci_base = ADDR_ERROR; 828 base_addr = addr & 0xfff00000; 829 offset = addr & 0x000fffff; 830 831 for (i = 0; i < MAX_CRB_XFORM; i++) { 832 if (crb_addr_xform[i] == base_addr) { 833 pci_base = i << 20; 834 break; 835 } 836 } 837 if (pci_base == ADDR_ERROR) 838 return pci_base; 839 return pci_base + offset; 840} 841 842static long rom_max_timeout = 100; 843static long qla82xx_rom_lock_timeout = 100; 844 845static int 846qla82xx_rom_lock(struct qla_hw_data *ha) 847{ 848 int done = 0, timeout = 0; 849 850 while (!done) { 851 /* acquire semaphore2 from PCI HW block */ 852 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 853 if (done == 1) 854 break; 855 if (timeout >= qla82xx_rom_lock_timeout) 856 return -1; 857 timeout++; 858 } 859 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 860 return 0; 861} 862 863static void 864qla82xx_rom_unlock(struct qla_hw_data *ha) 865{ 866 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 867} 868 869static int 870qla82xx_wait_rom_busy(struct qla_hw_data *ha) 871{ 872 long timeout = 0; 873 long done = 0 ; 874 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 875 876 while (done == 0) { 877 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 878 done &= 4; 879 timeout++; 880 if (timeout >= rom_max_timeout) { 881 ql_dbg(ql_dbg_p3p, vha, 0xb00a, 882 "%s: Timeout reached waiting for rom busy.\n", 883 QLA2XXX_DRIVER_NAME); 884 return -1; 885 } 886 } 887 return 0; 888} 889 890static int 891qla82xx_wait_rom_done(struct qla_hw_data *ha) 892{ 893 long timeout = 0; 894 long done = 0 ; 895 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 896 897 while (done == 0) { 898 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 899 done &= 2; 900 timeout++; 901 if (timeout >= rom_max_timeout) { 902 ql_dbg(ql_dbg_p3p, vha, 0xb00b, 903 "%s: Timeout reached waiting for rom done.\n", 904 QLA2XXX_DRIVER_NAME); 905 return -1; 906 } 907 } 908 return 0; 909} 910 911int 912qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 913{ 914 uint32_t off_value, rval = 0; 915 916 WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase), 917 (off & 0xFFFF0000)); 918 919 /* Read back value to make sure write has gone through */ 920 RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 921 off_value = (off & 0x0000FFFF); 922 923 if (flag) 924 WRT_REG_DWORD((void *) 925 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 926 data); 927 else 928 rval = RD_REG_DWORD((void *) 929 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 930 931 return rval; 932} 933 934static int 935qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 936{ 937 /* Dword reads to flash. */ 938 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); 939 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + 940 (addr & 0x0000FFFF), 0, 0); 941 942 return 0; 943} 944 945static int 946qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) 947{ 948 int ret, loops = 0; 949 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 950 951 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 952 udelay(100); 953 schedule(); 954 loops++; 955 } 956 if (loops >= 50000) { 957 ql_log(ql_log_fatal, vha, 0x00b9, 958 "Failed to aquire SEM2 lock.\n"); 959 return -1; 960 } 961 ret = qla82xx_do_rom_fast_read(ha, addr, valp); 962 qla82xx_rom_unlock(ha); 963 return ret; 964} 965 966static int 967qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) 968{ 969 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 970 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); 971 qla82xx_wait_rom_busy(ha); 972 if (qla82xx_wait_rom_done(ha)) { 973 ql_log(ql_log_warn, vha, 0xb00c, 974 "Error waiting for rom done.\n"); 975 return -1; 976 } 977 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 978 return 0; 979} 980 981static int 982qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) 983{ 984 long timeout = 0; 985 uint32_t done = 1 ; 986 uint32_t val; 987 int ret = 0; 988 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 989 990 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 991 while ((done != 0) && (ret == 0)) { 992 ret = qla82xx_read_status_reg(ha, &val); 993 done = val & 1; 994 timeout++; 995 udelay(10); 996 cond_resched(); 997 if (timeout >= 50000) { 998 ql_log(ql_log_warn, vha, 0xb00d, 999 "Timeout reached waiting for write finish.\n"); 1000 return -1; 1001 } 1002 } 1003 return ret; 1004} 1005 1006static int 1007qla82xx_flash_set_write_enable(struct qla_hw_data *ha) 1008{ 1009 uint32_t val; 1010 qla82xx_wait_rom_busy(ha); 1011 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 1012 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); 1013 qla82xx_wait_rom_busy(ha); 1014 if (qla82xx_wait_rom_done(ha)) 1015 return -1; 1016 if (qla82xx_read_status_reg(ha, &val) != 0) 1017 return -1; 1018 if ((val & 2) != 2) 1019 return -1; 1020 return 0; 1021} 1022 1023static int 1024qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) 1025{ 1026 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1027 if (qla82xx_flash_set_write_enable(ha)) 1028 return -1; 1029 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); 1030 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); 1031 if (qla82xx_wait_rom_done(ha)) { 1032 ql_log(ql_log_warn, vha, 0xb00e, 1033 "Error waiting for rom done.\n"); 1034 return -1; 1035 } 1036 return qla82xx_flash_wait_write_finish(ha); 1037} 1038 1039static int 1040qla82xx_write_disable_flash(struct qla_hw_data *ha) 1041{ 1042 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1043 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); 1044 if (qla82xx_wait_rom_done(ha)) { 1045 ql_log(ql_log_warn, vha, 0xb00f, 1046 "Error waiting for rom done.\n"); 1047 return -1; 1048 } 1049 return 0; 1050} 1051 1052static int 1053ql82xx_rom_lock_d(struct qla_hw_data *ha) 1054{ 1055 int loops = 0; 1056 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1057 1058 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { 1059 udelay(100); 1060 cond_resched(); 1061 loops++; 1062 } 1063 if (loops >= 50000) { 1064 ql_log(ql_log_warn, vha, 0xb010, 1065 "ROM lock failed.\n"); 1066 return -1; 1067 } 1068 return 0; 1069} 1070 1071static int 1072qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, 1073 uint32_t data) 1074{ 1075 int ret = 0; 1076 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1077 1078 ret = ql82xx_rom_lock_d(ha); 1079 if (ret < 0) { 1080 ql_log(ql_log_warn, vha, 0xb011, 1081 "ROM lock failed.\n"); 1082 return ret; 1083 } 1084 1085 if (qla82xx_flash_set_write_enable(ha)) 1086 goto done_write; 1087 1088 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); 1089 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); 1090 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 1091 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); 1092 qla82xx_wait_rom_busy(ha); 1093 if (qla82xx_wait_rom_done(ha)) { 1094 ql_log(ql_log_warn, vha, 0xb012, 1095 "Error waiting for rom done.\n"); 1096 ret = -1; 1097 goto done_write; 1098 } 1099 1100 ret = qla82xx_flash_wait_write_finish(ha); 1101 1102done_write: 1103 qla82xx_rom_unlock(ha); 1104 return ret; 1105} 1106 1107/* This routine does CRB initialize sequence 1108 * to put the ISP into operational state 1109 */ 1110static int 1111qla82xx_pinit_from_rom(scsi_qla_host_t *vha) 1112{ 1113 int addr, val; 1114 int i ; 1115 struct crb_addr_pair *buf; 1116 unsigned long off; 1117 unsigned offset, n; 1118 struct qla_hw_data *ha = vha->hw; 1119 1120 struct crb_addr_pair { 1121 long addr; 1122 long data; 1123 }; 1124 1125 /* Halt all the indiviual PEGs and other blocks of the ISP */ 1126 qla82xx_rom_lock(ha); 1127 1128 /* disable all I2Q */ 1129 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 1130 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 1131 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1132 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1133 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1134 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1135 1136 /* disable all niu interrupts */ 1137 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1138 /* disable xge rx/tx */ 1139 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1140 /* disable xg1 rx/tx */ 1141 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1142 /* disable sideband mac */ 1143 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1144 /* disable ap0 mac */ 1145 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1146 /* disable ap1 mac */ 1147 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1148 1149 /* halt sre */ 1150 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1151 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1152 1153 /* halt epg */ 1154 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1155 1156 /* halt timers */ 1157 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1158 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1159 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1160 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1161 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1162 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1163 1164 /* halt pegs */ 1165 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1166 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1167 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1168 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1169 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1170 msleep(20); 1171 1172 /* big hammer */ 1173 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 1174 /* don't reset CAM block on reset */ 1175 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1176 else 1177 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1178 qla82xx_rom_unlock(ha); 1179 1180 /* Read the signature value from the flash. 1181 * Offset 0: Contain signature (0xcafecafe) 1182 * Offset 4: Offset and number of addr/value pairs 1183 * that present in CRB initialize sequence 1184 */ 1185 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1186 qla82xx_rom_fast_read(ha, 4, &n) != 0) { 1187 ql_log(ql_log_fatal, vha, 0x006e, 1188 "Error Reading crb_init area: n: %08x.\n", n); 1189 return -1; 1190 } 1191 1192 /* Offset in flash = lower 16 bits 1193 * Number of enteries = upper 16 bits 1194 */ 1195 offset = n & 0xffffU; 1196 n = (n >> 16) & 0xffffU; 1197 1198 /* number of addr/value pair should not exceed 1024 enteries */ 1199 if (n >= 1024) { 1200 ql_log(ql_log_fatal, vha, 0x0071, 1201 "Card flash not initialized:n=0x%x.\n", n); 1202 return -1; 1203 } 1204 1205 ql_log(ql_log_info, vha, 0x0072, 1206 "%d CRB init values found in ROM.\n", n); 1207 1208 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1209 if (buf == NULL) { 1210 ql_log(ql_log_fatal, vha, 0x010c, 1211 "Unable to allocate memory.\n"); 1212 return -1; 1213 } 1214 1215 for (i = 0; i < n; i++) { 1216 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1217 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { 1218 kfree(buf); 1219 return -1; 1220 } 1221 1222 buf[i].addr = addr; 1223 buf[i].data = val; 1224 } 1225 1226 for (i = 0; i < n; i++) { 1227 /* Translate internal CRB initialization 1228 * address to PCI bus address 1229 */ 1230 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1231 QLA82XX_PCI_CRBSPACE; 1232 /* Not all CRB addr/value pair to be written, 1233 * some of them are skipped 1234 */ 1235 1236 /* skipping cold reboot MAGIC */ 1237 if (off == QLA82XX_CAM_RAM(0x1fc)) 1238 continue; 1239 1240 /* do not reset PCI */ 1241 if (off == (ROMUSB_GLB + 0xbc)) 1242 continue; 1243 1244 /* skip core clock, so that firmware can increase the clock */ 1245 if (off == (ROMUSB_GLB + 0xc8)) 1246 continue; 1247 1248 /* skip the function enable register */ 1249 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1250 continue; 1251 1252 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1253 continue; 1254 1255 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1256 continue; 1257 1258 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1259 continue; 1260 1261 if (off == ADDR_ERROR) { 1262 ql_log(ql_log_fatal, vha, 0x0116, 1263 "Unknow addr: 0x%08lx.\n", buf[i].addr); 1264 continue; 1265 } 1266 1267 qla82xx_wr_32(ha, off, buf[i].data); 1268 1269 /* ISP requires much bigger delay to settle down, 1270 * else crb_window returns 0xffffffff 1271 */ 1272 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1273 msleep(1000); 1274 1275 /* ISP requires millisec delay between 1276 * successive CRB register updation 1277 */ 1278 msleep(1); 1279 } 1280 1281 kfree(buf); 1282 1283 /* Resetting the data and instruction cache */ 1284 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1285 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1286 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1287 1288 /* Clear all protocol processing engines */ 1289 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1290 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1291 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1292 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1293 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1294 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1295 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1296 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1297 return 0; 1298} 1299 1300static int 1301qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, 1302 u64 off, void *data, int size) 1303{ 1304 int i, j, ret = 0, loop, sz[2], off0; 1305 int scale, shift_amount, startword; 1306 uint32_t temp; 1307 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1308 1309 /* 1310 * If not MN, go check for MS or invalid. 1311 */ 1312 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1313 mem_crb = QLA82XX_CRB_QDR_NET; 1314 else { 1315 mem_crb = QLA82XX_CRB_DDR_NET; 1316 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1317 return qla82xx_pci_mem_write_direct(ha, 1318 off, data, size); 1319 } 1320 1321 off0 = off & 0x7; 1322 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1323 sz[1] = size - sz[0]; 1324 1325 off8 = off & 0xfffffff0; 1326 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1327 shift_amount = 4; 1328 scale = 2; 1329 startword = (off & 0xf)/8; 1330 1331 for (i = 0; i < loop; i++) { 1332 if (qla82xx_pci_mem_read_2M(ha, off8 + 1333 (i << shift_amount), &word[i * scale], 8)) 1334 return -1; 1335 } 1336 1337 switch (size) { 1338 case 1: 1339 tmpw = *((uint8_t *)data); 1340 break; 1341 case 2: 1342 tmpw = *((uint16_t *)data); 1343 break; 1344 case 4: 1345 tmpw = *((uint32_t *)data); 1346 break; 1347 case 8: 1348 default: 1349 tmpw = *((uint64_t *)data); 1350 break; 1351 } 1352 1353 if (sz[0] == 8) { 1354 word[startword] = tmpw; 1355 } else { 1356 word[startword] &= 1357 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1358 word[startword] |= tmpw << (off0 * 8); 1359 } 1360 if (sz[1] != 0) { 1361 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1362 word[startword+1] |= tmpw >> (sz[0] * 8); 1363 } 1364 1365 for (i = 0; i < loop; i++) { 1366 temp = off8 + (i << shift_amount); 1367 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1368 temp = 0; 1369 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1370 temp = word[i * scale] & 0xffffffff; 1371 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1372 temp = (word[i * scale] >> 32) & 0xffffffff; 1373 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1374 temp = word[i*scale + 1] & 0xffffffff; 1375 qla82xx_wr_32(ha, mem_crb + 1376 MIU_TEST_AGT_WRDATA_UPPER_LO, temp); 1377 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1378 qla82xx_wr_32(ha, mem_crb + 1379 MIU_TEST_AGT_WRDATA_UPPER_HI, temp); 1380 1381 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1382 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1383 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1384 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1385 1386 for (j = 0; j < MAX_CTL_CHECK; j++) { 1387 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1388 if ((temp & MIU_TA_CTL_BUSY) == 0) 1389 break; 1390 } 1391 1392 if (j >= MAX_CTL_CHECK) { 1393 if (printk_ratelimit()) 1394 dev_err(&ha->pdev->dev, 1395 "failed to write through agent.\n"); 1396 ret = -1; 1397 break; 1398 } 1399 } 1400 1401 return ret; 1402} 1403 1404static int 1405qla82xx_fw_load_from_flash(struct qla_hw_data *ha) 1406{ 1407 int i; 1408 long size = 0; 1409 long flashaddr = ha->flt_region_bootload << 2; 1410 long memaddr = BOOTLD_START; 1411 u64 data; 1412 u32 high, low; 1413 size = (IMAGE_START - BOOTLD_START) / 8; 1414 1415 for (i = 0; i < size; i++) { 1416 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1417 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { 1418 return -1; 1419 } 1420 data = ((u64)high << 32) | low ; 1421 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 1422 flashaddr += 8; 1423 memaddr += 8; 1424 1425 if (i % 0x1000 == 0) 1426 msleep(1); 1427 } 1428 udelay(100); 1429 read_lock(&ha->hw_lock); 1430 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1431 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1432 read_unlock(&ha->hw_lock); 1433 return 0; 1434} 1435 1436int 1437qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, 1438 u64 off, void *data, int size) 1439{ 1440 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1441 int shift_amount; 1442 uint32_t temp; 1443 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1444 1445 /* 1446 * If not MN, go check for MS or invalid. 1447 */ 1448 1449 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1450 mem_crb = QLA82XX_CRB_QDR_NET; 1451 else { 1452 mem_crb = QLA82XX_CRB_DDR_NET; 1453 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) 1454 return qla82xx_pci_mem_read_direct(ha, 1455 off, data, size); 1456 } 1457 1458 off8 = off & 0xfffffff0; 1459 off0[0] = off & 0xf; 1460 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1461 shift_amount = 4; 1462 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1463 off0[1] = 0; 1464 sz[1] = size - sz[0]; 1465 1466 for (i = 0; i < loop; i++) { 1467 temp = off8 + (i << shift_amount); 1468 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1469 temp = 0; 1470 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1471 temp = MIU_TA_CTL_ENABLE; 1472 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1473 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1474 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1475 1476 for (j = 0; j < MAX_CTL_CHECK; j++) { 1477 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1478 if ((temp & MIU_TA_CTL_BUSY) == 0) 1479 break; 1480 } 1481 1482 if (j >= MAX_CTL_CHECK) { 1483 if (printk_ratelimit()) 1484 dev_err(&ha->pdev->dev, 1485 "failed to read through agent.\n"); 1486 break; 1487 } 1488 1489 start = off0[i] >> 2; 1490 end = (off0[i] + sz[i] - 1) >> 2; 1491 for (k = start; k <= end; k++) { 1492 temp = qla82xx_rd_32(ha, 1493 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1494 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1495 } 1496 } 1497 1498 if (j >= MAX_CTL_CHECK) 1499 return -1; 1500 1501 if ((off0[0] & 7) == 0) { 1502 val = word[0]; 1503 } else { 1504 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1505 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1506 } 1507 1508 switch (size) { 1509 case 1: 1510 *(uint8_t *)data = val; 1511 break; 1512 case 2: 1513 *(uint16_t *)data = val; 1514 break; 1515 case 4: 1516 *(uint32_t *)data = val; 1517 break; 1518 case 8: 1519 *(uint64_t *)data = val; 1520 break; 1521 } 1522 return 0; 1523} 1524 1525 1526static struct qla82xx_uri_table_desc * 1527qla82xx_get_table_desc(const u8 *unirom, int section) 1528{ 1529 uint32_t i; 1530 struct qla82xx_uri_table_desc *directory = 1531 (struct qla82xx_uri_table_desc *)&unirom[0]; 1532 __le32 offset; 1533 __le32 tab_type; 1534 __le32 entries = cpu_to_le32(directory->num_entries); 1535 1536 for (i = 0; i < entries; i++) { 1537 offset = cpu_to_le32(directory->findex) + 1538 (i * cpu_to_le32(directory->entry_size)); 1539 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); 1540 1541 if (tab_type == section) 1542 return (struct qla82xx_uri_table_desc *)&unirom[offset]; 1543 } 1544 1545 return NULL; 1546} 1547 1548static struct qla82xx_uri_data_desc * 1549qla82xx_get_data_desc(struct qla_hw_data *ha, 1550 u32 section, u32 idx_offset) 1551{ 1552 const u8 *unirom = ha->hablob->fw->data; 1553 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); 1554 struct qla82xx_uri_table_desc *tab_desc = NULL; 1555 __le32 offset; 1556 1557 tab_desc = qla82xx_get_table_desc(unirom, section); 1558 if (!tab_desc) 1559 return NULL; 1560 1561 offset = cpu_to_le32(tab_desc->findex) + 1562 (cpu_to_le32(tab_desc->entry_size) * idx); 1563 1564 return (struct qla82xx_uri_data_desc *)&unirom[offset]; 1565} 1566 1567static u8 * 1568qla82xx_get_bootld_offset(struct qla_hw_data *ha) 1569{ 1570 u32 offset = BOOTLD_START; 1571 struct qla82xx_uri_data_desc *uri_desc = NULL; 1572 1573 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1574 uri_desc = qla82xx_get_data_desc(ha, 1575 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); 1576 if (uri_desc) 1577 offset = cpu_to_le32(uri_desc->findex); 1578 } 1579 1580 return (u8 *)&ha->hablob->fw->data[offset]; 1581} 1582 1583static __le32 1584qla82xx_get_fw_size(struct qla_hw_data *ha) 1585{ 1586 struct qla82xx_uri_data_desc *uri_desc = NULL; 1587 1588 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1589 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1590 QLA82XX_URI_FIRMWARE_IDX_OFF); 1591 if (uri_desc) 1592 return cpu_to_le32(uri_desc->size); 1593 } 1594 1595 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); 1596} 1597 1598static u8 * 1599qla82xx_get_fw_offs(struct qla_hw_data *ha) 1600{ 1601 u32 offset = IMAGE_START; 1602 struct qla82xx_uri_data_desc *uri_desc = NULL; 1603 1604 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1605 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, 1606 QLA82XX_URI_FIRMWARE_IDX_OFF); 1607 if (uri_desc) 1608 offset = cpu_to_le32(uri_desc->findex); 1609 } 1610 1611 return (u8 *)&ha->hablob->fw->data[offset]; 1612} 1613 1614/* PCI related functions */ 1615char * 1616qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) 1617{ 1618 int pcie_reg; 1619 struct qla_hw_data *ha = vha->hw; 1620 char lwstr[6]; 1621 uint16_t lnk; 1622 1623 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1624 pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); 1625 ha->link_width = (lnk >> 4) & 0x3f; 1626 1627 strcpy(str, "PCIe ("); 1628 strcat(str, "2.5Gb/s "); 1629 snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); 1630 strcat(str, lwstr); 1631 return str; 1632} 1633 1634int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) 1635{ 1636 unsigned long val = 0; 1637 u32 control; 1638 1639 switch (region) { 1640 case 0: 1641 val = 0; 1642 break; 1643 case 1: 1644 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); 1645 val = control + QLA82XX_MSIX_TBL_SPACE; 1646 break; 1647 } 1648 return val; 1649} 1650 1651 1652int 1653qla82xx_iospace_config(struct qla_hw_data *ha) 1654{ 1655 uint32_t len = 0; 1656 1657 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { 1658 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, 1659 "Failed to reserver selected regions.\n"); 1660 goto iospace_error_exit; 1661 } 1662 1663 /* Use MMIO operations for all accesses. */ 1664 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 1665 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, 1666 "Region #0 not an MMIO resource, aborting.\n"); 1667 goto iospace_error_exit; 1668 } 1669 1670 len = pci_resource_len(ha->pdev, 0); 1671 ha->nx_pcibase = 1672 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); 1673 if (!ha->nx_pcibase) { 1674 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1675 "Cannot remap pcibase MMIO, aborting.\n"); 1676 pci_release_regions(ha->pdev); 1677 goto iospace_error_exit; 1678 } 1679 1680 /* Mapping of IO base pointer */ 1681 ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + 1682 0xbc000 + (ha->pdev->devfn << 11)); 1683 1684 if (!ql2xdbwr) { 1685 ha->nxdb_wr_ptr = 1686 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + 1687 (ha->pdev->devfn << 12)), 4); 1688 if (!ha->nxdb_wr_ptr) { 1689 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1690 "Cannot remap MMIO, aborting.\n"); 1691 pci_release_regions(ha->pdev); 1692 goto iospace_error_exit; 1693 } 1694 1695 /* Mapping of IO base pointer, 1696 * door bell read and write pointer 1697 */ 1698 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1699 (ha->pdev->devfn * 8); 1700 } else { 1701 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1702 QLA82XX_CAMRAM_DB1 : 1703 QLA82XX_CAMRAM_DB2); 1704 } 1705 1706 ha->max_req_queues = ha->max_rsp_queues = 1; 1707 ha->msix_count = ha->max_rsp_queues + 1; 1708 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1709 "nx_pci_base=%p iobase=%p " 1710 "max_req_queues=%d msix_count=%d.\n", 1711 (void *)ha->nx_pcibase, ha->iobase, 1712 ha->max_req_queues, ha->msix_count); 1713 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1714 "nx_pci_base=%p iobase=%p " 1715 "max_req_queues=%d msix_count=%d.\n", 1716 (void *)ha->nx_pcibase, ha->iobase, 1717 ha->max_req_queues, ha->msix_count); 1718 return 0; 1719 1720iospace_error_exit: 1721 return -ENOMEM; 1722} 1723 1724/* GS related functions */ 1725 1726/* Initialization related functions */ 1727 1728/** 1729 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. 1730 * @ha: HA context 1731 * 1732 * Returns 0 on success. 1733*/ 1734int 1735qla82xx_pci_config(scsi_qla_host_t *vha) 1736{ 1737 struct qla_hw_data *ha = vha->hw; 1738 int ret; 1739 1740 pci_set_master(ha->pdev); 1741 ret = pci_set_mwi(ha->pdev); 1742 ha->chip_revision = ha->pdev->revision; 1743 ql_dbg(ql_dbg_init, vha, 0x0043, 1744 "Chip revision:%d.\n", 1745 ha->chip_revision); 1746 return 0; 1747} 1748 1749/** 1750 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. 1751 * @ha: HA context 1752 * 1753 * Returns 0 on success. 1754 */ 1755void 1756qla82xx_reset_chip(scsi_qla_host_t *vha) 1757{ 1758 struct qla_hw_data *ha = vha->hw; 1759 ha->isp_ops->disable_intrs(ha); 1760} 1761 1762void qla82xx_config_rings(struct scsi_qla_host *vha) 1763{ 1764 struct qla_hw_data *ha = vha->hw; 1765 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 1766 struct init_cb_81xx *icb; 1767 struct req_que *req = ha->req_q_map[0]; 1768 struct rsp_que *rsp = ha->rsp_q_map[0]; 1769 1770 /* Setup ring parameters in initialization control block. */ 1771 icb = (struct init_cb_81xx *)ha->init_cb; 1772 icb->request_q_outpointer = __constant_cpu_to_le16(0); 1773 icb->response_q_inpointer = __constant_cpu_to_le16(0); 1774 icb->request_q_length = cpu_to_le16(req->length); 1775 icb->response_q_length = cpu_to_le16(rsp->length); 1776 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1777 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1778 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1779 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1780 1781 WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); 1782 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); 1783 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); 1784} 1785 1786void qla82xx_reset_adapter(struct scsi_qla_host *vha) 1787{ 1788 struct qla_hw_data *ha = vha->hw; 1789 vha->flags.online = 0; 1790 qla2x00_try_to_stop_firmware(vha); 1791 ha->isp_ops->disable_intrs(ha); 1792} 1793 1794static int 1795qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1796{ 1797 u64 *ptr64; 1798 u32 i, flashaddr, size; 1799 __le64 data; 1800 1801 size = (IMAGE_START - BOOTLD_START) / 8; 1802 1803 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); 1804 flashaddr = BOOTLD_START; 1805 1806 for (i = 0; i < size; i++) { 1807 data = cpu_to_le64(ptr64[i]); 1808 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1809 return -EIO; 1810 flashaddr += 8; 1811 } 1812 1813 flashaddr = FLASH_ADDR_START; 1814 size = (__force u32)qla82xx_get_fw_size(ha) / 8; 1815 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); 1816 1817 for (i = 0; i < size; i++) { 1818 data = cpu_to_le64(ptr64[i]); 1819 1820 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) 1821 return -EIO; 1822 flashaddr += 8; 1823 } 1824 udelay(100); 1825 1826 /* Write a magic value to CAMRAM register 1827 * at a specified offset to indicate 1828 * that all data is written and 1829 * ready for firmware to initialize. 1830 */ 1831 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); 1832 1833 read_lock(&ha->hw_lock); 1834 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1835 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1836 read_unlock(&ha->hw_lock); 1837 return 0; 1838} 1839 1840static int 1841qla82xx_set_product_offset(struct qla_hw_data *ha) 1842{ 1843 struct qla82xx_uri_table_desc *ptab_desc = NULL; 1844 const uint8_t *unirom = ha->hablob->fw->data; 1845 uint32_t i; 1846 __le32 entries; 1847 __le32 flags, file_chiprev, offset; 1848 uint8_t chiprev = ha->chip_revision; 1849 /* Hardcoding mn_present flag for P3P */ 1850 int mn_present = 0; 1851 uint32_t flagbit; 1852 1853 ptab_desc = qla82xx_get_table_desc(unirom, 1854 QLA82XX_URI_DIR_SECT_PRODUCT_TBL); 1855 if (!ptab_desc) 1856 return -1; 1857 1858 entries = cpu_to_le32(ptab_desc->num_entries); 1859 1860 for (i = 0; i < entries; i++) { 1861 offset = cpu_to_le32(ptab_desc->findex) + 1862 (i * cpu_to_le32(ptab_desc->entry_size)); 1863 flags = cpu_to_le32(*((int *)&unirom[offset] + 1864 QLA82XX_URI_FLAGS_OFF)); 1865 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + 1866 QLA82XX_URI_CHIP_REV_OFF)); 1867 1868 flagbit = mn_present ? 1 : 2; 1869 1870 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { 1871 ha->file_prd_off = offset; 1872 return 0; 1873 } 1874 } 1875 return -1; 1876} 1877 1878int 1879qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1880{ 1881 __le32 val; 1882 uint32_t min_size; 1883 struct qla_hw_data *ha = vha->hw; 1884 const struct firmware *fw = ha->hablob->fw; 1885 1886 ha->fw_type = fw_type; 1887 1888 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { 1889 if (qla82xx_set_product_offset(ha)) 1890 return -EINVAL; 1891 1892 min_size = QLA82XX_URI_FW_MIN_SIZE; 1893 } else { 1894 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); 1895 if ((__force u32)val != QLA82XX_BDINFO_MAGIC) 1896 return -EINVAL; 1897 1898 min_size = QLA82XX_FW_MIN_SIZE; 1899 } 1900 1901 if (fw->size < min_size) 1902 return -EINVAL; 1903 return 0; 1904} 1905 1906static int 1907qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) 1908{ 1909 u32 val = 0; 1910 int retries = 60; 1911 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1912 1913 do { 1914 read_lock(&ha->hw_lock); 1915 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); 1916 read_unlock(&ha->hw_lock); 1917 1918 switch (val) { 1919 case PHAN_INITIALIZE_COMPLETE: 1920 case PHAN_INITIALIZE_ACK: 1921 return QLA_SUCCESS; 1922 case PHAN_INITIALIZE_FAILED: 1923 break; 1924 default: 1925 break; 1926 } 1927 ql_log(ql_log_info, vha, 0x00a8, 1928 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", 1929 val, retries); 1930 1931 msleep(500); 1932 1933 } while (--retries); 1934 1935 ql_log(ql_log_fatal, vha, 0x00a9, 1936 "Cmd Peg initialization failed: 0x%x.\n", val); 1937 1938 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1939 read_lock(&ha->hw_lock); 1940 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); 1941 read_unlock(&ha->hw_lock); 1942 return QLA_FUNCTION_FAILED; 1943} 1944 1945static int 1946qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) 1947{ 1948 u32 val = 0; 1949 int retries = 60; 1950 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 1951 1952 do { 1953 read_lock(&ha->hw_lock); 1954 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); 1955 read_unlock(&ha->hw_lock); 1956 1957 switch (val) { 1958 case PHAN_INITIALIZE_COMPLETE: 1959 case PHAN_INITIALIZE_ACK: 1960 return QLA_SUCCESS; 1961 case PHAN_INITIALIZE_FAILED: 1962 break; 1963 default: 1964 break; 1965 } 1966 ql_log(ql_log_info, vha, 0x00ab, 1967 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", 1968 val, retries); 1969 1970 msleep(500); 1971 1972 } while (--retries); 1973 1974 ql_log(ql_log_fatal, vha, 0x00ac, 1975 "Rcv Peg initializatin failed: 0x%x.\n", val); 1976 read_lock(&ha->hw_lock); 1977 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); 1978 read_unlock(&ha->hw_lock); 1979 return QLA_FUNCTION_FAILED; 1980} 1981 1982/* ISR related functions */ 1983uint32_t qla82xx_isr_int_target_mask_enable[8] = { 1984 ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, 1985 ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, 1986 ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, 1987 ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 1988}; 1989 1990uint32_t qla82xx_isr_int_target_status[8] = { 1991 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, 1992 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, 1993 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, 1994 ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 1995}; 1996 1997static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1998 QLA82XX_LEGACY_INTR_CONFIG; 1999 2000/* 2001 * qla82xx_mbx_completion() - Process mailbox command completions. 2002 * @ha: SCSI driver HA context 2003 * @mb0: Mailbox0 register 2004 */ 2005static void 2006qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) 2007{ 2008 uint16_t cnt; 2009 uint16_t __iomem *wptr; 2010 struct qla_hw_data *ha = vha->hw; 2011 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; 2012 wptr = (uint16_t __iomem *)®->mailbox_out[1]; 2013 2014 /* Load return mailbox registers. */ 2015 ha->flags.mbox_int = 1; 2016 ha->mailbox_out[0] = mb0; 2017 2018 for (cnt = 1; cnt < ha->mbx_count; cnt++) { 2019 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 2020 wptr++; 2021 } 2022 2023 if (!ha->mcp) 2024 ql_dbg(ql_dbg_async, vha, 0x5053, 2025 "MBX pointer ERROR.\n"); 2026} 2027 2028/* 2029 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. 2030 * @irq: 2031 * @dev_id: SCSI driver HA context 2032 * @regs: 2033 * 2034 * Called by system whenever the host adapter generates an interrupt. 2035 * 2036 * Returns handled flag. 2037 */ 2038irqreturn_t 2039qla82xx_intr_handler(int irq, void *dev_id) 2040{ 2041 scsi_qla_host_t *vha; 2042 struct qla_hw_data *ha; 2043 struct rsp_que *rsp; 2044 struct device_reg_82xx __iomem *reg; 2045 int status = 0, status1 = 0; 2046 unsigned long flags; 2047 unsigned long iter; 2048 uint32_t stat = 0; 2049 uint16_t mb[4]; 2050 2051 rsp = (struct rsp_que *) dev_id; 2052 if (!rsp) { 2053 ql_log(ql_log_info, NULL, 0xb054, 2054 "%s: NULL response queue pointer.\n", __func__); 2055 return IRQ_NONE; 2056 } 2057 ha = rsp->hw; 2058 2059 if (!ha->flags.msi_enabled) { 2060 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); 2061 if (!(status & ha->nx_legacy_intr.int_vec_bit)) 2062 return IRQ_NONE; 2063 2064 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); 2065 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) 2066 return IRQ_NONE; 2067 } 2068 2069 /* clear the interrupt */ 2070 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); 2071 2072 /* read twice to ensure write is flushed */ 2073 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2074 qla82xx_rd_32(ha, ISR_INT_VECTOR); 2075 2076 reg = &ha->iobase->isp82; 2077 2078 spin_lock_irqsave(&ha->hardware_lock, flags); 2079 vha = pci_get_drvdata(ha->pdev); 2080 for (iter = 1; iter--; ) { 2081 2082 if (RD_REG_DWORD(®->host_int)) { 2083 stat = RD_REG_DWORD(®->host_status); 2084 2085 switch (stat & 0xff) { 2086 case 0x1: 2087 case 0x2: 2088 case 0x10: 2089 case 0x11: 2090 qla82xx_mbx_completion(vha, MSW(stat)); 2091 status |= MBX_INTERRUPT; 2092 break; 2093 case 0x12: 2094 mb[0] = MSW(stat); 2095 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2096 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2097 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2098 qla2x00_async_event(vha, rsp, mb); 2099 break; 2100 case 0x13: 2101 qla24xx_process_response_queue(vha, rsp); 2102 break; 2103 default: 2104 ql_dbg(ql_dbg_async, vha, 0x5054, 2105 "Unrecognized interrupt type (%d).\n", 2106 stat & 0xff); 2107 break; 2108 } 2109 } 2110 WRT_REG_DWORD(®->host_int, 0); 2111 } 2112 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2113 if (!ha->flags.msi_enabled) 2114 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2115 2116#ifdef QL_DEBUG_LEVEL_17 2117 if (!irq && ha->flags.eeh_busy) 2118 ql_log(ql_log_warn, vha, 0x503d, 2119 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2120 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2121#endif 2122 2123 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2124 (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2125 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2126 complete(&ha->mbx_intr_comp); 2127 } 2128 return IRQ_HANDLED; 2129} 2130 2131irqreturn_t 2132qla82xx_msix_default(int irq, void *dev_id) 2133{ 2134 scsi_qla_host_t *vha; 2135 struct qla_hw_data *ha; 2136 struct rsp_que *rsp; 2137 struct device_reg_82xx __iomem *reg; 2138 int status = 0; 2139 unsigned long flags; 2140 uint32_t stat = 0; 2141 uint16_t mb[4]; 2142 2143 rsp = (struct rsp_que *) dev_id; 2144 if (!rsp) { 2145 printk(KERN_INFO 2146 "%s(): NULL response queue pointer.\n", __func__); 2147 return IRQ_NONE; 2148 } 2149 ha = rsp->hw; 2150 2151 reg = &ha->iobase->isp82; 2152 2153 spin_lock_irqsave(&ha->hardware_lock, flags); 2154 vha = pci_get_drvdata(ha->pdev); 2155 do { 2156 if (RD_REG_DWORD(®->host_int)) { 2157 stat = RD_REG_DWORD(®->host_status); 2158 2159 switch (stat & 0xff) { 2160 case 0x1: 2161 case 0x2: 2162 case 0x10: 2163 case 0x11: 2164 qla82xx_mbx_completion(vha, MSW(stat)); 2165 status |= MBX_INTERRUPT; 2166 break; 2167 case 0x12: 2168 mb[0] = MSW(stat); 2169 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2170 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2171 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2172 qla2x00_async_event(vha, rsp, mb); 2173 break; 2174 case 0x13: 2175 qla24xx_process_response_queue(vha, rsp); 2176 break; 2177 default: 2178 ql_dbg(ql_dbg_async, vha, 0x5041, 2179 "Unrecognized interrupt type (%d).\n", 2180 stat & 0xff); 2181 break; 2182 } 2183 } 2184 WRT_REG_DWORD(®->host_int, 0); 2185 } while (0); 2186 2187 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2188 2189#ifdef QL_DEBUG_LEVEL_17 2190 if (!irq && ha->flags.eeh_busy) 2191 ql_log(ql_log_warn, vha, 0x5044, 2192 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", 2193 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); 2194#endif 2195 2196 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && 2197 (status & MBX_INTERRUPT) && ha->flags.mbox_int) { 2198 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 2199 complete(&ha->mbx_intr_comp); 2200 } 2201 return IRQ_HANDLED; 2202} 2203 2204irqreturn_t 2205qla82xx_msix_rsp_q(int irq, void *dev_id) 2206{ 2207 scsi_qla_host_t *vha; 2208 struct qla_hw_data *ha; 2209 struct rsp_que *rsp; 2210 struct device_reg_82xx __iomem *reg; 2211 unsigned long flags; 2212 2213 rsp = (struct rsp_que *) dev_id; 2214 if (!rsp) { 2215 printk(KERN_INFO 2216 "%s(): NULL response queue pointer.\n", __func__); 2217 return IRQ_NONE; 2218 } 2219 2220 ha = rsp->hw; 2221 reg = &ha->iobase->isp82; 2222 spin_lock_irqsave(&ha->hardware_lock, flags); 2223 vha = pci_get_drvdata(ha->pdev); 2224 qla24xx_process_response_queue(vha, rsp); 2225 WRT_REG_DWORD(®->host_int, 0); 2226 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2227 return IRQ_HANDLED; 2228} 2229 2230void 2231qla82xx_poll(int irq, void *dev_id) 2232{ 2233 scsi_qla_host_t *vha; 2234 struct qla_hw_data *ha; 2235 struct rsp_que *rsp; 2236 struct device_reg_82xx __iomem *reg; 2237 int status = 0; 2238 uint32_t stat; 2239 uint16_t mb[4]; 2240 unsigned long flags; 2241 2242 rsp = (struct rsp_que *) dev_id; 2243 if (!rsp) { 2244 printk(KERN_INFO 2245 "%s(): NULL response queue pointer.\n", __func__); 2246 return; 2247 } 2248 ha = rsp->hw; 2249 2250 reg = &ha->iobase->isp82; 2251 spin_lock_irqsave(&ha->hardware_lock, flags); 2252 vha = pci_get_drvdata(ha->pdev); 2253 2254 if (RD_REG_DWORD(®->host_int)) { 2255 stat = RD_REG_DWORD(®->host_status); 2256 switch (stat & 0xff) { 2257 case 0x1: 2258 case 0x2: 2259 case 0x10: 2260 case 0x11: 2261 qla82xx_mbx_completion(vha, MSW(stat)); 2262 status |= MBX_INTERRUPT; 2263 break; 2264 case 0x12: 2265 mb[0] = MSW(stat); 2266 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 2267 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 2268 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 2269 qla2x00_async_event(vha, rsp, mb); 2270 break; 2271 case 0x13: 2272 qla24xx_process_response_queue(vha, rsp); 2273 break; 2274 default: 2275 ql_dbg(ql_dbg_p3p, vha, 0xb013, 2276 "Unrecognized interrupt type (%d).\n", 2277 stat * 0xff); 2278 break; 2279 } 2280 } 2281 WRT_REG_DWORD(®->host_int, 0); 2282 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2283} 2284 2285void 2286qla82xx_enable_intrs(struct qla_hw_data *ha) 2287{ 2288 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2289 qla82xx_mbx_intr_enable(vha); 2290 spin_lock_irq(&ha->hardware_lock); 2291 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2292 spin_unlock_irq(&ha->hardware_lock); 2293 ha->interrupts_on = 1; 2294} 2295 2296void 2297qla82xx_disable_intrs(struct qla_hw_data *ha) 2298{ 2299 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2300 qla82xx_mbx_intr_disable(vha); 2301 spin_lock_irq(&ha->hardware_lock); 2302 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2303 spin_unlock_irq(&ha->hardware_lock); 2304 ha->interrupts_on = 0; 2305} 2306 2307void qla82xx_init_flags(struct qla_hw_data *ha) 2308{ 2309 struct qla82xx_legacy_intr_set *nx_legacy_intr; 2310 2311 /* ISP 8021 initializations */ 2312 rwlock_init(&ha->hw_lock); 2313 ha->qdr_sn_window = -1; 2314 ha->ddr_mn_window = -1; 2315 ha->curr_window = 255; 2316 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2317 nx_legacy_intr = &legacy_intr[ha->portnum]; 2318 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; 2319 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; 2320 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; 2321 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; 2322} 2323 2324inline void 2325qla82xx_set_drv_active(scsi_qla_host_t *vha) 2326{ 2327 uint32_t drv_active; 2328 struct qla_hw_data *ha = vha->hw; 2329 2330 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2331 2332 /* If reset value is all FF's, initialize DRV_ACTIVE */ 2333 if (drv_active == 0xffffffff) { 2334 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 2335 QLA82XX_DRV_NOT_ACTIVE); 2336 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2337 } 2338 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2339 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2340} 2341 2342inline void 2343qla82xx_clear_drv_active(struct qla_hw_data *ha) 2344{ 2345 uint32_t drv_active; 2346 2347 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2348 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 2349 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 2350} 2351 2352static inline int 2353qla82xx_need_reset(struct qla_hw_data *ha) 2354{ 2355 uint32_t drv_state; 2356 int rval; 2357 2358 if (ha->flags.isp82xx_reset_owner) 2359 return 1; 2360 else { 2361 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2362 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2363 return rval; 2364 } 2365} 2366 2367static inline void 2368qla82xx_set_rst_ready(struct qla_hw_data *ha) 2369{ 2370 uint32_t drv_state; 2371 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2372 2373 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2374 2375 /* If reset value is all FF's, initialize DRV_STATE */ 2376 if (drv_state == 0xffffffff) { 2377 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); 2378 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2379 } 2380 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2381 ql_dbg(ql_dbg_init, vha, 0x00bb, 2382 "drv_state = 0x%08x.\n", drv_state); 2383 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2384} 2385 2386static inline void 2387qla82xx_clear_rst_ready(struct qla_hw_data *ha) 2388{ 2389 uint32_t drv_state; 2390 2391 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2392 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); 2393 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 2394} 2395 2396static inline void 2397qla82xx_set_qsnt_ready(struct qla_hw_data *ha) 2398{ 2399 uint32_t qsnt_state; 2400 2401 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2402 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2403 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2404} 2405 2406void 2407qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) 2408{ 2409 struct qla_hw_data *ha = vha->hw; 2410 uint32_t qsnt_state; 2411 2412 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2413 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); 2414 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 2415} 2416 2417static int 2418qla82xx_load_fw(scsi_qla_host_t *vha) 2419{ 2420 int rst; 2421 struct fw_blob *blob; 2422 struct qla_hw_data *ha = vha->hw; 2423 2424 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { 2425 ql_log(ql_log_fatal, vha, 0x009f, 2426 "Error during CRB initialization.\n"); 2427 return QLA_FUNCTION_FAILED; 2428 } 2429 udelay(500); 2430 2431 /* Bring QM and CAMRAM out of reset */ 2432 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 2433 rst &= ~((1 << 28) | (1 << 24)); 2434 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 2435 2436 /* 2437 * FW Load priority: 2438 * 1) Operational firmware residing in flash. 2439 * 2) Firmware via request-firmware interface (.bin file). 2440 */ 2441 if (ql2xfwloadbin == 2) 2442 goto try_blob_fw; 2443 2444 ql_log(ql_log_info, vha, 0x00a0, 2445 "Attempting to load firmware from flash.\n"); 2446 2447 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { 2448 ql_log(ql_log_info, vha, 0x00a1, 2449 "Firmware loaded successully from flash.\n"); 2450 return QLA_SUCCESS; 2451 } else { 2452 ql_log(ql_log_warn, vha, 0x0108, 2453 "Firmware load from flash failed.\n"); 2454 } 2455 2456try_blob_fw: 2457 ql_log(ql_log_info, vha, 0x00a2, 2458 "Attempting to load firmware from blob.\n"); 2459 2460 /* Load firmware blob. */ 2461 blob = ha->hablob = qla2x00_request_firmware(vha); 2462 if (!blob) { 2463 ql_log(ql_log_fatal, vha, 0x00a3, 2464 "Firmware image not preset.\n"); 2465 goto fw_load_failed; 2466 } 2467 2468 /* Validating firmware blob */ 2469 if (qla82xx_validate_firmware_blob(vha, 2470 QLA82XX_FLASH_ROMIMAGE)) { 2471 /* Fallback to URI format */ 2472 if (qla82xx_validate_firmware_blob(vha, 2473 QLA82XX_UNIFIED_ROMIMAGE)) { 2474 ql_log(ql_log_fatal, vha, 0x00a4, 2475 "No valid firmware image found.\n"); 2476 return QLA_FUNCTION_FAILED; 2477 } 2478 } 2479 2480 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { 2481 ql_log(ql_log_info, vha, 0x00a5, 2482 "Firmware loaded successfully from binary blob.\n"); 2483 return QLA_SUCCESS; 2484 } else { 2485 ql_log(ql_log_fatal, vha, 0x00a6, 2486 "Firmware load failed for binary blob.\n"); 2487 blob->fw = NULL; 2488 blob = NULL; 2489 goto fw_load_failed; 2490 } 2491 return QLA_SUCCESS; 2492 2493fw_load_failed: 2494 return QLA_FUNCTION_FAILED; 2495} 2496 2497int 2498qla82xx_start_firmware(scsi_qla_host_t *vha) 2499{ 2500 int pcie_cap; 2501 uint16_t lnk; 2502 struct qla_hw_data *ha = vha->hw; 2503 2504 /* scrub dma mask expansion register */ 2505 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); 2506 2507 /* Put both the PEG CMD and RCV PEG to default state 2508 * of 0 before resetting the hardware 2509 */ 2510 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 2511 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 2512 2513 /* Overwrite stale initialization register values */ 2514 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 2515 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 2516 2517 if (qla82xx_load_fw(vha) != QLA_SUCCESS) { 2518 ql_log(ql_log_fatal, vha, 0x00a7, 2519 "Error trying to start fw.\n"); 2520 return QLA_FUNCTION_FAILED; 2521 } 2522 2523 /* Handshake with the card before we register the devices. */ 2524 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { 2525 ql_log(ql_log_fatal, vha, 0x00aa, 2526 "Error during card handshake.\n"); 2527 return QLA_FUNCTION_FAILED; 2528 } 2529 2530 /* Negotiated Link width */ 2531 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 2532 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 2533 ha->link_width = (lnk >> 4) & 0x3f; 2534 2535 /* Synchronize with Receive peg */ 2536 return qla82xx_check_rcvpeg_state(ha); 2537} 2538 2539static uint32_t * 2540qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2541 uint32_t length) 2542{ 2543 uint32_t i; 2544 uint32_t val; 2545 struct qla_hw_data *ha = vha->hw; 2546 2547 /* Dword reads to flash. */ 2548 for (i = 0; i < length/4; i++, faddr += 4) { 2549 if (qla82xx_rom_fast_read(ha, faddr, &val)) { 2550 ql_log(ql_log_warn, vha, 0x0106, 2551 "Do ROM fast read failed.\n"); 2552 goto done_read; 2553 } 2554 dwptr[i] = __constant_cpu_to_le32(val); 2555 } 2556done_read: 2557 return dwptr; 2558} 2559 2560static int 2561qla82xx_unprotect_flash(struct qla_hw_data *ha) 2562{ 2563 int ret; 2564 uint32_t val; 2565 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2566 2567 ret = ql82xx_rom_lock_d(ha); 2568 if (ret < 0) { 2569 ql_log(ql_log_warn, vha, 0xb014, 2570 "ROM Lock failed.\n"); 2571 return ret; 2572 } 2573 2574 ret = qla82xx_read_status_reg(ha, &val); 2575 if (ret < 0) 2576 goto done_unprotect; 2577 2578 val &= ~(BLOCK_PROTECT_BITS << 2); 2579 ret = qla82xx_write_status_reg(ha, val); 2580 if (ret < 0) { 2581 val |= (BLOCK_PROTECT_BITS << 2); 2582 qla82xx_write_status_reg(ha, val); 2583 } 2584 2585 if (qla82xx_write_disable_flash(ha) != 0) 2586 ql_log(ql_log_warn, vha, 0xb015, 2587 "Write disable failed.\n"); 2588 2589done_unprotect: 2590 qla82xx_rom_unlock(ha); 2591 return ret; 2592} 2593 2594static int 2595qla82xx_protect_flash(struct qla_hw_data *ha) 2596{ 2597 int ret; 2598 uint32_t val; 2599 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2600 2601 ret = ql82xx_rom_lock_d(ha); 2602 if (ret < 0) { 2603 ql_log(ql_log_warn, vha, 0xb016, 2604 "ROM Lock failed.\n"); 2605 return ret; 2606 } 2607 2608 ret = qla82xx_read_status_reg(ha, &val); 2609 if (ret < 0) 2610 goto done_protect; 2611 2612 val |= (BLOCK_PROTECT_BITS << 2); 2613 /* LOCK all sectors */ 2614 ret = qla82xx_write_status_reg(ha, val); 2615 if (ret < 0) 2616 ql_log(ql_log_warn, vha, 0xb017, 2617 "Write status register failed.\n"); 2618 2619 if (qla82xx_write_disable_flash(ha) != 0) 2620 ql_log(ql_log_warn, vha, 0xb018, 2621 "Write disable failed.\n"); 2622done_protect: 2623 qla82xx_rom_unlock(ha); 2624 return ret; 2625} 2626 2627static int 2628qla82xx_erase_sector(struct qla_hw_data *ha, int addr) 2629{ 2630 int ret = 0; 2631 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2632 2633 ret = ql82xx_rom_lock_d(ha); 2634 if (ret < 0) { 2635 ql_log(ql_log_warn, vha, 0xb019, 2636 "ROM Lock failed.\n"); 2637 return ret; 2638 } 2639 2640 qla82xx_flash_set_write_enable(ha); 2641 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 2642 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 2643 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); 2644 2645 if (qla82xx_wait_rom_done(ha)) { 2646 ql_log(ql_log_warn, vha, 0xb01a, 2647 "Error waiting for rom done.\n"); 2648 ret = -1; 2649 goto done; 2650 } 2651 ret = qla82xx_flash_wait_write_finish(ha); 2652done: 2653 qla82xx_rom_unlock(ha); 2654 return ret; 2655} 2656 2657/* 2658 * Address and length are byte address 2659 */ 2660uint8_t * 2661qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2662 uint32_t offset, uint32_t length) 2663{ 2664 scsi_block_requests(vha->host); 2665 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); 2666 scsi_unblock_requests(vha->host); 2667 return buf; 2668} 2669 2670static int 2671qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, 2672 uint32_t faddr, uint32_t dwords) 2673{ 2674 int ret; 2675 uint32_t liter; 2676 uint32_t sec_mask, rest_addr; 2677 dma_addr_t optrom_dma; 2678 void *optrom = NULL; 2679 int page_mode = 0; 2680 struct qla_hw_data *ha = vha->hw; 2681 2682 ret = -1; 2683 2684 /* Prepare burst-capable write on supported ISPs. */ 2685 if (page_mode && !(faddr & 0xfff) && 2686 dwords > OPTROM_BURST_DWORDS) { 2687 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2688 &optrom_dma, GFP_KERNEL); 2689 if (!optrom) { 2690 ql_log(ql_log_warn, vha, 0xb01b, 2691 "Unable to allocate memory " 2692 "for optron burst write (%x KB).\n", 2693 OPTROM_BURST_SIZE / 1024); 2694 } 2695 } 2696 2697 rest_addr = ha->fdt_block_size - 1; 2698 sec_mask = ~rest_addr; 2699 2700 ret = qla82xx_unprotect_flash(ha); 2701 if (ret) { 2702 ql_log(ql_log_warn, vha, 0xb01c, 2703 "Unable to unprotect flash for update.\n"); 2704 goto write_done; 2705 } 2706 2707 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 2708 /* Are we at the beginning of a sector? */ 2709 if ((faddr & rest_addr) == 0) { 2710 2711 ret = qla82xx_erase_sector(ha, faddr); 2712 if (ret) { 2713 ql_log(ql_log_warn, vha, 0xb01d, 2714 "Unable to erase sector: address=%x.\n", 2715 faddr); 2716 break; 2717 } 2718 } 2719 2720 /* Go with burst-write. */ 2721 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 2722 /* Copy data to DMA'ble buffer. */ 2723 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 2724 2725 ret = qla2x00_load_ram(vha, optrom_dma, 2726 (ha->flash_data_off | faddr), 2727 OPTROM_BURST_DWORDS); 2728 if (ret != QLA_SUCCESS) { 2729 ql_log(ql_log_warn, vha, 0xb01e, 2730 "Unable to burst-write optrom segment " 2731 "(%x/%x/%llx).\n", ret, 2732 (ha->flash_data_off | faddr), 2733 (unsigned long long)optrom_dma); 2734 ql_log(ql_log_warn, vha, 0xb01f, 2735 "Reverting to slow-write.\n"); 2736 2737 dma_free_coherent(&ha->pdev->dev, 2738 OPTROM_BURST_SIZE, optrom, optrom_dma); 2739 optrom = NULL; 2740 } else { 2741 liter += OPTROM_BURST_DWORDS - 1; 2742 faddr += OPTROM_BURST_DWORDS - 1; 2743 dwptr += OPTROM_BURST_DWORDS - 1; 2744 continue; 2745 } 2746 } 2747 2748 ret = qla82xx_write_flash_dword(ha, faddr, 2749 cpu_to_le32(*dwptr)); 2750 if (ret) { 2751 ql_dbg(ql_dbg_p3p, vha, 0xb020, 2752 "Unable to program flash address=%x data=%x.\n", 2753 faddr, *dwptr); 2754 break; 2755 } 2756 } 2757 2758 ret = qla82xx_protect_flash(ha); 2759 if (ret) 2760 ql_log(ql_log_warn, vha, 0xb021, 2761 "Unable to protect flash after update.\n"); 2762write_done: 2763 if (optrom) 2764 dma_free_coherent(&ha->pdev->dev, 2765 OPTROM_BURST_SIZE, optrom, optrom_dma); 2766 return ret; 2767} 2768 2769int 2770qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2771 uint32_t offset, uint32_t length) 2772{ 2773 int rval; 2774 2775 /* Suspend HBA. */ 2776 scsi_block_requests(vha->host); 2777 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, 2778 length >> 2); 2779 scsi_unblock_requests(vha->host); 2780 2781 /* Convert return ISP82xx to generic */ 2782 if (rval) 2783 rval = QLA_FUNCTION_FAILED; 2784 else 2785 rval = QLA_SUCCESS; 2786 return rval; 2787} 2788 2789void 2790qla82xx_start_iocbs(scsi_qla_host_t *vha) 2791{ 2792 struct qla_hw_data *ha = vha->hw; 2793 struct req_que *req = ha->req_q_map[0]; 2794 struct device_reg_82xx __iomem *reg; 2795 uint32_t dbval; 2796 2797 /* Adjust ring index. */ 2798 req->ring_index++; 2799 if (req->ring_index == req->length) { 2800 req->ring_index = 0; 2801 req->ring_ptr = req->ring; 2802 } else 2803 req->ring_ptr++; 2804 2805 reg = &ha->iobase->isp82; 2806 dbval = 0x04 | (ha->portnum << 5); 2807 2808 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2809 if (ql2xdbwr) 2810 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2811 else { 2812 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2813 wmb(); 2814 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 2815 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 2816 dbval); 2817 wmb(); 2818 } 2819 } 2820} 2821 2822void qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2823{ 2824 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2825 2826 if (qla82xx_rom_lock(ha)) 2827 /* Someone else is holding the lock. */ 2828 ql_log(ql_log_info, vha, 0xb022, 2829 "Resetting rom_lock.\n"); 2830 2831 /* 2832 * Either we got the lock, or someone 2833 * else died while holding it. 2834 * In either case, unlock. 2835 */ 2836 qla82xx_rom_unlock(ha); 2837} 2838 2839/* 2840 * qla82xx_device_bootstrap 2841 * Initialize device, set DEV_READY, start fw 2842 * 2843 * Note: 2844 * IDC lock must be held upon entry 2845 * 2846 * Return: 2847 * Success : 0 2848 * Failed : 1 2849 */ 2850static int 2851qla82xx_device_bootstrap(scsi_qla_host_t *vha) 2852{ 2853 int rval = QLA_SUCCESS; 2854 int i, timeout; 2855 uint32_t old_count, count; 2856 struct qla_hw_data *ha = vha->hw; 2857 int need_reset = 0, peg_stuck = 1; 2858 2859 need_reset = qla82xx_need_reset(ha); 2860 2861 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2862 2863 for (i = 0; i < 10; i++) { 2864 timeout = msleep_interruptible(200); 2865 if (timeout) { 2866 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2867 QLA82XX_DEV_FAILED); 2868 return QLA_FUNCTION_FAILED; 2869 } 2870 2871 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2872 if (count != old_count) 2873 peg_stuck = 0; 2874 } 2875 2876 if (need_reset) { 2877 /* We are trying to perform a recovery here. */ 2878 if (peg_stuck) 2879 qla82xx_rom_lock_recovery(ha); 2880 goto dev_initialize; 2881 } else { 2882 /* Start of day for this ha context. */ 2883 if (peg_stuck) { 2884 /* Either we are the first or recovery in progress. */ 2885 qla82xx_rom_lock_recovery(ha); 2886 goto dev_initialize; 2887 } else 2888 /* Firmware already running. */ 2889 goto dev_ready; 2890 } 2891 2892 return rval; 2893 2894dev_initialize: 2895 /* set to DEV_INITIALIZING */ 2896 ql_log(ql_log_info, vha, 0x009e, 2897 "HW State: INITIALIZING.\n"); 2898 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 2899 2900 /* Driver that sets device state to initializating sets IDC version */ 2901 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 2902 2903 qla82xx_idc_unlock(ha); 2904 rval = qla82xx_start_firmware(vha); 2905 qla82xx_idc_lock(ha); 2906 2907 if (rval != QLA_SUCCESS) { 2908 ql_log(ql_log_fatal, vha, 0x00ad, 2909 "HW State: FAILED.\n"); 2910 qla82xx_clear_drv_active(ha); 2911 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 2912 return rval; 2913 } 2914 2915dev_ready: 2916 ql_log(ql_log_info, vha, 0x00ae, 2917 "HW State: READY.\n"); 2918 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 2919 2920 return QLA_SUCCESS; 2921} 2922 2923/* 2924* qla82xx_need_qsnt_handler 2925* Code to start quiescence sequence 2926* 2927* Note: 2928* IDC lock must be held upon entry 2929* 2930* Return: void 2931*/ 2932 2933static void 2934qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) 2935{ 2936 struct qla_hw_data *ha = vha->hw; 2937 uint32_t dev_state, drv_state, drv_active; 2938 unsigned long reset_timeout; 2939 2940 if (vha->flags.online) { 2941 /*Block any further I/O and wait for pending cmnds to complete*/ 2942 qla82xx_quiescent_state_cleanup(vha); 2943 } 2944 2945 /* Set the quiescence ready bit */ 2946 qla82xx_set_qsnt_ready(ha); 2947 2948 /*wait for 30 secs for other functions to ack */ 2949 reset_timeout = jiffies + (30 * HZ); 2950 2951 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2952 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2953 /* Its 2 that is written when qsnt is acked, moving one bit */ 2954 drv_active = drv_active << 0x01; 2955 2956 while (drv_state != drv_active) { 2957 2958 if (time_after_eq(jiffies, reset_timeout)) { 2959 /* quiescence timeout, other functions didn't ack 2960 * changing the state to DEV_READY 2961 */ 2962 ql_log(ql_log_info, vha, 0xb023, 2963 "%s : QUIESCENT TIMEOUT.\n", QLA2XXX_DRIVER_NAME); 2964 ql_log(ql_log_info, vha, 0xb024, 2965 "DRV_ACTIVE:%d DRV_STATE:%d.\n", 2966 drv_active, drv_state); 2967 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2968 QLA82XX_DEV_READY); 2969 ql_log(ql_log_info, vha, 0xb025, 2970 "HW State: DEV_READY.\n"); 2971 qla82xx_idc_unlock(ha); 2972 qla2x00_perform_loop_resync(vha); 2973 qla82xx_idc_lock(ha); 2974 2975 qla82xx_clear_qsnt_ready(vha); 2976 return; 2977 } 2978 2979 qla82xx_idc_unlock(ha); 2980 msleep(1000); 2981 qla82xx_idc_lock(ha); 2982 2983 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2984 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2985 drv_active = drv_active << 0x01; 2986 } 2987 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2988 /* everyone acked so set the state to DEV_QUIESCENCE */ 2989 if (dev_state == QLA82XX_DEV_NEED_QUIESCENT) { 2990 ql_log(ql_log_info, vha, 0xb026, 2991 "HW State: DEV_QUIESCENT.\n"); 2992 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_QUIESCENT); 2993 } 2994} 2995 2996/* 2997* qla82xx_wait_for_state_change 2998* Wait for device state to change from given current state 2999* 3000* Note: 3001* IDC lock must not be held upon entry 3002* 3003* Return: 3004* Changed device state. 3005*/ 3006uint32_t 3007qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) 3008{ 3009 struct qla_hw_data *ha = vha->hw; 3010 uint32_t dev_state; 3011 3012 do { 3013 msleep(1000); 3014 qla82xx_idc_lock(ha); 3015 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3016 qla82xx_idc_unlock(ha); 3017 } while (dev_state == curr_state); 3018 3019 return dev_state; 3020} 3021 3022static void 3023qla82xx_dev_failed_handler(scsi_qla_host_t *vha) 3024{ 3025 struct qla_hw_data *ha = vha->hw; 3026 3027 /* Disable the board */ 3028 ql_log(ql_log_fatal, vha, 0x00b8, 3029 "Disabling the board.\n"); 3030 3031 qla82xx_idc_lock(ha); 3032 qla82xx_clear_drv_active(ha); 3033 qla82xx_idc_unlock(ha); 3034 3035 /* Set DEV_FAILED flag to disable timer */ 3036 vha->device_flags |= DFLG_DEV_FAILED; 3037 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3038 qla2x00_mark_all_devices_lost(vha, 0); 3039 vha->flags.online = 0; 3040 vha->flags.init_done = 0; 3041} 3042 3043/* 3044 * qla82xx_need_reset_handler 3045 * Code to start reset sequence 3046 * 3047 * Note: 3048 * IDC lock must be held upon entry 3049 * 3050 * Return: 3051 * Success : 0 3052 * Failed : 1 3053 */ 3054static void 3055qla82xx_need_reset_handler(scsi_qla_host_t *vha) 3056{ 3057 uint32_t dev_state, drv_state, drv_active; 3058 uint32_t active_mask = 0; 3059 unsigned long reset_timeout; 3060 struct qla_hw_data *ha = vha->hw; 3061 struct req_que *req = ha->req_q_map[0]; 3062 3063 if (vha->flags.online) { 3064 qla82xx_idc_unlock(ha); 3065 qla2x00_abort_isp_cleanup(vha); 3066 ha->isp_ops->get_flash_version(vha, req->ring); 3067 ha->isp_ops->nvram_config(vha); 3068 qla82xx_idc_lock(ha); 3069 } 3070 3071 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3072 if (!ha->flags.isp82xx_reset_owner) { 3073 ql_dbg(ql_dbg_p3p, vha, 0xb028, 3074 "reset_acknowledged by 0x%x\n", ha->portnum); 3075 qla82xx_set_rst_ready(ha); 3076 } else { 3077 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); 3078 drv_active &= active_mask; 3079 ql_dbg(ql_dbg_p3p, vha, 0xb029, 3080 "active_mask: 0x%08x\n", active_mask); 3081 } 3082 3083 /* wait for 10 seconds for reset ack from all functions */ 3084 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3085 3086 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3087 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3088 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3089 3090 ql_dbg(ql_dbg_p3p, vha, 0xb02a, 3091 "drv_state: 0x%08x, drv_active: 0x%08x, " 3092 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3093 drv_state, drv_active, dev_state, active_mask); 3094 3095 while (drv_state != drv_active && 3096 dev_state != QLA82XX_DEV_INITIALIZING) { 3097 if (time_after_eq(jiffies, reset_timeout)) { 3098 ql_log(ql_log_warn, vha, 0x00b5, 3099 "Reset timeout.\n"); 3100 break; 3101 } 3102 qla82xx_idc_unlock(ha); 3103 msleep(1000); 3104 qla82xx_idc_lock(ha); 3105 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3106 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3107 if (ha->flags.isp82xx_reset_owner) 3108 drv_active &= active_mask; 3109 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3110 } 3111 3112 ql_dbg(ql_dbg_p3p, vha, 0xb02b, 3113 "drv_state: 0x%08x, drv_active: 0x%08x, " 3114 "dev_state: 0x%08x, active_mask: 0x%08x\n", 3115 drv_state, drv_active, dev_state, active_mask); 3116 3117 ql_log(ql_log_info, vha, 0x00b6, 3118 "Device state is 0x%x = %s.\n", 3119 dev_state, 3120 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3121 3122 /* Force to DEV_COLD unless someone else is starting a reset */ 3123 if (dev_state != QLA82XX_DEV_INITIALIZING && 3124 dev_state != QLA82XX_DEV_COLD) { 3125 ql_log(ql_log_info, vha, 0x00b7, 3126 "HW State: COLD/RE-INIT.\n"); 3127 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 3128 qla82xx_set_rst_ready(ha); 3129 if (ql2xmdenable) { 3130 if (qla82xx_md_collect(vha)) 3131 ql_log(ql_log_warn, vha, 0xb02c, 3132 "Not able to collect minidump.\n"); 3133 } else 3134 ql_log(ql_log_warn, vha, 0xb04f, 3135 "Minidump disabled.\n"); 3136 } 3137} 3138 3139int 3140qla82xx_check_md_needed(scsi_qla_host_t *vha) 3141{ 3142 struct qla_hw_data *ha = vha->hw; 3143 uint16_t fw_major_version, fw_minor_version, fw_subminor_version; 3144 int rval = QLA_SUCCESS; 3145 3146 fw_major_version = ha->fw_major_version; 3147 fw_minor_version = ha->fw_minor_version; 3148 fw_subminor_version = ha->fw_subminor_version; 3149 3150 rval = qla2x00_get_fw_version(vha); 3151 if (rval != QLA_SUCCESS) 3152 return rval; 3153 3154 if (ql2xmdenable) { 3155 if (!ha->fw_dumped) { 3156 if (fw_major_version != ha->fw_major_version || 3157 fw_minor_version != ha->fw_minor_version || 3158 fw_subminor_version != ha->fw_subminor_version) { 3159 ql_log(ql_log_info, vha, 0xb02d, 3160 "Firmware version differs " 3161 "Previous version: %d:%d:%d - " 3162 "New version: %d:%d:%d\n", 3163 ha->fw_major_version, 3164 ha->fw_minor_version, 3165 ha->fw_subminor_version, 3166 fw_major_version, fw_minor_version, 3167 fw_subminor_version); 3168 /* Release MiniDump resources */ 3169 qla82xx_md_free(vha); 3170 /* ALlocate MiniDump resources */ 3171 qla82xx_md_prep(vha); 3172 } 3173 } else 3174 ql_log(ql_log_info, vha, 0xb02e, 3175 "Firmware dump available to retrieve\n"); 3176 } 3177 return rval; 3178} 3179 3180 3181int 3182qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3183{ 3184 uint32_t fw_heartbeat_counter; 3185 int status = 0; 3186 3187 fw_heartbeat_counter = qla82xx_rd_32(vha->hw, 3188 QLA82XX_PEG_ALIVE_COUNTER); 3189 /* all 0xff, assume AER/EEH in progress, ignore */ 3190 if (fw_heartbeat_counter == 0xffffffff) { 3191 ql_dbg(ql_dbg_timer, vha, 0x6003, 3192 "FW heartbeat counter is 0xffffffff, " 3193 "returning status=%d.\n", status); 3194 return status; 3195 } 3196 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 3197 vha->seconds_since_last_heartbeat++; 3198 /* FW not alive after 2 seconds */ 3199 if (vha->seconds_since_last_heartbeat == 2) { 3200 vha->seconds_since_last_heartbeat = 0; 3201 status = 1; 3202 } 3203 } else 3204 vha->seconds_since_last_heartbeat = 0; 3205 vha->fw_heartbeat_counter = fw_heartbeat_counter; 3206 if (status) 3207 ql_dbg(ql_dbg_timer, vha, 0x6004, 3208 "Returning status=%d.\n", status); 3209 return status; 3210} 3211 3212/* 3213 * qla82xx_device_state_handler 3214 * Main state handler 3215 * 3216 * Note: 3217 * IDC lock must be held upon entry 3218 * 3219 * Return: 3220 * Success : 0 3221 * Failed : 1 3222 */ 3223int 3224qla82xx_device_state_handler(scsi_qla_host_t *vha) 3225{ 3226 uint32_t dev_state; 3227 uint32_t old_dev_state; 3228 int rval = QLA_SUCCESS; 3229 unsigned long dev_init_timeout; 3230 struct qla_hw_data *ha = vha->hw; 3231 int loopcount = 0; 3232 3233 qla82xx_idc_lock(ha); 3234 if (!vha->flags.init_done) 3235 qla82xx_set_drv_active(vha); 3236 3237 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3238 old_dev_state = dev_state; 3239 ql_log(ql_log_info, vha, 0x009b, 3240 "Device state is 0x%x = %s.\n", 3241 dev_state, 3242 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3243 3244 /* wait for 30 seconds for device to go ready */ 3245 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3246 3247 while (1) { 3248 3249 if (time_after_eq(jiffies, dev_init_timeout)) { 3250 ql_log(ql_log_fatal, vha, 0x009c, 3251 "Device init failed.\n"); 3252 rval = QLA_FUNCTION_FAILED; 3253 break; 3254 } 3255 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3256 if (old_dev_state != dev_state) { 3257 loopcount = 0; 3258 old_dev_state = dev_state; 3259 } 3260 if (loopcount < 5) { 3261 ql_log(ql_log_info, vha, 0x009d, 3262 "Device state is 0x%x = %s.\n", 3263 dev_state, 3264 dev_state < MAX_STATES ? qdev_state(dev_state) : 3265 "Unknown"); 3266 } 3267 3268 switch (dev_state) { 3269 case QLA82XX_DEV_READY: 3270 ha->flags.isp82xx_reset_owner = 0; 3271 goto exit; 3272 case QLA82XX_DEV_COLD: 3273 rval = qla82xx_device_bootstrap(vha); 3274 break; 3275 case QLA82XX_DEV_INITIALIZING: 3276 qla82xx_idc_unlock(ha); 3277 msleep(1000); 3278 qla82xx_idc_lock(ha); 3279 break; 3280 case QLA82XX_DEV_NEED_RESET: 3281 if (!ql2xdontresethba) 3282 qla82xx_need_reset_handler(vha); 3283 else { 3284 qla82xx_idc_unlock(ha); 3285 msleep(1000); 3286 qla82xx_idc_lock(ha); 3287 } 3288 dev_init_timeout = jiffies + 3289 (ha->nx_dev_init_timeout * HZ); 3290 break; 3291 case QLA82XX_DEV_NEED_QUIESCENT: 3292 qla82xx_need_qsnt_handler(vha); 3293 /* Reset timeout value after quiescence handler */ 3294 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3295 * HZ); 3296 break; 3297 case QLA82XX_DEV_QUIESCENT: 3298 /* Owner will exit and other will wait for the state 3299 * to get changed 3300 */ 3301 if (ha->flags.quiesce_owner) 3302 goto exit; 3303 3304 qla82xx_idc_unlock(ha); 3305 msleep(1000); 3306 qla82xx_idc_lock(ha); 3307 3308 /* Reset timeout value after quiescence handler */ 3309 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ 3310 * HZ); 3311 break; 3312 case QLA82XX_DEV_FAILED: 3313 qla82xx_dev_failed_handler(vha); 3314 rval = QLA_FUNCTION_FAILED; 3315 goto exit; 3316 default: 3317 qla82xx_idc_unlock(ha); 3318 msleep(1000); 3319 qla82xx_idc_lock(ha); 3320 } 3321 loopcount++; 3322 } 3323exit: 3324 qla82xx_idc_unlock(ha); 3325 return rval; 3326} 3327 3328void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) 3329{ 3330 struct qla_hw_data *ha = vha->hw; 3331 3332 if (ha->flags.mbox_busy) { 3333 ha->flags.mbox_int = 1; 3334 ha->flags.mbox_busy = 0; 3335 ql_log(ql_log_warn, vha, 0x6010, 3336 "Doing premature completion of mbx command.\n"); 3337 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) 3338 complete(&ha->mbx_intr_comp); 3339 } 3340} 3341 3342void qla82xx_watchdog(scsi_qla_host_t *vha) 3343{ 3344 uint32_t dev_state, halt_status; 3345 struct qla_hw_data *ha = vha->hw; 3346 3347 /* don't poll if reset is going on */ 3348 if (!ha->flags.isp82xx_reset_hdlr_active) { 3349 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3350 if (dev_state == QLA82XX_DEV_NEED_RESET && 3351 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 3352 ql_log(ql_log_warn, vha, 0x6001, 3353 "Adapter reset needed.\n"); 3354 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3355 qla2xxx_wake_dpc(vha); 3356 } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT && 3357 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 3358 ql_log(ql_log_warn, vha, 0x6002, 3359 "Quiescent needed.\n"); 3360 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 3361 qla2xxx_wake_dpc(vha); 3362 } else { 3363 if (qla82xx_check_fw_alive(vha)) { 3364 ql_dbg(ql_dbg_timer, vha, 0x6011, 3365 "disabling pause transmit on port 0 & 1.\n"); 3366 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 3367 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1); 3368 halt_status = qla82xx_rd_32(ha, 3369 QLA82XX_PEG_HALT_STATUS1); 3370 ql_log(ql_log_info, vha, 0x6005, 3371 "dumping hw/fw registers:.\n " 3372 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " 3373 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " 3374 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " 3375 " PEG_NET_4_PC: 0x%x.\n", halt_status, 3376 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), 3377 qla82xx_rd_32(ha, 3378 QLA82XX_CRB_PEG_NET_0 + 0x3c), 3379 qla82xx_rd_32(ha, 3380 QLA82XX_CRB_PEG_NET_1 + 0x3c), 3381 qla82xx_rd_32(ha, 3382 QLA82XX_CRB_PEG_NET_2 + 0x3c), 3383 qla82xx_rd_32(ha, 3384 QLA82XX_CRB_PEG_NET_3 + 0x3c), 3385 qla82xx_rd_32(ha, 3386 QLA82XX_CRB_PEG_NET_4 + 0x3c)); 3387 if (((halt_status & 0x1fffff00) >> 8) == 0x67) 3388 ql_log(ql_log_warn, vha, 0xb052, 3389 "Firmware aborted with " 3390 "error code 0x00006700. Device is " 3391 "being reset.\n"); 3392 if (halt_status & HALT_STATUS_UNRECOVERABLE) { 3393 set_bit(ISP_UNRECOVERABLE, 3394 &vha->dpc_flags); 3395 } else { 3396 ql_log(ql_log_info, vha, 0x6006, 3397 "Detect abort needed.\n"); 3398 set_bit(ISP_ABORT_NEEDED, 3399 &vha->dpc_flags); 3400 } 3401 qla2xxx_wake_dpc(vha); 3402 ha->flags.isp82xx_fw_hung = 1; 3403 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); 3404 qla82xx_clear_pending_mbx(vha); 3405 } 3406 } 3407 } 3408} 3409 3410int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 3411{ 3412 int rval; 3413 rval = qla82xx_device_state_handler(vha); 3414 return rval; 3415} 3416 3417void 3418qla82xx_set_reset_owner(scsi_qla_host_t *vha) 3419{ 3420 struct qla_hw_data *ha = vha->hw; 3421 uint32_t dev_state; 3422 3423 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3424 if (dev_state == QLA82XX_DEV_READY) { 3425 ql_log(ql_log_info, vha, 0xb02f, 3426 "HW State: NEED RESET\n"); 3427 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3428 QLA82XX_DEV_NEED_RESET); 3429 ha->flags.isp82xx_reset_owner = 1; 3430 ql_dbg(ql_dbg_p3p, vha, 0xb030, 3431 "reset_owner is 0x%x\n", ha->portnum); 3432 } else 3433 ql_log(ql_log_info, vha, 0xb031, 3434 "Device state is 0x%x = %s.\n", 3435 dev_state, 3436 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); 3437} 3438 3439/* 3440 * qla82xx_abort_isp 3441 * Resets ISP and aborts all outstanding commands. 3442 * 3443 * Input: 3444 * ha = adapter block pointer. 3445 * 3446 * Returns: 3447 * 0 = success 3448 */ 3449int 3450qla82xx_abort_isp(scsi_qla_host_t *vha) 3451{ 3452 int rval; 3453 struct qla_hw_data *ha = vha->hw; 3454 3455 if (vha->device_flags & DFLG_DEV_FAILED) { 3456 ql_log(ql_log_warn, vha, 0x8024, 3457 "Device in failed state, exiting.\n"); 3458 return QLA_SUCCESS; 3459 } 3460 ha->flags.isp82xx_reset_hdlr_active = 1; 3461 3462 qla82xx_idc_lock(ha); 3463 qla82xx_set_reset_owner(vha); 3464 qla82xx_idc_unlock(ha); 3465 3466 rval = qla82xx_device_state_handler(vha); 3467 3468 qla82xx_idc_lock(ha); 3469 qla82xx_clear_rst_ready(ha); 3470 qla82xx_idc_unlock(ha); 3471 3472 if (rval == QLA_SUCCESS) { 3473 ha->flags.isp82xx_fw_hung = 0; 3474 ha->flags.isp82xx_reset_hdlr_active = 0; 3475 qla82xx_restart_isp(vha); 3476 } 3477 3478 if (rval) { 3479 vha->flags.online = 1; 3480 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 3481 if (ha->isp_abort_cnt == 0) { 3482 ql_log(ql_log_warn, vha, 0x8027, 3483 "ISP error recover failed - board " 3484 "disabled.\n"); 3485 /* 3486 * The next call disables the board 3487 * completely. 3488 */ 3489 ha->isp_ops->reset_adapter(vha); 3490 vha->flags.online = 0; 3491 clear_bit(ISP_ABORT_RETRY, 3492 &vha->dpc_flags); 3493 rval = QLA_SUCCESS; 3494 } else { /* schedule another ISP abort */ 3495 ha->isp_abort_cnt--; 3496 ql_log(ql_log_warn, vha, 0x8036, 3497 "ISP abort - retry remaining %d.\n", 3498 ha->isp_abort_cnt); 3499 rval = QLA_FUNCTION_FAILED; 3500 } 3501 } else { 3502 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3503 ql_dbg(ql_dbg_taskm, vha, 0x8029, 3504 "ISP error recovery - retrying (%d) more times.\n", 3505 ha->isp_abort_cnt); 3506 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3507 rval = QLA_FUNCTION_FAILED; 3508 } 3509 } 3510 return rval; 3511} 3512 3513/* 3514 * qla82xx_fcoe_ctx_reset 3515 * Perform a quick reset and aborts all outstanding commands. 3516 * This will only perform an FCoE context reset and avoids a full blown 3517 * chip reset. 3518 * 3519 * Input: 3520 * ha = adapter block pointer. 3521 * is_reset_path = flag for identifying the reset path. 3522 * 3523 * Returns: 3524 * 0 = success 3525 */ 3526int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) 3527{ 3528 int rval = QLA_FUNCTION_FAILED; 3529 3530 if (vha->flags.online) { 3531 /* Abort all outstanding commands, so as to be requeued later */ 3532 qla2x00_abort_isp_cleanup(vha); 3533 } 3534 3535 /* Stop currently executing firmware. 3536 * This will destroy existing FCoE context at the F/W end. 3537 */ 3538 qla2x00_try_to_stop_firmware(vha); 3539 3540 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ 3541 rval = qla82xx_restart_isp(vha); 3542 3543 return rval; 3544} 3545 3546/* 3547 * qla2x00_wait_for_fcoe_ctx_reset 3548 * Wait till the FCoE context is reset. 3549 * 3550 * Note: 3551 * Does context switching here. 3552 * Release SPIN_LOCK (if any) before calling this routine. 3553 * 3554 * Return: 3555 * Success (fcoe_ctx reset is done) : 0 3556 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 3557 */ 3558int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) 3559{ 3560 int status = QLA_FUNCTION_FAILED; 3561 unsigned long wait_reset; 3562 3563 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 3564 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 3565 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) 3566 && time_before(jiffies, wait_reset)) { 3567 3568 set_current_state(TASK_UNINTERRUPTIBLE); 3569 schedule_timeout(HZ); 3570 3571 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && 3572 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { 3573 status = QLA_SUCCESS; 3574 break; 3575 } 3576 } 3577 ql_dbg(ql_dbg_p3p, vha, 0xb027, 3578 "%s: status=%d.\n", __func__, status); 3579 3580 return status; 3581} 3582 3583void 3584qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) 3585{ 3586 int i; 3587 unsigned long flags; 3588 struct qla_hw_data *ha = vha->hw; 3589 3590 /* Check if 82XX firmware is alive or not 3591 * We may have arrived here from NEED_RESET 3592 * detection only 3593 */ 3594 if (!ha->flags.isp82xx_fw_hung) { 3595 for (i = 0; i < 2; i++) { 3596 msleep(1000); 3597 if (qla82xx_check_fw_alive(vha)) { 3598 ha->flags.isp82xx_fw_hung = 1; 3599 qla82xx_clear_pending_mbx(vha); 3600 break; 3601 } 3602 } 3603 } 3604 ql_dbg(ql_dbg_init, vha, 0x00b0, 3605 "Entered %s fw_hung=%d.\n", 3606 __func__, ha->flags.isp82xx_fw_hung); 3607 3608 /* Abort all commands gracefully if fw NOT hung */ 3609 if (!ha->flags.isp82xx_fw_hung) { 3610 int cnt, que; 3611 srb_t *sp; 3612 struct req_que *req; 3613 3614 spin_lock_irqsave(&ha->hardware_lock, flags); 3615 for (que = 0; que < ha->max_req_queues; que++) { 3616 req = ha->req_q_map[que]; 3617 if (!req) 3618 continue; 3619 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { 3620 sp = req->outstanding_cmds[cnt]; 3621 if (sp) { 3622 if (!sp->u.scmd.ctx || 3623 (sp->flags & SRB_FCP_CMND_DMA_VALID)) { 3624 spin_unlock_irqrestore( 3625 &ha->hardware_lock, flags); 3626 if (ha->isp_ops->abort_command(sp)) { 3627 ql_log(ql_log_info, vha, 3628 0x00b1, 3629 "mbx abort failed.\n"); 3630 } else { 3631 ql_log(ql_log_info, vha, 3632 0x00b2, 3633 "mbx abort success.\n"); 3634 } 3635 spin_lock_irqsave(&ha->hardware_lock, flags); 3636 } 3637 } 3638 } 3639 } 3640 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3641 3642 /* Wait for pending cmds (physical and virtual) to complete */ 3643 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, 3644 WAIT_HOST) == QLA_SUCCESS) { 3645 ql_dbg(ql_dbg_init, vha, 0x00b3, 3646 "Done wait for " 3647 "pending commands.\n"); 3648 } 3649 } 3650} 3651 3652/* Minidump related functions */ 3653static int 3654qla82xx_minidump_process_control(scsi_qla_host_t *vha, 3655 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3656{ 3657 struct qla_hw_data *ha = vha->hw; 3658 struct qla82xx_md_entry_crb *crb_entry; 3659 uint32_t read_value, opcode, poll_time; 3660 uint32_t addr, index, crb_addr; 3661 unsigned long wtime; 3662 struct qla82xx_md_template_hdr *tmplt_hdr; 3663 uint32_t rval = QLA_SUCCESS; 3664 int i; 3665 3666 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 3667 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; 3668 crb_addr = crb_entry->addr; 3669 3670 for (i = 0; i < crb_entry->op_count; i++) { 3671 opcode = crb_entry->crb_ctrl.opcode; 3672 if (opcode & QLA82XX_DBG_OPCODE_WR) { 3673 qla82xx_md_rw_32(ha, crb_addr, 3674 crb_entry->value_1, 1); 3675 opcode &= ~QLA82XX_DBG_OPCODE_WR; 3676 } 3677 3678 if (opcode & QLA82XX_DBG_OPCODE_RW) { 3679 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3680 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3681 opcode &= ~QLA82XX_DBG_OPCODE_RW; 3682 } 3683 3684 if (opcode & QLA82XX_DBG_OPCODE_AND) { 3685 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3686 read_value &= crb_entry->value_2; 3687 opcode &= ~QLA82XX_DBG_OPCODE_AND; 3688 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3689 read_value |= crb_entry->value_3; 3690 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3691 } 3692 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3693 } 3694 3695 if (opcode & QLA82XX_DBG_OPCODE_OR) { 3696 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3697 read_value |= crb_entry->value_3; 3698 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); 3699 opcode &= ~QLA82XX_DBG_OPCODE_OR; 3700 } 3701 3702 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 3703 poll_time = crb_entry->crb_strd.poll_timeout; 3704 wtime = jiffies + poll_time; 3705 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); 3706 3707 do { 3708 if ((read_value & crb_entry->value_2) 3709 == crb_entry->value_1) 3710 break; 3711 else if (time_after_eq(jiffies, wtime)) { 3712 /* capturing dump failed */ 3713 rval = QLA_FUNCTION_FAILED; 3714 break; 3715 } else 3716 read_value = qla82xx_md_rw_32(ha, 3717 crb_addr, 0, 0); 3718 } while (1); 3719 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 3720 } 3721 3722 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 3723 if (crb_entry->crb_strd.state_index_a) { 3724 index = crb_entry->crb_strd.state_index_a; 3725 addr = tmplt_hdr->saved_state_array[index]; 3726 } else 3727 addr = crb_addr; 3728 3729 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3730 index = crb_entry->crb_ctrl.state_index_v; 3731 tmplt_hdr->saved_state_array[index] = read_value; 3732 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 3733 } 3734 3735 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 3736 if (crb_entry->crb_strd.state_index_a) { 3737 index = crb_entry->crb_strd.state_index_a; 3738 addr = tmplt_hdr->saved_state_array[index]; 3739 } else 3740 addr = crb_addr; 3741 3742 if (crb_entry->crb_ctrl.state_index_v) { 3743 index = crb_entry->crb_ctrl.state_index_v; 3744 read_value = 3745 tmplt_hdr->saved_state_array[index]; 3746 } else 3747 read_value = crb_entry->value_1; 3748 3749 qla82xx_md_rw_32(ha, addr, read_value, 1); 3750 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 3751 } 3752 3753 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 3754 index = crb_entry->crb_ctrl.state_index_v; 3755 read_value = tmplt_hdr->saved_state_array[index]; 3756 read_value <<= crb_entry->crb_ctrl.shl; 3757 read_value >>= crb_entry->crb_ctrl.shr; 3758 if (crb_entry->value_2) 3759 read_value &= crb_entry->value_2; 3760 read_value |= crb_entry->value_3; 3761 read_value += crb_entry->value_1; 3762 tmplt_hdr->saved_state_array[index] = read_value; 3763 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 3764 } 3765 crb_addr += crb_entry->crb_strd.addr_stride; 3766 } 3767 return rval; 3768} 3769 3770static void 3771qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, 3772 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3773{ 3774 struct qla_hw_data *ha = vha->hw; 3775 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3776 struct qla82xx_md_entry_rdocm *ocm_hdr; 3777 uint32_t *data_ptr = *d_ptr; 3778 3779 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; 3780 r_addr = ocm_hdr->read_addr; 3781 r_stride = ocm_hdr->read_addr_stride; 3782 loop_cnt = ocm_hdr->op_count; 3783 3784 for (i = 0; i < loop_cnt; i++) { 3785 r_value = RD_REG_DWORD((void *)(r_addr + ha->nx_pcibase)); 3786 *data_ptr++ = cpu_to_le32(r_value); 3787 r_addr += r_stride; 3788 } 3789 *d_ptr = data_ptr; 3790} 3791 3792static void 3793qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, 3794 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3795{ 3796 struct qla_hw_data *ha = vha->hw; 3797 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 3798 struct qla82xx_md_entry_mux *mux_hdr; 3799 uint32_t *data_ptr = *d_ptr; 3800 3801 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; 3802 r_addr = mux_hdr->read_addr; 3803 s_addr = mux_hdr->select_addr; 3804 s_stride = mux_hdr->select_value_stride; 3805 s_value = mux_hdr->select_value; 3806 loop_cnt = mux_hdr->op_count; 3807 3808 for (i = 0; i < loop_cnt; i++) { 3809 qla82xx_md_rw_32(ha, s_addr, s_value, 1); 3810 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3811 *data_ptr++ = cpu_to_le32(s_value); 3812 *data_ptr++ = cpu_to_le32(r_value); 3813 s_value += s_stride; 3814 } 3815 *d_ptr = data_ptr; 3816} 3817 3818static void 3819qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, 3820 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3821{ 3822 struct qla_hw_data *ha = vha->hw; 3823 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 3824 struct qla82xx_md_entry_crb *crb_hdr; 3825 uint32_t *data_ptr = *d_ptr; 3826 3827 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; 3828 r_addr = crb_hdr->addr; 3829 r_stride = crb_hdr->crb_strd.addr_stride; 3830 loop_cnt = crb_hdr->op_count; 3831 3832 for (i = 0; i < loop_cnt; i++) { 3833 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3834 *data_ptr++ = cpu_to_le32(r_addr); 3835 *data_ptr++ = cpu_to_le32(r_value); 3836 r_addr += r_stride; 3837 } 3838 *d_ptr = data_ptr; 3839} 3840 3841static int 3842qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, 3843 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3844{ 3845 struct qla_hw_data *ha = vha->hw; 3846 uint32_t addr, r_addr, c_addr, t_r_addr; 3847 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3848 unsigned long p_wait, w_time, p_mask; 3849 uint32_t c_value_w, c_value_r; 3850 struct qla82xx_md_entry_cache *cache_hdr; 3851 int rval = QLA_FUNCTION_FAILED; 3852 uint32_t *data_ptr = *d_ptr; 3853 3854 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3855 loop_count = cache_hdr->op_count; 3856 r_addr = cache_hdr->read_addr; 3857 c_addr = cache_hdr->control_addr; 3858 c_value_w = cache_hdr->cache_ctrl.write_value; 3859 3860 t_r_addr = cache_hdr->tag_reg_addr; 3861 t_value = cache_hdr->addr_ctrl.init_tag_value; 3862 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3863 p_wait = cache_hdr->cache_ctrl.poll_wait; 3864 p_mask = cache_hdr->cache_ctrl.poll_mask; 3865 3866 for (i = 0; i < loop_count; i++) { 3867 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3868 if (c_value_w) 3869 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3870 3871 if (p_mask) { 3872 w_time = jiffies + p_wait; 3873 do { 3874 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); 3875 if ((c_value_r & p_mask) == 0) 3876 break; 3877 else if (time_after_eq(jiffies, w_time)) { 3878 /* capturing dump failed */ 3879 ql_dbg(ql_dbg_p3p, vha, 0xb032, 3880 "c_value_r: 0x%x, poll_mask: 0x%lx, " 3881 "w_time: 0x%lx\n", 3882 c_value_r, p_mask, w_time); 3883 return rval; 3884 } 3885 } while (1); 3886 } 3887 3888 addr = r_addr; 3889 for (k = 0; k < r_cnt; k++) { 3890 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3891 *data_ptr++ = cpu_to_le32(r_value); 3892 addr += cache_hdr->read_ctrl.read_addr_stride; 3893 } 3894 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3895 } 3896 *d_ptr = data_ptr; 3897 return QLA_SUCCESS; 3898} 3899 3900static void 3901qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, 3902 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3903{ 3904 struct qla_hw_data *ha = vha->hw; 3905 uint32_t addr, r_addr, c_addr, t_r_addr; 3906 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 3907 uint32_t c_value_w; 3908 struct qla82xx_md_entry_cache *cache_hdr; 3909 uint32_t *data_ptr = *d_ptr; 3910 3911 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; 3912 loop_count = cache_hdr->op_count; 3913 r_addr = cache_hdr->read_addr; 3914 c_addr = cache_hdr->control_addr; 3915 c_value_w = cache_hdr->cache_ctrl.write_value; 3916 3917 t_r_addr = cache_hdr->tag_reg_addr; 3918 t_value = cache_hdr->addr_ctrl.init_tag_value; 3919 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 3920 3921 for (i = 0; i < loop_count; i++) { 3922 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); 3923 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); 3924 addr = r_addr; 3925 for (k = 0; k < r_cnt; k++) { 3926 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); 3927 *data_ptr++ = cpu_to_le32(r_value); 3928 addr += cache_hdr->read_ctrl.read_addr_stride; 3929 } 3930 t_value += cache_hdr->addr_ctrl.tag_value_stride; 3931 } 3932 *d_ptr = data_ptr; 3933} 3934 3935static void 3936qla82xx_minidump_process_queue(scsi_qla_host_t *vha, 3937 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3938{ 3939 struct qla_hw_data *ha = vha->hw; 3940 uint32_t s_addr, r_addr; 3941 uint32_t r_stride, r_value, r_cnt, qid = 0; 3942 uint32_t i, k, loop_cnt; 3943 struct qla82xx_md_entry_queue *q_hdr; 3944 uint32_t *data_ptr = *d_ptr; 3945 3946 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; 3947 s_addr = q_hdr->select_addr; 3948 r_cnt = q_hdr->rd_strd.read_addr_cnt; 3949 r_stride = q_hdr->rd_strd.read_addr_stride; 3950 loop_cnt = q_hdr->op_count; 3951 3952 for (i = 0; i < loop_cnt; i++) { 3953 qla82xx_md_rw_32(ha, s_addr, qid, 1); 3954 r_addr = q_hdr->read_addr; 3955 for (k = 0; k < r_cnt; k++) { 3956 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); 3957 *data_ptr++ = cpu_to_le32(r_value); 3958 r_addr += r_stride; 3959 } 3960 qid += q_hdr->q_strd.queue_id_stride; 3961 } 3962 *d_ptr = data_ptr; 3963} 3964 3965static void 3966qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, 3967 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3968{ 3969 struct qla_hw_data *ha = vha->hw; 3970 uint32_t r_addr, r_value; 3971 uint32_t i, loop_cnt; 3972 struct qla82xx_md_entry_rdrom *rom_hdr; 3973 uint32_t *data_ptr = *d_ptr; 3974 3975 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; 3976 r_addr = rom_hdr->read_addr; 3977 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 3978 3979 for (i = 0; i < loop_cnt; i++) { 3980 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 3981 (r_addr & 0xFFFF0000), 1); 3982 r_value = qla82xx_md_rw_32(ha, 3983 MD_DIRECT_ROM_READ_BASE + 3984 (r_addr & 0x0000FFFF), 0, 0); 3985 *data_ptr++ = cpu_to_le32(r_value); 3986 r_addr += sizeof(uint32_t); 3987 } 3988 *d_ptr = data_ptr; 3989} 3990 3991static int 3992qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, 3993 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) 3994{ 3995 struct qla_hw_data *ha = vha->hw; 3996 uint32_t r_addr, r_value, r_data; 3997 uint32_t i, j, loop_cnt; 3998 struct qla82xx_md_entry_rdmem *m_hdr; 3999 unsigned long flags; 4000 int rval = QLA_FUNCTION_FAILED; 4001 uint32_t *data_ptr = *d_ptr; 4002 4003 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; 4004 r_addr = m_hdr->read_addr; 4005 loop_cnt = m_hdr->read_data_size/16; 4006 4007 if (r_addr & 0xf) { 4008 ql_log(ql_log_warn, vha, 0xb033, 4009 "Read addr 0x%x not 16 bytes alligned\n", r_addr); 4010 return rval; 4011 } 4012 4013 if (m_hdr->read_data_size % 16) { 4014 ql_log(ql_log_warn, vha, 0xb034, 4015 "Read data[0x%x] not multiple of 16 bytes\n", 4016 m_hdr->read_data_size); 4017 return rval; 4018 } 4019 4020 ql_dbg(ql_dbg_p3p, vha, 0xb035, 4021 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 4022 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 4023 4024 write_lock_irqsave(&ha->hw_lock, flags); 4025 for (i = 0; i < loop_cnt; i++) { 4026 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 4027 r_value = 0; 4028 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 4029 r_value = MIU_TA_CTL_ENABLE; 4030 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4031 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 4032 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 4033 4034 for (j = 0; j < MAX_CTL_CHECK; j++) { 4035 r_value = qla82xx_md_rw_32(ha, 4036 MD_MIU_TEST_AGT_CTRL, 0, 0); 4037 if ((r_value & MIU_TA_CTL_BUSY) == 0) 4038 break; 4039 } 4040 4041 if (j >= MAX_CTL_CHECK) { 4042 printk_ratelimited(KERN_ERR 4043 "failed to read through agent\n"); 4044 write_unlock_irqrestore(&ha->hw_lock, flags); 4045 return rval; 4046 } 4047 4048 for (j = 0; j < 4; j++) { 4049 r_data = qla82xx_md_rw_32(ha, 4050 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); 4051 *data_ptr++ = cpu_to_le32(r_data); 4052 } 4053 r_addr += 16; 4054 } 4055 write_unlock_irqrestore(&ha->hw_lock, flags); 4056 *d_ptr = data_ptr; 4057 return QLA_SUCCESS; 4058} 4059 4060static int 4061qla82xx_validate_template_chksum(scsi_qla_host_t *vha) 4062{ 4063 struct qla_hw_data *ha = vha->hw; 4064 uint64_t chksum = 0; 4065 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; 4066 int count = ha->md_template_size/sizeof(uint32_t); 4067 4068 while (count-- > 0) 4069 chksum += *d_ptr++; 4070 while (chksum >> 32) 4071 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); 4072 return ~chksum; 4073} 4074 4075static void 4076qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, 4077 qla82xx_md_entry_hdr_t *entry_hdr, int index) 4078{ 4079 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 4080 ql_dbg(ql_dbg_p3p, vha, 0xb036, 4081 "Skipping entry[%d]: " 4082 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4083 index, entry_hdr->entry_type, 4084 entry_hdr->d_ctrl.entry_capture_mask); 4085} 4086 4087int 4088qla82xx_md_collect(scsi_qla_host_t *vha) 4089{ 4090 struct qla_hw_data *ha = vha->hw; 4091 int no_entry_hdr = 0; 4092 qla82xx_md_entry_hdr_t *entry_hdr; 4093 struct qla82xx_md_template_hdr *tmplt_hdr; 4094 uint32_t *data_ptr; 4095 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; 4096 int i = 0, rval = QLA_FUNCTION_FAILED; 4097 4098 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4099 data_ptr = (uint32_t *)ha->md_dump; 4100 4101 if (ha->fw_dumped) { 4102 ql_log(ql_log_warn, vha, 0xb037, 4103 "Firmware has been previously dumped (%p) " 4104 "-- ignoring request.\n", ha->fw_dump); 4105 goto md_failed; 4106 } 4107 4108 ha->fw_dumped = 0; 4109 4110 if (!ha->md_tmplt_hdr || !ha->md_dump) { 4111 ql_log(ql_log_warn, vha, 0xb038, 4112 "Memory not allocated for minidump capture\n"); 4113 goto md_failed; 4114 } 4115 4116 if (qla82xx_validate_template_chksum(vha)) { 4117 ql_log(ql_log_info, vha, 0xb039, 4118 "Template checksum validation error\n"); 4119 goto md_failed; 4120 } 4121 4122 no_entry_hdr = tmplt_hdr->num_of_entries; 4123 ql_dbg(ql_dbg_p3p, vha, 0xb03a, 4124 "No of entry headers in Template: 0x%x\n", no_entry_hdr); 4125 4126 ql_dbg(ql_dbg_p3p, vha, 0xb03b, 4127 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 4128 4129 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 4130 4131 /* Validate whether required debug level is set */ 4132 if ((f_capture_mask & 0x3) != 0x3) { 4133 ql_log(ql_log_warn, vha, 0xb03c, 4134 "Minimum required capture mask[0x%x] level not set\n", 4135 f_capture_mask); 4136 goto md_failed; 4137 } 4138 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 4139 4140 tmplt_hdr->driver_info[0] = vha->host_no; 4141 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | 4142 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | 4143 QLA_DRIVER_BETA_VER; 4144 4145 total_data_size = ha->md_dump_size; 4146 4147 ql_dbg(ql_dbg_p3p, vha, 0xb03d, 4148 "Total minidump data_size 0x%x to be captured\n", total_data_size); 4149 4150 /* Check whether template obtained is valid */ 4151 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { 4152 ql_log(ql_log_warn, vha, 0xb04e, 4153 "Bad template header entry type: 0x%x obtained\n", 4154 tmplt_hdr->entry_type); 4155 goto md_failed; 4156 } 4157 4158 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4159 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 4160 4161 /* Walk through the entry headers */ 4162 for (i = 0; i < no_entry_hdr; i++) { 4163 4164 if (data_collected > total_data_size) { 4165 ql_log(ql_log_warn, vha, 0xb03e, 4166 "More MiniDump data collected: [0x%x]\n", 4167 data_collected); 4168 goto md_failed; 4169 } 4170 4171 if (!(entry_hdr->d_ctrl.entry_capture_mask & 4172 ql2xmdcapmask)) { 4173 entry_hdr->d_ctrl.driver_flags |= 4174 QLA82XX_DBG_SKIPPED_FLAG; 4175 ql_dbg(ql_dbg_p3p, vha, 0xb03f, 4176 "Skipping entry[%d]: " 4177 "ETYPE[0x%x]-ELEVEL[0x%x]\n", 4178 i, entry_hdr->entry_type, 4179 entry_hdr->d_ctrl.entry_capture_mask); 4180 goto skip_nxt_entry; 4181 } 4182 4183 ql_dbg(ql_dbg_p3p, vha, 0xb040, 4184 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" 4185 "entry_type: 0x%x, captrue_mask: 0x%x\n", 4186 __func__, i, data_ptr, entry_hdr, 4187 entry_hdr->entry_type, 4188 entry_hdr->d_ctrl.entry_capture_mask); 4189 4190 ql_dbg(ql_dbg_p3p, vha, 0xb041, 4191 "Data collected: [0x%x], Dump size left:[0x%x]\n", 4192 data_collected, (ha->md_dump_size - data_collected)); 4193 4194 /* Decode the entry type and take 4195 * required action to capture debug data */ 4196 switch (entry_hdr->entry_type) { 4197 case QLA82XX_RDEND: 4198 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4199 break; 4200 case QLA82XX_CNTRL: 4201 rval = qla82xx_minidump_process_control(vha, 4202 entry_hdr, &data_ptr); 4203 if (rval != QLA_SUCCESS) { 4204 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4205 goto md_failed; 4206 } 4207 break; 4208 case QLA82XX_RDCRB: 4209 qla82xx_minidump_process_rdcrb(vha, 4210 entry_hdr, &data_ptr); 4211 break; 4212 case QLA82XX_RDMEM: 4213 rval = qla82xx_minidump_process_rdmem(vha, 4214 entry_hdr, &data_ptr); 4215 if (rval != QLA_SUCCESS) { 4216 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4217 goto md_failed; 4218 } 4219 break; 4220 case QLA82XX_BOARD: 4221 case QLA82XX_RDROM: 4222 qla82xx_minidump_process_rdrom(vha, 4223 entry_hdr, &data_ptr); 4224 break; 4225 case QLA82XX_L2DTG: 4226 case QLA82XX_L2ITG: 4227 case QLA82XX_L2DAT: 4228 case QLA82XX_L2INS: 4229 rval = qla82xx_minidump_process_l2tag(vha, 4230 entry_hdr, &data_ptr); 4231 if (rval != QLA_SUCCESS) { 4232 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4233 goto md_failed; 4234 } 4235 break; 4236 case QLA82XX_L1DAT: 4237 case QLA82XX_L1INS: 4238 qla82xx_minidump_process_l1cache(vha, 4239 entry_hdr, &data_ptr); 4240 break; 4241 case QLA82XX_RDOCM: 4242 qla82xx_minidump_process_rdocm(vha, 4243 entry_hdr, &data_ptr); 4244 break; 4245 case QLA82XX_RDMUX: 4246 qla82xx_minidump_process_rdmux(vha, 4247 entry_hdr, &data_ptr); 4248 break; 4249 case QLA82XX_QUEUE: 4250 qla82xx_minidump_process_queue(vha, 4251 entry_hdr, &data_ptr); 4252 break; 4253 case QLA82XX_RDNOP: 4254 default: 4255 qla82xx_mark_entry_skipped(vha, entry_hdr, i); 4256 break; 4257 } 4258 4259 ql_dbg(ql_dbg_p3p, vha, 0xb042, 4260 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); 4261 4262 data_collected = (uint8_t *)data_ptr - 4263 (uint8_t *)ha->md_dump; 4264skip_nxt_entry: 4265 entry_hdr = (qla82xx_md_entry_hdr_t *) \ 4266 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 4267 } 4268 4269 if (data_collected != total_data_size) { 4270 ql_dbg(ql_dbg_p3p, vha, 0xb043, 4271 "MiniDump data mismatch: Data collected: [0x%x]," 4272 "total_data_size:[0x%x]\n", 4273 data_collected, total_data_size); 4274 goto md_failed; 4275 } 4276 4277 ql_log(ql_log_info, vha, 0xb044, 4278 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 4279 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 4280 ha->fw_dumped = 1; 4281 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 4282 4283md_failed: 4284 return rval; 4285} 4286 4287int 4288qla82xx_md_alloc(scsi_qla_host_t *vha) 4289{ 4290 struct qla_hw_data *ha = vha->hw; 4291 int i, k; 4292 struct qla82xx_md_template_hdr *tmplt_hdr; 4293 4294 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; 4295 4296 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { 4297 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; 4298 ql_log(ql_log_info, vha, 0xb045, 4299 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", 4300 ql2xmdcapmask); 4301 } 4302 4303 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { 4304 if (i & ql2xmdcapmask) 4305 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; 4306 } 4307 4308 if (ha->md_dump) { 4309 ql_log(ql_log_warn, vha, 0xb046, 4310 "Firmware dump previously allocated.\n"); 4311 return 1; 4312 } 4313 4314 ha->md_dump = vmalloc(ha->md_dump_size); 4315 if (ha->md_dump == NULL) { 4316 ql_log(ql_log_warn, vha, 0xb047, 4317 "Unable to allocate memory for Minidump size " 4318 "(0x%x).\n", ha->md_dump_size); 4319 return 1; 4320 } 4321 return 0; 4322} 4323 4324void 4325qla82xx_md_free(scsi_qla_host_t *vha) 4326{ 4327 struct qla_hw_data *ha = vha->hw; 4328 4329 /* Release the template header allocated */ 4330 if (ha->md_tmplt_hdr) { 4331 ql_log(ql_log_info, vha, 0xb048, 4332 "Free MiniDump template: %p, size (%d KB)\n", 4333 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4334 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4335 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4336 ha->md_tmplt_hdr = 0; 4337 } 4338 4339 /* Release the template data buffer allocated */ 4340 if (ha->md_dump) { 4341 ql_log(ql_log_info, vha, 0xb049, 4342 "Free MiniDump memory: %p, size (%d KB)\n", 4343 ha->md_dump, ha->md_dump_size / 1024); 4344 vfree(ha->md_dump); 4345 ha->md_dump_size = 0; 4346 ha->md_dump = 0; 4347 } 4348} 4349 4350void 4351qla82xx_md_prep(scsi_qla_host_t *vha) 4352{ 4353 struct qla_hw_data *ha = vha->hw; 4354 int rval; 4355 4356 /* Get Minidump template size */ 4357 rval = qla82xx_md_get_template_size(vha); 4358 if (rval == QLA_SUCCESS) { 4359 ql_log(ql_log_info, vha, 0xb04a, 4360 "MiniDump Template size obtained (%d KB)\n", 4361 ha->md_template_size / 1024); 4362 4363 /* Get Minidump template */ 4364 rval = qla82xx_md_get_template(vha); 4365 if (rval == QLA_SUCCESS) { 4366 ql_dbg(ql_dbg_p3p, vha, 0xb04b, 4367 "MiniDump Template obtained\n"); 4368 4369 /* Allocate memory for minidump */ 4370 rval = qla82xx_md_alloc(vha); 4371 if (rval == QLA_SUCCESS) 4372 ql_log(ql_log_info, vha, 0xb04c, 4373 "MiniDump memory allocated (%d KB)\n", 4374 ha->md_dump_size / 1024); 4375 else { 4376 ql_log(ql_log_info, vha, 0xb04d, 4377 "Free MiniDump template: %p, size: (%d KB)\n", 4378 ha->md_tmplt_hdr, 4379 ha->md_template_size / 1024); 4380 dma_free_coherent(&ha->pdev->dev, 4381 ha->md_template_size, 4382 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4383 ha->md_tmplt_hdr = 0; 4384 } 4385 4386 } 4387 } 4388} 4389 4390int 4391qla82xx_beacon_on(struct scsi_qla_host *vha) 4392{ 4393 4394 int rval; 4395 struct qla_hw_data *ha = vha->hw; 4396 qla82xx_idc_lock(ha); 4397 rval = qla82xx_mbx_beacon_ctl(vha, 1); 4398 4399 if (rval) { 4400 ql_log(ql_log_warn, vha, 0xb050, 4401 "mbx set led config failed in %s\n", __func__); 4402 goto exit; 4403 } 4404 ha->beacon_blink_led = 1; 4405exit: 4406 qla82xx_idc_unlock(ha); 4407 return rval; 4408} 4409 4410int 4411qla82xx_beacon_off(struct scsi_qla_host *vha) 4412{ 4413 4414 int rval; 4415 struct qla_hw_data *ha = vha->hw; 4416 qla82xx_idc_lock(ha); 4417 rval = qla82xx_mbx_beacon_ctl(vha, 0); 4418 4419 if (rval) { 4420 ql_log(ql_log_warn, vha, 0xb051, 4421 "mbx set led config failed in %s\n", __func__); 4422 goto exit; 4423 } 4424 ha->beacon_blink_led = 0; 4425exit: 4426 qla82xx_idc_unlock(ha); 4427 return rval; 4428} 4429