driver_chipcommon_pmu.c revision c35deb4e70d52ed564c58569fe059dd7ca5f4eec
1/* 2 * Sonics Silicon Backplane 3 * Broadcom ChipCommon Power Management Unit driver 4 * 5 * Copyright 2009, Michael Buesch <mb@bu3sch.de> 6 * Copyright 2007, Broadcom Corporation 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11#include <linux/ssb/ssb.h> 12#include <linux/ssb/ssb_regs.h> 13#include <linux/ssb/ssb_driver_chipcommon.h> 14#include <linux/delay.h> 15 16#include "ssb_private.h" 17 18static u32 ssb_chipco_pll_read(struct ssb_chipcommon *cc, u32 offset) 19{ 20 chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset); 21 return chipco_read32(cc, SSB_CHIPCO_PLLCTL_DATA); 22} 23 24static void ssb_chipco_pll_write(struct ssb_chipcommon *cc, 25 u32 offset, u32 value) 26{ 27 chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset); 28 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value); 29} 30 31static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc, 32 u32 offset, u32 mask, u32 set) 33{ 34 u32 value; 35 36 chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR); 37 chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset); 38 chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR); 39 value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA); 40 value &= mask; 41 value |= set; 42 chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value); 43 chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA); 44} 45 46struct pmu0_plltab_entry { 47 u16 freq; /* Crystal frequency in kHz.*/ 48 u8 xf; /* Crystal frequency value for PMU control */ 49 u8 wb_int; 50 u32 wb_frac; 51}; 52 53static const struct pmu0_plltab_entry pmu0_plltab[] = { 54 { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, }, 55 { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, }, 56 { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, }, 57 { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, }, 58 { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, }, 59 { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, }, 60 { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, }, 61 { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, }, 62 { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, }, 63 { .freq = 25000, .xf = 10, .wb_int = 70, .wb_frac = 419430, }, 64 { .freq = 26000, .xf = 11, .wb_int = 67, .wb_frac = 725937, }, 65 { .freq = 30000, .xf = 12, .wb_int = 58, .wb_frac = 699050, }, 66 { .freq = 38400, .xf = 13, .wb_int = 45, .wb_frac = 873813, }, 67 { .freq = 40000, .xf = 14, .wb_int = 45, .wb_frac = 0, }, 68}; 69#define SSB_PMU0_DEFAULT_XTALFREQ 20000 70 71static const struct pmu0_plltab_entry * pmu0_plltab_find_entry(u32 crystalfreq) 72{ 73 const struct pmu0_plltab_entry *e; 74 unsigned int i; 75 76 for (i = 0; i < ARRAY_SIZE(pmu0_plltab); i++) { 77 e = &pmu0_plltab[i]; 78 if (e->freq == crystalfreq) 79 return e; 80 } 81 82 return NULL; 83} 84 85/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */ 86static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc, 87 u32 crystalfreq) 88{ 89 struct ssb_bus *bus = cc->dev->bus; 90 const struct pmu0_plltab_entry *e = NULL; 91 u32 pmuctl, tmp, pllctl; 92 unsigned int i; 93 94 if ((bus->chip_id == 0x5354) && !crystalfreq) { 95 /* The 5354 crystal freq is 25MHz */ 96 crystalfreq = 25000; 97 } 98 if (crystalfreq) 99 e = pmu0_plltab_find_entry(crystalfreq); 100 if (!e) 101 e = pmu0_plltab_find_entry(SSB_PMU0_DEFAULT_XTALFREQ); 102 BUG_ON(!e); 103 crystalfreq = e->freq; 104 cc->pmu.crystalfreq = e->freq; 105 106 /* Check if the PLL already is programmed to this frequency. */ 107 pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL); 108 if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) { 109 /* We're already there... */ 110 return; 111 } 112 113 ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n", 114 (crystalfreq / 1000), (crystalfreq % 1000)); 115 116 /* First turn the PLL off. */ 117 switch (bus->chip_id) { 118 case 0x4328: 119 chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 120 ~(1 << SSB_PMURES_4328_BB_PLL_PU)); 121 chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, 122 ~(1 << SSB_PMURES_4328_BB_PLL_PU)); 123 break; 124 case 0x5354: 125 chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 126 ~(1 << SSB_PMURES_5354_BB_PLL_PU)); 127 chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, 128 ~(1 << SSB_PMURES_5354_BB_PLL_PU)); 129 break; 130 default: 131 SSB_WARN_ON(1); 132 } 133 for (i = 1500; i; i--) { 134 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); 135 if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)) 136 break; 137 udelay(10); 138 } 139 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); 140 if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT) 141 ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n"); 142 143 /* Set PDIV in PLL control 0. */ 144 pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0); 145 if (crystalfreq >= SSB_PMU0_PLLCTL0_PDIV_FREQ) 146 pllctl |= SSB_PMU0_PLLCTL0_PDIV_MSK; 147 else 148 pllctl &= ~SSB_PMU0_PLLCTL0_PDIV_MSK; 149 ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl); 150 151 /* Set WILD in PLL control 1. */ 152 pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL1); 153 pllctl &= ~SSB_PMU0_PLLCTL1_STOPMOD; 154 pllctl &= ~(SSB_PMU0_PLLCTL1_WILD_IMSK | SSB_PMU0_PLLCTL1_WILD_FMSK); 155 pllctl |= ((u32)e->wb_int << SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_IMSK; 156 pllctl |= ((u32)e->wb_frac << SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_FMSK; 157 if (e->wb_frac == 0) 158 pllctl |= SSB_PMU0_PLLCTL1_STOPMOD; 159 ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl); 160 161 /* Set WILD in PLL control 2. */ 162 pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL2); 163 pllctl &= ~SSB_PMU0_PLLCTL2_WILD_IMSKHI; 164 pllctl |= (((u32)e->wb_int >> 4) << SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT) & SSB_PMU0_PLLCTL2_WILD_IMSKHI; 165 ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl); 166 167 /* Set the crystalfrequency and the divisor. */ 168 pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL); 169 pmuctl &= ~SSB_CHIPCO_PMU_CTL_ILP_DIV; 170 pmuctl |= (((crystalfreq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT) 171 & SSB_CHIPCO_PMU_CTL_ILP_DIV; 172 pmuctl &= ~SSB_CHIPCO_PMU_CTL_XTALFREQ; 173 pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ; 174 chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl); 175} 176 177struct pmu1_plltab_entry { 178 u16 freq; /* Crystal frequency in kHz.*/ 179 u8 xf; /* Crystal frequency value for PMU control */ 180 u8 ndiv_int; 181 u32 ndiv_frac; 182 u8 p1div; 183 u8 p2div; 184}; 185 186static const struct pmu1_plltab_entry pmu1_plltab[] = { 187 { .freq = 12000, .xf = 1, .p1div = 3, .p2div = 22, .ndiv_int = 0x9, .ndiv_frac = 0xFFFFEF, }, 188 { .freq = 13000, .xf = 2, .p1div = 1, .p2div = 6, .ndiv_int = 0xb, .ndiv_frac = 0x483483, }, 189 { .freq = 14400, .xf = 3, .p1div = 1, .p2div = 10, .ndiv_int = 0xa, .ndiv_frac = 0x1C71C7, }, 190 { .freq = 15360, .xf = 4, .p1div = 1, .p2div = 5, .ndiv_int = 0xb, .ndiv_frac = 0x755555, }, 191 { .freq = 16200, .xf = 5, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x6E9E06, }, 192 { .freq = 16800, .xf = 6, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x3CF3CF, }, 193 { .freq = 19200, .xf = 7, .p1div = 1, .p2div = 9, .ndiv_int = 0x5, .ndiv_frac = 0x17B425, }, 194 { .freq = 19800, .xf = 8, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0xA57EB, }, 195 { .freq = 20000, .xf = 9, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0, }, 196 { .freq = 24000, .xf = 10, .p1div = 3, .p2div = 11, .ndiv_int = 0xa, .ndiv_frac = 0, }, 197 { .freq = 25000, .xf = 11, .p1div = 5, .p2div = 16, .ndiv_int = 0xb, .ndiv_frac = 0, }, 198 { .freq = 26000, .xf = 12, .p1div = 1, .p2div = 2, .ndiv_int = 0x10, .ndiv_frac = 0xEC4EC4, }, 199 { .freq = 30000, .xf = 13, .p1div = 3, .p2div = 8, .ndiv_int = 0xb, .ndiv_frac = 0, }, 200 { .freq = 38400, .xf = 14, .p1div = 1, .p2div = 5, .ndiv_int = 0x4, .ndiv_frac = 0x955555, }, 201 { .freq = 40000, .xf = 15, .p1div = 1, .p2div = 2, .ndiv_int = 0xb, .ndiv_frac = 0, }, 202}; 203 204#define SSB_PMU1_DEFAULT_XTALFREQ 15360 205 206static const struct pmu1_plltab_entry * pmu1_plltab_find_entry(u32 crystalfreq) 207{ 208 const struct pmu1_plltab_entry *e; 209 unsigned int i; 210 211 for (i = 0; i < ARRAY_SIZE(pmu1_plltab); i++) { 212 e = &pmu1_plltab[i]; 213 if (e->freq == crystalfreq) 214 return e; 215 } 216 217 return NULL; 218} 219 220/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */ 221static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc, 222 u32 crystalfreq) 223{ 224 struct ssb_bus *bus = cc->dev->bus; 225 const struct pmu1_plltab_entry *e = NULL; 226 u32 buffer_strength = 0; 227 u32 tmp, pllctl, pmuctl; 228 unsigned int i; 229 230 if (bus->chip_id == 0x4312) { 231 /* We do not touch the BCM4312 PLL and assume 232 * the default crystal settings work out-of-the-box. */ 233 cc->pmu.crystalfreq = 20000; 234 return; 235 } 236 237 if (crystalfreq) 238 e = pmu1_plltab_find_entry(crystalfreq); 239 if (!e) 240 e = pmu1_plltab_find_entry(SSB_PMU1_DEFAULT_XTALFREQ); 241 BUG_ON(!e); 242 crystalfreq = e->freq; 243 cc->pmu.crystalfreq = e->freq; 244 245 /* Check if the PLL already is programmed to this frequency. */ 246 pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL); 247 if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) { 248 /* We're already there... */ 249 return; 250 } 251 252 ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n", 253 (crystalfreq / 1000), (crystalfreq % 1000)); 254 255 /* First turn the PLL off. */ 256 switch (bus->chip_id) { 257 case 0x4325: 258 chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 259 ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) | 260 (1 << SSB_PMURES_4325_HT_AVAIL))); 261 chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, 262 ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) | 263 (1 << SSB_PMURES_4325_HT_AVAIL))); 264 /* Adjust the BBPLL to 2 on all channels later. */ 265 buffer_strength = 0x222222; 266 break; 267 default: 268 SSB_WARN_ON(1); 269 } 270 for (i = 1500; i; i--) { 271 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); 272 if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)) 273 break; 274 udelay(10); 275 } 276 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); 277 if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT) 278 ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n"); 279 280 /* Set p1div and p2div. */ 281 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0); 282 pllctl &= ~(SSB_PMU1_PLLCTL0_P1DIV | SSB_PMU1_PLLCTL0_P2DIV); 283 pllctl |= ((u32)e->p1div << SSB_PMU1_PLLCTL0_P1DIV_SHIFT) & SSB_PMU1_PLLCTL0_P1DIV; 284 pllctl |= ((u32)e->p2div << SSB_PMU1_PLLCTL0_P2DIV_SHIFT) & SSB_PMU1_PLLCTL0_P2DIV; 285 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl); 286 287 /* Set ndiv int and ndiv mode */ 288 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL2); 289 pllctl &= ~(SSB_PMU1_PLLCTL2_NDIVINT | SSB_PMU1_PLLCTL2_NDIVMODE); 290 pllctl |= ((u32)e->ndiv_int << SSB_PMU1_PLLCTL2_NDIVINT_SHIFT) & SSB_PMU1_PLLCTL2_NDIVINT; 291 pllctl |= (1 << SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT) & SSB_PMU1_PLLCTL2_NDIVMODE; 292 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, pllctl); 293 294 /* Set ndiv frac */ 295 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL3); 296 pllctl &= ~SSB_PMU1_PLLCTL3_NDIVFRAC; 297 pllctl |= ((u32)e->ndiv_frac << SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT) & SSB_PMU1_PLLCTL3_NDIVFRAC; 298 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, pllctl); 299 300 /* Change the drive strength, if required. */ 301 if (buffer_strength) { 302 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL5); 303 pllctl &= ~SSB_PMU1_PLLCTL5_CLKDRV; 304 pllctl |= (buffer_strength << SSB_PMU1_PLLCTL5_CLKDRV_SHIFT) & SSB_PMU1_PLLCTL5_CLKDRV; 305 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, pllctl); 306 } 307 308 /* Tune the crystalfreq and the divisor. */ 309 pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL); 310 pmuctl &= ~(SSB_CHIPCO_PMU_CTL_ILP_DIV | SSB_CHIPCO_PMU_CTL_XTALFREQ); 311 pmuctl |= ((((u32)e->freq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT) 312 & SSB_CHIPCO_PMU_CTL_ILP_DIV; 313 pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ; 314 chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl); 315} 316 317static void ssb_pmu_pll_init(struct ssb_chipcommon *cc) 318{ 319 struct ssb_bus *bus = cc->dev->bus; 320 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */ 321 322 if (bus->bustype == SSB_BUSTYPE_SSB) { 323 /* TODO: The user may override the crystal frequency. */ 324 } 325 326 switch (bus->chip_id) { 327 case 0x4312: 328 case 0x4325: 329 ssb_pmu1_pllinit_r0(cc, crystalfreq); 330 break; 331 case 0x4328: 332 case 0x5354: 333 ssb_pmu0_pllinit_r0(cc, crystalfreq); 334 break; 335 case 0x4322: 336 if (cc->pmu.rev == 2) { 337 chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A); 338 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0); 339 } 340 break; 341 default: 342 ssb_printk(KERN_ERR PFX 343 "ERROR: PLL init unknown for device %04X\n", 344 bus->chip_id); 345 } 346} 347 348struct pmu_res_updown_tab_entry { 349 u8 resource; /* The resource number */ 350 u16 updown; /* The updown value */ 351}; 352 353enum pmu_res_depend_tab_task { 354 PMU_RES_DEP_SET = 1, 355 PMU_RES_DEP_ADD, 356 PMU_RES_DEP_REMOVE, 357}; 358 359struct pmu_res_depend_tab_entry { 360 u8 resource; /* The resource number */ 361 u8 task; /* SET | ADD | REMOVE */ 362 u32 depend; /* The depend mask */ 363}; 364 365static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4328a0[] = { 366 { .resource = SSB_PMURES_4328_EXT_SWITCHER_PWM, .updown = 0x0101, }, 367 { .resource = SSB_PMURES_4328_BB_SWITCHER_PWM, .updown = 0x1F01, }, 368 { .resource = SSB_PMURES_4328_BB_SWITCHER_BURST, .updown = 0x010F, }, 369 { .resource = SSB_PMURES_4328_BB_EXT_SWITCHER_BURST, .updown = 0x0101, }, 370 { .resource = SSB_PMURES_4328_ILP_REQUEST, .updown = 0x0202, }, 371 { .resource = SSB_PMURES_4328_RADIO_SWITCHER_PWM, .updown = 0x0F01, }, 372 { .resource = SSB_PMURES_4328_RADIO_SWITCHER_BURST, .updown = 0x0F01, }, 373 { .resource = SSB_PMURES_4328_ROM_SWITCH, .updown = 0x0101, }, 374 { .resource = SSB_PMURES_4328_PA_REF_LDO, .updown = 0x0F01, }, 375 { .resource = SSB_PMURES_4328_RADIO_LDO, .updown = 0x0F01, }, 376 { .resource = SSB_PMURES_4328_AFE_LDO, .updown = 0x0F01, }, 377 { .resource = SSB_PMURES_4328_PLL_LDO, .updown = 0x0F01, }, 378 { .resource = SSB_PMURES_4328_BG_FILTBYP, .updown = 0x0101, }, 379 { .resource = SSB_PMURES_4328_TX_FILTBYP, .updown = 0x0101, }, 380 { .resource = SSB_PMURES_4328_RX_FILTBYP, .updown = 0x0101, }, 381 { .resource = SSB_PMURES_4328_XTAL_PU, .updown = 0x0101, }, 382 { .resource = SSB_PMURES_4328_XTAL_EN, .updown = 0xA001, }, 383 { .resource = SSB_PMURES_4328_BB_PLL_FILTBYP, .updown = 0x0101, }, 384 { .resource = SSB_PMURES_4328_RF_PLL_FILTBYP, .updown = 0x0101, }, 385 { .resource = SSB_PMURES_4328_BB_PLL_PU, .updown = 0x0701, }, 386}; 387 388static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4328a0[] = { 389 { 390 /* Adjust ILP Request to avoid forcing EXT/BB into burst mode. */ 391 .resource = SSB_PMURES_4328_ILP_REQUEST, 392 .task = PMU_RES_DEP_SET, 393 .depend = ((1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) | 394 (1 << SSB_PMURES_4328_BB_SWITCHER_PWM)), 395 }, 396}; 397 398static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4325a0[] = { 399 { .resource = SSB_PMURES_4325_XTAL_PU, .updown = 0x1501, }, 400}; 401 402static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4325a0[] = { 403 { 404 /* Adjust HT-Available dependencies. */ 405 .resource = SSB_PMURES_4325_HT_AVAIL, 406 .task = PMU_RES_DEP_ADD, 407 .depend = ((1 << SSB_PMURES_4325_RX_PWRSW_PU) | 408 (1 << SSB_PMURES_4325_TX_PWRSW_PU) | 409 (1 << SSB_PMURES_4325_LOGEN_PWRSW_PU) | 410 (1 << SSB_PMURES_4325_AFE_PWRSW_PU)), 411 }, 412}; 413 414static void ssb_pmu_resources_init(struct ssb_chipcommon *cc) 415{ 416 struct ssb_bus *bus = cc->dev->bus; 417 u32 min_msk = 0, max_msk = 0; 418 unsigned int i; 419 const struct pmu_res_updown_tab_entry *updown_tab = NULL; 420 unsigned int updown_tab_size; 421 const struct pmu_res_depend_tab_entry *depend_tab = NULL; 422 unsigned int depend_tab_size; 423 424 switch (bus->chip_id) { 425 case 0x4312: 426 case 0x4322: 427 /* We keep the default settings: 428 * min_msk = 0xCBB 429 * max_msk = 0x7FFFF 430 */ 431 break; 432 case 0x4325: 433 /* Power OTP down later. */ 434 min_msk = (1 << SSB_PMURES_4325_CBUCK_BURST) | 435 (1 << SSB_PMURES_4325_LNLDO2_PU); 436 if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) & 437 SSB_CHIPCO_CHST_4325_PMUTOP_2B) 438 min_msk |= (1 << SSB_PMURES_4325_CLDO_CBUCK_BURST); 439 /* The PLL may turn on, if it decides so. */ 440 max_msk = 0xFFFFF; 441 updown_tab = pmu_res_updown_tab_4325a0; 442 updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4325a0); 443 depend_tab = pmu_res_depend_tab_4325a0; 444 depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4325a0); 445 break; 446 case 0x4328: 447 min_msk = (1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) | 448 (1 << SSB_PMURES_4328_BB_SWITCHER_PWM) | 449 (1 << SSB_PMURES_4328_XTAL_EN); 450 /* The PLL may turn on, if it decides so. */ 451 max_msk = 0xFFFFF; 452 updown_tab = pmu_res_updown_tab_4328a0; 453 updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4328a0); 454 depend_tab = pmu_res_depend_tab_4328a0; 455 depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4328a0); 456 break; 457 case 0x5354: 458 /* The PLL may turn on, if it decides so. */ 459 max_msk = 0xFFFFF; 460 break; 461 default: 462 ssb_printk(KERN_ERR PFX 463 "ERROR: PMU resource config unknown for device %04X\n", 464 bus->chip_id); 465 } 466 467 if (updown_tab) { 468 for (i = 0; i < updown_tab_size; i++) { 469 chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL, 470 updown_tab[i].resource); 471 chipco_write32(cc, SSB_CHIPCO_PMU_RES_UPDNTM, 472 updown_tab[i].updown); 473 } 474 } 475 if (depend_tab) { 476 for (i = 0; i < depend_tab_size; i++) { 477 chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL, 478 depend_tab[i].resource); 479 switch (depend_tab[i].task) { 480 case PMU_RES_DEP_SET: 481 chipco_write32(cc, SSB_CHIPCO_PMU_RES_DEPMSK, 482 depend_tab[i].depend); 483 break; 484 case PMU_RES_DEP_ADD: 485 chipco_set32(cc, SSB_CHIPCO_PMU_RES_DEPMSK, 486 depend_tab[i].depend); 487 break; 488 case PMU_RES_DEP_REMOVE: 489 chipco_mask32(cc, SSB_CHIPCO_PMU_RES_DEPMSK, 490 ~(depend_tab[i].depend)); 491 break; 492 default: 493 SSB_WARN_ON(1); 494 } 495 } 496 } 497 498 /* Set the resource masks. */ 499 if (min_msk) 500 chipco_write32(cc, SSB_CHIPCO_PMU_MINRES_MSK, min_msk); 501 if (max_msk) 502 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk); 503} 504 505/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */ 506void ssb_pmu_init(struct ssb_chipcommon *cc) 507{ 508 u32 pmucap; 509 510 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU)) 511 return; 512 513 pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP); 514 cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION); 515 516 ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n", 517 cc->pmu.rev, pmucap); 518 519 if (cc->pmu.rev == 1) 520 chipco_mask32(cc, SSB_CHIPCO_PMU_CTL, 521 ~SSB_CHIPCO_PMU_CTL_NOILPONW); 522 else 523 chipco_set32(cc, SSB_CHIPCO_PMU_CTL, 524 SSB_CHIPCO_PMU_CTL_NOILPONW); 525 ssb_pmu_pll_init(cc); 526 ssb_pmu_resources_init(cc); 527} 528 529void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc, 530 enum ssb_pmu_ldo_volt_id id, u32 voltage) 531{ 532 struct ssb_bus *bus = cc->dev->bus; 533 u32 addr, shift, mask; 534 535 switch (bus->chip_id) { 536 case 0x4328: 537 case 0x5354: 538 switch (id) { 539 case LDO_VOLT1: 540 addr = 2; 541 shift = 25; 542 mask = 0xF; 543 break; 544 case LDO_VOLT2: 545 addr = 3; 546 shift = 1; 547 mask = 0xF; 548 break; 549 case LDO_VOLT3: 550 addr = 3; 551 shift = 9; 552 mask = 0xF; 553 break; 554 case LDO_PAREF: 555 addr = 3; 556 shift = 17; 557 mask = 0x3F; 558 break; 559 default: 560 SSB_WARN_ON(1); 561 return; 562 } 563 break; 564 case 0x4312: 565 if (SSB_WARN_ON(id != LDO_PAREF)) 566 return; 567 addr = 0; 568 shift = 21; 569 mask = 0x3F; 570 break; 571 default: 572 return; 573 } 574 575 ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift), 576 (voltage & mask) << shift); 577} 578 579void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on) 580{ 581 struct ssb_bus *bus = cc->dev->bus; 582 int ldo; 583 584 switch (bus->chip_id) { 585 case 0x4312: 586 ldo = SSB_PMURES_4312_PA_REF_LDO; 587 break; 588 case 0x4328: 589 ldo = SSB_PMURES_4328_PA_REF_LDO; 590 break; 591 case 0x5354: 592 ldo = SSB_PMURES_5354_PA_REF_LDO; 593 break; 594 default: 595 return; 596 } 597 598 if (on) 599 chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo); 600 else 601 chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo)); 602 chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read? 603} 604 605EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage); 606EXPORT_SYMBOL(ssb_pmu_set_ldo_paref); 607