comedi.h revision b464f791caf66b6120c3cd8a77ad313ed532667a
1/* 2 include/comedi.h (installed as /usr/include/comedi.h) 3 header file for comedi 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU Lesser General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 22*/ 23 24#ifndef _COMEDI_H 25#define _COMEDI_H 26 27#define COMEDI_MAJORVERSION 0 28#define COMEDI_MINORVERSION 7 29#define COMEDI_MICROVERSION 76 30#define VERSION "0.7.76" 31 32/* comedi's major device number */ 33#define COMEDI_MAJOR 98 34 35/* 36 maximum number of minor devices. This can be increased, although 37 kernel structures are currently statically allocated, thus you 38 don't want this to be much more than you actually use. 39 */ 40#define COMEDI_NDEVICES 16 41 42/* number of config options in the config structure */ 43#define COMEDI_NDEVCONFOPTS 32 44/*length of nth chunk of firmware data*/ 45#define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25 46#define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26 47#define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27 48#define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28 49/* most significant 32 bits of pointer address (if needed) */ 50#define COMEDI_DEVCONF_AUX_DATA_HI 29 51/* least significant 32 bits of pointer address */ 52#define COMEDI_DEVCONF_AUX_DATA_LO 30 53#define COMEDI_DEVCONF_AUX_DATA_LENGTH 31 /* total data length */ 54 55/* max length of device and driver names */ 56#define COMEDI_NAMELEN 20 57 58/* packs and unpacks a channel/range number */ 59 60#define CR_PACK(chan, rng, aref) \ 61 ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan)) 62#define CR_PACK_FLAGS(chan, range, aref, flags) \ 63 (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK)) 64 65#define CR_CHAN(a) ((a)&0xffff) 66#define CR_RANGE(a) (((a)>>16)&0xff) 67#define CR_AREF(a) (((a)>>24)&0x03) 68 69#define CR_FLAGS_MASK 0xfc000000 70#define CR_ALT_FILTER (1<<26) 71#define CR_DITHER CR_ALT_FILTER 72#define CR_DEGLITCH CR_ALT_FILTER 73#define CR_ALT_SOURCE (1<<27) 74#define CR_EDGE (1<<30) 75#define CR_INVERT (1<<31) 76 77#define AREF_GROUND 0x00 /* analog ref = analog ground */ 78#define AREF_COMMON 0x01 /* analog ref = analog common */ 79#define AREF_DIFF 0x02 /* analog ref = differential */ 80#define AREF_OTHER 0x03 /* analog ref = other (undefined) */ 81 82/* counters -- these are arbitrary values */ 83#define GPCT_RESET 0x0001 84#define GPCT_SET_SOURCE 0x0002 85#define GPCT_SET_GATE 0x0004 86#define GPCT_SET_DIRECTION 0x0008 87#define GPCT_SET_OPERATION 0x0010 88#define GPCT_ARM 0x0020 89#define GPCT_DISARM 0x0040 90#define GPCT_GET_INT_CLK_FRQ 0x0080 91 92#define GPCT_INT_CLOCK 0x0001 93#define GPCT_EXT_PIN 0x0002 94#define GPCT_NO_GATE 0x0004 95#define GPCT_UP 0x0008 96#define GPCT_DOWN 0x0010 97#define GPCT_HWUD 0x0020 98#define GPCT_SIMPLE_EVENT 0x0040 99#define GPCT_SINGLE_PERIOD 0x0080 100#define GPCT_SINGLE_PW 0x0100 101#define GPCT_CONT_PULSE_OUT 0x0200 102#define GPCT_SINGLE_PULSE_OUT 0x0400 103 104/* instructions */ 105 106#define INSN_MASK_WRITE 0x8000000 107#define INSN_MASK_READ 0x4000000 108#define INSN_MASK_SPECIAL 0x2000000 109 110#define INSN_READ (0 | INSN_MASK_READ) 111#define INSN_WRITE (1 | INSN_MASK_WRITE) 112#define INSN_BITS (2 | INSN_MASK_READ|INSN_MASK_WRITE) 113#define INSN_CONFIG (3 | INSN_MASK_READ|INSN_MASK_WRITE) 114#define INSN_GTOD (4 | INSN_MASK_READ|INSN_MASK_SPECIAL) 115#define INSN_WAIT (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL) 116#define INSN_INTTRIG (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL) 117 118/* trigger flags */ 119/* These flags are used in comedi_trig structures */ 120 121#define TRIG_BOGUS 0x0001 /* do the motions */ 122#define TRIG_DITHER 0x0002 /* enable dithering */ 123#define TRIG_DEGLITCH 0x0004 /* enable deglitching */ 124 /*#define TRIG_RT 0x0008 *//* perform op in real time */ 125#define TRIG_CONFIG 0x0010 /* perform configuration, not triggering */ 126#define TRIG_WAKE_EOS 0x0020 /* wake up on end-of-scan events */ 127 /*#define TRIG_WRITE 0x0040*//* write to bidirectional devices */ 128 129/* command flags */ 130/* These flags are used in comedi_cmd structures */ 131 132/* try to use a real-time interrupt while performing command */ 133#define CMDF_PRIORITY 0x00000008 134 135#define TRIG_RT CMDF_PRIORITY /* compatibility definition */ 136 137#define CMDF_WRITE 0x00000040 138#define TRIG_WRITE CMDF_WRITE /* compatibility definition */ 139 140#define CMDF_RAWDATA 0x00000080 141 142#define COMEDI_EV_START 0x00040000 143#define COMEDI_EV_SCAN_BEGIN 0x00080000 144#define COMEDI_EV_CONVERT 0x00100000 145#define COMEDI_EV_SCAN_END 0x00200000 146#define COMEDI_EV_STOP 0x00400000 147 148#define TRIG_ROUND_MASK 0x00030000 149#define TRIG_ROUND_NEAREST 0x00000000 150#define TRIG_ROUND_DOWN 0x00010000 151#define TRIG_ROUND_UP 0x00020000 152#define TRIG_ROUND_UP_NEXT 0x00030000 153 154/* trigger sources */ 155 156#define TRIG_ANY 0xffffffff 157#define TRIG_INVALID 0x00000000 158 159#define TRIG_NONE 0x00000001 /* never trigger */ 160#define TRIG_NOW 0x00000002 /* trigger now + N ns */ 161#define TRIG_FOLLOW 0x00000004 /* trigger on next lower level trig */ 162#define TRIG_TIME 0x00000008 /* trigger at time N ns */ 163#define TRIG_TIMER 0x00000010 /* trigger at rate N ns */ 164#define TRIG_COUNT 0x00000020 /* trigger when count reaches N */ 165#define TRIG_EXT 0x00000040 /* trigger on external signal N */ 166#define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */ 167#define TRIG_OTHER 0x00000100 /* driver defined */ 168 169/* subdevice flags */ 170 171#define SDF_BUSY 0x0001 /* device is busy */ 172#define SDF_BUSY_OWNER 0x0002 /* device is busy with your job */ 173#define SDF_LOCKED 0x0004 /* subdevice is locked */ 174#define SDF_LOCK_OWNER 0x0008 /* you own lock */ 175#define SDF_MAXDATA 0x0010 /* maxdata depends on channel */ 176#define SDF_FLAGS 0x0020 /* flags depend on channel */ 177#define SDF_RANGETYPE 0x0040 /* range type depends on channel */ 178#define SDF_MODE0 0x0080 /* can do mode 0 */ 179#define SDF_MODE1 0x0100 /* can do mode 1 */ 180#define SDF_MODE2 0x0200 /* can do mode 2 */ 181#define SDF_MODE3 0x0400 /* can do mode 3 */ 182#define SDF_MODE4 0x0800 /* can do mode 4 */ 183#define SDF_CMD 0x1000 /* can do commands (deprecated) */ 184#define SDF_SOFT_CALIBRATED 0x2000 /* subdevice uses software calibration */ 185#define SDF_CMD_WRITE 0x4000 /* can do output commands */ 186#define SDF_CMD_READ 0x8000 /* can do input commands */ 187 188/* subdevice can be read (e.g. analog input) */ 189#define SDF_READABLE 0x00010000 190/* subdevice can be written (e.g. analog output) */ 191#define SDF_WRITABLE 0x00020000 192#define SDF_WRITEABLE SDF_WRITABLE /* spelling error in API */ 193/* subdevice does not have externally visible lines */ 194#define SDF_INTERNAL 0x00040000 195#define SDF_GROUND 0x00100000 /* can do aref=ground */ 196#define SDF_COMMON 0x00200000 /* can do aref=common */ 197#define SDF_DIFF 0x00400000 /* can do aref=diff */ 198#define SDF_OTHER 0x00800000 /* can do aref=other */ 199#define SDF_DITHER 0x01000000 /* can do dithering */ 200#define SDF_DEGLITCH 0x02000000 /* can do deglitching */ 201#define SDF_MMAP 0x04000000 /* can do mmap() */ 202#define SDF_RUNNING 0x08000000 /* subdevice is acquiring data */ 203#define SDF_LSAMPL 0x10000000 /* subdevice uses 32-bit samples */ 204#define SDF_PACKED 0x20000000 /* subdevice can do packed DIO */ 205/* re recyle these flags for PWM */ 206#define SDF_PWM_COUNTER SDF_MODE0 /* PWM can automatically switch off */ 207#define SDF_PWM_HBRIDGE SDF_MODE1 /* PWM is signed (H-bridge) */ 208 209/* subdevice types */ 210 211 enum comedi_subdevice_type { 212 COMEDI_SUBD_UNUSED, /* unused by driver */ 213 COMEDI_SUBD_AI, /* analog input */ 214 COMEDI_SUBD_AO, /* analog output */ 215 COMEDI_SUBD_DI, /* digital input */ 216 COMEDI_SUBD_DO, /* digital output */ 217 COMEDI_SUBD_DIO, /* digital input/output */ 218 COMEDI_SUBD_COUNTER, /* counter */ 219 COMEDI_SUBD_TIMER, /* timer */ 220 COMEDI_SUBD_MEMORY, /* memory, EEPROM, DPRAM */ 221 COMEDI_SUBD_CALIB, /* calibration DACs */ 222 COMEDI_SUBD_PROC, /* processor, DSP */ 223 COMEDI_SUBD_SERIAL, /* serial IO */ 224 COMEDI_SUBD_PWM /* PWM */ 225 }; 226 227/* configuration instructions */ 228 229 enum configuration_ids { 230 INSN_CONFIG_DIO_INPUT = 0, 231 INSN_CONFIG_DIO_OUTPUT = 1, 232 INSN_CONFIG_DIO_OPENDRAIN = 2, 233 INSN_CONFIG_ANALOG_TRIG = 16, 234/* INSN_CONFIG_WAVEFORM = 17, */ 235/* INSN_CONFIG_TRIG = 18, */ 236/* INSN_CONFIG_COUNTER = 19, */ 237 INSN_CONFIG_ALT_SOURCE = 20, 238 INSN_CONFIG_DIGITAL_TRIG = 21, 239 INSN_CONFIG_BLOCK_SIZE = 22, 240 INSN_CONFIG_TIMER_1 = 23, 241 INSN_CONFIG_FILTER = 24, 242 INSN_CONFIG_CHANGE_NOTIFY = 25, 243 244 /*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26, 245 INSN_CONFIG_BIDIRECTIONAL_DATA = 27, 246 INSN_CONFIG_DIO_QUERY = 28, 247 INSN_CONFIG_PWM_OUTPUT = 29, 248 INSN_CONFIG_GET_PWM_OUTPUT = 30, 249 INSN_CONFIG_ARM = 31, 250 INSN_CONFIG_DISARM = 32, 251 INSN_CONFIG_GET_COUNTER_STATUS = 33, 252 INSN_CONFIG_RESET = 34, 253 /* Use CTR as single pulsegenerator */ 254 INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, 255 /* Use CTR as pulsetraingenerator */ 256 INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002, 257 /* Use the counter as encoder */ 258 INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003, 259 INSN_CONFIG_SET_GATE_SRC = 2001, /* Set gate source */ 260 INSN_CONFIG_GET_GATE_SRC = 2002, /* Get gate source */ 261 /* Set master clock source */ 262 INSN_CONFIG_SET_CLOCK_SRC = 2003, 263 INSN_CONFIG_GET_CLOCK_SRC = 2004, /* Get master clock source */ 264 INSN_CONFIG_SET_OTHER_SRC = 2005, /* Set other source */ 265 /* INSN_CONFIG_GET_OTHER_SRC = 2006,*//* Get other source */ 266 /* Get size in bytes of subdevice's on-board fifos used during 267 * streaming input/output */ 268 INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006, 269 INSN_CONFIG_SET_COUNTER_MODE = 4097, 270 INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE, /* deprecated */ 271 INSN_CONFIG_8254_READ_STATUS = 4098, 272 INSN_CONFIG_SET_ROUTING = 4099, 273 INSN_CONFIG_GET_ROUTING = 4109, 274/* PWM */ 275 INSN_CONFIG_PWM_SET_PERIOD = 5000, /* sets frequency */ 276 INSN_CONFIG_PWM_GET_PERIOD = 5001, /* gets frequency */ 277 INSN_CONFIG_GET_PWM_STATUS = 5002, /* is it running? */ 278 /* sets H bridge: duty cycle and sign bit for a relay at the 279 * same time */ 280 INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, 281 /* gets H bridge data: duty cycle and the sign bit */ 282 INSN_CONFIG_PWM_GET_H_BRIDGE = 5004 283 }; 284 285 enum comedi_io_direction { 286 COMEDI_INPUT = 0, 287 COMEDI_OUTPUT = 1, 288 COMEDI_OPENDRAIN = 2 289 }; 290 291 enum comedi_support_level { 292 COMEDI_UNKNOWN_SUPPORT = 0, 293 COMEDI_SUPPORTED, 294 COMEDI_UNSUPPORTED 295 }; 296 297/* ioctls */ 298 299#define CIO 'd' 300#define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig) 301#define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo) 302#define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo) 303#define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo) 304#define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig) 305#define COMEDI_LOCK _IO(CIO, 5) 306#define COMEDI_UNLOCK _IO(CIO, 6) 307#define COMEDI_CANCEL _IO(CIO, 7) 308#define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo) 309#define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd) 310#define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd) 311#define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist) 312#define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn) 313#define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig) 314#define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo) 315#define COMEDI_POLL _IO(CIO, 15) 316 317/* structures */ 318 319 struct comedi_trig { 320 unsigned int subdev; /* subdevice */ 321 unsigned int mode; /* mode */ 322 unsigned int flags; 323 unsigned int n_chan; /* number of channels */ 324 unsigned int *chanlist; /* channel/range list */ 325 short *data; /* data list, size depends on subd flags */ 326 unsigned int n; /* number of scans */ 327 unsigned int trigsrc; 328 unsigned int trigvar; 329 unsigned int trigvar1; 330 unsigned int data_len; 331 unsigned int unused[3]; 332 }; 333 334 struct comedi_insn { 335 unsigned int insn; 336 unsigned int n; 337 unsigned int __user *data; 338 unsigned int subdev; 339 unsigned int chanspec; 340 unsigned int unused[3]; 341 }; 342 343 struct comedi_insnlist { 344 unsigned int n_insns; 345 struct comedi_insn __user *insns; 346 }; 347 348 struct comedi_cmd { 349 unsigned int subdev; 350 unsigned int flags; 351 352 unsigned int start_src; 353 unsigned int start_arg; 354 355 unsigned int scan_begin_src; 356 unsigned int scan_begin_arg; 357 358 unsigned int convert_src; 359 unsigned int convert_arg; 360 361 unsigned int scan_end_src; 362 unsigned int scan_end_arg; 363 364 unsigned int stop_src; 365 unsigned int stop_arg; 366 367 unsigned int __user *chanlist; /* channel/range list */ 368 unsigned int chanlist_len; 369 370 short __user *data; /* data list, size depends on subd flags */ 371 unsigned int data_len; 372 }; 373 374 struct comedi_chaninfo { 375 unsigned int subdev; 376 unsigned int __user *maxdata_list; 377 unsigned int __user *flaglist; 378 unsigned int __user *rangelist; 379 unsigned int unused[4]; 380 }; 381 382 struct comedi_rangeinfo { 383 unsigned int range_type; 384 void __user *range_ptr; 385 }; 386 387 struct comedi_krange { 388 int min; /* fixed point, multiply by 1e-6 */ 389 int max; /* fixed point, multiply by 1e-6 */ 390 unsigned int flags; 391 }; 392 393 struct comedi_subdinfo { 394 unsigned int type; 395 unsigned int n_chan; 396 unsigned int subd_flags; 397 unsigned int timer_type; 398 unsigned int len_chanlist; 399 unsigned int maxdata; 400 unsigned int flags; /* channel flags */ 401 unsigned int range_type; /* lookup in kernel */ 402 unsigned int settling_time_0; 403 /* see support_level enum for values */ 404 unsigned insn_bits_support; 405 unsigned int unused[8]; 406 }; 407 408 struct comedi_devinfo { 409 unsigned int version_code; 410 unsigned int n_subdevs; 411 char driver_name[COMEDI_NAMELEN]; 412 char board_name[COMEDI_NAMELEN]; 413 int read_subdevice; 414 int write_subdevice; 415 int unused[30]; 416 }; 417 418 struct comedi_devconfig { 419 char board_name[COMEDI_NAMELEN]; 420 int options[COMEDI_NDEVCONFOPTS]; 421 }; 422 423 struct comedi_bufconfig { 424 unsigned int subdevice; 425 unsigned int flags; 426 427 unsigned int maximum_size; 428 unsigned int size; 429 430 unsigned int unused[4]; 431 }; 432 433 struct comedi_bufinfo { 434 unsigned int subdevice; 435 unsigned int bytes_read; 436 437 unsigned int buf_write_ptr; 438 unsigned int buf_read_ptr; 439 unsigned int buf_write_count; 440 unsigned int buf_read_count; 441 442 unsigned int bytes_written; 443 444 unsigned int unused[4]; 445 }; 446 447/* range stuff */ 448 449#define __RANGE(a, b) ((((a)&0xffff)<<16)|((b)&0xffff)) 450 451#define RANGE_OFFSET(a) (((a)>>16)&0xffff) 452#define RANGE_LENGTH(b) ((b)&0xffff) 453 454#define RF_UNIT(flags) ((flags)&0xff) 455#define RF_EXTERNAL (1<<8) 456 457#define UNIT_volt 0 458#define UNIT_mA 1 459#define UNIT_none 2 460 461#define COMEDI_MIN_SPEED ((unsigned int)0xffffffff) 462 463/* callback stuff */ 464/* only relevant to kernel modules. */ 465 466#define COMEDI_CB_EOS 1 /* end of scan */ 467#define COMEDI_CB_EOA 2 /* end of acquisition */ 468#define COMEDI_CB_BLOCK 4 /* data has arrived: 469 * wakes up read() / write() */ 470#define COMEDI_CB_EOBUF 8 /* DEPRECATED: end of buffer */ 471#define COMEDI_CB_ERROR 16 /* card error during acquisition */ 472#define COMEDI_CB_OVERFLOW 32 /* buffer overflow/underflow */ 473 474/**********************************************************/ 475/* everything after this line is ALPHA */ 476/**********************************************************/ 477 478/* 479 8254 specific configuration. 480 481 It supports two config commands: 482 483 0 ID: INSN_CONFIG_SET_COUNTER_MODE 484 1 8254 Mode 485 I8254_MODE0, I8254_MODE1, ..., I8254_MODE5 486 OR'ed with: 487 I8254_BCD, I8254_BINARY 488 489 0 ID: INSN_CONFIG_8254_READ_STATUS 490 1 <-- Status byte returned here. 491 B7 = Output 492 B6 = NULL Count 493 B5 - B0 Current mode. 494 495*/ 496 497 enum i8254_mode { 498 I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */ 499 I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */ 500 I8254_MODE2 = (2 << 1), /* Rate generator */ 501 I8254_MODE3 = (3 << 1), /* Square wave mode */ 502 I8254_MODE4 = (4 << 1), /* Software triggered strobe */ 503 I8254_MODE5 = (5 << 1), /* Hardware triggered strobe 504 * (retriggerable) */ 505 I8254_BCD = 1, /* use binary-coded decimal instead of binary 506 * (pretty useless) */ 507 I8254_BINARY = 0 508 }; 509 510 static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel) 511 { 512 if (pfi_channel < 10) 513 return 0x1 + pfi_channel; 514 else 515 return 0xb + pfi_channel; 516 } static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel) { 517 if (rtsi_channel < 7) 518 return 0xb + rtsi_channel; 519 else 520 return 0x1b; 521 } 522/* mode bits for NI general-purpose counters, set with 523 * INSN_CONFIG_SET_COUNTER_MODE */ 524#define NI_GPCT_COUNTING_MODE_SHIFT 16 525#define NI_GPCT_INDEX_PHASE_BITSHIFT 20 526#define NI_GPCT_COUNTING_DIRECTION_SHIFT 24 527 enum ni_gpct_mode_bits { 528 NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4, 529 NI_GPCT_EDGE_GATE_MODE_MASK = 0x18, 530 NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0, 531 NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8, 532 NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10, 533 NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18, 534 NI_GPCT_STOP_MODE_MASK = 0x60, 535 NI_GPCT_STOP_ON_GATE_BITS = 0x00, 536 NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20, 537 NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40, 538 NI_GPCT_LOAD_B_SELECT_BIT = 0x80, 539 NI_GPCT_OUTPUT_MODE_MASK = 0x300, 540 NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100, 541 NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200, 542 NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300, 543 NI_GPCT_HARDWARE_DISARM_MASK = 0xc00, 544 NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000, 545 NI_GPCT_DISARM_AT_TC_BITS = 0x400, 546 NI_GPCT_DISARM_AT_GATE_BITS = 0x800, 547 NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00, 548 NI_GPCT_LOADING_ON_TC_BIT = 0x1000, 549 NI_GPCT_LOADING_ON_GATE_BIT = 0x4000, 550 NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT, 551 NI_GPCT_COUNTING_MODE_NORMAL_BITS = 552 0x0 << NI_GPCT_COUNTING_MODE_SHIFT, 553 NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS = 554 0x1 << NI_GPCT_COUNTING_MODE_SHIFT, 555 NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS = 556 0x2 << NI_GPCT_COUNTING_MODE_SHIFT, 557 NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS = 558 0x3 << NI_GPCT_COUNTING_MODE_SHIFT, 559 NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS = 560 0x4 << NI_GPCT_COUNTING_MODE_SHIFT, 561 NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS = 562 0x6 << NI_GPCT_COUNTING_MODE_SHIFT, 563 NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 564 NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS = 565 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT, 566 NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS = 567 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT, 568 NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS = 569 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT, 570 NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS = 571 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 572 NI_GPCT_INDEX_ENABLE_BIT = 0x400000, 573 NI_GPCT_COUNTING_DIRECTION_MASK = 574 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 575 NI_GPCT_COUNTING_DIRECTION_DOWN_BITS = 576 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 577 NI_GPCT_COUNTING_DIRECTION_UP_BITS = 578 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 579 NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS = 580 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 581 NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS = 582 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 583 NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000, 584 NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0, 585 NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000, 586 NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000, 587 NI_GPCT_OR_GATE_BIT = 0x10000000, 588 NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000 589 }; 590 591/* Bits for setting a clock source with 592 * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */ 593 enum ni_gpct_clock_source_bits { 594 NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f, 595 NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0, 596 NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1, 597 NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2, 598 NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3, 599 NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4, 600 NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5, 601 NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6, /* NI 660x-specific */ 602 NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7, 603 NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8, 604 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9, 605 NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000, 606 NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0, 607 NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, /* divide source by 2 */ 608 NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, /* divide source by 8 */ 609 NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000 610 }; 611 static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n) 612 { 613 /* NI 660x-specific */ 614 return 0x10 + n; 615 } 616 static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n) 617 { 618 return 0x18 + n; 619 } 620 static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n) 621 { 622 /* no pfi on NI 660x */ 623 return 0x20 + n; 624 } 625 626/* Possibilities for setting a gate source with 627INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters. 628May be bitwise-or'd with CR_EDGE or CR_INVERT. */ 629 enum ni_gpct_gate_select { 630 /* m-series gates */ 631 NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0, 632 NI_GPCT_AI_START2_GATE_SELECT = 0x12, 633 NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13, 634 NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14, 635 NI_GPCT_AI_START1_GATE_SELECT = 0x1c, 636 NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d, 637 NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e, 638 NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f, 639 /* more gates for 660x */ 640 NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100, 641 NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101, 642 /* more gates for 660x "second gate" */ 643 NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201, 644 NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e, 645 /* m-series "second gate" sources are unknown, 646 * we should add them here with an offset of 0x300 when 647 * known. */ 648 NI_GPCT_DISABLED_GATE_SELECT = 0x8000, 649 }; 650 static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n) 651 { 652 return 0x102 + n; 653 } 654 static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n) 655 { 656 return NI_USUAL_RTSI_SELECT(n); 657 } 658 static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n) 659 { 660 return NI_USUAL_PFI_SELECT(n); 661 } 662 static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n) 663 { 664 return 0x202 + n; 665 } 666 667/* Possibilities for setting a source with 668INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */ 669 enum ni_gpct_other_index { 670 NI_GPCT_SOURCE_ENCODER_A, 671 NI_GPCT_SOURCE_ENCODER_B, 672 NI_GPCT_SOURCE_ENCODER_Z 673 }; 674 enum ni_gpct_other_select { 675 /* m-series gates */ 676 /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */ 677 NI_GPCT_DISABLED_OTHER_SELECT = 0x8000, 678 }; 679 static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n) 680 { 681 return NI_USUAL_PFI_SELECT(n); 682 } 683 684/* start sources for ni general-purpose counters for use with 685INSN_CONFIG_ARM */ 686 enum ni_gpct_arm_source { 687 NI_GPCT_ARM_IMMEDIATE = 0x0, 688 NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter 689 * and the adjacent paired 690 * counter simultaneously */ 691 /* NI doesn't document bits for selecting hardware arm triggers. 692 * If the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least 693 * significant bits (3 bits for 660x or 5 bits for m-series) 694 * through to the hardware. This will at least allow someone to 695 * figure out what the bits do later. */ 696 NI_GPCT_ARM_UNKNOWN = 0x1000, 697 }; 698 699/* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */ 700 enum ni_gpct_filter_select { 701 NI_GPCT_FILTER_OFF = 0x0, 702 NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1, 703 NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2, 704 NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3, 705 NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4, 706 NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5, 707 NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6 708 }; 709 710/* PFI digital filtering options for ni m-series for use with 711 * INSN_CONFIG_FILTER. */ 712 enum ni_pfi_filter_select { 713 NI_PFI_FILTER_OFF = 0x0, 714 NI_PFI_FILTER_125ns = 0x1, 715 NI_PFI_FILTER_6425ns = 0x2, 716 NI_PFI_FILTER_2550us = 0x3 717 }; 718 719/* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */ 720 enum ni_mio_clock_source { 721 NI_MIO_INTERNAL_CLOCK = 0, 722 NI_MIO_RTSI_CLOCK = 1, /* doesn't work for m-series, use 723 NI_MIO_PLL_RTSI_CLOCK() */ 724 /* the NI_MIO_PLL_* sources are m-series only */ 725 NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2, 726 NI_MIO_PLL_PXI10_CLOCK = 3, 727 NI_MIO_PLL_RTSI0_CLOCK = 4 728 }; 729 static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel) 730 { 731 return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel; 732 } 733 734/* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING. 735 The numbers assigned are not arbitrary, they correspond to the bits required 736 to program the board. */ 737 enum ni_rtsi_routing { 738 NI_RTSI_OUTPUT_ADR_START1 = 0, 739 NI_RTSI_OUTPUT_ADR_START2 = 1, 740 NI_RTSI_OUTPUT_SCLKG = 2, 741 NI_RTSI_OUTPUT_DACUPDN = 3, 742 NI_RTSI_OUTPUT_DA_START1 = 4, 743 NI_RTSI_OUTPUT_G_SRC0 = 5, 744 NI_RTSI_OUTPUT_G_GATE0 = 6, 745 NI_RTSI_OUTPUT_RGOUT0 = 7, 746 NI_RTSI_OUTPUT_RTSI_BRD_0 = 8, 747 NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI 748 * clock on line 7 */ 749 }; 750 static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n) 751 { 752 return NI_RTSI_OUTPUT_RTSI_BRD_0 + n; 753 } 754 755/* Signals which can be routed to an NI PFI pin on an m-series board with 756 * INSN_CONFIG_SET_ROUTING. These numbers are also returned by 757 * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing 758 * cannot be changed. The numbers assigned are not arbitrary, they correspond 759 * to the bits required to program the board. */ 760 enum ni_pfi_routing { 761 NI_PFI_OUTPUT_PFI_DEFAULT = 0, 762 NI_PFI_OUTPUT_AI_START1 = 1, 763 NI_PFI_OUTPUT_AI_START2 = 2, 764 NI_PFI_OUTPUT_AI_CONVERT = 3, 765 NI_PFI_OUTPUT_G_SRC1 = 4, 766 NI_PFI_OUTPUT_G_GATE1 = 5, 767 NI_PFI_OUTPUT_AO_UPDATE_N = 6, 768 NI_PFI_OUTPUT_AO_START1 = 7, 769 NI_PFI_OUTPUT_AI_START_PULSE = 8, 770 NI_PFI_OUTPUT_G_SRC0 = 9, 771 NI_PFI_OUTPUT_G_GATE0 = 10, 772 NI_PFI_OUTPUT_EXT_STROBE = 11, 773 NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12, 774 NI_PFI_OUTPUT_GOUT0 = 13, 775 NI_PFI_OUTPUT_GOUT1 = 14, 776 NI_PFI_OUTPUT_FREQ_OUT = 15, 777 NI_PFI_OUTPUT_PFI_DO = 16, 778 NI_PFI_OUTPUT_I_ATRIG = 17, 779 NI_PFI_OUTPUT_RTSI0 = 18, 780 NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26, 781 NI_PFI_OUTPUT_SCXI_TRIG1 = 27, 782 NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28, 783 NI_PFI_OUTPUT_CDI_SAMPLE = 29, 784 NI_PFI_OUTPUT_CDO_UPDATE = 30 785 }; 786 static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel) 787 { 788 return NI_PFI_OUTPUT_RTSI0 + rtsi_channel; 789 } 790 791/* Signals which can be routed to output on a NI PFI pin on a 660x board 792 with INSN_CONFIG_SET_ROUTING. The numbers assigned are 793 not arbitrary, they correspond to the bits required 794 to program the board. Lines 0 to 7 can only be set to 795 NI_660X_PFI_OUTPUT_DIO. Lines 32 to 39 can only be set to 796 NI_660X_PFI_OUTPUT_COUNTER. */ 797 enum ni_660x_pfi_routing { 798 NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */ 799 NI_660X_PFI_OUTPUT_DIO = 2, /* static digital output */ 800 }; 801 802/* NI External Trigger lines. These values are not arbitrary, but are related 803 * to the bits required to program the board (offset by 1 for historical 804 * reasons). */ 805 static inline unsigned NI_EXT_PFI(unsigned pfi_channel) 806 { 807 return NI_USUAL_PFI_SELECT(pfi_channel) - 1; 808 } 809 static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel) 810 { 811 return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1; 812 } 813 814/* status bits for INSN_CONFIG_GET_COUNTER_STATUS */ 815 enum comedi_counter_status_flags { 816 COMEDI_COUNTER_ARMED = 0x1, 817 COMEDI_COUNTER_COUNTING = 0x2, 818 COMEDI_COUNTER_TERMINAL_COUNT = 0x4, 819 }; 820 821/* Clock sources for CDIO subdevice on NI m-series boards. Used as the 822 * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd 823 * with CR_INVERT to change polarity. */ 824 enum ni_m_series_cdio_scan_begin_src { 825 NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0, 826 NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18, 827 NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19, 828 NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20, 829 NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28, 830 NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29, 831 NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30, 832 NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31, 833 NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32, 834 NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33 835 }; 836 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) 837 { 838 return NI_USUAL_PFI_SELECT(pfi_channel); 839 } 840 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel) 841 { 842 return NI_USUAL_RTSI_SELECT(rtsi_channel); 843 } 844 845/* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI 846 * boards. These scan begin sources can also be bitwise-or'd with CR_INVERT to 847 * change polarity. */ 848 static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) 849 { 850 return NI_USUAL_PFI_SELECT(pfi_channel); 851 } 852 static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel) 853 { 854 return NI_USUAL_RTSI_SELECT(rtsi_channel); 855 } 856 857/* Bits for setting a clock source with 858 * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */ 859 enum ni_freq_out_clock_source_bits { 860 NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */ 861 NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC /* 100 KHz */ 862 }; 863 864/* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for 865 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */ 866 enum amplc_dio_clock_source { 867 AMPLC_DIO_CLK_CLKN, /* per channel external clock 868 input/output pin (pin is only an 869 input when clock source set to this 870 value, otherwise it is an output) */ 871 AMPLC_DIO_CLK_10MHZ, /* 10 MHz internal clock */ 872 AMPLC_DIO_CLK_1MHZ, /* 1 MHz internal clock */ 873 AMPLC_DIO_CLK_100KHZ, /* 100 kHz internal clock */ 874 AMPLC_DIO_CLK_10KHZ, /* 10 kHz internal clock */ 875 AMPLC_DIO_CLK_1KHZ, /* 1 kHz internal clock */ 876 AMPLC_DIO_CLK_OUTNM1, /* output of preceding counter channel 877 (for channel 0, preceding counter 878 channel is channel 2 on preceding 879 counter subdevice, for first counter 880 subdevice, preceding counter 881 subdevice is the last counter 882 subdevice) */ 883 AMPLC_DIO_CLK_EXT /* per chip external input pin */ 884 }; 885 886/* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for 887 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */ 888 enum amplc_dio_gate_source { 889 AMPLC_DIO_GAT_VCC, /* internal high logic level */ 890 AMPLC_DIO_GAT_GND, /* internal low logic level */ 891 AMPLC_DIO_GAT_GATN, /* per channel external gate input */ 892 AMPLC_DIO_GAT_NOUTNM2, /* negated output of counter channel 893 minus 2 (for channels 0 or 1, 894 channel minus 2 is channel 1 or 2 on 895 the preceding counter subdevice, for 896 the first counter subdevice the 897 preceding counter subdevice is the 898 last counter subdevice) */ 899 AMPLC_DIO_GAT_RESERVED4, 900 AMPLC_DIO_GAT_RESERVED5, 901 AMPLC_DIO_GAT_RESERVED6, 902 AMPLC_DIO_GAT_RESERVED7 903 }; 904 905#endif /* _COMEDI_H */ 906