comedi.h revision e0dcef71f6ea63f80631d2e87d06a9ae05624eef
1/* 2 include/comedi.h (installed as /usr/include/comedi.h) 3 header file for comedi 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU Lesser General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 22*/ 23 24#ifndef _COMEDI_H 25#define _COMEDI_H 26 27#ifdef __cplusplus 28extern "C" { 29#endif 30 31#define COMEDI_MAJORVERSION 0 32#define COMEDI_MINORVERSION 7 33#define COMEDI_MICROVERSION 76 34#define VERSION "0.7.76" 35 36/* comedi's major device number */ 37#define COMEDI_MAJOR 98 38 39/* 40 maximum number of minor devices. This can be increased, although 41 kernel structures are currently statically allocated, thus you 42 don't want this to be much more than you actually use. 43 */ 44#define COMEDI_NDEVICES 16 45 46/* number of config options in the config structure */ 47#define COMEDI_NDEVCONFOPTS 32 48/*length of nth chunk of firmware data*/ 49#define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25 50#define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26 51#define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27 52#define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28 53#define COMEDI_DEVCONF_AUX_DATA_HI 29 /* most significant 32 bits of pointer address (if needed) */ 54#define COMEDI_DEVCONF_AUX_DATA_LO 30 /* least significant 32 bits of pointer address */ 55#define COMEDI_DEVCONF_AUX_DATA_LENGTH 31 /* total data length */ 56 57/* max length of device and driver names */ 58#define COMEDI_NAMELEN 20 59 60 typedef unsigned int lsampl_t; 61 typedef unsigned short sampl_t; 62 63/* packs and unpacks a channel/range number */ 64 65#define CR_PACK(chan, rng, aref) ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan)) 66#define CR_PACK_FLAGS(chan, range, aref, flags) (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK)) 67 68#define CR_CHAN(a) ((a)&0xffff) 69#define CR_RANGE(a) (((a)>>16)&0xff) 70#define CR_AREF(a) (((a)>>24)&0x03) 71 72#define CR_FLAGS_MASK 0xfc000000 73#define CR_ALT_FILTER (1<<26) 74#define CR_DITHER CR_ALT_FILTER 75#define CR_DEGLITCH CR_ALT_FILTER 76#define CR_ALT_SOURCE (1<<27) 77#define CR_EDGE (1<<30) 78#define CR_INVERT (1<<31) 79 80#define AREF_GROUND 0x00 /* analog ref = analog ground */ 81#define AREF_COMMON 0x01 /* analog ref = analog common */ 82#define AREF_DIFF 0x02 /* analog ref = differential */ 83#define AREF_OTHER 0x03 /* analog ref = other (undefined) */ 84 85/* counters -- these are arbitrary values */ 86#define GPCT_RESET 0x0001 87#define GPCT_SET_SOURCE 0x0002 88#define GPCT_SET_GATE 0x0004 89#define GPCT_SET_DIRECTION 0x0008 90#define GPCT_SET_OPERATION 0x0010 91#define GPCT_ARM 0x0020 92#define GPCT_DISARM 0x0040 93#define GPCT_GET_INT_CLK_FRQ 0x0080 94 95#define GPCT_INT_CLOCK 0x0001 96#define GPCT_EXT_PIN 0x0002 97#define GPCT_NO_GATE 0x0004 98#define GPCT_UP 0x0008 99#define GPCT_DOWN 0x0010 100#define GPCT_HWUD 0x0020 101#define GPCT_SIMPLE_EVENT 0x0040 102#define GPCT_SINGLE_PERIOD 0x0080 103#define GPCT_SINGLE_PW 0x0100 104#define GPCT_CONT_PULSE_OUT 0x0200 105#define GPCT_SINGLE_PULSE_OUT 0x0400 106 107/* instructions */ 108 109#define INSN_MASK_WRITE 0x8000000 110#define INSN_MASK_READ 0x4000000 111#define INSN_MASK_SPECIAL 0x2000000 112 113#define INSN_READ (0 | INSN_MASK_READ) 114#define INSN_WRITE (1 | INSN_MASK_WRITE) 115#define INSN_BITS (2 | INSN_MASK_READ|INSN_MASK_WRITE) 116#define INSN_CONFIG (3 | INSN_MASK_READ|INSN_MASK_WRITE) 117#define INSN_GTOD (4 | INSN_MASK_READ|INSN_MASK_SPECIAL) 118#define INSN_WAIT (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL) 119#define INSN_INTTRIG (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL) 120 121/* trigger flags */ 122/* These flags are used in comedi_trig structures */ 123 124#define TRIG_BOGUS 0x0001 /* do the motions */ 125#define TRIG_DITHER 0x0002 /* enable dithering */ 126#define TRIG_DEGLITCH 0x0004 /* enable deglitching */ 127/*#define TRIG_RT 0x0008 */ /* perform op in real time */ 128#define TRIG_CONFIG 0x0010 /* perform configuration, not triggering */ 129#define TRIG_WAKE_EOS 0x0020 /* wake up on end-of-scan events */ 130/*#define TRIG_WRITE 0x0040*/ /* write to bidirectional devices */ 131 132/* command flags */ 133/* These flags are used in comedi_cmd structures */ 134 135#define CMDF_PRIORITY 0x00000008 /* try to use a real-time interrupt while performing command */ 136 137#define TRIG_RT CMDF_PRIORITY /* compatibility definition */ 138 139#define CMDF_WRITE 0x00000040 140#define TRIG_WRITE CMDF_WRITE /* compatibility definition */ 141 142#define CMDF_RAWDATA 0x00000080 143 144#define COMEDI_EV_START 0x00040000 145#define COMEDI_EV_SCAN_BEGIN 0x00080000 146#define COMEDI_EV_CONVERT 0x00100000 147#define COMEDI_EV_SCAN_END 0x00200000 148#define COMEDI_EV_STOP 0x00400000 149 150#define TRIG_ROUND_MASK 0x00030000 151#define TRIG_ROUND_NEAREST 0x00000000 152#define TRIG_ROUND_DOWN 0x00010000 153#define TRIG_ROUND_UP 0x00020000 154#define TRIG_ROUND_UP_NEXT 0x00030000 155 156/* trigger sources */ 157 158#define TRIG_ANY 0xffffffff 159#define TRIG_INVALID 0x00000000 160 161#define TRIG_NONE 0x00000001 /* never trigger */ 162#define TRIG_NOW 0x00000002 /* trigger now + N ns */ 163#define TRIG_FOLLOW 0x00000004 /* trigger on next lower level trig */ 164#define TRIG_TIME 0x00000008 /* trigger at time N ns */ 165#define TRIG_TIMER 0x00000010 /* trigger at rate N ns */ 166#define TRIG_COUNT 0x00000020 /* trigger when count reaches N */ 167#define TRIG_EXT 0x00000040 /* trigger on external signal N */ 168#define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */ 169#define TRIG_OTHER 0x00000100 /* driver defined */ 170 171/* subdevice flags */ 172 173#define SDF_BUSY 0x0001 /* device is busy */ 174#define SDF_BUSY_OWNER 0x0002 /* device is busy with your job */ 175#define SDF_LOCKED 0x0004 /* subdevice is locked */ 176#define SDF_LOCK_OWNER 0x0008 /* you own lock */ 177#define SDF_MAXDATA 0x0010 /* maxdata depends on channel */ 178#define SDF_FLAGS 0x0020 /* flags depend on channel */ 179#define SDF_RANGETYPE 0x0040 /* range type depends on channel */ 180#define SDF_MODE0 0x0080 /* can do mode 0 */ 181#define SDF_MODE1 0x0100 /* can do mode 1 */ 182#define SDF_MODE2 0x0200 /* can do mode 2 */ 183#define SDF_MODE3 0x0400 /* can do mode 3 */ 184#define SDF_MODE4 0x0800 /* can do mode 4 */ 185#define SDF_CMD 0x1000 /* can do commands (deprecated) */ 186#define SDF_SOFT_CALIBRATED 0x2000 /* subdevice uses software calibration */ 187#define SDF_CMD_WRITE 0x4000 /* can do output commands */ 188#define SDF_CMD_READ 0x8000 /* can do input commands */ 189 190#define SDF_READABLE 0x00010000 /* subdevice can be read (e.g. analog input) */ 191#define SDF_WRITABLE 0x00020000 /* subdevice can be written (e.g. analog output) */ 192#define SDF_WRITEABLE SDF_WRITABLE /* spelling error in API */ 193#define SDF_INTERNAL 0x00040000 /* subdevice does not have externally visible lines */ 194#define SDF_RT 0x00080000 /* DEPRECATED: subdevice is RT capable */ 195#define SDF_GROUND 0x00100000 /* can do aref=ground */ 196#define SDF_COMMON 0x00200000 /* can do aref=common */ 197#define SDF_DIFF 0x00400000 /* can do aref=diff */ 198#define SDF_OTHER 0x00800000 /* can do aref=other */ 199#define SDF_DITHER 0x01000000 /* can do dithering */ 200#define SDF_DEGLITCH 0x02000000 /* can do deglitching */ 201#define SDF_MMAP 0x04000000 /* can do mmap() */ 202#define SDF_RUNNING 0x08000000 /* subdevice is acquiring data */ 203#define SDF_LSAMPL 0x10000000 /* subdevice uses 32-bit samples */ 204#define SDF_PACKED 0x20000000 /* subdevice can do packed DIO */ 205/* re recyle these flags for PWM */ 206#define SDF_PWM_COUNTER SDF_MODE0 /* PWM can automatically switch off */ 207#define SDF_PWM_HBRIDGE SDF_MODE1 /* PWM is signed (H-bridge) */ 208 209 210 211/* subdevice types */ 212 213enum comedi_subdevice_type { 214 COMEDI_SUBD_UNUSED, /* unused by driver */ 215 COMEDI_SUBD_AI, /* analog input */ 216 COMEDI_SUBD_AO, /* analog output */ 217 COMEDI_SUBD_DI, /* digital input */ 218 COMEDI_SUBD_DO, /* digital output */ 219 COMEDI_SUBD_DIO, /* digital input/output */ 220 COMEDI_SUBD_COUNTER, /* counter */ 221 COMEDI_SUBD_TIMER, /* timer */ 222 COMEDI_SUBD_MEMORY, /* memory, EEPROM, DPRAM */ 223 COMEDI_SUBD_CALIB, /* calibration DACs */ 224 COMEDI_SUBD_PROC, /* processor, DSP */ 225 COMEDI_SUBD_SERIAL, /* serial IO */ 226 COMEDI_SUBD_PWM /* PWM */ 227}; 228 229/* configuration instructions */ 230 231enum configuration_ids { 232 INSN_CONFIG_DIO_INPUT = 0, 233 INSN_CONFIG_DIO_OUTPUT = 1, 234 INSN_CONFIG_DIO_OPENDRAIN = 2, 235 INSN_CONFIG_ANALOG_TRIG = 16, 236/* INSN_CONFIG_WAVEFORM = 17, */ 237/* INSN_CONFIG_TRIG = 18, */ 238/* INSN_CONFIG_COUNTER = 19, */ 239 INSN_CONFIG_ALT_SOURCE = 20, 240 INSN_CONFIG_DIGITAL_TRIG = 21, 241 INSN_CONFIG_BLOCK_SIZE = 22, 242 INSN_CONFIG_TIMER_1 = 23, 243 INSN_CONFIG_FILTER = 24, 244 INSN_CONFIG_CHANGE_NOTIFY = 25, 245 246 /*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26, 247 INSN_CONFIG_BIDIRECTIONAL_DATA = 27, 248 INSN_CONFIG_DIO_QUERY = 28, 249 INSN_CONFIG_PWM_OUTPUT = 29, 250 INSN_CONFIG_GET_PWM_OUTPUT = 30, 251 INSN_CONFIG_ARM = 31, 252 INSN_CONFIG_DISARM = 32, 253 INSN_CONFIG_GET_COUNTER_STATUS = 33, 254 INSN_CONFIG_RESET = 34, 255 INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, /* Use CTR as single pulsegenerator */ 256 INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002, /* Use CTR as pulsetraingenerator */ 257 INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003, /* Use the counter as encoder */ 258 INSN_CONFIG_SET_GATE_SRC = 2001, /* Set gate source */ 259 INSN_CONFIG_GET_GATE_SRC = 2002, /* Get gate source */ 260 INSN_CONFIG_SET_CLOCK_SRC = 2003, /* Set master clock source */ 261 INSN_CONFIG_GET_CLOCK_SRC = 2004, /* Get master clock source */ 262 INSN_CONFIG_SET_OTHER_SRC = 2005, /* Set other source */ 263/* INSN_CONFIG_GET_OTHER_SRC = 2006,*/ /* Get other source */ 264 INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE, /* Get size in bytes of 265 subdevice's on-board fifos 266 used during streaming 267 input/output */ 268 INSN_CONFIG_SET_COUNTER_MODE = 4097, 269 INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE, /* deprecated */ 270 INSN_CONFIG_8254_READ_STATUS = 4098, 271 INSN_CONFIG_SET_ROUTING = 4099, 272 INSN_CONFIG_GET_ROUTING = 4109, 273/* PWM */ 274 INSN_CONFIG_PWM_SET_PERIOD = 5000, /* sets frequency */ 275 INSN_CONFIG_PWM_GET_PERIOD = 5001, /* gets frequency */ 276 INSN_CONFIG_GET_PWM_STATUS = 5002, /* is it running? */ 277 INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, /* sets H bridge: duty cycle and sign bit for a relay at the same time*/ 278 INSN_CONFIG_PWM_GET_H_BRIDGE = 5004 /* gets H bridge data: duty cycle and the sign bit */ 279}; 280 281enum comedi_io_direction { 282 COMEDI_INPUT = 0, 283 COMEDI_OUTPUT = 1, 284 COMEDI_OPENDRAIN = 2 285}; 286 287enum comedi_support_level { 288 COMEDI_UNKNOWN_SUPPORT = 0, 289 COMEDI_SUPPORTED, 290 COMEDI_UNSUPPORTED 291}; 292 293/* ioctls */ 294 295#define CIO 'd' 296#define COMEDI_DEVCONFIG _IOW(CIO, 0, comedi_devconfig) 297#define COMEDI_DEVINFO _IOR(CIO, 1, comedi_devinfo) 298#define COMEDI_SUBDINFO _IOR(CIO, 2, comedi_subdinfo) 299#define COMEDI_CHANINFO _IOR(CIO, 3, comedi_chaninfo) 300#define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig) 301#define COMEDI_LOCK _IO(CIO, 5) 302#define COMEDI_UNLOCK _IO(CIO, 6) 303#define COMEDI_CANCEL _IO(CIO, 7) 304#define COMEDI_RANGEINFO _IOR(CIO, 8, comedi_rangeinfo) 305#define COMEDI_CMD _IOR(CIO, 9, comedi_cmd) 306#define COMEDI_CMDTEST _IOR(CIO, 10, comedi_cmd) 307#define COMEDI_INSNLIST _IOR(CIO, 11, comedi_insnlist) 308#define COMEDI_INSN _IOR(CIO, 12, comedi_insn) 309#define COMEDI_BUFCONFIG _IOR(CIO, 13, comedi_bufconfig) 310#define COMEDI_BUFINFO _IOWR(CIO, 14, comedi_bufinfo) 311#define COMEDI_POLL _IO(CIO, 15) 312 313/* structures */ 314 315typedef struct comedi_trig_struct comedi_trig; 316typedef struct comedi_cmd_struct comedi_cmd; 317typedef struct comedi_insn_struct comedi_insn; 318typedef struct comedi_insnlist_struct comedi_insnlist; 319typedef struct comedi_chaninfo_struct comedi_chaninfo; 320typedef struct comedi_subdinfo_struct comedi_subdinfo; 321typedef struct comedi_devinfo_struct comedi_devinfo; 322typedef struct comedi_devconfig_struct comedi_devconfig; 323typedef struct comedi_rangeinfo_struct comedi_rangeinfo; 324typedef struct comedi_krange_struct comedi_krange; 325typedef struct comedi_bufconfig_struct comedi_bufconfig; 326typedef struct comedi_bufinfo_struct comedi_bufinfo; 327 328struct comedi_trig_struct { 329 unsigned int subdev; /* subdevice */ 330 unsigned int mode; /* mode */ 331 unsigned int flags; 332 unsigned int n_chan; /* number of channels */ 333 unsigned int *chanlist; /* channel/range list */ 334 sampl_t *data; /* data list, size depends on subd flags */ 335 unsigned int n; /* number of scans */ 336 unsigned int trigsrc; 337 unsigned int trigvar; 338 unsigned int trigvar1; 339 unsigned int data_len; 340 unsigned int unused[3]; 341}; 342 343struct comedi_insn_struct { 344 unsigned int insn; 345 unsigned int n; 346 lsampl_t *data; 347 unsigned int subdev; 348 unsigned int chanspec; 349 unsigned int unused[3]; 350}; 351 352struct comedi_insnlist_struct { 353 unsigned int n_insns; 354 comedi_insn *insns; 355}; 356 357struct comedi_cmd_struct { 358 unsigned int subdev; 359 unsigned int flags; 360 361 unsigned int start_src; 362 unsigned int start_arg; 363 364 unsigned int scan_begin_src; 365 unsigned int scan_begin_arg; 366 367 unsigned int convert_src; 368 unsigned int convert_arg; 369 370 unsigned int scan_end_src; 371 unsigned int scan_end_arg; 372 373 unsigned int stop_src; 374 unsigned int stop_arg; 375 376 unsigned int *chanlist; /* channel/range list */ 377 unsigned int chanlist_len; 378 379 sampl_t *data; /* data list, size depends on subd flags */ 380 unsigned int data_len; 381}; 382 383struct comedi_chaninfo_struct { 384 unsigned int subdev; 385 lsampl_t *maxdata_list; 386 unsigned int *flaglist; 387 unsigned int *rangelist; 388 unsigned int unused[4]; 389}; 390 391struct comedi_rangeinfo_struct { 392 unsigned int range_type; 393 void *range_ptr; 394}; 395 396struct comedi_krange_struct { 397 int min; /* fixed point, multiply by 1e-6 */ 398 int max; /* fixed point, multiply by 1e-6 */ 399 unsigned int flags; 400}; 401 402 403struct comedi_subdinfo_struct { 404 unsigned int type; 405 unsigned int n_chan; 406 unsigned int subd_flags; 407 unsigned int timer_type; 408 unsigned int len_chanlist; 409 lsampl_t maxdata; 410 unsigned int flags; /* channel flags */ 411 unsigned int range_type; /* lookup in kernel */ 412 unsigned int settling_time_0; 413 unsigned insn_bits_support; /* see support_level enum for values*/ 414 unsigned int unused[8]; 415}; 416 417struct comedi_devinfo_struct { 418 unsigned int version_code; 419 unsigned int n_subdevs; 420 char driver_name[COMEDI_NAMELEN]; 421 char board_name[COMEDI_NAMELEN]; 422 int read_subdevice; 423 int write_subdevice; 424 int unused[30]; 425}; 426 427struct comedi_devconfig_struct { 428 char board_name[COMEDI_NAMELEN]; 429 int options[COMEDI_NDEVCONFOPTS]; 430}; 431 432struct comedi_bufconfig_struct { 433 unsigned int subdevice; 434 unsigned int flags; 435 436 unsigned int maximum_size; 437 unsigned int size; 438 439 unsigned int unused[4]; 440}; 441 442struct comedi_bufinfo_struct { 443 unsigned int subdevice; 444 unsigned int bytes_read; 445 446 unsigned int buf_write_ptr; 447 unsigned int buf_read_ptr; 448 unsigned int buf_write_count; 449 unsigned int buf_read_count; 450 451 unsigned int bytes_written; 452 453 unsigned int unused[4]; 454}; 455 456/* range stuff */ 457 458#define __RANGE(a, b) ((((a)&0xffff)<<16)|((b)&0xffff)) 459 460#define RANGE_OFFSET(a) (((a)>>16)&0xffff) 461#define RANGE_LENGTH(b) ((b)&0xffff) 462 463#define RF_UNIT(flags) ((flags)&0xff) 464#define RF_EXTERNAL (1<<8) 465 466#define UNIT_volt 0 467#define UNIT_mA 1 468#define UNIT_none 2 469 470#define COMEDI_MIN_SPEED ((unsigned int)0xffffffff) 471 472/* callback stuff */ 473/* only relevant to kernel modules. */ 474 475#define COMEDI_CB_EOS 1 /* end of scan */ 476#define COMEDI_CB_EOA 2 /* end of acquisition */ 477#define COMEDI_CB_BLOCK 4 /* DEPRECATED: convenient block size */ 478#define COMEDI_CB_EOBUF 8 /* DEPRECATED: end of buffer */ 479#define COMEDI_CB_ERROR 16 /* card error during acquisition */ 480#define COMEDI_CB_OVERFLOW 32 /* buffer overflow/underflow */ 481 482/**********************************************************/ 483/* everything after this line is ALPHA */ 484/**********************************************************/ 485 486/* 487 8254 specific configuration. 488 489 It supports two config commands: 490 491 0 ID: INSN_CONFIG_SET_COUNTER_MODE 492 1 8254 Mode 493 I8254_MODE0, I8254_MODE1, ..., I8254_MODE5 494 OR'ed with: 495 I8254_BCD, I8254_BINARY 496 497 0 ID: INSN_CONFIG_8254_READ_STATUS 498 1 <-- Status byte returned here. 499 B7 = Output 500 B6 = NULL Count 501 B5 - B0 Current mode. 502 503*/ 504 505enum i8254_mode { 506 I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */ 507 I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */ 508 I8254_MODE2 = (2 << 1), /* Rate generator */ 509 I8254_MODE3 = (3 << 1), /* Square wave mode */ 510 I8254_MODE4 = (4 << 1), /* Software triggered strobe */ 511 I8254_MODE5 = (5 << 1), /* Hardware triggered strobe (retriggerable) */ 512 I8254_BCD = 1, /* use binary-coded decimal instead of binary (pretty useless) */ 513 I8254_BINARY = 0 514}; 515 516static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel) 517{ 518 if (pfi_channel < 10) 519 return 0x1 + pfi_channel; 520 else 521 return 0xb + pfi_channel; 522} 523static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel) 524{ 525 if (rtsi_channel < 7) 526 return 0xb + rtsi_channel; 527 else 528 return 0x1b; 529} 530/* mode bits for NI general-purpose counters, set with 531 * INSN_CONFIG_SET_COUNTER_MODE */ 532#define NI_GPCT_COUNTING_MODE_SHIFT 16 533#define NI_GPCT_INDEX_PHASE_BITSHIFT 20 534#define NI_GPCT_COUNTING_DIRECTION_SHIFT 24 535enum ni_gpct_mode_bits { 536 NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4, 537 NI_GPCT_EDGE_GATE_MODE_MASK = 0x18, 538 NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0, 539 NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8, 540 NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10, 541 NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18, 542 NI_GPCT_STOP_MODE_MASK = 0x60, 543 NI_GPCT_STOP_ON_GATE_BITS = 0x00, 544 NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20, 545 NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40, 546 NI_GPCT_LOAD_B_SELECT_BIT = 0x80, 547 NI_GPCT_OUTPUT_MODE_MASK = 0x300, 548 NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100, 549 NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200, 550 NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300, 551 NI_GPCT_HARDWARE_DISARM_MASK = 0xc00, 552 NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000, 553 NI_GPCT_DISARM_AT_TC_BITS = 0x400, 554 NI_GPCT_DISARM_AT_GATE_BITS = 0x800, 555 NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00, 556 NI_GPCT_LOADING_ON_TC_BIT = 0x1000, 557 NI_GPCT_LOADING_ON_GATE_BIT = 0x4000, 558 NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT, 559 NI_GPCT_COUNTING_MODE_NORMAL_BITS = 560 0x0 << NI_GPCT_COUNTING_MODE_SHIFT, 561 NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS = 562 0x1 << NI_GPCT_COUNTING_MODE_SHIFT, 563 NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS = 564 0x2 << NI_GPCT_COUNTING_MODE_SHIFT, 565 NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS = 566 0x3 << NI_GPCT_COUNTING_MODE_SHIFT, 567 NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS = 568 0x4 << NI_GPCT_COUNTING_MODE_SHIFT, 569 NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS = 570 0x6 << NI_GPCT_COUNTING_MODE_SHIFT, 571 NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 572 NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS = 573 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT, 574 NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS = 575 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT, 576 NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS = 577 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT, 578 NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS = 579 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 580 NI_GPCT_INDEX_ENABLE_BIT = 0x400000, 581 NI_GPCT_COUNTING_DIRECTION_MASK = 582 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 583 NI_GPCT_COUNTING_DIRECTION_DOWN_BITS = 584 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 585 NI_GPCT_COUNTING_DIRECTION_UP_BITS = 586 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 587 NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS = 588 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 589 NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS = 590 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 591 NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000, 592 NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0, 593 NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000, 594 NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000, 595 NI_GPCT_OR_GATE_BIT = 0x10000000, 596 NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000 597}; 598 599/* Bits for setting a clock source with 600 * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */ 601enum ni_gpct_clock_source_bits { 602 NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f, 603 NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0, 604 NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1, 605 NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2, 606 NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3, 607 NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4, 608 NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5, 609 NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6, /* NI 660x-specific */ 610 NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7, 611 NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8, 612 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9, 613 NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000, 614 NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0, 615 NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, /* divide source by 2 */ 616 NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, /* divide source by 8 */ 617 NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000 618}; 619static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n) 620{ 621 /* NI 660x-specific */ 622 return 0x10 + n; 623} 624static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n) 625{ 626 return 0x18 + n; 627} 628static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n) 629{ 630 /* no pfi on NI 660x */ 631 return 0x20 + n; 632} 633 634/* Possibilities for setting a gate source with 635INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters. 636May be bitwise-or'd with CR_EDGE or CR_INVERT. */ 637enum ni_gpct_gate_select { 638 /* m-series gates */ 639 NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0, 640 NI_GPCT_AI_START2_GATE_SELECT = 0x12, 641 NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13, 642 NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14, 643 NI_GPCT_AI_START1_GATE_SELECT = 0x1c, 644 NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d, 645 NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e, 646 NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f, 647 /* more gates for 660x */ 648 NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100, 649 NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101, 650 /* more gates for 660x "second gate" */ 651 NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201, 652 NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e, 653 /* m-series "second gate" sources are unknown, 654 we should add them here with an offset of 0x300 when known. */ 655 NI_GPCT_DISABLED_GATE_SELECT = 0x8000, 656}; 657static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n) 658{ 659 return 0x102 + n; 660} 661static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n) 662{ 663 return NI_USUAL_RTSI_SELECT(n); 664} 665static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n) 666{ 667 return NI_USUAL_PFI_SELECT(n); 668} 669static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n) 670{ 671 return 0x202 + n; 672} 673 674/* Possibilities for setting a source with 675INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */ 676enum ni_gpct_other_index { 677 NI_GPCT_SOURCE_ENCODER_A, 678 NI_GPCT_SOURCE_ENCODER_B, 679 NI_GPCT_SOURCE_ENCODER_Z 680}; 681enum ni_gpct_other_select { 682 /* m-series gates */ 683 /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */ 684 NI_GPCT_DISABLED_OTHER_SELECT = 0x8000, 685}; 686static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n) 687{ 688 return NI_USUAL_PFI_SELECT(n); 689} 690 691/* start sources for ni general-purpose counters for use with 692INSN_CONFIG_ARM */ 693enum ni_gpct_arm_source { 694 NI_GPCT_ARM_IMMEDIATE = 0x0, 695 NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter and 696 the adjacent paired counter 697 simultaneously */ 698 /* NI doesn't document bits for selecting hardware arm triggers. If 699 * the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least 700 * significant bits (3 bits for 660x or 5 bits for m-series) through to 701 * the hardware. This will at least allow someone to figure out what 702 * the bits do later. */ 703 NI_GPCT_ARM_UNKNOWN = 0x1000, 704}; 705 706/* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */ 707enum ni_gpct_filter_select { 708 NI_GPCT_FILTER_OFF = 0x0, 709 NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1, 710 NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2, 711 NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3, 712 NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4, 713 NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5, 714 NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6 715}; 716 717/* PFI digital filtering options for ni m-series for use with 718 * INSN_CONFIG_FILTER. */ 719enum ni_pfi_filter_select { 720 NI_PFI_FILTER_OFF = 0x0, 721 NI_PFI_FILTER_125ns = 0x1, 722 NI_PFI_FILTER_6425ns = 0x2, 723 NI_PFI_FILTER_2550us = 0x3 724}; 725 726/* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */ 727enum ni_mio_clock_source { 728 NI_MIO_INTERNAL_CLOCK = 0, 729 NI_MIO_RTSI_CLOCK = 1, /* doesn't work for m-series, use 730 NI_MIO_PLL_RTSI_CLOCK() */ 731 /* the NI_MIO_PLL_* sources are m-series only */ 732 NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2, 733 NI_MIO_PLL_PXI10_CLOCK = 3, 734 NI_MIO_PLL_RTSI0_CLOCK = 4 735}; 736static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel) 737{ 738 return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel; 739} 740 741/* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING. 742 The numbers assigned are not arbitrary, they correspond to the bits required 743 to program the board. */ 744enum ni_rtsi_routing { 745 NI_RTSI_OUTPUT_ADR_START1 = 0, 746 NI_RTSI_OUTPUT_ADR_START2 = 1, 747 NI_RTSI_OUTPUT_SCLKG = 2, 748 NI_RTSI_OUTPUT_DACUPDN = 3, 749 NI_RTSI_OUTPUT_DA_START1 = 4, 750 NI_RTSI_OUTPUT_G_SRC0 = 5, 751 NI_RTSI_OUTPUT_G_GATE0 = 6, 752 NI_RTSI_OUTPUT_RGOUT0 = 7, 753 NI_RTSI_OUTPUT_RTSI_BRD_0 = 8, 754 NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI clock 755 on line 7 */ 756}; 757static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n) 758{ 759 return NI_RTSI_OUTPUT_RTSI_BRD_0 + n; 760} 761 762/* Signals which can be routed to an NI PFI pin on an m-series board with 763 * INSN_CONFIG_SET_ROUTING. These numbers are also returned by 764 * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing 765 * cannot be changed. The numbers assigned are not arbitrary, they correspond 766 * to the bits required to program the board. */ 767enum ni_pfi_routing { 768 NI_PFI_OUTPUT_PFI_DEFAULT = 0, 769 NI_PFI_OUTPUT_AI_START1 = 1, 770 NI_PFI_OUTPUT_AI_START2 = 2, 771 NI_PFI_OUTPUT_AI_CONVERT = 3, 772 NI_PFI_OUTPUT_G_SRC1 = 4, 773 NI_PFI_OUTPUT_G_GATE1 = 5, 774 NI_PFI_OUTPUT_AO_UPDATE_N = 6, 775 NI_PFI_OUTPUT_AO_START1 = 7, 776 NI_PFI_OUTPUT_AI_START_PULSE = 8, 777 NI_PFI_OUTPUT_G_SRC0 = 9, 778 NI_PFI_OUTPUT_G_GATE0 = 10, 779 NI_PFI_OUTPUT_EXT_STROBE = 11, 780 NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12, 781 NI_PFI_OUTPUT_GOUT0 = 13, 782 NI_PFI_OUTPUT_GOUT1 = 14, 783 NI_PFI_OUTPUT_FREQ_OUT = 15, 784 NI_PFI_OUTPUT_PFI_DO = 16, 785 NI_PFI_OUTPUT_I_ATRIG = 17, 786 NI_PFI_OUTPUT_RTSI0 = 18, 787 NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26, 788 NI_PFI_OUTPUT_SCXI_TRIG1 = 27, 789 NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28, 790 NI_PFI_OUTPUT_CDI_SAMPLE = 29, 791 NI_PFI_OUTPUT_CDO_UPDATE = 30 792}; 793static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel) 794{ 795 return NI_PFI_OUTPUT_RTSI0 + rtsi_channel; 796} 797 798/* Signals which can be routed to output on a NI PFI pin on a 660x board 799 with INSN_CONFIG_SET_ROUTING. The numbers assigned are 800 not arbitrary, they correspond to the bits required 801 to program the board. Lines 0 to 7 can only be set to 802 NI_660X_PFI_OUTPUT_DIO. Lines 32 to 39 can only be set to 803 NI_660X_PFI_OUTPUT_COUNTER. */ 804enum ni_660x_pfi_routing { 805 NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */ 806 NI_660X_PFI_OUTPUT_DIO = 2, /* static digital output */ 807}; 808 809/* NI External Trigger lines. These values are not arbitrary, but are related 810 * to the bits required to program the board (offset by 1 for historical 811 * reasons). */ 812static inline unsigned NI_EXT_PFI(unsigned pfi_channel) 813{ 814 return NI_USUAL_PFI_SELECT(pfi_channel) - 1; 815} 816static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel) 817{ 818 return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1; 819} 820 821/* status bits for INSN_CONFIG_GET_COUNTER_STATUS */ 822enum comedi_counter_status_flags { 823 COMEDI_COUNTER_ARMED = 0x1, 824 COMEDI_COUNTER_COUNTING = 0x2, 825 COMEDI_COUNTER_TERMINAL_COUNT = 0x4, 826}; 827 828/* Clock sources for CDIO subdevice on NI m-series boards. Used as the 829 * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd 830 * with CR_INVERT to change polarity. */ 831enum ni_m_series_cdio_scan_begin_src { 832 NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0, 833 NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18, 834 NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19, 835 NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20, 836 NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28, 837 NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29, 838 NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30, 839 NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31, 840 NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32, 841 NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33 842}; 843static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) 844{ 845 return NI_USUAL_PFI_SELECT(pfi_channel); 846} 847static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel) 848{ 849 return NI_USUAL_RTSI_SELECT(rtsi_channel); 850} 851 852/* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI 853 * boards. These scan begin sources can also be bitwise-or'd with CR_INVERT to 854 * change polarity. */ 855static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) 856{ 857 return NI_USUAL_PFI_SELECT(pfi_channel); 858} 859static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel) 860{ 861 return NI_USUAL_RTSI_SELECT(rtsi_channel); 862} 863 864/* Bits for setting a clock source with 865 * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */ 866enum ni_freq_out_clock_source_bits { 867 NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */ 868 NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC /* 100 KHz */ 869}; 870 871/* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for 872 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */ 873 enum amplc_dio_clock_source { 874 AMPLC_DIO_CLK_CLKN, /* per channel external clock 875 input/output pin (pin is only an 876 input when clock source set to this 877 value, otherwise it is an output) */ 878 AMPLC_DIO_CLK_10MHZ, /* 10 MHz internal clock */ 879 AMPLC_DIO_CLK_1MHZ, /* 1 MHz internal clock */ 880 AMPLC_DIO_CLK_100KHZ, /* 100 kHz internal clock */ 881 AMPLC_DIO_CLK_10KHZ, /* 10 kHz internal clock */ 882 AMPLC_DIO_CLK_1KHZ, /* 1 kHz internal clock */ 883 AMPLC_DIO_CLK_OUTNM1, /* output of preceding counter channel 884 (for channel 0, preceding counter 885 channel is channel 2 on preceding 886 counter subdevice, for first counter 887 subdevice, preceding counter 888 subdevice is the last counter 889 subdevice) */ 890 AMPLC_DIO_CLK_EXT /* per chip external input pin */ 891 }; 892 893/* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for 894 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */ 895 enum amplc_dio_gate_source { 896 AMPLC_DIO_GAT_VCC, /* internal high logic level */ 897 AMPLC_DIO_GAT_GND, /* internal low logic level */ 898 AMPLC_DIO_GAT_GATN, /* per channel external gate input */ 899 AMPLC_DIO_GAT_NOUTNM2, /* negated output of counter channel 900 minus 2 (for channels 0 or 1, 901 channel minus 2 is channel 1 or 2 on 902 the preceding counter subdevice, for 903 the first counter subdevice the 904 preceding counter subdevice is the 905 last counter subdevice) */ 906 AMPLC_DIO_GAT_RESERVED4, 907 AMPLC_DIO_GAT_RESERVED5, 908 AMPLC_DIO_GAT_RESERVED6, 909 AMPLC_DIO_GAT_RESERVED7 910 }; 911 912#ifdef __cplusplus 913} 914#endif 915 916#endif /* _COMEDI_H */ 917