comedi.h revision f80d1d22b6c30771f8d4576d5c741c33b0cfd8ab
1/* 2 include/comedi.h (installed as /usr/include/comedi.h) 3 header file for comedi 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU Lesser General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 22*/ 23 24#ifndef _COMEDI_H 25#define _COMEDI_H 26 27#define COMEDI_MAJORVERSION 0 28#define COMEDI_MINORVERSION 7 29#define COMEDI_MICROVERSION 76 30#define VERSION "0.7.76" 31 32/* comedi's major device number */ 33#define COMEDI_MAJOR 98 34 35/* 36 maximum number of minor devices. This can be increased, although 37 kernel structures are currently statically allocated, thus you 38 don't want this to be much more than you actually use. 39 */ 40#define COMEDI_NDEVICES 16 41 42/* number of config options in the config structure */ 43#define COMEDI_NDEVCONFOPTS 32 44/*length of nth chunk of firmware data*/ 45#define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25 46#define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26 47#define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27 48#define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28 49/* most significant 32 bits of pointer address (if needed) */ 50#define COMEDI_DEVCONF_AUX_DATA_HI 29 51/* least significant 32 bits of pointer address */ 52#define COMEDI_DEVCONF_AUX_DATA_LO 30 53#define COMEDI_DEVCONF_AUX_DATA_LENGTH 31 /* total data length */ 54 55/* max length of device and driver names */ 56#define COMEDI_NAMELEN 20 57 58/* packs and unpacks a channel/range number */ 59 60#define CR_PACK(chan, rng, aref) \ 61 ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan)) 62#define CR_PACK_FLAGS(chan, range, aref, flags) \ 63 (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK)) 64 65#define CR_CHAN(a) ((a)&0xffff) 66#define CR_RANGE(a) (((a)>>16)&0xff) 67#define CR_AREF(a) (((a)>>24)&0x03) 68 69#define CR_FLAGS_MASK 0xfc000000 70#define CR_ALT_FILTER (1<<26) 71#define CR_DITHER CR_ALT_FILTER 72#define CR_DEGLITCH CR_ALT_FILTER 73#define CR_ALT_SOURCE (1<<27) 74#define CR_EDGE (1<<30) 75#define CR_INVERT (1<<31) 76 77#define AREF_GROUND 0x00 /* analog ref = analog ground */ 78#define AREF_COMMON 0x01 /* analog ref = analog common */ 79#define AREF_DIFF 0x02 /* analog ref = differential */ 80#define AREF_OTHER 0x03 /* analog ref = other (undefined) */ 81 82/* counters -- these are arbitrary values */ 83#define GPCT_RESET 0x0001 84#define GPCT_SET_SOURCE 0x0002 85#define GPCT_SET_GATE 0x0004 86#define GPCT_SET_DIRECTION 0x0008 87#define GPCT_SET_OPERATION 0x0010 88#define GPCT_ARM 0x0020 89#define GPCT_DISARM 0x0040 90#define GPCT_GET_INT_CLK_FRQ 0x0080 91 92#define GPCT_INT_CLOCK 0x0001 93#define GPCT_EXT_PIN 0x0002 94#define GPCT_NO_GATE 0x0004 95#define GPCT_UP 0x0008 96#define GPCT_DOWN 0x0010 97#define GPCT_HWUD 0x0020 98#define GPCT_SIMPLE_EVENT 0x0040 99#define GPCT_SINGLE_PERIOD 0x0080 100#define GPCT_SINGLE_PW 0x0100 101#define GPCT_CONT_PULSE_OUT 0x0200 102#define GPCT_SINGLE_PULSE_OUT 0x0400 103 104/* instructions */ 105 106#define INSN_MASK_WRITE 0x8000000 107#define INSN_MASK_READ 0x4000000 108#define INSN_MASK_SPECIAL 0x2000000 109 110#define INSN_READ (0 | INSN_MASK_READ) 111#define INSN_WRITE (1 | INSN_MASK_WRITE) 112#define INSN_BITS (2 | INSN_MASK_READ|INSN_MASK_WRITE) 113#define INSN_CONFIG (3 | INSN_MASK_READ|INSN_MASK_WRITE) 114#define INSN_GTOD (4 | INSN_MASK_READ|INSN_MASK_SPECIAL) 115#define INSN_WAIT (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL) 116#define INSN_INTTRIG (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL) 117 118/* trigger flags */ 119/* These flags are used in comedi_trig structures */ 120 121#define TRIG_BOGUS 0x0001 /* do the motions */ 122#define TRIG_DITHER 0x0002 /* enable dithering */ 123#define TRIG_DEGLITCH 0x0004 /* enable deglitching */ 124 /*#define TRIG_RT 0x0008 *//* perform op in real time */ 125#define TRIG_CONFIG 0x0010 /* perform configuration, not triggering */ 126#define TRIG_WAKE_EOS 0x0020 /* wake up on end-of-scan events */ 127 /*#define TRIG_WRITE 0x0040*//* write to bidirectional devices */ 128 129/* command flags */ 130/* These flags are used in comedi_cmd structures */ 131 132/* try to use a real-time interrupt while performing command */ 133#define CMDF_PRIORITY 0x00000008 134 135#define TRIG_RT CMDF_PRIORITY /* compatibility definition */ 136 137#define CMDF_WRITE 0x00000040 138#define TRIG_WRITE CMDF_WRITE /* compatibility definition */ 139 140#define CMDF_RAWDATA 0x00000080 141 142#define COMEDI_EV_START 0x00040000 143#define COMEDI_EV_SCAN_BEGIN 0x00080000 144#define COMEDI_EV_CONVERT 0x00100000 145#define COMEDI_EV_SCAN_END 0x00200000 146#define COMEDI_EV_STOP 0x00400000 147 148#define TRIG_ROUND_MASK 0x00030000 149#define TRIG_ROUND_NEAREST 0x00000000 150#define TRIG_ROUND_DOWN 0x00010000 151#define TRIG_ROUND_UP 0x00020000 152#define TRIG_ROUND_UP_NEXT 0x00030000 153 154/* trigger sources */ 155 156#define TRIG_ANY 0xffffffff 157#define TRIG_INVALID 0x00000000 158 159#define TRIG_NONE 0x00000001 /* never trigger */ 160#define TRIG_NOW 0x00000002 /* trigger now + N ns */ 161#define TRIG_FOLLOW 0x00000004 /* trigger on next lower level trig */ 162#define TRIG_TIME 0x00000008 /* trigger at time N ns */ 163#define TRIG_TIMER 0x00000010 /* trigger at rate N ns */ 164#define TRIG_COUNT 0x00000020 /* trigger when count reaches N */ 165#define TRIG_EXT 0x00000040 /* trigger on external signal N */ 166#define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */ 167#define TRIG_OTHER 0x00000100 /* driver defined */ 168 169/* subdevice flags */ 170 171#define SDF_BUSY 0x0001 /* device is busy */ 172#define SDF_BUSY_OWNER 0x0002 /* device is busy with your job */ 173#define SDF_LOCKED 0x0004 /* subdevice is locked */ 174#define SDF_LOCK_OWNER 0x0008 /* you own lock */ 175#define SDF_MAXDATA 0x0010 /* maxdata depends on channel */ 176#define SDF_FLAGS 0x0020 /* flags depend on channel */ 177#define SDF_RANGETYPE 0x0040 /* range type depends on channel */ 178#define SDF_MODE0 0x0080 /* can do mode 0 */ 179#define SDF_MODE1 0x0100 /* can do mode 1 */ 180#define SDF_MODE2 0x0200 /* can do mode 2 */ 181#define SDF_MODE3 0x0400 /* can do mode 3 */ 182#define SDF_MODE4 0x0800 /* can do mode 4 */ 183#define SDF_CMD 0x1000 /* can do commands (deprecated) */ 184#define SDF_SOFT_CALIBRATED 0x2000 /* subdevice uses software calibration */ 185#define SDF_CMD_WRITE 0x4000 /* can do output commands */ 186#define SDF_CMD_READ 0x8000 /* can do input commands */ 187 188/* subdevice can be read (e.g. analog input) */ 189#define SDF_READABLE 0x00010000 190/* subdevice can be written (e.g. analog output) */ 191#define SDF_WRITABLE 0x00020000 192#define SDF_WRITEABLE SDF_WRITABLE /* spelling error in API */ 193/* subdevice does not have externally visible lines */ 194#define SDF_INTERNAL 0x00040000 195#define SDF_GROUND 0x00100000 /* can do aref=ground */ 196#define SDF_COMMON 0x00200000 /* can do aref=common */ 197#define SDF_DIFF 0x00400000 /* can do aref=diff */ 198#define SDF_OTHER 0x00800000 /* can do aref=other */ 199#define SDF_DITHER 0x01000000 /* can do dithering */ 200#define SDF_DEGLITCH 0x02000000 /* can do deglitching */ 201#define SDF_MMAP 0x04000000 /* can do mmap() */ 202#define SDF_RUNNING 0x08000000 /* subdevice is acquiring data */ 203#define SDF_LSAMPL 0x10000000 /* subdevice uses 32-bit samples */ 204#define SDF_PACKED 0x20000000 /* subdevice can do packed DIO */ 205/* re recyle these flags for PWM */ 206#define SDF_PWM_COUNTER SDF_MODE0 /* PWM can automatically switch off */ 207#define SDF_PWM_HBRIDGE SDF_MODE1 /* PWM is signed (H-bridge) */ 208 209/* subdevice types */ 210 211 enum comedi_subdevice_type { 212 COMEDI_SUBD_UNUSED, /* unused by driver */ 213 COMEDI_SUBD_AI, /* analog input */ 214 COMEDI_SUBD_AO, /* analog output */ 215 COMEDI_SUBD_DI, /* digital input */ 216 COMEDI_SUBD_DO, /* digital output */ 217 COMEDI_SUBD_DIO, /* digital input/output */ 218 COMEDI_SUBD_COUNTER, /* counter */ 219 COMEDI_SUBD_TIMER, /* timer */ 220 COMEDI_SUBD_MEMORY, /* memory, EEPROM, DPRAM */ 221 COMEDI_SUBD_CALIB, /* calibration DACs */ 222 COMEDI_SUBD_PROC, /* processor, DSP */ 223 COMEDI_SUBD_SERIAL, /* serial IO */ 224 COMEDI_SUBD_PWM /* PWM */ 225 }; 226 227/* configuration instructions */ 228 229 enum configuration_ids { 230 INSN_CONFIG_DIO_INPUT = 0, 231 INSN_CONFIG_DIO_OUTPUT = 1, 232 INSN_CONFIG_DIO_OPENDRAIN = 2, 233 INSN_CONFIG_ANALOG_TRIG = 16, 234/* INSN_CONFIG_WAVEFORM = 17, */ 235/* INSN_CONFIG_TRIG = 18, */ 236/* INSN_CONFIG_COUNTER = 19, */ 237 INSN_CONFIG_ALT_SOURCE = 20, 238 INSN_CONFIG_DIGITAL_TRIG = 21, 239 INSN_CONFIG_BLOCK_SIZE = 22, 240 INSN_CONFIG_TIMER_1 = 23, 241 INSN_CONFIG_FILTER = 24, 242 INSN_CONFIG_CHANGE_NOTIFY = 25, 243 244 /*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26, 245 INSN_CONFIG_BIDIRECTIONAL_DATA = 27, 246 INSN_CONFIG_DIO_QUERY = 28, 247 INSN_CONFIG_PWM_OUTPUT = 29, 248 INSN_CONFIG_GET_PWM_OUTPUT = 30, 249 INSN_CONFIG_ARM = 31, 250 INSN_CONFIG_DISARM = 32, 251 INSN_CONFIG_GET_COUNTER_STATUS = 33, 252 INSN_CONFIG_RESET = 34, 253 /* Use CTR as single pulsegenerator */ 254 INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, 255 /* Use CTR as pulsetraingenerator */ 256 INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002, 257 /* Use the counter as encoder */ 258 INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003, 259 INSN_CONFIG_SET_GATE_SRC = 2001, /* Set gate source */ 260 INSN_CONFIG_GET_GATE_SRC = 2002, /* Get gate source */ 261 /* Set master clock source */ 262 INSN_CONFIG_SET_CLOCK_SRC = 2003, 263 INSN_CONFIG_GET_CLOCK_SRC = 2004, /* Get master clock source */ 264 INSN_CONFIG_SET_OTHER_SRC = 2005, /* Set other source */ 265 /* INSN_CONFIG_GET_OTHER_SRC = 2006,*//* Get other source */ 266 /* Get size in bytes of subdevice's on-board fifos used during 267 * streaming input/output */ 268 INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006, 269 INSN_CONFIG_SET_COUNTER_MODE = 4097, 270 /* INSN_CONFIG_8254_SET_MODE is deprecated */ 271 INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE, 272 INSN_CONFIG_8254_READ_STATUS = 4098, 273 INSN_CONFIG_SET_ROUTING = 4099, 274 INSN_CONFIG_GET_ROUTING = 4109, 275/* PWM */ 276 INSN_CONFIG_PWM_SET_PERIOD = 5000, /* sets frequency */ 277 INSN_CONFIG_PWM_GET_PERIOD = 5001, /* gets frequency */ 278 INSN_CONFIG_GET_PWM_STATUS = 5002, /* is it running? */ 279 /* sets H bridge: duty cycle and sign bit for a relay at the 280 * same time */ 281 INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, 282 /* gets H bridge data: duty cycle and the sign bit */ 283 INSN_CONFIG_PWM_GET_H_BRIDGE = 5004 284 }; 285 286 enum comedi_io_direction { 287 COMEDI_INPUT = 0, 288 COMEDI_OUTPUT = 1, 289 COMEDI_OPENDRAIN = 2 290 }; 291 292 enum comedi_support_level { 293 COMEDI_UNKNOWN_SUPPORT = 0, 294 COMEDI_SUPPORTED, 295 COMEDI_UNSUPPORTED 296 }; 297 298/* ioctls */ 299 300#define CIO 'd' 301#define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig) 302#define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo) 303#define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo) 304#define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo) 305#define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig) 306#define COMEDI_LOCK _IO(CIO, 5) 307#define COMEDI_UNLOCK _IO(CIO, 6) 308#define COMEDI_CANCEL _IO(CIO, 7) 309#define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo) 310#define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd) 311#define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd) 312#define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist) 313#define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn) 314#define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig) 315#define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo) 316#define COMEDI_POLL _IO(CIO, 15) 317 318/* structures */ 319 320 struct comedi_trig { 321 unsigned int subdev; /* subdevice */ 322 unsigned int mode; /* mode */ 323 unsigned int flags; 324 unsigned int n_chan; /* number of channels */ 325 unsigned int *chanlist; /* channel/range list */ 326 short *data; /* data list, size depends on subd flags */ 327 unsigned int n; /* number of scans */ 328 unsigned int trigsrc; 329 unsigned int trigvar; 330 unsigned int trigvar1; 331 unsigned int data_len; 332 unsigned int unused[3]; 333 }; 334 335 struct comedi_insn { 336 unsigned int insn; 337 unsigned int n; 338 unsigned int __user *data; 339 unsigned int subdev; 340 unsigned int chanspec; 341 unsigned int unused[3]; 342 }; 343 344 struct comedi_insnlist { 345 unsigned int n_insns; 346 struct comedi_insn __user *insns; 347 }; 348 349 struct comedi_cmd { 350 unsigned int subdev; 351 unsigned int flags; 352 353 unsigned int start_src; 354 unsigned int start_arg; 355 356 unsigned int scan_begin_src; 357 unsigned int scan_begin_arg; 358 359 unsigned int convert_src; 360 unsigned int convert_arg; 361 362 unsigned int scan_end_src; 363 unsigned int scan_end_arg; 364 365 unsigned int stop_src; 366 unsigned int stop_arg; 367 368 unsigned int __user *chanlist; /* channel/range list */ 369 unsigned int chanlist_len; 370 371 short __user *data; /* data list, size depends on subd flags */ 372 unsigned int data_len; 373 }; 374 375 struct comedi_chaninfo { 376 unsigned int subdev; 377 unsigned int __user *maxdata_list; 378 unsigned int __user *flaglist; 379 unsigned int __user *rangelist; 380 unsigned int unused[4]; 381 }; 382 383 struct comedi_rangeinfo { 384 unsigned int range_type; 385 void __user *range_ptr; 386 }; 387 388 struct comedi_krange { 389 int min; /* fixed point, multiply by 1e-6 */ 390 int max; /* fixed point, multiply by 1e-6 */ 391 unsigned int flags; 392 }; 393 394 struct comedi_subdinfo { 395 unsigned int type; 396 unsigned int n_chan; 397 unsigned int subd_flags; 398 unsigned int timer_type; 399 unsigned int len_chanlist; 400 unsigned int maxdata; 401 unsigned int flags; /* channel flags */ 402 unsigned int range_type; /* lookup in kernel */ 403 unsigned int settling_time_0; 404 /* see support_level enum for values */ 405 unsigned insn_bits_support; 406 unsigned int unused[8]; 407 }; 408 409 struct comedi_devinfo { 410 unsigned int version_code; 411 unsigned int n_subdevs; 412 char driver_name[COMEDI_NAMELEN]; 413 char board_name[COMEDI_NAMELEN]; 414 int read_subdevice; 415 int write_subdevice; 416 int unused[30]; 417 }; 418 419 struct comedi_devconfig { 420 char board_name[COMEDI_NAMELEN]; 421 int options[COMEDI_NDEVCONFOPTS]; 422 }; 423 424 struct comedi_bufconfig { 425 unsigned int subdevice; 426 unsigned int flags; 427 428 unsigned int maximum_size; 429 unsigned int size; 430 431 unsigned int unused[4]; 432 }; 433 434 struct comedi_bufinfo { 435 unsigned int subdevice; 436 unsigned int bytes_read; 437 438 unsigned int buf_write_ptr; 439 unsigned int buf_read_ptr; 440 unsigned int buf_write_count; 441 unsigned int buf_read_count; 442 443 unsigned int bytes_written; 444 445 unsigned int unused[4]; 446 }; 447 448/* range stuff */ 449 450#define __RANGE(a, b) ((((a)&0xffff)<<16)|((b)&0xffff)) 451 452#define RANGE_OFFSET(a) (((a)>>16)&0xffff) 453#define RANGE_LENGTH(b) ((b)&0xffff) 454 455#define RF_UNIT(flags) ((flags)&0xff) 456#define RF_EXTERNAL (1<<8) 457 458#define UNIT_volt 0 459#define UNIT_mA 1 460#define UNIT_none 2 461 462#define COMEDI_MIN_SPEED ((unsigned int)0xffffffff) 463 464/* callback stuff */ 465/* only relevant to kernel modules. */ 466 467#define COMEDI_CB_EOS 1 /* end of scan */ 468#define COMEDI_CB_EOA 2 /* end of acquisition */ 469#define COMEDI_CB_BLOCK 4 /* data has arrived: 470 * wakes up read() / write() */ 471#define COMEDI_CB_EOBUF 8 /* DEPRECATED: end of buffer */ 472#define COMEDI_CB_ERROR 16 /* card error during acquisition */ 473#define COMEDI_CB_OVERFLOW 32 /* buffer overflow/underflow */ 474 475/**********************************************************/ 476/* everything after this line is ALPHA */ 477/**********************************************************/ 478 479/* 480 8254 specific configuration. 481 482 It supports two config commands: 483 484 0 ID: INSN_CONFIG_SET_COUNTER_MODE 485 1 8254 Mode 486 I8254_MODE0, I8254_MODE1, ..., I8254_MODE5 487 OR'ed with: 488 I8254_BCD, I8254_BINARY 489 490 0 ID: INSN_CONFIG_8254_READ_STATUS 491 1 <-- Status byte returned here. 492 B7 = Output 493 B6 = NULL Count 494 B5 - B0 Current mode. 495 496*/ 497 498 enum i8254_mode { 499 I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */ 500 I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */ 501 I8254_MODE2 = (2 << 1), /* Rate generator */ 502 I8254_MODE3 = (3 << 1), /* Square wave mode */ 503 I8254_MODE4 = (4 << 1), /* Software triggered strobe */ 504 I8254_MODE5 = (5 << 1), /* Hardware triggered strobe 505 * (retriggerable) */ 506 I8254_BCD = 1, /* use binary-coded decimal instead of binary 507 * (pretty useless) */ 508 I8254_BINARY = 0 509 }; 510 511 static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel) 512 { 513 if (pfi_channel < 10) 514 return 0x1 + pfi_channel; 515 else 516 return 0xb + pfi_channel; 517 } 518 519 static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel) 520 { 521 if (rtsi_channel < 7) 522 return 0xb + rtsi_channel; 523 else 524 return 0x1b; 525 } 526 527/* mode bits for NI general-purpose counters, set with 528 * INSN_CONFIG_SET_COUNTER_MODE */ 529#define NI_GPCT_COUNTING_MODE_SHIFT 16 530#define NI_GPCT_INDEX_PHASE_BITSHIFT 20 531#define NI_GPCT_COUNTING_DIRECTION_SHIFT 24 532 enum ni_gpct_mode_bits { 533 NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4, 534 NI_GPCT_EDGE_GATE_MODE_MASK = 0x18, 535 NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0, 536 NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8, 537 NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10, 538 NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18, 539 NI_GPCT_STOP_MODE_MASK = 0x60, 540 NI_GPCT_STOP_ON_GATE_BITS = 0x00, 541 NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20, 542 NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40, 543 NI_GPCT_LOAD_B_SELECT_BIT = 0x80, 544 NI_GPCT_OUTPUT_MODE_MASK = 0x300, 545 NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100, 546 NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200, 547 NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300, 548 NI_GPCT_HARDWARE_DISARM_MASK = 0xc00, 549 NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000, 550 NI_GPCT_DISARM_AT_TC_BITS = 0x400, 551 NI_GPCT_DISARM_AT_GATE_BITS = 0x800, 552 NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00, 553 NI_GPCT_LOADING_ON_TC_BIT = 0x1000, 554 NI_GPCT_LOADING_ON_GATE_BIT = 0x4000, 555 NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT, 556 NI_GPCT_COUNTING_MODE_NORMAL_BITS = 557 0x0 << NI_GPCT_COUNTING_MODE_SHIFT, 558 NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS = 559 0x1 << NI_GPCT_COUNTING_MODE_SHIFT, 560 NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS = 561 0x2 << NI_GPCT_COUNTING_MODE_SHIFT, 562 NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS = 563 0x3 << NI_GPCT_COUNTING_MODE_SHIFT, 564 NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS = 565 0x4 << NI_GPCT_COUNTING_MODE_SHIFT, 566 NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS = 567 0x6 << NI_GPCT_COUNTING_MODE_SHIFT, 568 NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 569 NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS = 570 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT, 571 NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS = 572 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT, 573 NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS = 574 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT, 575 NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS = 576 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 577 NI_GPCT_INDEX_ENABLE_BIT = 0x400000, 578 NI_GPCT_COUNTING_DIRECTION_MASK = 579 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 580 NI_GPCT_COUNTING_DIRECTION_DOWN_BITS = 581 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 582 NI_GPCT_COUNTING_DIRECTION_UP_BITS = 583 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 584 NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS = 585 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 586 NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS = 587 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 588 NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000, 589 NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0, 590 NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000, 591 NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000, 592 NI_GPCT_OR_GATE_BIT = 0x10000000, 593 NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000 594 }; 595 596/* Bits for setting a clock source with 597 * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */ 598 enum ni_gpct_clock_source_bits { 599 NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f, 600 NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0, 601 NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1, 602 NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2, 603 NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3, 604 NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4, 605 NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5, 606 /* NI 660x-specific */ 607 NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6, 608 NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7, 609 NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8, 610 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9, 611 NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000, 612 NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0, 613 /* divide source by 2 */ 614 NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, 615 /* divide source by 8 */ 616 NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, 617 NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000 618 }; 619 static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n) 620 { 621 /* NI 660x-specific */ 622 return 0x10 + n; 623 } 624 static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n) 625 { 626 return 0x18 + n; 627 } 628 static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n) 629 { 630 /* no pfi on NI 660x */ 631 return 0x20 + n; 632 } 633 634/* Possibilities for setting a gate source with 635INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters. 636May be bitwise-or'd with CR_EDGE or CR_INVERT. */ 637 enum ni_gpct_gate_select { 638 /* m-series gates */ 639 NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0, 640 NI_GPCT_AI_START2_GATE_SELECT = 0x12, 641 NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13, 642 NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14, 643 NI_GPCT_AI_START1_GATE_SELECT = 0x1c, 644 NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d, 645 NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e, 646 NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f, 647 /* more gates for 660x */ 648 NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100, 649 NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101, 650 /* more gates for 660x "second gate" */ 651 NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201, 652 NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e, 653 /* m-series "second gate" sources are unknown, 654 * we should add them here with an offset of 0x300 when 655 * known. */ 656 NI_GPCT_DISABLED_GATE_SELECT = 0x8000, 657 }; 658 static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n) 659 { 660 return 0x102 + n; 661 } 662 static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n) 663 { 664 return NI_USUAL_RTSI_SELECT(n); 665 } 666 static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n) 667 { 668 return NI_USUAL_PFI_SELECT(n); 669 } 670 static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n) 671 { 672 return 0x202 + n; 673 } 674 675/* Possibilities for setting a source with 676INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */ 677 enum ni_gpct_other_index { 678 NI_GPCT_SOURCE_ENCODER_A, 679 NI_GPCT_SOURCE_ENCODER_B, 680 NI_GPCT_SOURCE_ENCODER_Z 681 }; 682 enum ni_gpct_other_select { 683 /* m-series gates */ 684 /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */ 685 NI_GPCT_DISABLED_OTHER_SELECT = 0x8000, 686 }; 687 static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n) 688 { 689 return NI_USUAL_PFI_SELECT(n); 690 } 691 692/* start sources for ni general-purpose counters for use with 693INSN_CONFIG_ARM */ 694 enum ni_gpct_arm_source { 695 NI_GPCT_ARM_IMMEDIATE = 0x0, 696 NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter 697 * and the adjacent paired 698 * counter simultaneously */ 699 /* NI doesn't document bits for selecting hardware arm triggers. 700 * If the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least 701 * significant bits (3 bits for 660x or 5 bits for m-series) 702 * through to the hardware. This will at least allow someone to 703 * figure out what the bits do later. */ 704 NI_GPCT_ARM_UNKNOWN = 0x1000, 705 }; 706 707/* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */ 708 enum ni_gpct_filter_select { 709 NI_GPCT_FILTER_OFF = 0x0, 710 NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1, 711 NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2, 712 NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3, 713 NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4, 714 NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5, 715 NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6 716 }; 717 718/* PFI digital filtering options for ni m-series for use with 719 * INSN_CONFIG_FILTER. */ 720 enum ni_pfi_filter_select { 721 NI_PFI_FILTER_OFF = 0x0, 722 NI_PFI_FILTER_125ns = 0x1, 723 NI_PFI_FILTER_6425ns = 0x2, 724 NI_PFI_FILTER_2550us = 0x3 725 }; 726 727/* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */ 728 enum ni_mio_clock_source { 729 NI_MIO_INTERNAL_CLOCK = 0, 730 NI_MIO_RTSI_CLOCK = 1, /* doesn't work for m-series, use 731 NI_MIO_PLL_RTSI_CLOCK() */ 732 /* the NI_MIO_PLL_* sources are m-series only */ 733 NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2, 734 NI_MIO_PLL_PXI10_CLOCK = 3, 735 NI_MIO_PLL_RTSI0_CLOCK = 4 736 }; 737 static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel) 738 { 739 return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel; 740 } 741 742/* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING. 743 The numbers assigned are not arbitrary, they correspond to the bits required 744 to program the board. */ 745 enum ni_rtsi_routing { 746 NI_RTSI_OUTPUT_ADR_START1 = 0, 747 NI_RTSI_OUTPUT_ADR_START2 = 1, 748 NI_RTSI_OUTPUT_SCLKG = 2, 749 NI_RTSI_OUTPUT_DACUPDN = 3, 750 NI_RTSI_OUTPUT_DA_START1 = 4, 751 NI_RTSI_OUTPUT_G_SRC0 = 5, 752 NI_RTSI_OUTPUT_G_GATE0 = 6, 753 NI_RTSI_OUTPUT_RGOUT0 = 7, 754 NI_RTSI_OUTPUT_RTSI_BRD_0 = 8, 755 NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI 756 * clock on line 7 */ 757 }; 758 static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n) 759 { 760 return NI_RTSI_OUTPUT_RTSI_BRD_0 + n; 761 } 762 763/* Signals which can be routed to an NI PFI pin on an m-series board with 764 * INSN_CONFIG_SET_ROUTING. These numbers are also returned by 765 * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing 766 * cannot be changed. The numbers assigned are not arbitrary, they correspond 767 * to the bits required to program the board. */ 768 enum ni_pfi_routing { 769 NI_PFI_OUTPUT_PFI_DEFAULT = 0, 770 NI_PFI_OUTPUT_AI_START1 = 1, 771 NI_PFI_OUTPUT_AI_START2 = 2, 772 NI_PFI_OUTPUT_AI_CONVERT = 3, 773 NI_PFI_OUTPUT_G_SRC1 = 4, 774 NI_PFI_OUTPUT_G_GATE1 = 5, 775 NI_PFI_OUTPUT_AO_UPDATE_N = 6, 776 NI_PFI_OUTPUT_AO_START1 = 7, 777 NI_PFI_OUTPUT_AI_START_PULSE = 8, 778 NI_PFI_OUTPUT_G_SRC0 = 9, 779 NI_PFI_OUTPUT_G_GATE0 = 10, 780 NI_PFI_OUTPUT_EXT_STROBE = 11, 781 NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12, 782 NI_PFI_OUTPUT_GOUT0 = 13, 783 NI_PFI_OUTPUT_GOUT1 = 14, 784 NI_PFI_OUTPUT_FREQ_OUT = 15, 785 NI_PFI_OUTPUT_PFI_DO = 16, 786 NI_PFI_OUTPUT_I_ATRIG = 17, 787 NI_PFI_OUTPUT_RTSI0 = 18, 788 NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26, 789 NI_PFI_OUTPUT_SCXI_TRIG1 = 27, 790 NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28, 791 NI_PFI_OUTPUT_CDI_SAMPLE = 29, 792 NI_PFI_OUTPUT_CDO_UPDATE = 30 793 }; 794 static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel) 795 { 796 return NI_PFI_OUTPUT_RTSI0 + rtsi_channel; 797 } 798 799/* Signals which can be routed to output on a NI PFI pin on a 660x board 800 with INSN_CONFIG_SET_ROUTING. The numbers assigned are 801 not arbitrary, they correspond to the bits required 802 to program the board. Lines 0 to 7 can only be set to 803 NI_660X_PFI_OUTPUT_DIO. Lines 32 to 39 can only be set to 804 NI_660X_PFI_OUTPUT_COUNTER. */ 805 enum ni_660x_pfi_routing { 806 NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */ 807 NI_660X_PFI_OUTPUT_DIO = 2, /* static digital output */ 808 }; 809 810/* NI External Trigger lines. These values are not arbitrary, but are related 811 * to the bits required to program the board (offset by 1 for historical 812 * reasons). */ 813 static inline unsigned NI_EXT_PFI(unsigned pfi_channel) 814 { 815 return NI_USUAL_PFI_SELECT(pfi_channel) - 1; 816 } 817 static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel) 818 { 819 return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1; 820 } 821 822/* status bits for INSN_CONFIG_GET_COUNTER_STATUS */ 823 enum comedi_counter_status_flags { 824 COMEDI_COUNTER_ARMED = 0x1, 825 COMEDI_COUNTER_COUNTING = 0x2, 826 COMEDI_COUNTER_TERMINAL_COUNT = 0x4, 827 }; 828 829/* Clock sources for CDIO subdevice on NI m-series boards. Used as the 830 * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd 831 * with CR_INVERT to change polarity. */ 832 enum ni_m_series_cdio_scan_begin_src { 833 NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0, 834 NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18, 835 NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19, 836 NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20, 837 NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28, 838 NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29, 839 NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30, 840 NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31, 841 NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32, 842 NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33 843 }; 844 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) 845 { 846 return NI_USUAL_PFI_SELECT(pfi_channel); 847 } 848 static inline unsigned 849 NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel) 850 { 851 return NI_USUAL_RTSI_SELECT(rtsi_channel); 852 } 853 854/* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI 855 * boards. These scan begin sources can also be bitwise-or'd with CR_INVERT to 856 * change polarity. */ 857 static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) 858 { 859 return NI_USUAL_PFI_SELECT(pfi_channel); 860 } 861 static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel) 862 { 863 return NI_USUAL_RTSI_SELECT(rtsi_channel); 864 } 865 866/* Bits for setting a clock source with 867 * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */ 868 enum ni_freq_out_clock_source_bits { 869 NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */ 870 NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC /* 100 KHz */ 871 }; 872 873/* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for 874 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */ 875 enum amplc_dio_clock_source { 876 AMPLC_DIO_CLK_CLKN, /* per channel external clock 877 input/output pin (pin is only an 878 input when clock source set to this 879 value, otherwise it is an output) */ 880 AMPLC_DIO_CLK_10MHZ, /* 10 MHz internal clock */ 881 AMPLC_DIO_CLK_1MHZ, /* 1 MHz internal clock */ 882 AMPLC_DIO_CLK_100KHZ, /* 100 kHz internal clock */ 883 AMPLC_DIO_CLK_10KHZ, /* 10 kHz internal clock */ 884 AMPLC_DIO_CLK_1KHZ, /* 1 kHz internal clock */ 885 AMPLC_DIO_CLK_OUTNM1, /* output of preceding counter channel 886 (for channel 0, preceding counter 887 channel is channel 2 on preceding 888 counter subdevice, for first counter 889 subdevice, preceding counter 890 subdevice is the last counter 891 subdevice) */ 892 AMPLC_DIO_CLK_EXT /* per chip external input pin */ 893 }; 894 895/* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for 896 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */ 897 enum amplc_dio_gate_source { 898 AMPLC_DIO_GAT_VCC, /* internal high logic level */ 899 AMPLC_DIO_GAT_GND, /* internal low logic level */ 900 AMPLC_DIO_GAT_GATN, /* per channel external gate input */ 901 AMPLC_DIO_GAT_NOUTNM2, /* negated output of counter channel 902 minus 2 (for channels 0 or 1, 903 channel minus 2 is channel 1 or 2 on 904 the preceding counter subdevice, for 905 the first counter subdevice the 906 preceding counter subdevice is the 907 last counter subdevice) */ 908 AMPLC_DIO_GAT_RESERVED4, 909 AMPLC_DIO_GAT_RESERVED5, 910 AMPLC_DIO_GAT_RESERVED6, 911 AMPLC_DIO_GAT_RESERVED7 912 }; 913 914#endif /* _COMEDI_H */ 915