cb_pcidas.c revision 8bde85db943971ea57780823e25778068d77eead
1/* 2 comedi/drivers/cb_pcidas.c 3 4 Developed by Ivan Martinez and Frank Mori Hess, with valuable help from 5 David Schleef and the rest of the Comedi developers comunity. 6 7 Copyright (C) 2001-2003 Ivan Martinez <imr@oersted.dtu.dk> 8 Copyright (C) 2001,2002 Frank Mori Hess <fmhess@users.sourceforge.net> 9 10 COMEDI - Linux Control and Measurement Device Interface 11 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> 12 13 This program is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as published by 15 the Free Software Foundation; either version 2 of the License, or 16 (at your option) any later version. 17 18 This program is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with this program; if not, write to the Free Software 25 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 27************************************************************************ 28*/ 29/* 30Driver: cb_pcidas 31Description: MeasurementComputing PCI-DAS series with the AMCC S5933 PCI controller 32Author: Ivan Martinez <imr@oersted.dtu.dk>, 33 Frank Mori Hess <fmhess@users.sourceforge.net> 34Updated: 2003-3-11 35Devices: [Measurement Computing] PCI-DAS1602/16 (cb_pcidas), 36 PCI-DAS1602/16jr, PCI-DAS1602/12, PCI-DAS1200, PCI-DAS1200jr, 37 PCI-DAS1000, PCI-DAS1001, PCI_DAS1002 38 39Status: 40 There are many reports of the driver being used with most of the 41 supported cards. Despite no detailed log is maintained, it can 42 be said that the driver is quite tested and stable. 43 44 The boards may be autocalibrated using the comedi_calibrate 45 utility. 46 47Configuration options: 48 [0] - PCI bus of device (optional) 49 [1] - PCI slot of device (optional) 50 If bus/slot is not specified, the first supported 51 PCI device found will be used. 52 53For commands, the scanned channels must be consecutive 54(i.e. 4-5-6-7, 2-3-4,...), and must all have the same 55range and aref. 56 57AI Triggering: 58 For start_src == TRIG_EXT, the A/D EXTERNAL TRIGGER IN (pin 45) is used. 59 For 1602 series, the start_arg is interpreted as follows: 60 start_arg == 0 => gated triger (level high) 61 start_arg == CR_INVERT => gated triger (level low) 62 start_arg == CR_EDGE => Rising edge 63 start_arg == CR_EDGE | CR_INVERT => Falling edge 64 For the other boards the trigger will be done on rising edge 65*/ 66/* 67 68TODO: 69 70analog triggering on 1602 series 71*/ 72 73#include "../comedidev.h" 74#include <linux/delay.h> 75#include <linux/interrupt.h> 76 77#include "8253.h" 78#include "8255.h" 79#include "amcc_s5933.h" 80#include "comedi_pci.h" 81#include "comedi_fc.h" 82 83#undef CB_PCIDAS_DEBUG /* disable debugging code */ 84/* #define CB_PCIDAS_DEBUG enable debugging code */ 85 86/* PCI vendor number of ComputerBoards/MeasurementComputing */ 87#define PCI_VENDOR_ID_CB 0x1307 88#define TIMER_BASE 100 /* 10MHz master clock */ 89#define AI_BUFFER_SIZE 1024 /* maximum fifo size of any supported board */ 90#define AO_BUFFER_SIZE 1024 /* maximum fifo size of any supported board */ 91#define NUM_CHANNELS_8800 8 92#define NUM_CHANNELS_7376 1 93#define NUM_CHANNELS_8402 2 94#define NUM_CHANNELS_DAC08 1 95 96/* PCI-DAS base addresses */ 97 98/* indices of base address regions */ 99#define S5933_BADRINDEX 0 100#define CONT_STAT_BADRINDEX 1 101#define ADC_FIFO_BADRINDEX 2 102#define PACER_BADRINDEX 3 103#define AO_BADRINDEX 4 104/* sizes of io regions */ 105#define CONT_STAT_SIZE 10 106#define ADC_FIFO_SIZE 4 107#define PACER_SIZE 12 108#define AO_SIZE 4 109 110/* Control/Status registers */ 111#define INT_ADCFIFO 0 /* INTERRUPT / ADC FIFO register */ 112#define INT_EOS 0x1 /* interrupt end of scan */ 113#define INT_FHF 0x2 /* interrupt fifo half full */ 114#define INT_FNE 0x3 /* interrupt fifo not empty */ 115#define INT_MASK 0x3 /* mask of interrupt select bits */ 116#define INTE 0x4 /* interrupt enable */ 117#define DAHFIE 0x8 /* dac half full interrupt enable */ 118#define EOAIE 0x10 /* end of acquisition interrupt enable */ 119#define DAHFI 0x20 /* dac half full read status / write interrupt clear */ 120#define EOAI 0x40 /* read end of acq. interrupt status / write clear */ 121#define INT 0x80 /* read interrupt status / write clear */ 122#define EOBI 0x200 /* read end of burst interrupt status */ 123#define ADHFI 0x400 /* read half-full interrupt status */ 124#define ADNEI 0x800 /* read fifo not empty interrupt latch status */ 125#define ADNE 0x1000 /* read, fifo not empty (realtime, not latched) status */ 126#define DAEMIE 0x1000 /* write, dac empty interrupt enable */ 127#define LADFUL 0x2000 /* read fifo overflow / write clear */ 128#define DAEMI 0x4000 /* dac fifo empty interrupt status / write clear */ 129 130#define ADCMUX_CONT 2 /* ADC CHANNEL MUX AND CONTROL register */ 131#define BEGIN_SCAN(x) ((x) & 0xf) 132#define END_SCAN(x) (((x) & 0xf) << 4) 133#define GAIN_BITS(x) (((x) & 0x3) << 8) 134#define UNIP 0x800 /* Analog front-end unipolar for range */ 135#define SE 0x400 /* Inputs in single-ended mode */ 136#define PACER_MASK 0x3000 /* pacer source bits */ 137#define PACER_INT 0x1000 /* internal pacer */ 138#define PACER_EXT_FALL 0x2000 /* external falling edge */ 139#define PACER_EXT_RISE 0x3000 /* external rising edge */ 140#define EOC 0x4000 /* adc not busy */ 141 142#define TRIG_CONTSTAT 4 /* TRIGGER CONTROL/STATUS register */ 143#define SW_TRIGGER 0x1 /* software start trigger */ 144#define EXT_TRIGGER 0x2 /* external start trigger */ 145#define ANALOG_TRIGGER 0x3 /* external analog trigger */ 146#define TRIGGER_MASK 0x3 /* mask of bits that determine start trigger */ 147#define TGPOL 0x04 /* invert the edge/level of the external trigger (1602 only) */ 148#define TGSEL 0x08 /* if set edge triggered, otherwise level trigerred (1602 only) */ 149#define TGEN 0x10 /* enable external start trigger */ 150#define BURSTE 0x20 /* burst mode enable */ 151#define XTRCL 0x80 /* clear external trigger */ 152 153#define CALIBRATION_REG 6 /* CALIBRATION register */ 154#define SELECT_8800_BIT 0x100 /* select 8800 caldac */ 155#define SELECT_TRIMPOT_BIT 0x200 /* select ad7376 trim pot */ 156#define SELECT_DAC08_BIT 0x400 /* select dac08 caldac */ 157#define CAL_SRC_BITS(x) (((x) & 0x7) << 11) 158#define CAL_EN_BIT 0x4000 /* read calibration source instead of analog input channel 0 */ 159#define SERIAL_DATA_IN_BIT 0x8000 /* serial data stream going to 8800 and 7376 */ 160 161#define DAC_CSR 0x8 /* dac control and status register */ 162enum dac_csr_bits { 163 DACEN = 0x2, /* dac enable */ 164 DAC_MODE_UPDATE_BOTH = 0x80, /* update both dacs when dac0 is written */ 165}; 166static inline unsigned int DAC_RANGE(unsigned int channel, unsigned int range) 167{ 168 return (range & 0x3) << (8 + 2 * (channel & 0x1)); 169} 170 171static inline unsigned int DAC_RANGE_MASK(unsigned int channel) 172{ 173 return 0x3 << (8 + 2 * (channel & 0x1)); 174}; 175 176/* bits for 1602 series only */ 177enum dac_csr_bits_1602 { 178 DAC_EMPTY = 0x1, /* dac fifo empty, read, write clear */ 179 DAC_START = 0x4, /* start/arm dac fifo operations */ 180 DAC_PACER_MASK = 0x18, /* bits that set dac pacer source */ 181 DAC_PACER_INT = 0x8, /* dac internal pacing */ 182 DAC_PACER_EXT_FALL = 0x10, /* dac external pacing, falling edge */ 183 DAC_PACER_EXT_RISE = 0x18, /* dac external pacing, rising edge */ 184}; 185static inline unsigned int DAC_CHAN_EN(unsigned int channel) 186{ 187 return 1 << (5 + (channel & 0x1)); /* enable channel 0 or 1 */ 188}; 189 190/* analog input fifo */ 191#define ADCDATA 0 /* ADC DATA register */ 192#define ADCFIFOCLR 2 /* ADC FIFO CLEAR */ 193 194/* pacer, counter, dio registers */ 195#define ADC8254 0 196#define DIO_8255 4 197#define DAC8254 8 198 199/* analog output registers for 100x, 1200 series */ 200static inline unsigned int DAC_DATA_REG(unsigned int channel) 201{ 202 return 2 * (channel & 0x1); 203} 204 205/* analog output registers for 1602 series*/ 206#define DACDATA 0 /* DAC DATA register */ 207#define DACFIFOCLR 2 /* DAC FIFO CLEAR */ 208 209/* bit in hexadecimal representation of range index that indicates unipolar input range */ 210#define IS_UNIPOLAR 0x4 211/* analog input ranges for most boards */ 212static const struct comedi_lrange cb_pcidas_ranges = { 213 8, 214 { 215 BIP_RANGE(10), 216 BIP_RANGE(5), 217 BIP_RANGE(2.5), 218 BIP_RANGE(1.25), 219 UNI_RANGE(10), 220 UNI_RANGE(5), 221 UNI_RANGE(2.5), 222 UNI_RANGE(1.25) 223 } 224}; 225 226/* pci-das1001 input ranges */ 227static const struct comedi_lrange cb_pcidas_alt_ranges = { 228 8, 229 { 230 BIP_RANGE(10), 231 BIP_RANGE(1), 232 BIP_RANGE(0.1), 233 BIP_RANGE(0.01), 234 UNI_RANGE(10), 235 UNI_RANGE(1), 236 UNI_RANGE(0.1), 237 UNI_RANGE(0.01) 238 } 239}; 240 241/* analog output ranges */ 242static const struct comedi_lrange cb_pcidas_ao_ranges = { 243 4, 244 { 245 BIP_RANGE(5), 246 BIP_RANGE(10), 247 UNI_RANGE(5), 248 UNI_RANGE(10), 249 } 250}; 251 252enum trimpot_model { 253 AD7376, 254 AD8402, 255}; 256 257struct cb_pcidas_board { 258 const char *name; 259 unsigned short device_id; 260 int ai_se_chans; /* Inputs in single-ended mode */ 261 int ai_diff_chans; /* Inputs in differential mode */ 262 int ai_bits; /* analog input resolution */ 263 int ai_speed; /* fastest conversion period in ns */ 264 int ao_nchan; /* number of analog out channels */ 265 int has_ao_fifo; /* analog output has fifo */ 266 int ao_scan_speed; /* analog output speed for 1602 series (for a scan, not conversion) */ 267 int fifo_size; /* number of samples fifo can hold */ 268 const struct comedi_lrange *ranges; 269 enum trimpot_model trimpot; 270 unsigned has_dac08:1; 271 unsigned has_ai_trig_gated:1; /* Tells if the AI trigger can be gated */ 272 unsigned has_ai_trig_invert:1; /* Tells if the AI trigger can be inverted */ 273}; 274 275static const struct cb_pcidas_board cb_pcidas_boards[] = { 276 { 277 .name = "pci-das1602/16", 278 .device_id = 0x1, 279 .ai_se_chans = 16, 280 .ai_diff_chans = 8, 281 .ai_bits = 16, 282 .ai_speed = 5000, 283 .ao_nchan = 2, 284 .has_ao_fifo = 1, 285 .ao_scan_speed = 10000, 286 .fifo_size = 512, 287 .ranges = &cb_pcidas_ranges, 288 .trimpot = AD8402, 289 .has_dac08 = 1, 290 .has_ai_trig_gated = 1, 291 .has_ai_trig_invert = 1, 292 }, 293 { 294 .name = "pci-das1200", 295 .device_id = 0xF, 296 .ai_se_chans = 16, 297 .ai_diff_chans = 8, 298 .ai_bits = 12, 299 .ai_speed = 3200, 300 .ao_nchan = 2, 301 .has_ao_fifo = 0, 302 .fifo_size = 1024, 303 .ranges = &cb_pcidas_ranges, 304 .trimpot = AD7376, 305 .has_dac08 = 0, 306 .has_ai_trig_gated = 0, 307 .has_ai_trig_invert = 0, 308 }, 309 { 310 .name = "pci-das1602/12", 311 .device_id = 0x10, 312 .ai_se_chans = 16, 313 .ai_diff_chans = 8, 314 .ai_bits = 12, 315 .ai_speed = 3200, 316 .ao_nchan = 2, 317 .has_ao_fifo = 1, 318 .ao_scan_speed = 4000, 319 .fifo_size = 1024, 320 .ranges = &cb_pcidas_ranges, 321 .trimpot = AD7376, 322 .has_dac08 = 0, 323 .has_ai_trig_gated = 1, 324 .has_ai_trig_invert = 1, 325 }, 326 { 327 .name = "pci-das1200/jr", 328 .device_id = 0x19, 329 .ai_se_chans = 16, 330 .ai_diff_chans = 8, 331 .ai_bits = 12, 332 .ai_speed = 3200, 333 .ao_nchan = 0, 334 .has_ao_fifo = 0, 335 .fifo_size = 1024, 336 .ranges = &cb_pcidas_ranges, 337 .trimpot = AD7376, 338 .has_dac08 = 0, 339 .has_ai_trig_gated = 0, 340 .has_ai_trig_invert = 0, 341 }, 342 { 343 .name = "pci-das1602/16/jr", 344 .device_id = 0x1C, 345 .ai_se_chans = 16, 346 .ai_diff_chans = 8, 347 .ai_bits = 16, 348 .ai_speed = 5000, 349 .ao_nchan = 0, 350 .has_ao_fifo = 0, 351 .fifo_size = 512, 352 .ranges = &cb_pcidas_ranges, 353 .trimpot = AD8402, 354 .has_dac08 = 1, 355 .has_ai_trig_gated = 1, 356 .has_ai_trig_invert = 1, 357 }, 358 { 359 .name = "pci-das1000", 360 .device_id = 0x4C, 361 .ai_se_chans = 16, 362 .ai_diff_chans = 8, 363 .ai_bits = 12, 364 .ai_speed = 4000, 365 .ao_nchan = 0, 366 .has_ao_fifo = 0, 367 .fifo_size = 1024, 368 .ranges = &cb_pcidas_ranges, 369 .trimpot = AD7376, 370 .has_dac08 = 0, 371 .has_ai_trig_gated = 0, 372 .has_ai_trig_invert = 0, 373 }, 374 { 375 .name = "pci-das1001", 376 .device_id = 0x1a, 377 .ai_se_chans = 16, 378 .ai_diff_chans = 8, 379 .ai_bits = 12, 380 .ai_speed = 6800, 381 .ao_nchan = 2, 382 .has_ao_fifo = 0, 383 .fifo_size = 1024, 384 .ranges = &cb_pcidas_alt_ranges, 385 .trimpot = AD7376, 386 .has_dac08 = 0, 387 .has_ai_trig_gated = 0, 388 .has_ai_trig_invert = 0, 389 }, 390 { 391 .name = "pci-das1002", 392 .device_id = 0x1b, 393 .ai_se_chans = 16, 394 .ai_diff_chans = 8, 395 .ai_bits = 12, 396 .ai_speed = 6800, 397 .ao_nchan = 2, 398 .has_ao_fifo = 0, 399 .fifo_size = 1024, 400 .ranges = &cb_pcidas_ranges, 401 .trimpot = AD7376, 402 .has_dac08 = 0, 403 .has_ai_trig_gated = 0, 404 .has_ai_trig_invert = 0, 405 }, 406}; 407 408static DEFINE_PCI_DEVICE_TABLE(cb_pcidas_pci_table) = { 409 { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0001) }, 410 { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x000f) }, 411 { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0010) }, 412 { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0019) }, 413 { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x001c) }, 414 { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x004c) }, 415 { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x001a) }, 416 { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x001b) }, 417 { 0 } 418}; 419 420MODULE_DEVICE_TABLE(pci, cb_pcidas_pci_table); 421 422/* 423 * Useful for shorthand access to the particular board structure 424 */ 425#define thisboard ((const struct cb_pcidas_board *)dev->board_ptr) 426 427/* this structure is for data unique to this hardware driver. If 428 several hardware drivers keep similar information in this structure, 429 feel free to suggest moving the variable to the struct comedi_device struct. */ 430struct cb_pcidas_private { 431 /* would be useful for a PCI device */ 432 struct pci_dev *pci_dev; 433 /* base addresses */ 434 unsigned long s5933_config; 435 unsigned long control_status; 436 unsigned long adc_fifo; 437 unsigned long pacer_counter_dio; 438 unsigned long ao_registers; 439 /* divisors of master clock for analog input pacing */ 440 unsigned int divisor1; 441 unsigned int divisor2; 442 volatile unsigned int count; /* number of analog input samples remaining */ 443 volatile unsigned int adc_fifo_bits; /* bits to write to interrupt/adcfifo register */ 444 volatile unsigned int s5933_intcsr_bits; /* bits to write to amcc s5933 interrupt control/status register */ 445 volatile unsigned int ao_control_bits; /* bits to write to ao control and status register */ 446 short ai_buffer[AI_BUFFER_SIZE]; 447 short ao_buffer[AO_BUFFER_SIZE]; 448 /* divisors of master clock for analog output pacing */ 449 unsigned int ao_divisor1; 450 unsigned int ao_divisor2; 451 volatile unsigned int ao_count; /* number of analog output samples remaining */ 452 int ao_value[2]; /* remember what the analog outputs are set to, to allow readback */ 453 unsigned int caldac_value[NUM_CHANNELS_8800]; /* for readback of caldac */ 454 unsigned int trimpot_value[NUM_CHANNELS_8402]; /* for readback of trimpot */ 455 unsigned int dac08_value; 456 unsigned int calibration_source; 457}; 458 459/* 460 * most drivers define the following macro to make it easy to 461 * access the private structure. 462 */ 463#define devpriv ((struct cb_pcidas_private *)dev->private) 464 465/* 466 * The struct comedi_driver structure tells the Comedi core module 467 * which functions to call to configure/deconfigure (attach/detach) 468 * the board, and also about the kernel module that contains 469 * the device code. 470 */ 471static int cb_pcidas_attach(struct comedi_device *dev, 472 struct comedi_devconfig *it); 473static int cb_pcidas_detach(struct comedi_device *dev); 474static struct comedi_driver driver_cb_pcidas = { 475 .driver_name = "cb_pcidas", 476 .module = THIS_MODULE, 477 .attach = cb_pcidas_attach, 478 .detach = cb_pcidas_detach, 479}; 480 481static int cb_pcidas_ai_rinsn(struct comedi_device *dev, 482 struct comedi_subdevice *s, 483 struct comedi_insn *insn, unsigned int *data); 484static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s, 485 struct comedi_insn *insn, unsigned int *data); 486static int cb_pcidas_ao_nofifo_winsn(struct comedi_device *dev, 487 struct comedi_subdevice *s, 488 struct comedi_insn *insn, 489 unsigned int *data); 490static int cb_pcidas_ao_fifo_winsn(struct comedi_device *dev, 491 struct comedi_subdevice *s, 492 struct comedi_insn *insn, 493 unsigned int *data); 494static int cb_pcidas_ao_readback_insn(struct comedi_device *dev, 495 struct comedi_subdevice *s, 496 struct comedi_insn *insn, 497 unsigned int *data); 498static int cb_pcidas_ai_cmd(struct comedi_device *dev, 499 struct comedi_subdevice *s); 500static int cb_pcidas_ai_cmdtest(struct comedi_device *dev, 501 struct comedi_subdevice *s, 502 struct comedi_cmd *cmd); 503static int cb_pcidas_ao_cmd(struct comedi_device *dev, 504 struct comedi_subdevice *s); 505static int cb_pcidas_ao_inttrig(struct comedi_device *dev, 506 struct comedi_subdevice *subdev, 507 unsigned int trig_num); 508static int cb_pcidas_ao_cmdtest(struct comedi_device *dev, 509 struct comedi_subdevice *s, 510 struct comedi_cmd *cmd); 511static irqreturn_t cb_pcidas_interrupt(int irq, void *d); 512static void handle_ao_interrupt(struct comedi_device *dev, unsigned int status); 513static int cb_pcidas_cancel(struct comedi_device *dev, 514 struct comedi_subdevice *s); 515static int cb_pcidas_ao_cancel(struct comedi_device *dev, 516 struct comedi_subdevice *s); 517static void cb_pcidas_load_counters(struct comedi_device *dev, unsigned int *ns, 518 int round_flags); 519static int eeprom_read_insn(struct comedi_device *dev, 520 struct comedi_subdevice *s, 521 struct comedi_insn *insn, unsigned int *data); 522static int caldac_read_insn(struct comedi_device *dev, 523 struct comedi_subdevice *s, 524 struct comedi_insn *insn, unsigned int *data); 525static int caldac_write_insn(struct comedi_device *dev, 526 struct comedi_subdevice *s, 527 struct comedi_insn *insn, unsigned int *data); 528static int trimpot_read_insn(struct comedi_device *dev, 529 struct comedi_subdevice *s, 530 struct comedi_insn *insn, unsigned int *data); 531static int cb_pcidas_trimpot_write(struct comedi_device *dev, 532 unsigned int channel, unsigned int value); 533static int trimpot_write_insn(struct comedi_device *dev, 534 struct comedi_subdevice *s, 535 struct comedi_insn *insn, unsigned int *data); 536static int dac08_read_insn(struct comedi_device *dev, 537 struct comedi_subdevice *s, struct comedi_insn *insn, 538 unsigned int *data); 539static int dac08_write(struct comedi_device *dev, unsigned int value); 540static int dac08_write_insn(struct comedi_device *dev, 541 struct comedi_subdevice *s, 542 struct comedi_insn *insn, unsigned int *data); 543static int caldac_8800_write(struct comedi_device *dev, unsigned int address, 544 uint8_t value); 545static int trimpot_7376_write(struct comedi_device *dev, uint8_t value); 546static int trimpot_8402_write(struct comedi_device *dev, unsigned int channel, 547 uint8_t value); 548static int nvram_read(struct comedi_device *dev, unsigned int address, 549 uint8_t *data); 550 551static inline unsigned int cal_enable_bits(struct comedi_device *dev) 552{ 553 return CAL_EN_BIT | CAL_SRC_BITS(devpriv->calibration_source); 554} 555 556/* 557 * Attach is called by the Comedi core to configure the driver 558 * for a particular board. 559 */ 560static int cb_pcidas_attach(struct comedi_device *dev, 561 struct comedi_devconfig *it) 562{ 563 struct comedi_subdevice *s; 564 struct pci_dev *pcidev = NULL; 565 int index; 566 int i; 567 568/* 569 * Allocate the private structure area. 570 */ 571 if (alloc_private(dev, sizeof(struct cb_pcidas_private)) < 0) 572 return -ENOMEM; 573 574/* 575 * Probe the device to determine what device in the series it is. 576 */ 577 578 for_each_pci_dev(pcidev) { 579 /* is it not a computer boards card? */ 580 if (pcidev->vendor != PCI_VENDOR_ID_CB) 581 continue; 582 /* loop through cards supported by this driver */ 583 for (index = 0; index < ARRAY_SIZE(cb_pcidas_boards); index++) { 584 if (cb_pcidas_boards[index].device_id != pcidev->device) 585 continue; 586 /* was a particular bus/slot requested? */ 587 if (it->options[0] || it->options[1]) { 588 /* are we on the wrong bus/slot? */ 589 if (pcidev->bus->number != it->options[0] || 590 PCI_SLOT(pcidev->devfn) != it->options[1]) { 591 continue; 592 } 593 } 594 devpriv->pci_dev = pcidev; 595 dev->board_ptr = cb_pcidas_boards + index; 596 goto found; 597 } 598 } 599 600 dev_err(dev->hw_dev, "No supported ComputerBoards/MeasurementComputing card found on requested position\n"); 601 return -EIO; 602 603found: 604 605 dev_dbg(dev->hw_dev, "Found %s on bus %i, slot %i\n", 606 cb_pcidas_boards[index].name, pcidev->bus->number, 607 PCI_SLOT(pcidev->devfn)); 608 609 /* 610 * Enable PCI device and reserve I/O ports. 611 */ 612 if (comedi_pci_enable(pcidev, "cb_pcidas")) { 613 dev_err(dev->hw_dev, "Failed to enable PCI device and request regions\n"); 614 return -EIO; 615 } 616 /* 617 * Initialize devpriv->control_status and devpriv->adc_fifo to point to 618 * their base address. 619 */ 620 devpriv->s5933_config = 621 pci_resource_start(devpriv->pci_dev, S5933_BADRINDEX); 622 devpriv->control_status = 623 pci_resource_start(devpriv->pci_dev, CONT_STAT_BADRINDEX); 624 devpriv->adc_fifo = 625 pci_resource_start(devpriv->pci_dev, ADC_FIFO_BADRINDEX); 626 devpriv->pacer_counter_dio = 627 pci_resource_start(devpriv->pci_dev, PACER_BADRINDEX); 628 if (thisboard->ao_nchan) { 629 devpriv->ao_registers = 630 pci_resource_start(devpriv->pci_dev, AO_BADRINDEX); 631 } 632 /* disable and clear interrupts on amcc s5933 */ 633 outl(INTCSR_INBOX_INTR_STATUS, 634 devpriv->s5933_config + AMCC_OP_REG_INTCSR); 635 636 /* get irq */ 637 if (request_irq(devpriv->pci_dev->irq, cb_pcidas_interrupt, 638 IRQF_SHARED, "cb_pcidas", dev)) { 639 dev_dbg(dev->hw_dev, "unable to allocate irq %d\n", 640 devpriv->pci_dev->irq); 641 return -EINVAL; 642 } 643 dev->irq = devpriv->pci_dev->irq; 644 645 /* Initialize dev->board_name */ 646 dev->board_name = thisboard->name; 647 648/* 649 * Allocate the subdevice structures. 650 */ 651 if (alloc_subdevices(dev, 7) < 0) 652 return -ENOMEM; 653 654 s = dev->subdevices + 0; 655 /* analog input subdevice */ 656 dev->read_subdev = s; 657 s->type = COMEDI_SUBD_AI; 658 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF | SDF_CMD_READ; 659 /* WARNING: Number of inputs in differential mode is ignored */ 660 s->n_chan = thisboard->ai_se_chans; 661 s->len_chanlist = thisboard->ai_se_chans; 662 s->maxdata = (1 << thisboard->ai_bits) - 1; 663 s->range_table = thisboard->ranges; 664 s->insn_read = cb_pcidas_ai_rinsn; 665 s->insn_config = ai_config_insn; 666 s->do_cmd = cb_pcidas_ai_cmd; 667 s->do_cmdtest = cb_pcidas_ai_cmdtest; 668 s->cancel = cb_pcidas_cancel; 669 670 /* analog output subdevice */ 671 s = dev->subdevices + 1; 672 if (thisboard->ao_nchan) { 673 s->type = COMEDI_SUBD_AO; 674 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; 675 s->n_chan = thisboard->ao_nchan; 676 /* analog out resolution is the same as analog input resolution, so use ai_bits */ 677 s->maxdata = (1 << thisboard->ai_bits) - 1; 678 s->range_table = &cb_pcidas_ao_ranges; 679 s->insn_read = cb_pcidas_ao_readback_insn; 680 if (thisboard->has_ao_fifo) { 681 dev->write_subdev = s; 682 s->subdev_flags |= SDF_CMD_WRITE; 683 s->insn_write = cb_pcidas_ao_fifo_winsn; 684 s->do_cmdtest = cb_pcidas_ao_cmdtest; 685 s->do_cmd = cb_pcidas_ao_cmd; 686 s->cancel = cb_pcidas_ao_cancel; 687 } else { 688 s->insn_write = cb_pcidas_ao_nofifo_winsn; 689 } 690 } else { 691 s->type = COMEDI_SUBD_UNUSED; 692 } 693 694 /* 8255 */ 695 s = dev->subdevices + 2; 696 subdev_8255_init(dev, s, NULL, devpriv->pacer_counter_dio + DIO_8255); 697 698 /* serial EEPROM, */ 699 s = dev->subdevices + 3; 700 s->type = COMEDI_SUBD_MEMORY; 701 s->subdev_flags = SDF_READABLE | SDF_INTERNAL; 702 s->n_chan = 256; 703 s->maxdata = 0xff; 704 s->insn_read = eeprom_read_insn; 705 706 /* 8800 caldac */ 707 s = dev->subdevices + 4; 708 s->type = COMEDI_SUBD_CALIB; 709 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 710 s->n_chan = NUM_CHANNELS_8800; 711 s->maxdata = 0xff; 712 s->insn_read = caldac_read_insn; 713 s->insn_write = caldac_write_insn; 714 for (i = 0; i < s->n_chan; i++) 715 caldac_8800_write(dev, i, s->maxdata / 2); 716 717 /* trim potentiometer */ 718 s = dev->subdevices + 5; 719 s->type = COMEDI_SUBD_CALIB; 720 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 721 if (thisboard->trimpot == AD7376) { 722 s->n_chan = NUM_CHANNELS_7376; 723 s->maxdata = 0x7f; 724 } else { 725 s->n_chan = NUM_CHANNELS_8402; 726 s->maxdata = 0xff; 727 } 728 s->insn_read = trimpot_read_insn; 729 s->insn_write = trimpot_write_insn; 730 for (i = 0; i < s->n_chan; i++) 731 cb_pcidas_trimpot_write(dev, i, s->maxdata / 2); 732 733 /* dac08 caldac */ 734 s = dev->subdevices + 6; 735 if (thisboard->has_dac08) { 736 s->type = COMEDI_SUBD_CALIB; 737 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 738 s->n_chan = NUM_CHANNELS_DAC08; 739 s->insn_read = dac08_read_insn; 740 s->insn_write = dac08_write_insn; 741 s->maxdata = 0xff; 742 dac08_write(dev, s->maxdata / 2); 743 } else 744 s->type = COMEDI_SUBD_UNUSED; 745 746 /* make sure mailbox 4 is empty */ 747 inl(devpriv->s5933_config + AMCC_OP_REG_IMB4); 748 /* Set bits to enable incoming mailbox interrupts on amcc s5933. */ 749 devpriv->s5933_intcsr_bits = 750 INTCSR_INBOX_BYTE(3) | INTCSR_INBOX_SELECT(3) | 751 INTCSR_INBOX_FULL_INT; 752 /* clear and enable interrupt on amcc s5933 */ 753 outl(devpriv->s5933_intcsr_bits | INTCSR_INBOX_INTR_STATUS, 754 devpriv->s5933_config + AMCC_OP_REG_INTCSR); 755 756 return 1; 757} 758 759/* 760 * cb_pcidas_detach is called to deconfigure a device. It should deallocate 761 * resources. 762 * This function is also called when _attach() fails, so it should be 763 * careful not to release resources that were not necessarily 764 * allocated by _attach(). dev->private and dev->subdevices are 765 * deallocated automatically by the core. 766 */ 767static int cb_pcidas_detach(struct comedi_device *dev) 768{ 769 770 if (devpriv) { 771 if (devpriv->s5933_config) { 772 /* disable and clear interrupts on amcc s5933 */ 773 outl(INTCSR_INBOX_INTR_STATUS, 774 devpriv->s5933_config + AMCC_OP_REG_INTCSR); 775#ifdef CB_PCIDAS_DEBUG 776 printk("detaching, incsr is 0x%x\n", 777 inl(devpriv->s5933_config + AMCC_OP_REG_INTCSR)); 778#endif 779 } 780 } 781 if (dev->irq) 782 free_irq(dev->irq, dev); 783 if (dev->subdevices) 784 subdev_8255_cleanup(dev, dev->subdevices + 2); 785 if (devpriv && devpriv->pci_dev) { 786 if (devpriv->s5933_config) 787 comedi_pci_disable(devpriv->pci_dev); 788 pci_dev_put(devpriv->pci_dev); 789 } 790 791 return 0; 792} 793 794/* 795 * "instructions" read/write data in "one-shot" or "software-triggered" 796 * mode. 797 */ 798static int cb_pcidas_ai_rinsn(struct comedi_device *dev, 799 struct comedi_subdevice *s, 800 struct comedi_insn *insn, unsigned int *data) 801{ 802 int n, i; 803 unsigned int bits; 804 static const int timeout = 10000; 805 int channel; 806 /* enable calibration input if appropriate */ 807 if (insn->chanspec & CR_ALT_SOURCE) { 808 outw(cal_enable_bits(dev), 809 devpriv->control_status + CALIBRATION_REG); 810 channel = 0; 811 } else { 812 outw(0, devpriv->control_status + CALIBRATION_REG); 813 channel = CR_CHAN(insn->chanspec); 814 } 815 /* set mux limits and gain */ 816 bits = BEGIN_SCAN(channel) | 817 END_SCAN(channel) | GAIN_BITS(CR_RANGE(insn->chanspec)); 818 /* set unipolar/bipolar */ 819 if (CR_RANGE(insn->chanspec) & IS_UNIPOLAR) 820 bits |= UNIP; 821 /* set singleended/differential */ 822 if (CR_AREF(insn->chanspec) != AREF_DIFF) 823 bits |= SE; 824 outw(bits, devpriv->control_status + ADCMUX_CONT); 825 826 /* clear fifo */ 827 outw(0, devpriv->adc_fifo + ADCFIFOCLR); 828 829 /* convert n samples */ 830 for (n = 0; n < insn->n; n++) { 831 /* trigger conversion */ 832 outw(0, devpriv->adc_fifo + ADCDATA); 833 834 /* wait for conversion to end */ 835 /* return -ETIMEDOUT if there is a timeout */ 836 for (i = 0; i < timeout; i++) { 837 if (inw(devpriv->control_status + ADCMUX_CONT) & EOC) 838 break; 839 } 840 if (i == timeout) 841 return -ETIMEDOUT; 842 843 /* read data */ 844 data[n] = inw(devpriv->adc_fifo + ADCDATA); 845 } 846 847 /* return the number of samples read/written */ 848 return n; 849} 850 851static int ai_config_calibration_source(struct comedi_device *dev, 852 unsigned int *data) 853{ 854 static const int num_calibration_sources = 8; 855 unsigned int source = data[1]; 856 857 if (source >= num_calibration_sources) { 858 printk("invalid calibration source: %i\n", source); 859 return -EINVAL; 860 } 861 862 devpriv->calibration_source = source; 863 864 return 2; 865} 866 867static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s, 868 struct comedi_insn *insn, unsigned int *data) 869{ 870 int id = data[0]; 871 872 switch (id) { 873 case INSN_CONFIG_ALT_SOURCE: 874 return ai_config_calibration_source(dev, data); 875 break; 876 default: 877 return -EINVAL; 878 break; 879 } 880 return -EINVAL; 881} 882 883/* analog output insn for pcidas-1000 and 1200 series */ 884static int cb_pcidas_ao_nofifo_winsn(struct comedi_device *dev, 885 struct comedi_subdevice *s, 886 struct comedi_insn *insn, 887 unsigned int *data) 888{ 889 int channel; 890 unsigned long flags; 891 892 /* set channel and range */ 893 channel = CR_CHAN(insn->chanspec); 894 spin_lock_irqsave(&dev->spinlock, flags); 895 devpriv->ao_control_bits &= 896 ~DAC_MODE_UPDATE_BOTH & ~DAC_RANGE_MASK(channel); 897 devpriv->ao_control_bits |= 898 DACEN | DAC_RANGE(channel, CR_RANGE(insn->chanspec)); 899 outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR); 900 spin_unlock_irqrestore(&dev->spinlock, flags); 901 902 /* remember value for readback */ 903 devpriv->ao_value[channel] = data[0]; 904 /* send data */ 905 outw(data[0], devpriv->ao_registers + DAC_DATA_REG(channel)); 906 907 return 1; 908} 909 910/* analog output insn for pcidas-1602 series */ 911static int cb_pcidas_ao_fifo_winsn(struct comedi_device *dev, 912 struct comedi_subdevice *s, 913 struct comedi_insn *insn, unsigned int *data) 914{ 915 int channel; 916 unsigned long flags; 917 918 /* clear dac fifo */ 919 outw(0, devpriv->ao_registers + DACFIFOCLR); 920 921 /* set channel and range */ 922 channel = CR_CHAN(insn->chanspec); 923 spin_lock_irqsave(&dev->spinlock, flags); 924 devpriv->ao_control_bits &= 925 ~DAC_CHAN_EN(0) & ~DAC_CHAN_EN(1) & ~DAC_RANGE_MASK(channel) & 926 ~DAC_PACER_MASK; 927 devpriv->ao_control_bits |= 928 DACEN | DAC_RANGE(channel, 929 CR_RANGE(insn-> 930 chanspec)) | DAC_CHAN_EN(channel) | 931 DAC_START; 932 outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR); 933 spin_unlock_irqrestore(&dev->spinlock, flags); 934 935 /* remember value for readback */ 936 devpriv->ao_value[channel] = data[0]; 937 /* send data */ 938 outw(data[0], devpriv->ao_registers + DACDATA); 939 940 return 1; 941} 942 943/* analog output readback insn */ 944/* XXX loses track of analog output value back after an analog ouput command is executed */ 945static int cb_pcidas_ao_readback_insn(struct comedi_device *dev, 946 struct comedi_subdevice *s, 947 struct comedi_insn *insn, 948 unsigned int *data) 949{ 950 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; 951 952 return 1; 953} 954 955static int eeprom_read_insn(struct comedi_device *dev, 956 struct comedi_subdevice *s, 957 struct comedi_insn *insn, unsigned int *data) 958{ 959 uint8_t nvram_data; 960 int retval; 961 962 retval = nvram_read(dev, CR_CHAN(insn->chanspec), &nvram_data); 963 if (retval < 0) 964 return retval; 965 966 data[0] = nvram_data; 967 968 return 1; 969} 970 971static int caldac_write_insn(struct comedi_device *dev, 972 struct comedi_subdevice *s, 973 struct comedi_insn *insn, unsigned int *data) 974{ 975 const unsigned int channel = CR_CHAN(insn->chanspec); 976 977 return caldac_8800_write(dev, channel, data[0]); 978} 979 980static int caldac_read_insn(struct comedi_device *dev, 981 struct comedi_subdevice *s, 982 struct comedi_insn *insn, unsigned int *data) 983{ 984 data[0] = devpriv->caldac_value[CR_CHAN(insn->chanspec)]; 985 986 return 1; 987} 988 989/* 1602/16 pregain offset */ 990static int dac08_write(struct comedi_device *dev, unsigned int value) 991{ 992 if (devpriv->dac08_value == value) 993 return 1; 994 995 devpriv->dac08_value = value; 996 997 outw(cal_enable_bits(dev) | (value & 0xff), 998 devpriv->control_status + CALIBRATION_REG); 999 udelay(1); 1000 outw(cal_enable_bits(dev) | SELECT_DAC08_BIT | (value & 0xff), 1001 devpriv->control_status + CALIBRATION_REG); 1002 udelay(1); 1003 outw(cal_enable_bits(dev) | (value & 0xff), 1004 devpriv->control_status + CALIBRATION_REG); 1005 udelay(1); 1006 1007 return 1; 1008} 1009 1010static int dac08_write_insn(struct comedi_device *dev, 1011 struct comedi_subdevice *s, 1012 struct comedi_insn *insn, unsigned int *data) 1013{ 1014 return dac08_write(dev, data[0]); 1015} 1016 1017static int dac08_read_insn(struct comedi_device *dev, 1018 struct comedi_subdevice *s, struct comedi_insn *insn, 1019 unsigned int *data) 1020{ 1021 data[0] = devpriv->dac08_value; 1022 1023 return 1; 1024} 1025 1026static int cb_pcidas_trimpot_write(struct comedi_device *dev, 1027 unsigned int channel, unsigned int value) 1028{ 1029 if (devpriv->trimpot_value[channel] == value) 1030 return 1; 1031 1032 devpriv->trimpot_value[channel] = value; 1033 switch (thisboard->trimpot) { 1034 case AD7376: 1035 trimpot_7376_write(dev, value); 1036 break; 1037 case AD8402: 1038 trimpot_8402_write(dev, channel, value); 1039 break; 1040 default: 1041 comedi_error(dev, "driver bug?"); 1042 return -1; 1043 break; 1044 } 1045 1046 return 1; 1047} 1048 1049static int trimpot_write_insn(struct comedi_device *dev, 1050 struct comedi_subdevice *s, 1051 struct comedi_insn *insn, unsigned int *data) 1052{ 1053 unsigned int channel = CR_CHAN(insn->chanspec); 1054 1055 return cb_pcidas_trimpot_write(dev, channel, data[0]); 1056} 1057 1058static int trimpot_read_insn(struct comedi_device *dev, 1059 struct comedi_subdevice *s, 1060 struct comedi_insn *insn, unsigned int *data) 1061{ 1062 unsigned int channel = CR_CHAN(insn->chanspec); 1063 1064 data[0] = devpriv->trimpot_value[channel]; 1065 1066 return 1; 1067} 1068 1069static int cb_pcidas_ai_cmdtest(struct comedi_device *dev, 1070 struct comedi_subdevice *s, 1071 struct comedi_cmd *cmd) 1072{ 1073 int err = 0; 1074 int tmp; 1075 int i, gain, start_chan; 1076 1077 /* cmdtest tests a particular command to see if it is valid. 1078 * Using the cmdtest ioctl, a user can create a valid cmd 1079 * and then have it executes by the cmd ioctl. 1080 * 1081 * cmdtest returns 1,2,3,4 or 0, depending on which tests 1082 * the command passes. */ 1083 1084 /* step 1: make sure trigger sources are trivially valid */ 1085 1086 tmp = cmd->start_src; 1087 cmd->start_src &= TRIG_NOW | TRIG_EXT; 1088 if (!cmd->start_src || tmp != cmd->start_src) 1089 err++; 1090 1091 tmp = cmd->scan_begin_src; 1092 cmd->scan_begin_src &= TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT; 1093 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 1094 err++; 1095 1096 tmp = cmd->convert_src; 1097 cmd->convert_src &= TRIG_TIMER | TRIG_NOW | TRIG_EXT; 1098 if (!cmd->convert_src || tmp != cmd->convert_src) 1099 err++; 1100 1101 tmp = cmd->scan_end_src; 1102 cmd->scan_end_src &= TRIG_COUNT; 1103 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 1104 err++; 1105 1106 tmp = cmd->stop_src; 1107 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 1108 if (!cmd->stop_src || tmp != cmd->stop_src) 1109 err++; 1110 1111 if (err) 1112 return 1; 1113 1114 /* step 2: make sure trigger sources are unique and mutually compatible */ 1115 1116 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) 1117 err++; 1118 if (cmd->scan_begin_src != TRIG_FOLLOW && 1119 cmd->scan_begin_src != TRIG_TIMER && 1120 cmd->scan_begin_src != TRIG_EXT) 1121 err++; 1122 if (cmd->convert_src != TRIG_TIMER && 1123 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW) 1124 err++; 1125 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 1126 err++; 1127 1128 /* make sure trigger sources are compatible with each other */ 1129 if (cmd->scan_begin_src == TRIG_FOLLOW && cmd->convert_src == TRIG_NOW) 1130 err++; 1131 if (cmd->scan_begin_src != TRIG_FOLLOW && cmd->convert_src != TRIG_NOW) 1132 err++; 1133 if (cmd->start_src == TRIG_EXT && 1134 (cmd->convert_src == TRIG_EXT || cmd->scan_begin_src == TRIG_EXT)) 1135 err++; 1136 1137 if (err) 1138 return 2; 1139 1140 /* step 3: make sure arguments are trivially compatible */ 1141 1142 switch (cmd->start_src) { 1143 case TRIG_EXT: 1144 /* External trigger, only CR_EDGE and CR_INVERT flags allowed */ 1145 if ((cmd->start_arg 1146 & (CR_FLAGS_MASK & ~(CR_EDGE | CR_INVERT))) != 0) { 1147 cmd->start_arg &= 1148 ~(CR_FLAGS_MASK & ~(CR_EDGE | CR_INVERT)); 1149 err++; 1150 } 1151 if (!thisboard->has_ai_trig_invert && 1152 (cmd->start_arg & CR_INVERT)) { 1153 cmd->start_arg &= (CR_FLAGS_MASK & ~CR_INVERT); 1154 err++; 1155 } 1156 break; 1157 default: 1158 if (cmd->start_arg != 0) { 1159 cmd->start_arg = 0; 1160 err++; 1161 } 1162 break; 1163 } 1164 1165 if (cmd->scan_begin_src == TRIG_TIMER) { 1166 if (cmd->scan_begin_arg < 1167 thisboard->ai_speed * cmd->chanlist_len) { 1168 cmd->scan_begin_arg = 1169 thisboard->ai_speed * cmd->chanlist_len; 1170 err++; 1171 } 1172 } 1173 if (cmd->convert_src == TRIG_TIMER) { 1174 if (cmd->convert_arg < thisboard->ai_speed) { 1175 cmd->convert_arg = thisboard->ai_speed; 1176 err++; 1177 } 1178 } 1179 1180 if (cmd->scan_end_arg != cmd->chanlist_len) { 1181 cmd->scan_end_arg = cmd->chanlist_len; 1182 err++; 1183 } 1184 if (cmd->stop_src == TRIG_NONE) { 1185 /* TRIG_NONE */ 1186 if (cmd->stop_arg != 0) { 1187 cmd->stop_arg = 0; 1188 err++; 1189 } 1190 } 1191 1192 if (err) 1193 return 3; 1194 1195 /* step 4: fix up any arguments */ 1196 1197 if (cmd->scan_begin_src == TRIG_TIMER) { 1198 tmp = cmd->scan_begin_arg; 1199 i8253_cascade_ns_to_timer_2div(TIMER_BASE, 1200 &(devpriv->divisor1), 1201 &(devpriv->divisor2), 1202 &(cmd->scan_begin_arg), 1203 cmd->flags & TRIG_ROUND_MASK); 1204 if (tmp != cmd->scan_begin_arg) 1205 err++; 1206 } 1207 if (cmd->convert_src == TRIG_TIMER) { 1208 tmp = cmd->convert_arg; 1209 i8253_cascade_ns_to_timer_2div(TIMER_BASE, 1210 &(devpriv->divisor1), 1211 &(devpriv->divisor2), 1212 &(cmd->convert_arg), 1213 cmd->flags & TRIG_ROUND_MASK); 1214 if (tmp != cmd->convert_arg) 1215 err++; 1216 } 1217 1218 if (err) 1219 return 4; 1220 1221 /* check channel/gain list against card's limitations */ 1222 if (cmd->chanlist) { 1223 gain = CR_RANGE(cmd->chanlist[0]); 1224 start_chan = CR_CHAN(cmd->chanlist[0]); 1225 for (i = 1; i < cmd->chanlist_len; i++) { 1226 if (CR_CHAN(cmd->chanlist[i]) != 1227 (start_chan + i) % s->n_chan) { 1228 comedi_error(dev, 1229 "entries in chanlist must be consecutive channels, counting upwards\n"); 1230 err++; 1231 } 1232 if (CR_RANGE(cmd->chanlist[i]) != gain) { 1233 comedi_error(dev, 1234 "entries in chanlist must all have the same gain\n"); 1235 err++; 1236 } 1237 } 1238 } 1239 1240 if (err) 1241 return 5; 1242 1243 return 0; 1244} 1245 1246static int cb_pcidas_ai_cmd(struct comedi_device *dev, 1247 struct comedi_subdevice *s) 1248{ 1249 struct comedi_async *async = s->async; 1250 struct comedi_cmd *cmd = &async->cmd; 1251 unsigned int bits; 1252 unsigned long flags; 1253 1254 /* make sure CAL_EN_BIT is disabled */ 1255 outw(0, devpriv->control_status + CALIBRATION_REG); 1256 /* initialize before settings pacer source and count values */ 1257 outw(0, devpriv->control_status + TRIG_CONTSTAT); 1258 /* clear fifo */ 1259 outw(0, devpriv->adc_fifo + ADCFIFOCLR); 1260 1261 /* set mux limits, gain and pacer source */ 1262 bits = BEGIN_SCAN(CR_CHAN(cmd->chanlist[0])) | 1263 END_SCAN(CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])) | 1264 GAIN_BITS(CR_RANGE(cmd->chanlist[0])); 1265 /* set unipolar/bipolar */ 1266 if (CR_RANGE(cmd->chanlist[0]) & IS_UNIPOLAR) 1267 bits |= UNIP; 1268 /* set singleended/differential */ 1269 if (CR_AREF(cmd->chanlist[0]) != AREF_DIFF) 1270 bits |= SE; 1271 /* set pacer source */ 1272 if (cmd->convert_src == TRIG_EXT || cmd->scan_begin_src == TRIG_EXT) 1273 bits |= PACER_EXT_RISE; 1274 else 1275 bits |= PACER_INT; 1276 outw(bits, devpriv->control_status + ADCMUX_CONT); 1277 1278#ifdef CB_PCIDAS_DEBUG 1279 printk("comedi: sent 0x%x to adcmux control\n", bits); 1280#endif 1281 1282 /* load counters */ 1283 if (cmd->convert_src == TRIG_TIMER) 1284 cb_pcidas_load_counters(dev, &cmd->convert_arg, 1285 cmd->flags & TRIG_ROUND_MASK); 1286 else if (cmd->scan_begin_src == TRIG_TIMER) 1287 cb_pcidas_load_counters(dev, &cmd->scan_begin_arg, 1288 cmd->flags & TRIG_ROUND_MASK); 1289 1290 /* set number of conversions */ 1291 if (cmd->stop_src == TRIG_COUNT) 1292 devpriv->count = cmd->chanlist_len * cmd->stop_arg; 1293 /* enable interrupts */ 1294 spin_lock_irqsave(&dev->spinlock, flags); 1295 devpriv->adc_fifo_bits |= INTE; 1296 devpriv->adc_fifo_bits &= ~INT_MASK; 1297 if (cmd->flags & TRIG_WAKE_EOS) { 1298 if (cmd->convert_src == TRIG_NOW && cmd->chanlist_len > 1) 1299 devpriv->adc_fifo_bits |= INT_EOS; /* interrupt end of burst */ 1300 else 1301 devpriv->adc_fifo_bits |= INT_FNE; /* interrupt fifo not empty */ 1302 } else { 1303 devpriv->adc_fifo_bits |= INT_FHF; /* interrupt fifo half full */ 1304 } 1305#ifdef CB_PCIDAS_DEBUG 1306 printk("comedi: adc_fifo_bits are 0x%x\n", devpriv->adc_fifo_bits); 1307#endif 1308 /* enable (and clear) interrupts */ 1309 outw(devpriv->adc_fifo_bits | EOAI | INT | LADFUL, 1310 devpriv->control_status + INT_ADCFIFO); 1311 spin_unlock_irqrestore(&dev->spinlock, flags); 1312 1313 /* set start trigger and burst mode */ 1314 bits = 0; 1315 if (cmd->start_src == TRIG_NOW) 1316 bits |= SW_TRIGGER; 1317 else if (cmd->start_src == TRIG_EXT) { 1318 bits |= EXT_TRIGGER | TGEN | XTRCL; 1319 if (thisboard->has_ai_trig_invert 1320 && (cmd->start_arg & CR_INVERT)) 1321 bits |= TGPOL; 1322 if (thisboard->has_ai_trig_gated && (cmd->start_arg & CR_EDGE)) 1323 bits |= TGSEL; 1324 } else { 1325 comedi_error(dev, "bug!"); 1326 return -1; 1327 } 1328 if (cmd->convert_src == TRIG_NOW && cmd->chanlist_len > 1) 1329 bits |= BURSTE; 1330 outw(bits, devpriv->control_status + TRIG_CONTSTAT); 1331#ifdef CB_PCIDAS_DEBUG 1332 printk("comedi: sent 0x%x to trig control\n", bits); 1333#endif 1334 1335 return 0; 1336} 1337 1338static int cb_pcidas_ao_cmdtest(struct comedi_device *dev, 1339 struct comedi_subdevice *s, 1340 struct comedi_cmd *cmd) 1341{ 1342 int err = 0; 1343 int tmp; 1344 1345 /* cmdtest tests a particular command to see if it is valid. 1346 * Using the cmdtest ioctl, a user can create a valid cmd 1347 * and then have it executes by the cmd ioctl. 1348 * 1349 * cmdtest returns 1,2,3,4 or 0, depending on which tests 1350 * the command passes. */ 1351 1352 /* step 1: make sure trigger sources are trivially valid */ 1353 1354 tmp = cmd->start_src; 1355 cmd->start_src &= TRIG_INT; 1356 if (!cmd->start_src || tmp != cmd->start_src) 1357 err++; 1358 1359 tmp = cmd->scan_begin_src; 1360 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; 1361 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 1362 err++; 1363 1364 tmp = cmd->convert_src; 1365 cmd->convert_src &= TRIG_NOW; 1366 if (!cmd->convert_src || tmp != cmd->convert_src) 1367 err++; 1368 1369 tmp = cmd->scan_end_src; 1370 cmd->scan_end_src &= TRIG_COUNT; 1371 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 1372 err++; 1373 1374 tmp = cmd->stop_src; 1375 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 1376 if (!cmd->stop_src || tmp != cmd->stop_src) 1377 err++; 1378 1379 if (err) 1380 return 1; 1381 1382 /* step 2: make sure trigger sources are unique and mutually compatible */ 1383 1384 if (cmd->scan_begin_src != TRIG_TIMER && 1385 cmd->scan_begin_src != TRIG_EXT) 1386 err++; 1387 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 1388 err++; 1389 1390 if (err) 1391 return 2; 1392 1393 /* step 3: make sure arguments are trivially compatible */ 1394 1395 if (cmd->start_arg != 0) { 1396 cmd->start_arg = 0; 1397 err++; 1398 } 1399 1400 if (cmd->scan_begin_src == TRIG_TIMER) { 1401 if (cmd->scan_begin_arg < thisboard->ao_scan_speed) { 1402 cmd->scan_begin_arg = thisboard->ao_scan_speed; 1403 err++; 1404 } 1405 } 1406 1407 if (cmd->scan_end_arg != cmd->chanlist_len) { 1408 cmd->scan_end_arg = cmd->chanlist_len; 1409 err++; 1410 } 1411 if (cmd->stop_src == TRIG_NONE) { 1412 /* TRIG_NONE */ 1413 if (cmd->stop_arg != 0) { 1414 cmd->stop_arg = 0; 1415 err++; 1416 } 1417 } 1418 1419 if (err) 1420 return 3; 1421 1422 /* step 4: fix up any arguments */ 1423 1424 if (cmd->scan_begin_src == TRIG_TIMER) { 1425 tmp = cmd->scan_begin_arg; 1426 i8253_cascade_ns_to_timer_2div(TIMER_BASE, 1427 &(devpriv->ao_divisor1), 1428 &(devpriv->ao_divisor2), 1429 &(cmd->scan_begin_arg), 1430 cmd->flags & TRIG_ROUND_MASK); 1431 if (tmp != cmd->scan_begin_arg) 1432 err++; 1433 } 1434 1435 if (err) 1436 return 4; 1437 1438 /* check channel/gain list against card's limitations */ 1439 if (cmd->chanlist && cmd->chanlist_len > 1) { 1440 if (CR_CHAN(cmd->chanlist[0]) != 0 || 1441 CR_CHAN(cmd->chanlist[1]) != 1) { 1442 comedi_error(dev, 1443 "channels must be ordered channel 0, channel 1 in chanlist\n"); 1444 err++; 1445 } 1446 } 1447 1448 if (err) 1449 return 5; 1450 1451 return 0; 1452} 1453 1454static int cb_pcidas_ao_cmd(struct comedi_device *dev, 1455 struct comedi_subdevice *s) 1456{ 1457 struct comedi_async *async = s->async; 1458 struct comedi_cmd *cmd = &async->cmd; 1459 unsigned int i; 1460 unsigned long flags; 1461 1462 /* set channel limits, gain */ 1463 spin_lock_irqsave(&dev->spinlock, flags); 1464 for (i = 0; i < cmd->chanlist_len; i++) { 1465 /* enable channel */ 1466 devpriv->ao_control_bits |= 1467 DAC_CHAN_EN(CR_CHAN(cmd->chanlist[i])); 1468 /* set range */ 1469 devpriv->ao_control_bits |= DAC_RANGE(CR_CHAN(cmd->chanlist[i]), 1470 CR_RANGE(cmd-> 1471 chanlist[i])); 1472 } 1473 1474 /* disable analog out before settings pacer source and count values */ 1475 outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR); 1476 spin_unlock_irqrestore(&dev->spinlock, flags); 1477 1478 /* clear fifo */ 1479 outw(0, devpriv->ao_registers + DACFIFOCLR); 1480 1481 /* load counters */ 1482 if (cmd->scan_begin_src == TRIG_TIMER) { 1483 i8253_cascade_ns_to_timer_2div(TIMER_BASE, 1484 &(devpriv->ao_divisor1), 1485 &(devpriv->ao_divisor2), 1486 &(cmd->scan_begin_arg), 1487 cmd->flags); 1488 1489 /* Write the values of ctr1 and ctr2 into counters 1 and 2 */ 1490 i8254_load(devpriv->pacer_counter_dio + DAC8254, 0, 1, 1491 devpriv->ao_divisor1, 2); 1492 i8254_load(devpriv->pacer_counter_dio + DAC8254, 0, 2, 1493 devpriv->ao_divisor2, 2); 1494 } 1495 /* set number of conversions */ 1496 if (cmd->stop_src == TRIG_COUNT) 1497 devpriv->ao_count = cmd->chanlist_len * cmd->stop_arg; 1498 /* set pacer source */ 1499 spin_lock_irqsave(&dev->spinlock, flags); 1500 switch (cmd->scan_begin_src) { 1501 case TRIG_TIMER: 1502 devpriv->ao_control_bits |= DAC_PACER_INT; 1503 break; 1504 case TRIG_EXT: 1505 devpriv->ao_control_bits |= DAC_PACER_EXT_RISE; 1506 break; 1507 default: 1508 spin_unlock_irqrestore(&dev->spinlock, flags); 1509 comedi_error(dev, "error setting dac pacer source"); 1510 return -1; 1511 break; 1512 } 1513 spin_unlock_irqrestore(&dev->spinlock, flags); 1514 1515 async->inttrig = cb_pcidas_ao_inttrig; 1516 1517 return 0; 1518} 1519 1520static int cb_pcidas_ao_inttrig(struct comedi_device *dev, 1521 struct comedi_subdevice *s, 1522 unsigned int trig_num) 1523{ 1524 unsigned int num_bytes, num_points = thisboard->fifo_size; 1525 struct comedi_async *async = s->async; 1526 struct comedi_cmd *cmd = &s->async->cmd; 1527 unsigned long flags; 1528 1529 if (trig_num != 0) 1530 return -EINVAL; 1531 1532 /* load up fifo */ 1533 if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count < num_points) 1534 num_points = devpriv->ao_count; 1535 1536 num_bytes = cfc_read_array_from_buffer(s, devpriv->ao_buffer, 1537 num_points * sizeof(short)); 1538 num_points = num_bytes / sizeof(short); 1539 1540 if (cmd->stop_src == TRIG_COUNT) 1541 devpriv->ao_count -= num_points; 1542 /* write data to board's fifo */ 1543 outsw(devpriv->ao_registers + DACDATA, devpriv->ao_buffer, num_bytes); 1544 1545 /* enable dac half-full and empty interrupts */ 1546 spin_lock_irqsave(&dev->spinlock, flags); 1547 devpriv->adc_fifo_bits |= DAEMIE | DAHFIE; 1548#ifdef CB_PCIDAS_DEBUG 1549 printk("comedi: adc_fifo_bits are 0x%x\n", devpriv->adc_fifo_bits); 1550#endif 1551 /* enable and clear interrupts */ 1552 outw(devpriv->adc_fifo_bits | DAEMI | DAHFI, 1553 devpriv->control_status + INT_ADCFIFO); 1554 1555 /* start dac */ 1556 devpriv->ao_control_bits |= DAC_START | DACEN | DAC_EMPTY; 1557 outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR); 1558#ifdef CB_PCIDAS_DEBUG 1559 printk("comedi: sent 0x%x to dac control\n", devpriv->ao_control_bits); 1560#endif 1561 spin_unlock_irqrestore(&dev->spinlock, flags); 1562 1563 async->inttrig = NULL; 1564 1565 return 0; 1566} 1567 1568static irqreturn_t cb_pcidas_interrupt(int irq, void *d) 1569{ 1570 struct comedi_device *dev = (struct comedi_device *)d; 1571 struct comedi_subdevice *s = dev->read_subdev; 1572 struct comedi_async *async; 1573 int status, s5933_status; 1574 int half_fifo = thisboard->fifo_size / 2; 1575 unsigned int num_samples, i; 1576 static const int timeout = 10000; 1577 unsigned long flags; 1578 1579 if (dev->attached == 0) 1580 return IRQ_NONE; 1581 1582 async = s->async; 1583 async->events = 0; 1584 1585 s5933_status = inl(devpriv->s5933_config + AMCC_OP_REG_INTCSR); 1586#ifdef CB_PCIDAS_DEBUG 1587 printk("intcsr 0x%x\n", s5933_status); 1588 printk("mbef 0x%x\n", inl(devpriv->s5933_config + AMCC_OP_REG_MBEF)); 1589#endif 1590 1591 if ((INTCSR_INTR_ASSERTED & s5933_status) == 0) 1592 return IRQ_NONE; 1593 1594 /* make sure mailbox 4 is empty */ 1595 inl_p(devpriv->s5933_config + AMCC_OP_REG_IMB4); 1596 /* clear interrupt on amcc s5933 */ 1597 outl(devpriv->s5933_intcsr_bits | INTCSR_INBOX_INTR_STATUS, 1598 devpriv->s5933_config + AMCC_OP_REG_INTCSR); 1599 1600 status = inw(devpriv->control_status + INT_ADCFIFO); 1601#ifdef CB_PCIDAS_DEBUG 1602 if ((status & (INT | EOAI | LADFUL | DAHFI | DAEMI)) == 0) 1603 comedi_error(dev, "spurious interrupt"); 1604#endif 1605 1606 /* check for analog output interrupt */ 1607 if (status & (DAHFI | DAEMI)) 1608 handle_ao_interrupt(dev, status); 1609 /* check for analog input interrupts */ 1610 /* if fifo half-full */ 1611 if (status & ADHFI) { 1612 /* read data */ 1613 num_samples = half_fifo; 1614 if (async->cmd.stop_src == TRIG_COUNT && 1615 num_samples > devpriv->count) { 1616 num_samples = devpriv->count; 1617 } 1618 insw(devpriv->adc_fifo + ADCDATA, devpriv->ai_buffer, 1619 num_samples); 1620 cfc_write_array_to_buffer(s, devpriv->ai_buffer, 1621 num_samples * sizeof(short)); 1622 devpriv->count -= num_samples; 1623 if (async->cmd.stop_src == TRIG_COUNT && devpriv->count == 0) { 1624 async->events |= COMEDI_CB_EOA; 1625 cb_pcidas_cancel(dev, s); 1626 } 1627 /* clear half-full interrupt latch */ 1628 spin_lock_irqsave(&dev->spinlock, flags); 1629 outw(devpriv->adc_fifo_bits | INT, 1630 devpriv->control_status + INT_ADCFIFO); 1631 spin_unlock_irqrestore(&dev->spinlock, flags); 1632 /* else if fifo not empty */ 1633 } else if (status & (ADNEI | EOBI)) { 1634 for (i = 0; i < timeout; i++) { 1635 /* break if fifo is empty */ 1636 if ((ADNE & inw(devpriv->control_status + 1637 INT_ADCFIFO)) == 0) 1638 break; 1639 cfc_write_to_buffer(s, inw(devpriv->adc_fifo)); 1640 if (async->cmd.stop_src == TRIG_COUNT && --devpriv->count == 0) { /* end of acquisition */ 1641 cb_pcidas_cancel(dev, s); 1642 async->events |= COMEDI_CB_EOA; 1643 break; 1644 } 1645 } 1646 /* clear not-empty interrupt latch */ 1647 spin_lock_irqsave(&dev->spinlock, flags); 1648 outw(devpriv->adc_fifo_bits | INT, 1649 devpriv->control_status + INT_ADCFIFO); 1650 spin_unlock_irqrestore(&dev->spinlock, flags); 1651 } else if (status & EOAI) { 1652 comedi_error(dev, 1653 "bug! encountered end of acquisition interrupt?"); 1654 /* clear EOA interrupt latch */ 1655 spin_lock_irqsave(&dev->spinlock, flags); 1656 outw(devpriv->adc_fifo_bits | EOAI, 1657 devpriv->control_status + INT_ADCFIFO); 1658 spin_unlock_irqrestore(&dev->spinlock, flags); 1659 } 1660 /* check for fifo overflow */ 1661 if (status & LADFUL) { 1662 comedi_error(dev, "fifo overflow"); 1663 /* clear overflow interrupt latch */ 1664 spin_lock_irqsave(&dev->spinlock, flags); 1665 outw(devpriv->adc_fifo_bits | LADFUL, 1666 devpriv->control_status + INT_ADCFIFO); 1667 spin_unlock_irqrestore(&dev->spinlock, flags); 1668 cb_pcidas_cancel(dev, s); 1669 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 1670 } 1671 1672 comedi_event(dev, s); 1673 1674 return IRQ_HANDLED; 1675} 1676 1677static void handle_ao_interrupt(struct comedi_device *dev, unsigned int status) 1678{ 1679 struct comedi_subdevice *s = dev->write_subdev; 1680 struct comedi_async *async = s->async; 1681 struct comedi_cmd *cmd = &async->cmd; 1682 unsigned int half_fifo = thisboard->fifo_size / 2; 1683 unsigned int num_points; 1684 unsigned long flags; 1685 1686 async->events = 0; 1687 1688 if (status & DAEMI) { 1689 /* clear dac empty interrupt latch */ 1690 spin_lock_irqsave(&dev->spinlock, flags); 1691 outw(devpriv->adc_fifo_bits | DAEMI, 1692 devpriv->control_status + INT_ADCFIFO); 1693 spin_unlock_irqrestore(&dev->spinlock, flags); 1694 if (inw(devpriv->ao_registers + DAC_CSR) & DAC_EMPTY) { 1695 if (cmd->stop_src == TRIG_NONE || 1696 (cmd->stop_src == TRIG_COUNT 1697 && devpriv->ao_count)) { 1698 comedi_error(dev, "dac fifo underflow"); 1699 cb_pcidas_ao_cancel(dev, s); 1700 async->events |= COMEDI_CB_ERROR; 1701 } 1702 async->events |= COMEDI_CB_EOA; 1703 } 1704 } else if (status & DAHFI) { 1705 unsigned int num_bytes; 1706 1707 /* figure out how many points we are writing to fifo */ 1708 num_points = half_fifo; 1709 if (cmd->stop_src == TRIG_COUNT && 1710 devpriv->ao_count < num_points) 1711 num_points = devpriv->ao_count; 1712 num_bytes = 1713 cfc_read_array_from_buffer(s, devpriv->ao_buffer, 1714 num_points * sizeof(short)); 1715 num_points = num_bytes / sizeof(short); 1716 1717 if (async->cmd.stop_src == TRIG_COUNT) 1718 devpriv->ao_count -= num_points; 1719 /* write data to board's fifo */ 1720 outsw(devpriv->ao_registers + DACDATA, devpriv->ao_buffer, 1721 num_points); 1722 /* clear half-full interrupt latch */ 1723 spin_lock_irqsave(&dev->spinlock, flags); 1724 outw(devpriv->adc_fifo_bits | DAHFI, 1725 devpriv->control_status + INT_ADCFIFO); 1726 spin_unlock_irqrestore(&dev->spinlock, flags); 1727 } 1728 1729 comedi_event(dev, s); 1730} 1731 1732/* cancel analog input command */ 1733static int cb_pcidas_cancel(struct comedi_device *dev, 1734 struct comedi_subdevice *s) 1735{ 1736 unsigned long flags; 1737 1738 spin_lock_irqsave(&dev->spinlock, flags); 1739 /* disable interrupts */ 1740 devpriv->adc_fifo_bits &= ~INTE & ~EOAIE; 1741 outw(devpriv->adc_fifo_bits, devpriv->control_status + INT_ADCFIFO); 1742 spin_unlock_irqrestore(&dev->spinlock, flags); 1743 1744 /* disable start trigger source and burst mode */ 1745 outw(0, devpriv->control_status + TRIG_CONTSTAT); 1746 /* software pacer source */ 1747 outw(0, devpriv->control_status + ADCMUX_CONT); 1748 1749 return 0; 1750} 1751 1752/* cancel analog output command */ 1753static int cb_pcidas_ao_cancel(struct comedi_device *dev, 1754 struct comedi_subdevice *s) 1755{ 1756 unsigned long flags; 1757 1758 spin_lock_irqsave(&dev->spinlock, flags); 1759 /* disable interrupts */ 1760 devpriv->adc_fifo_bits &= ~DAHFIE & ~DAEMIE; 1761 outw(devpriv->adc_fifo_bits, devpriv->control_status + INT_ADCFIFO); 1762 1763 /* disable output */ 1764 devpriv->ao_control_bits &= ~DACEN & ~DAC_PACER_MASK; 1765 outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR); 1766 spin_unlock_irqrestore(&dev->spinlock, flags); 1767 1768 return 0; 1769} 1770 1771static void cb_pcidas_load_counters(struct comedi_device *dev, unsigned int *ns, 1772 int rounding_flags) 1773{ 1774 i8253_cascade_ns_to_timer_2div(TIMER_BASE, &(devpriv->divisor1), 1775 &(devpriv->divisor2), ns, 1776 rounding_flags & TRIG_ROUND_MASK); 1777 1778 /* Write the values of ctr1 and ctr2 into counters 1 and 2 */ 1779 i8254_load(devpriv->pacer_counter_dio + ADC8254, 0, 1, 1780 devpriv->divisor1, 2); 1781 i8254_load(devpriv->pacer_counter_dio + ADC8254, 0, 2, 1782 devpriv->divisor2, 2); 1783} 1784 1785static void write_calibration_bitstream(struct comedi_device *dev, 1786 unsigned int register_bits, 1787 unsigned int bitstream, 1788 unsigned int bitstream_length) 1789{ 1790 static const int write_delay = 1; 1791 unsigned int bit; 1792 1793 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { 1794 if (bitstream & bit) 1795 register_bits |= SERIAL_DATA_IN_BIT; 1796 else 1797 register_bits &= ~SERIAL_DATA_IN_BIT; 1798 udelay(write_delay); 1799 outw(register_bits, devpriv->control_status + CALIBRATION_REG); 1800 } 1801} 1802 1803static int caldac_8800_write(struct comedi_device *dev, unsigned int address, 1804 uint8_t value) 1805{ 1806 static const int num_caldac_channels = 8; 1807 static const int bitstream_length = 11; 1808 unsigned int bitstream = ((address & 0x7) << 8) | value; 1809 static const int caldac_8800_udelay = 1; 1810 1811 if (address >= num_caldac_channels) { 1812 comedi_error(dev, "illegal caldac channel"); 1813 return -1; 1814 } 1815 1816 if (value == devpriv->caldac_value[address]) 1817 return 1; 1818 1819 devpriv->caldac_value[address] = value; 1820 1821 write_calibration_bitstream(dev, cal_enable_bits(dev), bitstream, 1822 bitstream_length); 1823 1824 udelay(caldac_8800_udelay); 1825 outw(cal_enable_bits(dev) | SELECT_8800_BIT, 1826 devpriv->control_status + CALIBRATION_REG); 1827 udelay(caldac_8800_udelay); 1828 outw(cal_enable_bits(dev), devpriv->control_status + CALIBRATION_REG); 1829 1830 return 1; 1831} 1832 1833static int trimpot_7376_write(struct comedi_device *dev, uint8_t value) 1834{ 1835 static const int bitstream_length = 7; 1836 unsigned int bitstream = value & 0x7f; 1837 unsigned int register_bits; 1838 static const int ad7376_udelay = 1; 1839 1840 register_bits = cal_enable_bits(dev) | SELECT_TRIMPOT_BIT; 1841 udelay(ad7376_udelay); 1842 outw(register_bits, devpriv->control_status + CALIBRATION_REG); 1843 1844 write_calibration_bitstream(dev, register_bits, bitstream, 1845 bitstream_length); 1846 1847 udelay(ad7376_udelay); 1848 outw(cal_enable_bits(dev), devpriv->control_status + CALIBRATION_REG); 1849 1850 return 0; 1851} 1852 1853/* For 1602/16 only 1854 * ch 0 : adc gain 1855 * ch 1 : adc postgain offset */ 1856static int trimpot_8402_write(struct comedi_device *dev, unsigned int channel, 1857 uint8_t value) 1858{ 1859 static const int bitstream_length = 10; 1860 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff); 1861 unsigned int register_bits; 1862 static const int ad8402_udelay = 1; 1863 1864 register_bits = cal_enable_bits(dev) | SELECT_TRIMPOT_BIT; 1865 udelay(ad8402_udelay); 1866 outw(register_bits, devpriv->control_status + CALIBRATION_REG); 1867 1868 write_calibration_bitstream(dev, register_bits, bitstream, 1869 bitstream_length); 1870 1871 udelay(ad8402_udelay); 1872 outw(cal_enable_bits(dev), devpriv->control_status + CALIBRATION_REG); 1873 1874 return 0; 1875} 1876 1877static int wait_for_nvram_ready(unsigned long s5933_base_addr) 1878{ 1879 static const int timeout = 1000; 1880 unsigned int i; 1881 1882 for (i = 0; i < timeout; i++) { 1883 if ((inb(s5933_base_addr + 1884 AMCC_OP_REG_MCSR_NVCMD) & MCSR_NV_BUSY) 1885 == 0) 1886 return 0; 1887 udelay(1); 1888 } 1889 return -1; 1890} 1891 1892static int nvram_read(struct comedi_device *dev, unsigned int address, 1893 uint8_t *data) 1894{ 1895 unsigned long iobase = devpriv->s5933_config; 1896 1897 if (wait_for_nvram_ready(iobase) < 0) 1898 return -ETIMEDOUT; 1899 1900 outb(MCSR_NV_ENABLE | MCSR_NV_LOAD_LOW_ADDR, 1901 iobase + AMCC_OP_REG_MCSR_NVCMD); 1902 outb(address & 0xff, iobase + AMCC_OP_REG_MCSR_NVDATA); 1903 outb(MCSR_NV_ENABLE | MCSR_NV_LOAD_HIGH_ADDR, 1904 iobase + AMCC_OP_REG_MCSR_NVCMD); 1905 outb((address >> 8) & 0xff, iobase + AMCC_OP_REG_MCSR_NVDATA); 1906 outb(MCSR_NV_ENABLE | MCSR_NV_READ, iobase + AMCC_OP_REG_MCSR_NVCMD); 1907 1908 if (wait_for_nvram_ready(iobase) < 0) 1909 return -ETIMEDOUT; 1910 1911 *data = inb(iobase + AMCC_OP_REG_MCSR_NVDATA); 1912 1913 return 0; 1914} 1915 1916/* 1917 * A convenient macro that defines init_module() and cleanup_module(), 1918 * as necessary. 1919 */ 1920static int __devinit driver_cb_pcidas_pci_probe(struct pci_dev *dev, 1921 const struct pci_device_id *ent) 1922{ 1923 return comedi_pci_auto_config(dev, driver_cb_pcidas.driver_name); 1924} 1925 1926static void __devexit driver_cb_pcidas_pci_remove(struct pci_dev *dev) 1927{ 1928 comedi_pci_auto_unconfig(dev); 1929} 1930 1931static struct pci_driver driver_cb_pcidas_pci_driver = { 1932 .id_table = cb_pcidas_pci_table, 1933 .probe = &driver_cb_pcidas_pci_probe, 1934 .remove = __devexit_p(&driver_cb_pcidas_pci_remove) 1935}; 1936 1937static int __init driver_cb_pcidas_init_module(void) 1938{ 1939 int retval; 1940 1941 retval = comedi_driver_register(&driver_cb_pcidas); 1942 if (retval < 0) 1943 return retval; 1944 1945 driver_cb_pcidas_pci_driver.name = (char *)driver_cb_pcidas.driver_name; 1946 return pci_register_driver(&driver_cb_pcidas_pci_driver); 1947} 1948 1949static void __exit driver_cb_pcidas_cleanup_module(void) 1950{ 1951 pci_unregister_driver(&driver_cb_pcidas_pci_driver); 1952 comedi_driver_unregister(&driver_cb_pcidas); 1953} 1954 1955module_init(driver_cb_pcidas_init_module); 1956module_exit(driver_cb_pcidas_cleanup_module); 1957 1958MODULE_AUTHOR("Comedi http://www.comedi.org"); 1959MODULE_DESCRIPTION("Comedi low-level driver"); 1960MODULE_LICENSE("GPL"); 1961