cb_pcidas64.c revision 558587e2d96a4f5439a609509e4ea88f7536203b
1/* 2 comedi/drivers/cb_pcidas64.c 3 This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS 4 64xx, 60xx, and 4020 cards. 5 6 Author: Frank Mori Hess <fmhess@users.sourceforge.net> 7 Copyright (C) 2001, 2002 Frank Mori Hess 8 9 Thanks also go to the following people: 10 11 Steve Rosenbluth, for providing the source code for 12 his pci-das6402 driver, and source code for working QNX pci-6402 13 drivers by Greg Laird and Mariusz Bogacz. None of the code was 14 used directly here, but it was useful as an additional source of 15 documentation on how to program the boards. 16 17 John Sims, for much testing and feedback on pcidas-4020 support. 18 19 COMEDI - Linux Control and Measurement Device Interface 20 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> 21 22 This program is free software; you can redistribute it and/or modify 23 it under the terms of the GNU General Public License as published by 24 the Free Software Foundation; either version 2 of the License, or 25 (at your option) any later version. 26 27 This program is distributed in the hope that it will be useful, 28 but WITHOUT ANY WARRANTY; without even the implied warranty of 29 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 GNU General Public License for more details. 31 32 You should have received a copy of the GNU General Public License 33 along with this program; if not, write to the Free Software 34 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 35 36************************************************************************/ 37 38/* 39 40Driver: cb_pcidas64 41Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series with the PLX 9080 PCI controller 42Author: Frank Mori Hess <fmhess@users.sourceforge.net> 43Status: works 44Updated: 2002-10-09 45Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64), 46 PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16, 47 PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR, 48 PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14, 49 PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014, 50 PCI-DAS6023, PCI-DAS6025, PCI-DAS6030, 51 PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034, 52 PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052, 53 PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12 54 55Configuration options: 56 [0] - PCI bus of device (optional) 57 [1] - PCI slot of device (optional) 58 59These boards may be autocalibrated with the comedi_calibrate utility. 60 61To select the bnc trigger input on the 4020 (instead of the dio input), 62specify a nonzero channel in the chanspec. If you wish to use an external 63master clock on the 4020, you may do so by setting the scan_begin_src 64to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn 65to configure the divisor to use for the external clock. 66 67Some devices are not identified because the PCI device IDs are not yet 68known. If you have such a board, please file a bug report at 69https://bugs.comedi.org. 70 71*/ 72 73/* 74 75TODO: 76 make it return error if user attempts an ai command that uses the 77 external queue, and an ao command simultaneously 78 user counter subdevice 79 there are a number of boards this driver will support when they are 80 fully released, but does not yet since the pci device id numbers 81 are not yet available. 82 support prescaled 100khz clock for slow pacing (not available on 6000 series?) 83 make ao fifo size adjustable like ai fifo 84*/ 85 86#include "../comedidev.h" 87#include <linux/delay.h> 88#include <linux/interrupt.h> 89#include <asm/system.h> 90 91#include "comedi_pci.h" 92#include "8253.h" 93#include "8255.h" 94#include "plx9080.h" 95#include "comedi_fc.h" 96 97#undef PCIDAS64_DEBUG /* disable debugging code */ 98/* #define PCIDAS64_DEBUG enable debugging code */ 99 100#ifdef PCIDAS64_DEBUG 101#define DEBUG_PRINT(format, args...) printk(format , ## args) 102#else 103#define DEBUG_PRINT(format, args...) 104#endif 105 106#define TIMER_BASE 25 /* 40MHz master clock */ 107#define PRESCALED_TIMER_BASE 10000 /* 100kHz 'prescaled' clock for slow aquisition, maybe I'll support this someday */ 108#define DMA_BUFFER_SIZE 0x1000 109 110#define PCI_VENDOR_ID_COMPUTERBOARDS 0x1307 111 112/* maximum value that can be loaded into board's 24-bit counters*/ 113static const int max_counter_value = 0xffffff; 114 115/* PCI-DAS64xxx base addresses */ 116 117/* indices of base address regions */ 118enum base_address_regions { 119 PLX9080_BADDRINDEX = 0, 120 MAIN_BADDRINDEX = 2, 121 DIO_COUNTER_BADDRINDEX = 3, 122}; 123 124/* priv(dev)->main_iobase registers */ 125enum write_only_registers { 126 INTR_ENABLE_REG = 0x0, /* interrupt enable register */ 127 HW_CONFIG_REG = 0x2, /* hardware config register */ 128 DAQ_SYNC_REG = 0xc, 129 DAQ_ATRIG_LOW_4020_REG = 0xc, 130 ADC_CONTROL0_REG = 0x10, /* adc control register 0 */ 131 ADC_CONTROL1_REG = 0x12, /* adc control register 1 */ 132 CALIBRATION_REG = 0x14, 133 ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16, /* lower 16 bits of adc sample interval counter */ 134 ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18, /* upper 8 bits of adc sample interval counter */ 135 ADC_DELAY_INTERVAL_LOWER_REG = 0x1a, /* lower 16 bits of delay interval counter */ 136 ADC_DELAY_INTERVAL_UPPER_REG = 0x1c, /* upper 8 bits of delay interval counter */ 137 ADC_COUNT_LOWER_REG = 0x1e, /* lower 16 bits of hardware conversion/scan counter */ 138 ADC_COUNT_UPPER_REG = 0x20, /* upper 8 bits of hardware conversion/scan counter */ 139 ADC_START_REG = 0x22, /* software trigger to start aquisition */ 140 ADC_CONVERT_REG = 0x24, /* initiates single conversion */ 141 ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */ 142 ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */ 143 ADC_BUFFER_CLEAR_REG = 0x2a, 144 ADC_QUEUE_HIGH_REG = 0x2c, /* high channel for internal queue, use adc_chan_bits() inline above */ 145 DAC_CONTROL0_REG = 0x50, /* dac control register 0 */ 146 DAC_CONTROL1_REG = 0x52, /* dac control register 0 */ 147 DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54, /* lower 16 bits of dac sample interval counter */ 148 DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56, /* upper 8 bits of dac sample interval counter */ 149 DAC_SELECT_REG = 0x60, 150 DAC_START_REG = 0x64, 151 DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */ 152}; 153static inline unsigned int dac_convert_reg(unsigned int channel) 154{ 155 return 0x70 + (2 * (channel & 0x1)); 156} 157 158static inline unsigned int dac_lsb_4020_reg(unsigned int channel) 159{ 160 return 0x70 + (4 * (channel & 0x1)); 161} 162 163static inline unsigned int dac_msb_4020_reg(unsigned int channel) 164{ 165 return 0x72 + (4 * (channel & 0x1)); 166} 167 168enum read_only_registers { 169 HW_STATUS_REG = 0x0, /* hardware status register, reading this apparently clears pending interrupts as well */ 170 PIPE1_READ_REG = 0x4, 171 ADC_READ_PNTR_REG = 0x8, 172 LOWER_XFER_REG = 0x10, 173 ADC_WRITE_PNTR_REG = 0xc, 174 PREPOST_REG = 0x14, 175}; 176 177enum read_write_registers { 178 I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */ 179 ADC_QUEUE_FIFO_REG = 0x100, /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */ 180 ADC_FIFO_REG = 0x200, /* adc data fifo */ 181 DAC_FIFO_REG = 0x300, /* dac data fifo, has weird interactions with external channel queue */ 182}; 183 184/* priv(dev)->dio_counter_iobase registers */ 185enum dio_counter_registers { 186 DIO_8255_OFFSET = 0x0, 187 DO_REG = 0x20, 188 DI_REG = 0x28, 189 DIO_DIRECTION_60XX_REG = 0x40, 190 DIO_DATA_60XX_REG = 0x48, 191}; 192 193/* bit definitions for write-only registers */ 194 195enum intr_enable_contents { 196 ADC_INTR_SRC_MASK = 0x3, /* bits that set adc interrupt source */ 197 ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quater full */ 198 ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */ 199 ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */ 200 ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence (probably wont use this it's pretty fancy) */ 201 EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */ 202 EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc aquisition done interrupt */ 203 DAC_INTR_SRC_MASK = 0x30, 204 DAC_INTR_QEMPTY_BITS = 0x0, 205 DAC_INTR_HIGH_CHAN_BITS = 0x10, 206 EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */ 207 EN_DAC_DONE_INTR_BIT = 0x80, 208 EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */ 209 EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */ 210 EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */ 211 EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */ 212 EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */ 213}; 214 215enum hw_config_contents { 216 MASTER_CLOCK_4020_MASK = 0x3, /* bits that specify master clock source for 4020 */ 217 INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock for 4020 */ 218 BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */ 219 EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */ 220 EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue (more versatile than internal queue) */ 221 SLOW_DAC_BIT = 0x400, /* use 225 nanosec strobe when loading dac instead of 50 nanosec */ 222 HW_CONFIG_DUMMY_BITS = 0x2000, /* bit with unknown function yet given as default value in pci-das64 manual */ 223 DMA_CH_SELECT_BIT = 0x8000, /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */ 224 FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */ 225 DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */ 226 DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */ 227}; 228#define DAC_FIFO_SIZE 0x2000 229 230enum daq_atrig_low_4020_contents { 231 EXT_AGATE_BNC_BIT = 0x8000, /* use trig/ext clk bnc input for analog gate signal */ 232 EXT_STOP_TRIG_BNC_BIT = 0x4000, /* use trig/ext clk bnc input for external stop trigger signal */ 233 EXT_START_TRIG_BNC_BIT = 0x2000, /* use trig/ext clk bnc input for external start trigger signal */ 234}; 235static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold) 236{ 237 return threshold & 0xfff; 238} 239 240enum adc_control0_contents { 241 ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */ 242 ADC_SOFT_GATE_BITS = 0x1, /* software gate */ 243 ADC_EXT_GATE_BITS = 0x2, /* external digital gate */ 244 ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */ 245 ADC_GATE_LEVEL_BIT = 0x4, /* level-sensitive gate (for digital) */ 246 ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */ 247 ADC_START_TRIG_SOFT_BITS = 0x10, 248 ADC_START_TRIG_EXT_BITS = 0x20, 249 ADC_START_TRIG_ANALOG_BITS = 0x30, 250 ADC_START_TRIG_MASK = 0x30, 251 ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */ 252 ADC_EXT_CONV_FALLING_BIT = 0x800, /* external pacing uses falling edge */ 253 ADC_SAMPLE_COUNTER_EN_BIT = 0x1000, /* enable hardware scan counter */ 254 ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */ 255 ADC_ENABLE_BIT = 0x8000, /* master adc enable */ 256}; 257 258enum adc_control1_contents { 259 ADC_QUEUE_CONFIG_BIT = 0x1, /* should be set for boards with > 16 channels */ 260 CONVERT_POLARITY_BIT = 0x10, 261 EOC_POLARITY_BIT = 0x20, 262 ADC_SW_GATE_BIT = 0x40, /* software gate of adc */ 263 ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */ 264 RETRIGGER_BIT = 0x800, 265 ADC_LO_CHANNEL_4020_MASK = 0x300, 266 ADC_HI_CHANNEL_4020_MASK = 0xc00, 267 TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */ 268 FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */ 269 CHANNEL_MODE_4020_MASK = 0x3000, 270 ADC_MODE_MASK = 0xf000, 271}; 272static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel) 273{ 274 return (channel & 0x3) << 8; 275}; 276 277static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel) 278{ 279 return (channel & 0x3) << 10; 280}; 281 282static inline uint16_t adc_mode_bits(unsigned int mode) 283{ 284 return (mode & 0xf) << 12; 285}; 286 287enum calibration_contents { 288 SELECT_8800_BIT = 0x1, 289 SELECT_8402_64XX_BIT = 0x2, 290 SELECT_1590_60XX_BIT = 0x2, 291 CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */ 292 SERIAL_DATA_IN_BIT = 0x80, 293 SERIAL_CLOCK_BIT = 0x100, 294 CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */ 295 CAL_GAIN_BIT = 0x800, 296}; 297/* calibration sources for 6025 are: 298 * 0 : ground 299 * 1 : 10V 300 * 2 : 5V 301 * 3 : 0.5V 302 * 4 : 0.05V 303 * 5 : ground 304 * 6 : dac channel 0 305 * 7 : dac channel 1 306 */ 307static inline uint16_t adc_src_bits(unsigned int source) 308{ 309 return (source & 0xf) << 3; 310}; 311 312static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel) 313{ 314 return (channel & 0x3) << 8; 315}; 316 317enum adc_queue_load_contents { 318 UNIP_BIT = 0x800, /* unipolar/bipolar bit */ 319 ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */ 320 ADC_COMMON_BIT = 0x2000, /* non-referenced single-ended (common-mode input) */ 321 QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */ 322 QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */ 323}; 324static inline uint16_t adc_chan_bits(unsigned int channel) 325{ 326 return channel & 0x3f; 327}; 328 329enum dac_control0_contents { 330 DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */ 331 DAC_CYCLIC_STOP_BIT = 0x4000, 332 DAC_WAVEFORM_MODE_BIT = 0x100, 333 DAC_EXT_UPDATE_FALLING_BIT = 0x80, 334 DAC_EXT_UPDATE_ENABLE_BIT = 0x40, 335 WAVEFORM_TRIG_MASK = 0x30, 336 WAVEFORM_TRIG_DISABLED_BITS = 0x0, 337 WAVEFORM_TRIG_SOFT_BITS = 0x10, 338 WAVEFORM_TRIG_EXT_BITS = 0x20, 339 WAVEFORM_TRIG_ADC1_BITS = 0x30, 340 WAVEFORM_TRIG_FALLING_BIT = 0x8, 341 WAVEFORM_GATE_LEVEL_BIT = 0x4, 342 WAVEFORM_GATE_ENABLE_BIT = 0x2, 343 WAVEFORM_GATE_SELECT_BIT = 0x1, 344}; 345 346enum dac_control1_contents { 347 DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */ 348 DAC1_EXT_REF_BIT = 0x200, 349 DAC0_EXT_REF_BIT = 0x100, 350 DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */ 351 DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */ 352 DAC_SW_GATE_BIT = 0x20, 353 DAC1_UNIPOLAR_BIT = 0x8, 354 DAC0_UNIPOLAR_BIT = 0x2, 355}; 356 357/* bit definitions for read-only registers */ 358enum hw_status_contents { 359 DAC_UNDERRUN_BIT = 0x1, 360 ADC_OVERRUN_BIT = 0x2, 361 DAC_ACTIVE_BIT = 0x4, 362 ADC_ACTIVE_BIT = 0x8, 363 DAC_INTR_PENDING_BIT = 0x10, 364 ADC_INTR_PENDING_BIT = 0x20, 365 DAC_DONE_BIT = 0x40, 366 ADC_DONE_BIT = 0x80, 367 EXT_INTR_PENDING_BIT = 0x100, 368 ADC_STOP_BIT = 0x200, 369}; 370static inline uint16_t pipe_full_bits(uint16_t hw_status_bits) 371{ 372 return (hw_status_bits >> 10) & 0x3; 373}; 374 375static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits) 376{ 377 return (prepost_bits >> 6) & 0x3; 378} 379 380static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits) 381{ 382 return (prepost_bits >> 12) & 0x3; 383} 384 385static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits) 386{ 387 return (prepost_bits >> 14) & 0x3; 388} 389 390/* I2C addresses for 4020 */ 391enum i2c_addresses { 392 RANGE_CAL_I2C_ADDR = 0x20, 393 CALDAC0_I2C_ADDR = 0xc, 394 CALDAC1_I2C_ADDR = 0xd, 395}; 396 397enum range_cal_i2c_contents { 398 ADC_SRC_4020_MASK = 0x70, /* bits that set what source the adc converter measures */ 399 BNC_TRIG_THRESHOLD_0V_BIT = 0x80, /* make bnc trig/ext clock threshold 0V instead of 2.5V */ 400}; 401static inline uint8_t adc_src_4020_bits(unsigned int source) 402{ 403 return (source << 4) & ADC_SRC_4020_MASK; 404}; 405 406static inline uint8_t attenuate_bit(unsigned int channel) 407{ 408 /* attenuate channel (+-5V input range) */ 409 return 1 << (channel & 0x3); 410}; 411 412/* analog input ranges for 64xx boards */ 413static const struct comedi_lrange ai_ranges_64xx = { 414 8, 415 { 416 BIP_RANGE(10), 417 BIP_RANGE(5), 418 BIP_RANGE(2.5), 419 BIP_RANGE(1.25), 420 UNI_RANGE(10), 421 UNI_RANGE(5), 422 UNI_RANGE(2.5), 423 UNI_RANGE(1.25) 424 } 425}; 426 427/* analog input ranges for 60xx boards */ 428static const struct comedi_lrange ai_ranges_60xx = { 429 4, 430 { 431 BIP_RANGE(10), 432 BIP_RANGE(5), 433 BIP_RANGE(0.5), 434 BIP_RANGE(0.05), 435 } 436}; 437 438/* analog input ranges for 6030, etc boards */ 439static const struct comedi_lrange ai_ranges_6030 = { 440 14, 441 { 442 BIP_RANGE(10), 443 BIP_RANGE(5), 444 BIP_RANGE(2), 445 BIP_RANGE(1), 446 BIP_RANGE(0.5), 447 BIP_RANGE(0.2), 448 BIP_RANGE(0.1), 449 UNI_RANGE(10), 450 UNI_RANGE(5), 451 UNI_RANGE(2), 452 UNI_RANGE(1), 453 UNI_RANGE(0.5), 454 UNI_RANGE(0.2), 455 UNI_RANGE(0.1), 456 } 457}; 458 459/* analog input ranges for 6052, etc boards */ 460static const struct comedi_lrange ai_ranges_6052 = { 461 15, 462 { 463 BIP_RANGE(10), 464 BIP_RANGE(5), 465 BIP_RANGE(2.5), 466 BIP_RANGE(1), 467 BIP_RANGE(0.5), 468 BIP_RANGE(0.25), 469 BIP_RANGE(0.1), 470 BIP_RANGE(0.05), 471 UNI_RANGE(10), 472 UNI_RANGE(5), 473 UNI_RANGE(2), 474 UNI_RANGE(1), 475 UNI_RANGE(0.5), 476 UNI_RANGE(0.2), 477 UNI_RANGE(0.1), 478 } 479}; 480 481/* analog input ranges for 4020 board */ 482static const struct comedi_lrange ai_ranges_4020 = { 483 2, 484 { 485 BIP_RANGE(5), 486 BIP_RANGE(1), 487 } 488}; 489 490/* analog output ranges */ 491static const struct comedi_lrange ao_ranges_64xx = { 492 4, 493 { 494 BIP_RANGE(5), 495 BIP_RANGE(10), 496 UNI_RANGE(5), 497 UNI_RANGE(10), 498 } 499}; 500 501static const int ao_range_code_64xx[] = { 502 0x0, 503 0x1, 504 0x2, 505 0x3, 506}; 507 508static const struct comedi_lrange ao_ranges_60xx = { 509 1, 510 { 511 BIP_RANGE(10), 512 } 513}; 514 515static const int ao_range_code_60xx[] = { 516 0x0, 517}; 518 519static const struct comedi_lrange ao_ranges_6030 = { 520 2, 521 { 522 BIP_RANGE(10), 523 UNI_RANGE(10), 524 } 525}; 526 527static const int ao_range_code_6030[] = { 528 0x0, 529 0x2, 530}; 531 532static const struct comedi_lrange ao_ranges_4020 = { 533 2, 534 { 535 BIP_RANGE(5), 536 BIP_RANGE(10), 537 } 538}; 539 540static const int ao_range_code_4020[] = { 541 0x1, 542 0x0, 543}; 544 545enum register_layout { 546 LAYOUT_60XX, 547 LAYOUT_64XX, 548 LAYOUT_4020, 549}; 550 551struct hw_fifo_info { 552 unsigned int num_segments; 553 unsigned int max_segment_length; 554 unsigned int sample_packing_ratio; 555 uint16_t fifo_size_reg_mask; 556}; 557 558struct pcidas64_board { 559 const char *name; 560 int device_id; /* pci device id */ 561 int ai_se_chans; /* number of ai inputs in single-ended mode */ 562 int ai_bits; /* analog input resolution */ 563 int ai_speed; /* fastest conversion period in ns */ 564 const struct comedi_lrange *ai_range_table; 565 int ao_nchan; /* number of analog out channels */ 566 int ao_bits; /* analog output resolution */ 567 int ao_scan_speed; /* analog output speed (for a scan, not conversion) */ 568 const struct comedi_lrange *ao_range_table; 569 const int *ao_range_code; 570 const struct hw_fifo_info *const ai_fifo; 571 enum register_layout layout; /* different board families have slightly different registers */ 572 unsigned has_8255:1; 573}; 574 575static const struct hw_fifo_info ai_fifo_4020 = { 576 .num_segments = 2, 577 .max_segment_length = 0x8000, 578 .sample_packing_ratio = 2, 579 .fifo_size_reg_mask = 0x7f, 580}; 581 582static const struct hw_fifo_info ai_fifo_64xx = { 583 .num_segments = 4, 584 .max_segment_length = 0x800, 585 .sample_packing_ratio = 1, 586 .fifo_size_reg_mask = 0x3f, 587}; 588 589static const struct hw_fifo_info ai_fifo_60xx = { 590 .num_segments = 4, 591 .max_segment_length = 0x800, 592 .sample_packing_ratio = 1, 593 .fifo_size_reg_mask = 0x7f, 594}; 595 596/* maximum number of dma transfers we will chain together into a ring 597 * (and the maximum number of dma buffers we maintain) */ 598#define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE) 599#define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE) 600#define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE) 601static inline unsigned int ai_dma_ring_count(struct pcidas64_board *board) 602{ 603 if (board->layout == LAYOUT_4020) 604 return MAX_AI_DMA_RING_COUNT; 605 else 606 return MIN_AI_DMA_RING_COUNT; 607} 608 609static const int bytes_in_sample = 2; 610 611static const struct pcidas64_board pcidas64_boards[] = { 612 { 613 .name = "pci-das6402/16", 614 .device_id = 0x1d, 615 .ai_se_chans = 64, 616 .ai_bits = 16, 617 .ai_speed = 5000, 618 .ao_nchan = 2, 619 .ao_bits = 16, 620 .ao_scan_speed = 10000, 621 .layout = LAYOUT_64XX, 622 .ai_range_table = &ai_ranges_64xx, 623 .ao_range_table = &ao_ranges_64xx, 624 .ao_range_code = ao_range_code_64xx, 625 .ai_fifo = &ai_fifo_64xx, 626 .has_8255 = 1, 627 }, 628 { 629 .name = "pci-das6402/12", /* XXX check */ 630 .device_id = 0x1e, 631 .ai_se_chans = 64, 632 .ai_bits = 12, 633 .ai_speed = 5000, 634 .ao_nchan = 2, 635 .ao_bits = 12, 636 .ao_scan_speed = 10000, 637 .layout = LAYOUT_64XX, 638 .ai_range_table = &ai_ranges_64xx, 639 .ao_range_table = &ao_ranges_64xx, 640 .ao_range_code = ao_range_code_64xx, 641 .ai_fifo = &ai_fifo_64xx, 642 .has_8255 = 1, 643 }, 644 { 645 .name = "pci-das64/m1/16", 646 .device_id = 0x35, 647 .ai_se_chans = 64, 648 .ai_bits = 16, 649 .ai_speed = 1000, 650 .ao_nchan = 2, 651 .ao_bits = 16, 652 .ao_scan_speed = 10000, 653 .layout = LAYOUT_64XX, 654 .ai_range_table = &ai_ranges_64xx, 655 .ao_range_table = &ao_ranges_64xx, 656 .ao_range_code = ao_range_code_64xx, 657 .ai_fifo = &ai_fifo_64xx, 658 .has_8255 = 1, 659 }, 660 { 661 .name = "pci-das64/m2/16", 662 .device_id = 0x36, 663 .ai_se_chans = 64, 664 .ai_bits = 16, 665 .ai_speed = 500, 666 .ao_nchan = 2, 667 .ao_bits = 16, 668 .ao_scan_speed = 10000, 669 .layout = LAYOUT_64XX, 670 .ai_range_table = &ai_ranges_64xx, 671 .ao_range_table = &ao_ranges_64xx, 672 .ao_range_code = ao_range_code_64xx, 673 .ai_fifo = &ai_fifo_64xx, 674 .has_8255 = 1, 675 }, 676 { 677 .name = "pci-das64/m3/16", 678 .device_id = 0x37, 679 .ai_se_chans = 64, 680 .ai_bits = 16, 681 .ai_speed = 333, 682 .ao_nchan = 2, 683 .ao_bits = 16, 684 .ao_scan_speed = 10000, 685 .layout = LAYOUT_64XX, 686 .ai_range_table = &ai_ranges_64xx, 687 .ao_range_table = &ao_ranges_64xx, 688 .ao_range_code = ao_range_code_64xx, 689 .ai_fifo = &ai_fifo_64xx, 690 .has_8255 = 1, 691 }, 692 { 693 .name = "pci-das6013", 694 .device_id = 0x78, 695 .ai_se_chans = 16, 696 .ai_bits = 16, 697 .ai_speed = 5000, 698 .ao_nchan = 0, 699 .ao_bits = 16, 700 .layout = LAYOUT_60XX, 701 .ai_range_table = &ai_ranges_60xx, 702 .ao_range_table = &ao_ranges_60xx, 703 .ao_range_code = ao_range_code_60xx, 704 .ai_fifo = &ai_fifo_60xx, 705 .has_8255 = 0, 706 }, 707 { 708 .name = "pci-das6014", 709 .device_id = 0x79, 710 .ai_se_chans = 16, 711 .ai_bits = 16, 712 .ai_speed = 5000, 713 .ao_nchan = 2, 714 .ao_bits = 16, 715 .ao_scan_speed = 100000, 716 .layout = LAYOUT_60XX, 717 .ai_range_table = &ai_ranges_60xx, 718 .ao_range_table = &ao_ranges_60xx, 719 .ao_range_code = ao_range_code_60xx, 720 .ai_fifo = &ai_fifo_60xx, 721 .has_8255 = 0, 722 }, 723 { 724 .name = "pci-das6023", 725 .device_id = 0x5d, 726 .ai_se_chans = 16, 727 .ai_bits = 12, 728 .ai_speed = 5000, 729 .ao_nchan = 0, 730 .ao_scan_speed = 100000, 731 .layout = LAYOUT_60XX, 732 .ai_range_table = &ai_ranges_60xx, 733 .ao_range_table = &ao_ranges_60xx, 734 .ao_range_code = ao_range_code_60xx, 735 .ai_fifo = &ai_fifo_60xx, 736 .has_8255 = 1, 737 }, 738 { 739 .name = "pci-das6025", 740 .device_id = 0x5e, 741 .ai_se_chans = 16, 742 .ai_bits = 12, 743 .ai_speed = 5000, 744 .ao_nchan = 2, 745 .ao_bits = 12, 746 .ao_scan_speed = 100000, 747 .layout = LAYOUT_60XX, 748 .ai_range_table = &ai_ranges_60xx, 749 .ao_range_table = &ao_ranges_60xx, 750 .ao_range_code = ao_range_code_60xx, 751 .ai_fifo = &ai_fifo_60xx, 752 .has_8255 = 1, 753 }, 754 { 755 .name = "pci-das6030", 756 .device_id = 0x5f, 757 .ai_se_chans = 16, 758 .ai_bits = 16, 759 .ai_speed = 10000, 760 .ao_nchan = 2, 761 .ao_bits = 16, 762 .ao_scan_speed = 10000, 763 .layout = LAYOUT_60XX, 764 .ai_range_table = &ai_ranges_6030, 765 .ao_range_table = &ao_ranges_6030, 766 .ao_range_code = ao_range_code_6030, 767 .ai_fifo = &ai_fifo_60xx, 768 .has_8255 = 0, 769 }, 770 { 771 .name = "pci-das6031", 772 .device_id = 0x60, 773 .ai_se_chans = 64, 774 .ai_bits = 16, 775 .ai_speed = 10000, 776 .ao_nchan = 2, 777 .ao_bits = 16, 778 .ao_scan_speed = 10000, 779 .layout = LAYOUT_60XX, 780 .ai_range_table = &ai_ranges_6030, 781 .ao_range_table = &ao_ranges_6030, 782 .ao_range_code = ao_range_code_6030, 783 .ai_fifo = &ai_fifo_60xx, 784 .has_8255 = 0, 785 }, 786 { 787 .name = "pci-das6032", 788 .device_id = 0x61, 789 .ai_se_chans = 16, 790 .ai_bits = 16, 791 .ai_speed = 10000, 792 .ao_nchan = 0, 793 .layout = LAYOUT_60XX, 794 .ai_range_table = &ai_ranges_6030, 795 .ai_fifo = &ai_fifo_60xx, 796 .has_8255 = 0, 797 }, 798 { 799 .name = "pci-das6033", 800 .device_id = 0x62, 801 .ai_se_chans = 64, 802 .ai_bits = 16, 803 .ai_speed = 10000, 804 .ao_nchan = 0, 805 .layout = LAYOUT_60XX, 806 .ai_range_table = &ai_ranges_6030, 807 .ai_fifo = &ai_fifo_60xx, 808 .has_8255 = 0, 809 }, 810 { 811 .name = "pci-das6034", 812 .device_id = 0x63, 813 .ai_se_chans = 16, 814 .ai_bits = 16, 815 .ai_speed = 5000, 816 .ao_nchan = 0, 817 .ao_scan_speed = 0, 818 .layout = LAYOUT_60XX, 819 .ai_range_table = &ai_ranges_60xx, 820 .ai_fifo = &ai_fifo_60xx, 821 .has_8255 = 0, 822 }, 823 { 824 .name = "pci-das6035", 825 .device_id = 0x64, 826 .ai_se_chans = 16, 827 .ai_bits = 16, 828 .ai_speed = 5000, 829 .ao_nchan = 2, 830 .ao_bits = 12, 831 .ao_scan_speed = 100000, 832 .layout = LAYOUT_60XX, 833 .ai_range_table = &ai_ranges_60xx, 834 .ao_range_table = &ao_ranges_60xx, 835 .ao_range_code = ao_range_code_60xx, 836 .ai_fifo = &ai_fifo_60xx, 837 .has_8255 = 0, 838 }, 839 { 840 .name = "pci-das6036", 841 .device_id = 0x6f, 842 .ai_se_chans = 16, 843 .ai_bits = 16, 844 .ai_speed = 5000, 845 .ao_nchan = 2, 846 .ao_bits = 16, 847 .ao_scan_speed = 100000, 848 .layout = LAYOUT_60XX, 849 .ai_range_table = &ai_ranges_60xx, 850 .ao_range_table = &ao_ranges_60xx, 851 .ao_range_code = ao_range_code_60xx, 852 .ai_fifo = &ai_fifo_60xx, 853 .has_8255 = 0, 854 }, 855 { 856 .name = "pci-das6040", 857 .device_id = 0x65, 858 .ai_se_chans = 16, 859 .ai_bits = 12, 860 .ai_speed = 2000, 861 .ao_nchan = 2, 862 .ao_bits = 12, 863 .ao_scan_speed = 1000, 864 .layout = LAYOUT_60XX, 865 .ai_range_table = &ai_ranges_6052, 866 .ao_range_table = &ao_ranges_6030, 867 .ao_range_code = ao_range_code_6030, 868 .ai_fifo = &ai_fifo_60xx, 869 .has_8255 = 0, 870 }, 871 { 872 .name = "pci-das6052", 873 .device_id = 0x66, 874 .ai_se_chans = 16, 875 .ai_bits = 16, 876 .ai_speed = 3333, 877 .ao_nchan = 2, 878 .ao_bits = 16, 879 .ao_scan_speed = 3333, 880 .layout = LAYOUT_60XX, 881 .ai_range_table = &ai_ranges_6052, 882 .ao_range_table = &ao_ranges_6030, 883 .ao_range_code = ao_range_code_6030, 884 .ai_fifo = &ai_fifo_60xx, 885 .has_8255 = 0, 886 }, 887 { 888 .name = "pci-das6070", 889 .device_id = 0x67, 890 .ai_se_chans = 16, 891 .ai_bits = 12, 892 .ai_speed = 800, 893 .ao_nchan = 2, 894 .ao_bits = 12, 895 .ao_scan_speed = 1000, 896 .layout = LAYOUT_60XX, 897 .ai_range_table = &ai_ranges_6052, 898 .ao_range_table = &ao_ranges_6030, 899 .ao_range_code = ao_range_code_6030, 900 .ai_fifo = &ai_fifo_60xx, 901 .has_8255 = 0, 902 }, 903 { 904 .name = "pci-das6071", 905 .device_id = 0x68, 906 .ai_se_chans = 64, 907 .ai_bits = 12, 908 .ai_speed = 800, 909 .ao_nchan = 2, 910 .ao_bits = 12, 911 .ao_scan_speed = 1000, 912 .layout = LAYOUT_60XX, 913 .ai_range_table = &ai_ranges_6052, 914 .ao_range_table = &ao_ranges_6030, 915 .ao_range_code = ao_range_code_6030, 916 .ai_fifo = &ai_fifo_60xx, 917 .has_8255 = 0, 918 }, 919 { 920 .name = "pci-das4020/12", 921 .device_id = 0x52, 922 .ai_se_chans = 4, 923 .ai_bits = 12, 924 .ai_speed = 50, 925 .ao_bits = 12, 926 .ao_nchan = 2, 927 .ao_scan_speed = 0, /* no hardware pacing on ao */ 928 .layout = LAYOUT_4020, 929 .ai_range_table = &ai_ranges_4020, 930 .ao_range_table = &ao_ranges_4020, 931 .ao_range_code = ao_range_code_4020, 932 .ai_fifo = &ai_fifo_4020, 933 .has_8255 = 1, 934 }, 935#if 0 936 { 937 .name = "pci-das6402/16/jr", 938 .device_id = 0 /* XXX, */ 939 .ai_se_chans = 64, 940 .ai_bits = 16, 941 .ai_speed = 5000, 942 .ao_nchan = 0, 943 .ao_scan_speed = 10000, 944 .layout = LAYOUT_64XX, 945 .ai_range_table = &ai_ranges_64xx, 946 .ai_fifo = ai_fifo_64xx, 947 .has_8255 = 1, 948 }, 949 { 950 .name = "pci-das64/m1/16/jr", 951 .device_id = 0 /* XXX, */ 952 .ai_se_chans = 64, 953 .ai_bits = 16, 954 .ai_speed = 1000, 955 .ao_nchan = 0, 956 .ao_scan_speed = 10000, 957 .layout = LAYOUT_64XX, 958 .ai_range_table = &ai_ranges_64xx, 959 .ai_fifo = ai_fifo_64xx, 960 .has_8255 = 1, 961 }, 962 { 963 .name = "pci-das64/m2/16/jr", 964 .device_id = 0 /* XXX, */ 965 .ai_se_chans = 64, 966 .ai_bits = 16, 967 .ai_speed = 500, 968 .ao_nchan = 0, 969 .ao_scan_speed = 10000, 970 .layout = LAYOUT_64XX, 971 .ai_range_table = &ai_ranges_64xx, 972 .ai_fifo = ai_fifo_64xx, 973 .has_8255 = 1, 974 }, 975 { 976 .name = "pci-das64/m3/16/jr", 977 .device_id = 0 /* XXX, */ 978 .ai_se_chans = 64, 979 .ai_bits = 16, 980 .ai_speed = 333, 981 .ao_nchan = 0, 982 .ao_scan_speed = 10000, 983 .layout = LAYOUT_64XX, 984 .ai_range_table = &ai_ranges_64xx, 985 .ai_fifo = ai_fifo_64xx, 986 .has_8255 = 1, 987 }, 988 { 989 .name = "pci-das64/m1/14", 990 .device_id = 0, /* XXX */ 991 .ai_se_chans = 64, 992 .ai_bits = 14, 993 .ai_speed = 1000, 994 .ao_nchan = 2, 995 .ao_scan_speed = 10000, 996 .layout = LAYOUT_64XX, 997 .ai_range_table = &ai_ranges_64xx, 998 .ai_fifo = ai_fifo_64xx, 999 .has_8255 = 1, 1000 }, 1001 { 1002 .name = "pci-das64/m2/14", 1003 .device_id = 0, /* XXX */ 1004 .ai_se_chans = 64, 1005 .ai_bits = 14, 1006 .ai_speed = 500, 1007 .ao_nchan = 2, 1008 .ao_scan_speed = 10000, 1009 .layout = LAYOUT_64XX, 1010 .ai_range_table = &ai_ranges_64xx, 1011 .ai_fifo = ai_fifo_64xx, 1012 .has_8255 = 1, 1013 }, 1014 { 1015 .name = "pci-das64/m3/14", 1016 .device_id = 0, /* XXX */ 1017 .ai_se_chans = 64, 1018 .ai_bits = 14, 1019 .ai_speed = 333, 1020 .ao_nchan = 2, 1021 .ao_scan_speed = 10000, 1022 .layout = LAYOUT_64XX, 1023 .ai_range_table = &ai_ranges_64xx, 1024 .ai_fifo = ai_fifo_64xx, 1025 .has_8255 = 1, 1026 }, 1027#endif 1028}; 1029 1030static DEFINE_PCI_DEVICE_TABLE(pcidas64_pci_table) = { 1031 { 1032 PCI_VENDOR_ID_COMPUTERBOARDS, 0x001d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1033 { 1034 PCI_VENDOR_ID_COMPUTERBOARDS, 0x001e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1035 { 1036 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0035, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1037 { 1038 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0036, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1039 { 1040 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0037, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1041 { 1042 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0052, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1043 { 1044 PCI_VENDOR_ID_COMPUTERBOARDS, 0x005d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1045 { 1046 PCI_VENDOR_ID_COMPUTERBOARDS, 0x005e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1047 { 1048 PCI_VENDOR_ID_COMPUTERBOARDS, 0x005f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1049 { 1050 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0061, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1051 { 1052 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0062, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1053 { 1054 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0063, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1055 { 1056 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0064, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1057 { 1058 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0066, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1059 { 1060 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0067, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1061 { 1062 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0068, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1063 { 1064 PCI_VENDOR_ID_COMPUTERBOARDS, 0x006f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1065 { 1066 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0078, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1067 { 1068 PCI_VENDOR_ID_COMPUTERBOARDS, 0x0079, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1069 { 1070 0} 1071}; 1072 1073MODULE_DEVICE_TABLE(pci, pcidas64_pci_table); 1074 1075static inline struct pcidas64_board *board(const struct comedi_device *dev) 1076{ 1077 return (struct pcidas64_board *)dev->board_ptr; 1078} 1079 1080static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev, 1081 int use_differential) 1082{ 1083 if ((board(dev)->layout == LAYOUT_64XX && !use_differential) || 1084 (board(dev)->layout == LAYOUT_60XX && use_differential)) 1085 return ADC_SE_DIFF_BIT; 1086 else 1087 return 0; 1088}; 1089 1090struct ext_clock_info { 1091 unsigned int divisor; /* master clock divisor to use for scans with external master clock */ 1092 unsigned int chanspec; /* chanspec for master clock input when used as scan begin src */ 1093}; 1094 1095/* this structure is for data unique to this hardware driver. */ 1096struct pcidas64_private { 1097 1098 struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */ 1099 /* base addresses (physical) */ 1100 resource_size_t plx9080_phys_iobase; 1101 resource_size_t main_phys_iobase; 1102 resource_size_t dio_counter_phys_iobase; 1103 /* base addresses (ioremapped) */ 1104 void *plx9080_iobase; 1105 void *main_iobase; 1106 void *dio_counter_iobase; 1107 /* local address (used by dma controller) */ 1108 uint32_t local0_iobase; 1109 uint32_t local1_iobase; 1110 volatile unsigned int ai_count; /* number of analog input samples remaining */ 1111 uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT]; /* dma buffers for analog input */ 1112 dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT]; /* physical addresses of ai dma buffers */ 1113 struct plx_dma_desc *ai_dma_desc; /* array of ai dma descriptors read by plx9080, allocated to get proper alignment */ 1114 dma_addr_t ai_dma_desc_bus_addr; /* physical address of ai dma descriptor array */ 1115 volatile unsigned int ai_dma_index; /* index of the ai dma descriptor/buffer that is currently being used */ 1116 uint16_t *ao_buffer[AO_DMA_RING_COUNT]; /* dma buffers for analog output */ 1117 dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT]; /* physical addresses of ao dma buffers */ 1118 struct plx_dma_desc *ao_dma_desc; 1119 dma_addr_t ao_dma_desc_bus_addr; 1120 volatile unsigned int ao_dma_index; /* keeps track of buffer where the next ao sample should go */ 1121 volatile unsigned long ao_count; /* number of analog output samples remaining */ 1122 volatile unsigned int ao_value[2]; /* remember what the analog outputs are set to, to allow readback */ 1123 unsigned int hw_revision; /* stc chip hardware revision number */ 1124 volatile unsigned int intr_enable_bits; /* last bits sent to INTR_ENABLE_REG register */ 1125 volatile uint16_t adc_control1_bits; /* last bits sent to ADC_CONTROL1_REG register */ 1126 volatile uint16_t fifo_size_bits; /* last bits sent to FIFO_SIZE_REG register */ 1127 volatile uint16_t hw_config_bits; /* last bits sent to HW_CONFIG_REG register */ 1128 volatile uint16_t dac_control1_bits; 1129 volatile uint32_t plx_control_bits; /* last bits written to plx9080 control register */ 1130 volatile uint32_t plx_intcsr_bits; /* last bits written to plx interrupt control and status register */ 1131 volatile int calibration_source; /* index of calibration source readable through ai ch0 */ 1132 volatile uint8_t i2c_cal_range_bits; /* bits written to i2c calibration/range register */ 1133 volatile unsigned int ext_trig_falling; /* configure digital triggers to trigger on falling edge */ 1134 /* states of various devices stored to enable read-back */ 1135 unsigned int ad8402_state[2]; 1136 unsigned int caldac_state[8]; 1137 volatile short ai_cmd_running; 1138 unsigned int ai_fifo_segment_length; 1139 struct ext_clock_info ext_clock; 1140 short ao_bounce_buffer[DAC_FIFO_SIZE]; 1141}; 1142 1143/* inline function that makes it easier to 1144 * access the private structure. 1145 */ 1146static inline struct pcidas64_private *priv(struct comedi_device *dev) 1147{ 1148 return dev->private; 1149} 1150 1151/* 1152 * The comedi_driver structure tells the Comedi core module 1153 * which functions to call to configure/deconfigure (attach/detach) 1154 * the board, and also about the kernel module that contains 1155 * the device code. 1156 */ 1157static int attach(struct comedi_device *dev, struct comedi_devconfig *it); 1158static int detach(struct comedi_device *dev); 1159static struct comedi_driver driver_cb_pcidas = { 1160 .driver_name = "cb_pcidas64", 1161 .module = THIS_MODULE, 1162 .attach = attach, 1163 .detach = detach, 1164}; 1165 1166static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1167 struct comedi_insn *insn, unsigned int *data); 1168static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s, 1169 struct comedi_insn *insn, unsigned int *data); 1170static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 1171 struct comedi_insn *insn, unsigned int *data); 1172static int ao_readback_insn(struct comedi_device *dev, 1173 struct comedi_subdevice *s, 1174 struct comedi_insn *insn, unsigned int *data); 1175static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 1176static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 1177 struct comedi_cmd *cmd); 1178static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 1179static int ao_inttrig(struct comedi_device *dev, 1180 struct comedi_subdevice *subdev, unsigned int trig_num); 1181static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 1182 struct comedi_cmd *cmd); 1183static irqreturn_t handle_interrupt(int irq, void *d); 1184static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 1185static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 1186static int dio_callback(int dir, int port, int data, unsigned long arg); 1187static int dio_callback_4020(int dir, int port, int data, unsigned long arg); 1188static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s, 1189 struct comedi_insn *insn, unsigned int *data); 1190static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s, 1191 struct comedi_insn *insn, unsigned int *data); 1192static int dio_60xx_config_insn(struct comedi_device *dev, 1193 struct comedi_subdevice *s, 1194 struct comedi_insn *insn, unsigned int *data); 1195static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s, 1196 struct comedi_insn *insn, unsigned int *data); 1197static int calib_read_insn(struct comedi_device *dev, 1198 struct comedi_subdevice *s, struct comedi_insn *insn, 1199 unsigned int *data); 1200static int calib_write_insn(struct comedi_device *dev, 1201 struct comedi_subdevice *s, 1202 struct comedi_insn *insn, unsigned int *data); 1203static int ad8402_read_insn(struct comedi_device *dev, 1204 struct comedi_subdevice *s, 1205 struct comedi_insn *insn, unsigned int *data); 1206static void ad8402_write(struct comedi_device *dev, unsigned int channel, 1207 unsigned int value); 1208static int ad8402_write_insn(struct comedi_device *dev, 1209 struct comedi_subdevice *s, 1210 struct comedi_insn *insn, unsigned int *data); 1211static int eeprom_read_insn(struct comedi_device *dev, 1212 struct comedi_subdevice *s, 1213 struct comedi_insn *insn, unsigned int *data); 1214static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd); 1215static unsigned int get_divisor(unsigned int ns, unsigned int flags); 1216static void i2c_write(struct comedi_device *dev, unsigned int address, 1217 const uint8_t * data, unsigned int length); 1218static void caldac_write(struct comedi_device *dev, unsigned int channel, 1219 unsigned int value); 1220static int caldac_8800_write(struct comedi_device *dev, unsigned int address, 1221 uint8_t value); 1222/* static int dac_1590_write(struct comedi_device *dev, unsigned int dac_a, unsigned int dac_b); */ 1223static int caldac_i2c_write(struct comedi_device *dev, 1224 unsigned int caldac_channel, unsigned int value); 1225static void abort_dma(struct comedi_device *dev, unsigned int channel); 1226static void disable_plx_interrupts(struct comedi_device *dev); 1227static int set_ai_fifo_size(struct comedi_device *dev, 1228 unsigned int num_samples); 1229static unsigned int ai_fifo_size(struct comedi_device *dev); 1230static int set_ai_fifo_segment_length(struct comedi_device *dev, 1231 unsigned int num_entries); 1232static void disable_ai_pacing(struct comedi_device *dev); 1233static void disable_ai_interrupts(struct comedi_device *dev); 1234static void enable_ai_interrupts(struct comedi_device *dev, 1235 const struct comedi_cmd *cmd); 1236static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags); 1237static void load_ao_dma(struct comedi_device *dev, 1238 const struct comedi_cmd *cmd); 1239 1240COMEDI_PCI_INITCLEANUP(driver_cb_pcidas, pcidas64_pci_table); 1241 1242static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev, 1243 unsigned int range_index) 1244{ 1245 const struct comedi_krange *range = 1246 &board(dev)->ai_range_table->range[range_index]; 1247 unsigned int bits = 0; 1248 1249 switch (range->max) { 1250 case 10000000: 1251 bits = 0x000; 1252 break; 1253 case 5000000: 1254 bits = 0x100; 1255 break; 1256 case 2000000: 1257 case 2500000: 1258 bits = 0x200; 1259 break; 1260 case 1000000: 1261 case 1250000: 1262 bits = 0x300; 1263 break; 1264 case 500000: 1265 bits = 0x400; 1266 break; 1267 case 200000: 1268 case 250000: 1269 bits = 0x500; 1270 break; 1271 case 100000: 1272 bits = 0x600; 1273 break; 1274 case 50000: 1275 bits = 0x700; 1276 break; 1277 default: 1278 comedi_error(dev, "bug! in ai_range_bits_6xxx"); 1279 break; 1280 } 1281 if (range->min == 0) 1282 bits += 0x900; 1283 return bits; 1284} 1285 1286static unsigned int hw_revision(const struct comedi_device *dev, 1287 uint16_t hw_status_bits) 1288{ 1289 if (board(dev)->layout == LAYOUT_4020) 1290 return (hw_status_bits >> 13) & 0x7; 1291 1292 return (hw_status_bits >> 12) & 0xf; 1293} 1294 1295static void set_dac_range_bits(struct comedi_device *dev, 1296 volatile uint16_t * bits, unsigned int channel, 1297 unsigned int range) 1298{ 1299 unsigned int code = board(dev)->ao_range_code[range]; 1300 1301 if (channel > 1) 1302 comedi_error(dev, "bug! bad channel?"); 1303 if (code & ~0x3) 1304 comedi_error(dev, "bug! bad range code?"); 1305 1306 *bits &= ~(0x3 << (2 * channel)); 1307 *bits |= code << (2 * channel); 1308}; 1309 1310static inline int ao_cmd_is_supported(const struct pcidas64_board *board) 1311{ 1312 return board->ao_nchan && board->layout != LAYOUT_4020; 1313} 1314 1315/* initialize plx9080 chip */ 1316static void init_plx9080(struct comedi_device *dev) 1317{ 1318 uint32_t bits; 1319 void *plx_iobase = priv(dev)->plx9080_iobase; 1320 1321 priv(dev)->plx_control_bits = 1322 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG); 1323 1324 /* plx9080 dump */ 1325 DEBUG_PRINT(" plx interrupt status 0x%x\n", 1326 readl(plx_iobase + PLX_INTRCS_REG)); 1327 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG)); 1328 DEBUG_PRINT(" plx control reg 0x%x\n", priv(dev)->plx_control_bits); 1329 DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n", 1330 readl(plx_iobase + PLX_MARB_REG)); 1331 DEBUG_PRINT(" plx region0 reg 0x%x\n", 1332 readl(plx_iobase + PLX_REGION0_REG)); 1333 DEBUG_PRINT(" plx region1 reg 0x%x\n", 1334 readl(plx_iobase + PLX_REGION1_REG)); 1335 1336 DEBUG_PRINT(" plx revision 0x%x\n", 1337 readl(plx_iobase + PLX_REVISION_REG)); 1338 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n", 1339 readl(plx_iobase + PLX_DMA0_MODE_REG)); 1340 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n", 1341 readl(plx_iobase + PLX_DMA1_MODE_REG)); 1342 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n", 1343 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG)); 1344 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n", 1345 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG)); 1346 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n", 1347 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG)); 1348 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n", 1349 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG)); 1350 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n", 1351 readb(plx_iobase + PLX_DMA0_CS_REG)); 1352 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n", 1353 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG)); 1354 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG)); 1355 1356#ifdef __BIG_ENDIAN 1357 bits = BIGEND_DMA0 | BIGEND_DMA1; 1358#else 1359 bits = 0; 1360#endif 1361 writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG); 1362 1363 disable_plx_interrupts(dev); 1364 1365 abort_dma(dev, 0); 1366 abort_dma(dev, 1); 1367 1368 /* configure dma0 mode */ 1369 bits = 0; 1370 /* enable ready input, not sure if this is necessary */ 1371 bits |= PLX_DMA_EN_READYIN_BIT; 1372 /* enable bterm, not sure if this is necessary */ 1373 bits |= PLX_EN_BTERM_BIT; 1374 /* enable dma chaining */ 1375 bits |= PLX_EN_CHAIN_BIT; 1376 /* enable interrupt on dma done (probably don't need this, since chain never finishes) */ 1377 bits |= PLX_EN_DMA_DONE_INTR_BIT; 1378 /* don't increment local address during transfers (we are transferring from a fixed fifo register) */ 1379 bits |= PLX_LOCAL_ADDR_CONST_BIT; 1380 /* route dma interrupt to pci bus */ 1381 bits |= PLX_DMA_INTR_PCI_BIT; 1382 /* enable demand mode */ 1383 bits |= PLX_DEMAND_MODE_BIT; 1384 /* enable local burst mode */ 1385 bits |= PLX_DMA_LOCAL_BURST_EN_BIT; 1386 /* 4020 uses 32 bit dma */ 1387 if (board(dev)->layout == LAYOUT_4020) { 1388 bits |= PLX_LOCAL_BUS_32_WIDE_BITS; 1389 } else { /* localspace0 bus is 16 bits wide */ 1390 bits |= PLX_LOCAL_BUS_16_WIDE_BITS; 1391 } 1392 writel(bits, plx_iobase + PLX_DMA1_MODE_REG); 1393 if (ao_cmd_is_supported(board(dev))) 1394 writel(bits, plx_iobase + PLX_DMA0_MODE_REG); 1395 1396 /* enable interrupts on plx 9080 */ 1397 priv(dev)->plx_intcsr_bits |= 1398 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE | 1399 ICS_DMA0_E | ICS_DMA1_E; 1400 writel(priv(dev)->plx_intcsr_bits, 1401 priv(dev)->plx9080_iobase + PLX_INTRCS_REG); 1402} 1403 1404/* Allocate and initialize the subdevice structures. 1405 */ 1406static int setup_subdevices(struct comedi_device *dev) 1407{ 1408 struct comedi_subdevice *s; 1409 void *dio_8255_iobase; 1410 int i; 1411 1412 if (alloc_subdevices(dev, 10) < 0) 1413 return -ENOMEM; 1414 1415 s = dev->subdevices + 0; 1416 /* analog input subdevice */ 1417 dev->read_subdev = s; 1418 s->type = COMEDI_SUBD_AI; 1419 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ; 1420 if (board(dev)->layout == LAYOUT_60XX) 1421 s->subdev_flags |= SDF_COMMON | SDF_DIFF; 1422 else if (board(dev)->layout == LAYOUT_64XX) 1423 s->subdev_flags |= SDF_DIFF; 1424 /* XXX Number of inputs in differential mode is ignored */ 1425 s->n_chan = board(dev)->ai_se_chans; 1426 s->len_chanlist = 0x2000; 1427 s->maxdata = (1 << board(dev)->ai_bits) - 1; 1428 s->range_table = board(dev)->ai_range_table; 1429 s->insn_read = ai_rinsn; 1430 s->insn_config = ai_config_insn; 1431 s->do_cmd = ai_cmd; 1432 s->do_cmdtest = ai_cmdtest; 1433 s->cancel = ai_cancel; 1434 if (board(dev)->layout == LAYOUT_4020) { 1435 unsigned int i; 1436 uint8_t data; 1437 /* set adc to read from inputs (not internal calibration sources) */ 1438 priv(dev)->i2c_cal_range_bits = adc_src_4020_bits(4); 1439 /* set channels to +-5 volt input ranges */ 1440 for (i = 0; i < s->n_chan; i++) 1441 priv(dev)->i2c_cal_range_bits |= attenuate_bit(i); 1442 data = priv(dev)->i2c_cal_range_bits; 1443 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data)); 1444 } 1445 1446 /* analog output subdevice */ 1447 s = dev->subdevices + 1; 1448 if (board(dev)->ao_nchan) { 1449 s->type = COMEDI_SUBD_AO; 1450 s->subdev_flags = 1451 SDF_READABLE | SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE; 1452 s->n_chan = board(dev)->ao_nchan; 1453 s->maxdata = (1 << board(dev)->ao_bits) - 1; 1454 s->range_table = board(dev)->ao_range_table; 1455 s->insn_read = ao_readback_insn; 1456 s->insn_write = ao_winsn; 1457 if (ao_cmd_is_supported(board(dev))) { 1458 dev->write_subdev = s; 1459 s->do_cmdtest = ao_cmdtest; 1460 s->do_cmd = ao_cmd; 1461 s->len_chanlist = board(dev)->ao_nchan; 1462 s->cancel = ao_cancel; 1463 } 1464 } else { 1465 s->type = COMEDI_SUBD_UNUSED; 1466 } 1467 1468 /* digital input */ 1469 s = dev->subdevices + 2; 1470 if (board(dev)->layout == LAYOUT_64XX) { 1471 s->type = COMEDI_SUBD_DI; 1472 s->subdev_flags = SDF_READABLE; 1473 s->n_chan = 4; 1474 s->maxdata = 1; 1475 s->range_table = &range_digital; 1476 s->insn_bits = di_rbits; 1477 } else 1478 s->type = COMEDI_SUBD_UNUSED; 1479 1480 /* digital output */ 1481 if (board(dev)->layout == LAYOUT_64XX) { 1482 s = dev->subdevices + 3; 1483 s->type = COMEDI_SUBD_DO; 1484 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 1485 s->n_chan = 4; 1486 s->maxdata = 1; 1487 s->range_table = &range_digital; 1488 s->insn_bits = do_wbits; 1489 } else 1490 s->type = COMEDI_SUBD_UNUSED; 1491 1492 /* 8255 */ 1493 s = dev->subdevices + 4; 1494 if (board(dev)->has_8255) { 1495 if (board(dev)->layout == LAYOUT_4020) { 1496 dio_8255_iobase = 1497 priv(dev)->main_iobase + I8255_4020_REG; 1498 subdev_8255_init(dev, s, dio_callback_4020, 1499 (unsigned long)dio_8255_iobase); 1500 } else { 1501 dio_8255_iobase = 1502 priv(dev)->dio_counter_iobase + DIO_8255_OFFSET; 1503 subdev_8255_init(dev, s, dio_callback, 1504 (unsigned long)dio_8255_iobase); 1505 } 1506 } else 1507 s->type = COMEDI_SUBD_UNUSED; 1508 1509 /* 8 channel dio for 60xx */ 1510 s = dev->subdevices + 5; 1511 if (board(dev)->layout == LAYOUT_60XX) { 1512 s->type = COMEDI_SUBD_DIO; 1513 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 1514 s->n_chan = 8; 1515 s->maxdata = 1; 1516 s->range_table = &range_digital; 1517 s->insn_config = dio_60xx_config_insn; 1518 s->insn_bits = dio_60xx_wbits; 1519 } else 1520 s->type = COMEDI_SUBD_UNUSED; 1521 1522 /* caldac */ 1523 s = dev->subdevices + 6; 1524 s->type = COMEDI_SUBD_CALIB; 1525 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 1526 s->n_chan = 8; 1527 if (board(dev)->layout == LAYOUT_4020) 1528 s->maxdata = 0xfff; 1529 else 1530 s->maxdata = 0xff; 1531 s->insn_read = calib_read_insn; 1532 s->insn_write = calib_write_insn; 1533 for (i = 0; i < s->n_chan; i++) 1534 caldac_write(dev, i, s->maxdata / 2); 1535 1536 /* 2 channel ad8402 potentiometer */ 1537 s = dev->subdevices + 7; 1538 if (board(dev)->layout == LAYOUT_64XX) { 1539 s->type = COMEDI_SUBD_CALIB; 1540 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 1541 s->n_chan = 2; 1542 s->insn_read = ad8402_read_insn; 1543 s->insn_write = ad8402_write_insn; 1544 s->maxdata = 0xff; 1545 for (i = 0; i < s->n_chan; i++) 1546 ad8402_write(dev, i, s->maxdata / 2); 1547 } else 1548 s->type = COMEDI_SUBD_UNUSED; 1549 1550 /* serial EEPROM, if present */ 1551 s = dev->subdevices + 8; 1552 if (readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) { 1553 s->type = COMEDI_SUBD_MEMORY; 1554 s->subdev_flags = SDF_READABLE | SDF_INTERNAL; 1555 s->n_chan = 128; 1556 s->maxdata = 0xffff; 1557 s->insn_read = eeprom_read_insn; 1558 } else 1559 s->type = COMEDI_SUBD_UNUSED; 1560 1561 /* user counter subd XXX */ 1562 s = dev->subdevices + 9; 1563 s->type = COMEDI_SUBD_UNUSED; 1564 1565 return 0; 1566} 1567 1568static void disable_plx_interrupts(struct comedi_device *dev) 1569{ 1570 priv(dev)->plx_intcsr_bits = 0; 1571 writel(priv(dev)->plx_intcsr_bits, 1572 priv(dev)->plx9080_iobase + PLX_INTRCS_REG); 1573} 1574 1575static void init_stc_registers(struct comedi_device *dev) 1576{ 1577 uint16_t bits; 1578 unsigned long flags; 1579 1580 spin_lock_irqsave(&dev->spinlock, flags); 1581 1582 /* bit should be set for 6025, although docs say boards with <= 16 chans should be cleared XXX */ 1583 if (1) 1584 priv(dev)->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT; 1585 writew(priv(dev)->adc_control1_bits, 1586 priv(dev)->main_iobase + ADC_CONTROL1_REG); 1587 1588 /* 6402/16 manual says this register must be initialized to 0xff? */ 1589 writew(0xff, priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); 1590 1591 bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT; 1592 if (board(dev)->layout == LAYOUT_4020) 1593 bits |= INTERNAL_CLOCK_4020_BITS; 1594 priv(dev)->hw_config_bits |= bits; 1595 writew(priv(dev)->hw_config_bits, 1596 priv(dev)->main_iobase + HW_CONFIG_REG); 1597 1598 writew(0, priv(dev)->main_iobase + DAQ_SYNC_REG); 1599 writew(0, priv(dev)->main_iobase + CALIBRATION_REG); 1600 1601 spin_unlock_irqrestore(&dev->spinlock, flags); 1602 1603 /* set fifos to maximum size */ 1604 priv(dev)->fifo_size_bits |= DAC_FIFO_BITS; 1605 set_ai_fifo_segment_length(dev, 1606 board(dev)->ai_fifo->max_segment_length); 1607 1608 priv(dev)->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT; 1609 priv(dev)->intr_enable_bits = /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */ 1610 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT; 1611 writew(priv(dev)->intr_enable_bits, 1612 priv(dev)->main_iobase + INTR_ENABLE_REG); 1613 1614 disable_ai_pacing(dev); 1615}; 1616 1617int alloc_and_init_dma_members(struct comedi_device *dev) 1618{ 1619 int i; 1620 1621 /* alocate pci dma buffers */ 1622 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) { 1623 priv(dev)->ai_buffer[i] = 1624 pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE, 1625 &priv(dev)->ai_buffer_bus_addr[i]); 1626 if (priv(dev)->ai_buffer[i] == NULL) 1627 return -ENOMEM; 1628 1629 } 1630 for (i = 0; i < AO_DMA_RING_COUNT; i++) { 1631 if (ao_cmd_is_supported(board(dev))) { 1632 priv(dev)->ao_buffer[i] = 1633 pci_alloc_consistent(priv(dev)->hw_dev, 1634 DMA_BUFFER_SIZE, 1635 &priv(dev)-> 1636 ao_buffer_bus_addr[i]); 1637 if (priv(dev)->ao_buffer[i] == NULL) 1638 return -ENOMEM; 1639 1640 } 1641 } 1642 /* allocate dma descriptors */ 1643 priv(dev)->ai_dma_desc = 1644 pci_alloc_consistent(priv(dev)->hw_dev, 1645 sizeof(struct plx_dma_desc) * 1646 ai_dma_ring_count(board(dev)), 1647 &priv(dev)->ai_dma_desc_bus_addr); 1648 if (priv(dev)->ai_dma_desc == NULL) 1649 return -ENOMEM; 1650 1651 DEBUG_PRINT("ai dma descriptors start at bus addr 0x%x\n", 1652 priv(dev)->ai_dma_desc_bus_addr); 1653 if (ao_cmd_is_supported(board(dev))) { 1654 priv(dev)->ao_dma_desc = 1655 pci_alloc_consistent(priv(dev)->hw_dev, 1656 sizeof(struct plx_dma_desc) * 1657 AO_DMA_RING_COUNT, 1658 &priv(dev)->ao_dma_desc_bus_addr); 1659 if (priv(dev)->ao_dma_desc == NULL) 1660 return -ENOMEM; 1661 1662 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%x\n", 1663 priv(dev)->ao_dma_desc_bus_addr); 1664 } 1665 /* initialize dma descriptors */ 1666 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) { 1667 priv(dev)->ai_dma_desc[i].pci_start_addr = 1668 cpu_to_le32(priv(dev)->ai_buffer_bus_addr[i]); 1669 if (board(dev)->layout == LAYOUT_4020) 1670 priv(dev)->ai_dma_desc[i].local_start_addr = 1671 cpu_to_le32(priv(dev)->local1_iobase + 1672 ADC_FIFO_REG); 1673 else 1674 priv(dev)->ai_dma_desc[i].local_start_addr = 1675 cpu_to_le32(priv(dev)->local0_iobase + 1676 ADC_FIFO_REG); 1677 priv(dev)->ai_dma_desc[i].transfer_size = cpu_to_le32(0); 1678 priv(dev)->ai_dma_desc[i].next = 1679 cpu_to_le32((priv(dev)->ai_dma_desc_bus_addr + ((i + 1680 1) % 1681 ai_dma_ring_count 1682 (board 1683 (dev))) * 1684 sizeof(priv(dev)->ai_dma_desc[0])) | 1685 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT | 1686 PLX_XFER_LOCAL_TO_PCI); 1687 } 1688 if (ao_cmd_is_supported(board(dev))) { 1689 for (i = 0; i < AO_DMA_RING_COUNT; i++) { 1690 priv(dev)->ao_dma_desc[i].pci_start_addr = 1691 cpu_to_le32(priv(dev)->ao_buffer_bus_addr[i]); 1692 priv(dev)->ao_dma_desc[i].local_start_addr = 1693 cpu_to_le32(priv(dev)->local0_iobase + 1694 DAC_FIFO_REG); 1695 priv(dev)->ao_dma_desc[i].transfer_size = 1696 cpu_to_le32(0); 1697 priv(dev)->ao_dma_desc[i].next = 1698 cpu_to_le32((priv(dev)->ao_dma_desc_bus_addr + 1699 ((i + 1) % (AO_DMA_RING_COUNT)) * 1700 sizeof(priv(dev)->ao_dma_desc[0])) | 1701 PLX_DESC_IN_PCI_BIT | 1702 PLX_INTR_TERM_COUNT); 1703 } 1704 } 1705 return 0; 1706} 1707 1708static inline void warn_external_queue(struct comedi_device *dev) 1709{ 1710 comedi_error(dev, 1711 "AO command and AI external channel queue cannot be used simultaneously."); 1712 comedi_error(dev, 1713 "Use internal AI channel queue (channels must be consecutive and use same range/aref)"); 1714} 1715 1716/* 1717 * Attach is called by the Comedi core to configure the driver 1718 * for a particular board. 1719 */ 1720static int attach(struct comedi_device *dev, struct comedi_devconfig *it) 1721{ 1722 struct pci_dev *pcidev; 1723 int index; 1724 uint32_t local_range, local_decode; 1725 int retval; 1726 1727 printk("comedi%d: cb_pcidas64\n", dev->minor); 1728 1729/* 1730 * Allocate the private structure area. 1731 */ 1732 if (alloc_private(dev, sizeof(struct pcidas64_private)) < 0) 1733 return -ENOMEM; 1734 1735/* 1736 * Probe the device to determine what device in the series it is. 1737 */ 1738 1739 for (pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL); 1740 pcidev != NULL; 1741 pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pcidev)) { 1742 /* is it not a computer boards card? */ 1743 if (pcidev->vendor != PCI_VENDOR_ID_COMPUTERBOARDS) 1744 continue; 1745 /* loop through cards supported by this driver */ 1746 for (index = 0; index < ARRAY_SIZE(pcidas64_boards); index++) { 1747 if (pcidas64_boards[index].device_id != pcidev->device) 1748 continue; 1749 /* was a particular bus/slot requested? */ 1750 if (it->options[0] || it->options[1]) { 1751 /* are we on the wrong bus/slot? */ 1752 if (pcidev->bus->number != it->options[0] || 1753 PCI_SLOT(pcidev->devfn) != it->options[1]) { 1754 continue; 1755 } 1756 } 1757 priv(dev)->hw_dev = pcidev; 1758 dev->board_ptr = pcidas64_boards + index; 1759 break; 1760 } 1761 if (dev->board_ptr) 1762 break; 1763 } 1764 1765 if (dev->board_ptr == NULL) { 1766 printk 1767 ("No supported ComputerBoards/MeasurementComputing card found\n"); 1768 return -EIO; 1769 } 1770 1771 printk("Found %s on bus %i, slot %i\n", board(dev)->name, 1772 pcidev->bus->number, PCI_SLOT(pcidev->devfn)); 1773 1774 if (comedi_pci_enable(pcidev, driver_cb_pcidas.driver_name)) { 1775 printk(KERN_WARNING 1776 " failed to enable PCI device and request regions\n"); 1777 return -EIO; 1778 } 1779 pci_set_master(pcidev); 1780 1781 /* Initialize dev->board_name */ 1782 dev->board_name = board(dev)->name; 1783 1784 priv(dev)->plx9080_phys_iobase = 1785 pci_resource_start(pcidev, PLX9080_BADDRINDEX); 1786 priv(dev)->main_phys_iobase = 1787 pci_resource_start(pcidev, MAIN_BADDRINDEX); 1788 priv(dev)->dio_counter_phys_iobase = 1789 pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX); 1790 1791 /* remap, won't work with 2.0 kernels but who cares */ 1792 priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase, 1793 pci_resource_len(pcidev, 1794 PLX9080_BADDRINDEX)); 1795 priv(dev)->main_iobase = 1796 ioremap(priv(dev)->main_phys_iobase, 1797 pci_resource_len(pcidev, MAIN_BADDRINDEX)); 1798 priv(dev)->dio_counter_iobase = 1799 ioremap(priv(dev)->dio_counter_phys_iobase, 1800 pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX)); 1801 1802 if (!priv(dev)->plx9080_iobase || !priv(dev)->main_iobase 1803 || !priv(dev)->dio_counter_iobase) { 1804 printk(" failed to remap io memory\n"); 1805 return -ENOMEM; 1806 } 1807 1808 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase); 1809 DEBUG_PRINT(" main remapped to 0x%p\n", priv(dev)->main_iobase); 1810 DEBUG_PRINT(" diocounter remapped to 0x%p\n", 1811 priv(dev)->dio_counter_iobase); 1812 1813 /* figure out what local addresses are */ 1814 local_range = 1815 readl(priv(dev)->plx9080_iobase + PLX_LAS0RNG_REG) & LRNG_MEM_MASK; 1816 local_decode = 1817 readl(priv(dev)->plx9080_iobase + 1818 PLX_LAS0MAP_REG) & local_range & LMAP_MEM_MASK; 1819 priv(dev)->local0_iobase = 1820 ((uint32_t) priv(dev)->main_phys_iobase & ~local_range) | 1821 local_decode; 1822 local_range = 1823 readl(priv(dev)->plx9080_iobase + PLX_LAS1RNG_REG) & LRNG_MEM_MASK; 1824 local_decode = 1825 readl(priv(dev)->plx9080_iobase + 1826 PLX_LAS1MAP_REG) & local_range & LMAP_MEM_MASK; 1827 priv(dev)->local1_iobase = 1828 ((uint32_t) priv(dev)->dio_counter_phys_iobase & ~local_range) | 1829 local_decode; 1830 1831 DEBUG_PRINT(" local 0 io addr 0x%x\n", priv(dev)->local0_iobase); 1832 DEBUG_PRINT(" local 1 io addr 0x%x\n", priv(dev)->local1_iobase); 1833 1834 retval = alloc_and_init_dma_members(dev); 1835 if (retval < 0) 1836 return retval; 1837 1838 priv(dev)->hw_revision = 1839 hw_revision(dev, readw(priv(dev)->main_iobase + HW_STATUS_REG)); 1840 printk(" stc hardware revision %i\n", priv(dev)->hw_revision); 1841 init_plx9080(dev); 1842 init_stc_registers(dev); 1843 /* get irq */ 1844 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED, 1845 "cb_pcidas64", dev)) { 1846 printk(" unable to allocate irq %u\n", pcidev->irq); 1847 return -EINVAL; 1848 } 1849 dev->irq = pcidev->irq; 1850 printk(" irq %u\n", dev->irq); 1851 1852 retval = setup_subdevices(dev); 1853 if (retval < 0) 1854 return retval; 1855 1856 1857 return 0; 1858} 1859 1860/* 1861 * _detach is called to deconfigure a device. It should deallocate 1862 * resources. 1863 * This function is also called when _attach() fails, so it should be 1864 * careful not to release resources that were not necessarily 1865 * allocated by _attach(). dev->private and dev->subdevices are 1866 * deallocated automatically by the core. 1867 */ 1868static int detach(struct comedi_device *dev) 1869{ 1870 unsigned int i; 1871 1872 printk("comedi%d: cb_pcidas: remove\n", dev->minor); 1873 1874 if (dev->irq) 1875 free_irq(dev->irq, dev); 1876 if (priv(dev)) { 1877 if (priv(dev)->hw_dev) { 1878 if (priv(dev)->plx9080_iobase) { 1879 disable_plx_interrupts(dev); 1880 iounmap((void *)priv(dev)->plx9080_iobase); 1881 } 1882 if (priv(dev)->main_iobase) 1883 iounmap((void *)priv(dev)->main_iobase); 1884 if (priv(dev)->dio_counter_iobase) 1885 iounmap((void *)priv(dev)->dio_counter_iobase); 1886 /* free pci dma buffers */ 1887 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) { 1888 if (priv(dev)->ai_buffer[i]) 1889 pci_free_consistent(priv(dev)->hw_dev, 1890 DMA_BUFFER_SIZE, 1891 priv(dev)-> 1892 ai_buffer[i], 1893 priv 1894 (dev)->ai_buffer_bus_addr 1895 [i]); 1896 } 1897 for (i = 0; i < AO_DMA_RING_COUNT; i++) { 1898 if (priv(dev)->ao_buffer[i]) 1899 pci_free_consistent(priv(dev)->hw_dev, 1900 DMA_BUFFER_SIZE, 1901 priv(dev)-> 1902 ao_buffer[i], 1903 priv 1904 (dev)->ao_buffer_bus_addr 1905 [i]); 1906 } 1907 /* free dma descriptors */ 1908 if (priv(dev)->ai_dma_desc) 1909 pci_free_consistent(priv(dev)->hw_dev, 1910 sizeof(struct plx_dma_desc) 1911 * 1912 ai_dma_ring_count(board 1913 (dev)), 1914 priv(dev)->ai_dma_desc, 1915 priv(dev)-> 1916 ai_dma_desc_bus_addr); 1917 if (priv(dev)->ao_dma_desc) 1918 pci_free_consistent(priv(dev)->hw_dev, 1919 sizeof(struct plx_dma_desc) 1920 * AO_DMA_RING_COUNT, 1921 priv(dev)->ao_dma_desc, 1922 priv(dev)-> 1923 ao_dma_desc_bus_addr); 1924 if (priv(dev)->main_phys_iobase) 1925 comedi_pci_disable(priv(dev)->hw_dev); 1926 1927 pci_dev_put(priv(dev)->hw_dev); 1928 } 1929 } 1930 if (dev->subdevices) 1931 subdev_8255_cleanup(dev, dev->subdevices + 4); 1932 1933 return 0; 1934} 1935 1936static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1937 struct comedi_insn *insn, unsigned int *data) 1938{ 1939 unsigned int bits = 0, n, i; 1940 unsigned int channel, range, aref; 1941 unsigned long flags; 1942 static const int timeout = 100; 1943 1944 DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec); 1945 channel = CR_CHAN(insn->chanspec); 1946 range = CR_RANGE(insn->chanspec); 1947 aref = CR_AREF(insn->chanspec); 1948 1949 /* disable card's analog input interrupt sources and pacing */ 1950 /* 4020 generates dac done interrupts even though they are disabled */ 1951 disable_ai_pacing(dev); 1952 1953 spin_lock_irqsave(&dev->spinlock, flags); 1954 if (insn->chanspec & CR_ALT_FILTER) 1955 priv(dev)->adc_control1_bits |= ADC_DITHER_BIT; 1956 else 1957 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT; 1958 writew(priv(dev)->adc_control1_bits, 1959 priv(dev)->main_iobase + ADC_CONTROL1_REG); 1960 spin_unlock_irqrestore(&dev->spinlock, flags); 1961 1962 if (board(dev)->layout != LAYOUT_4020) { 1963 /* use internal queue */ 1964 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT; 1965 writew(priv(dev)->hw_config_bits, 1966 priv(dev)->main_iobase + HW_CONFIG_REG); 1967 1968 /* ALT_SOURCE is internal calibration reference */ 1969 if (insn->chanspec & CR_ALT_SOURCE) { 1970 unsigned int cal_en_bit; 1971 1972 DEBUG_PRINT("reading calibration source\n"); 1973 if (board(dev)->layout == LAYOUT_60XX) 1974 cal_en_bit = CAL_EN_60XX_BIT; 1975 else 1976 cal_en_bit = CAL_EN_64XX_BIT; 1977 /* select internal reference source to connect to channel 0 */ 1978 writew(cal_en_bit | 1979 adc_src_bits(priv(dev)->calibration_source), 1980 priv(dev)->main_iobase + CALIBRATION_REG); 1981 } else { 1982 /* make sure internal calibration source is turned off */ 1983 writew(0, priv(dev)->main_iobase + CALIBRATION_REG); 1984 } 1985 /* load internal queue */ 1986 bits = 0; 1987 /* set gain */ 1988 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec)); 1989 /* set single-ended / differential */ 1990 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF); 1991 if (aref == AREF_COMMON) 1992 bits |= ADC_COMMON_BIT; 1993 bits |= adc_chan_bits(channel); 1994 /* set stop channel */ 1995 writew(adc_chan_bits(channel), 1996 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG); 1997 /* set start channel, and rest of settings */ 1998 writew(bits, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG); 1999 } else { 2000 uint8_t old_cal_range_bits = priv(dev)->i2c_cal_range_bits; 2001 2002 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK; 2003 if (insn->chanspec & CR_ALT_SOURCE) { 2004 DEBUG_PRINT("reading calibration source\n"); 2005 priv(dev)->i2c_cal_range_bits |= 2006 adc_src_4020_bits(priv(dev)->calibration_source); 2007 } else { /* select BNC inputs */ 2008 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4); 2009 } 2010 /* select range */ 2011 if (range == 0) 2012 priv(dev)->i2c_cal_range_bits |= attenuate_bit(channel); 2013 else 2014 priv(dev)->i2c_cal_range_bits &= 2015 ~attenuate_bit(channel); 2016 /* update calibration/range i2c register only if necessary, as it is very slow */ 2017 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) { 2018 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits; 2019 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data, 2020 sizeof(i2c_data)); 2021 } 2022 2023 /* 4020 manual asks that sample interval register to be set before writing to convert register. 2024 * Using somewhat arbitrary setting of 4 master clock ticks = 0.1 usec */ 2025 writew(0, 2026 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); 2027 writew(2, 2028 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG); 2029 } 2030 2031 for (n = 0; n < insn->n; n++) { 2032 2033 /* clear adc buffer (inside loop for 4020 sake) */ 2034 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG); 2035 2036 /* trigger conversion, bits sent only matter for 4020 */ 2037 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)), 2038 priv(dev)->main_iobase + ADC_CONVERT_REG); 2039 2040 /* wait for data */ 2041 for (i = 0; i < timeout; i++) { 2042 bits = readw(priv(dev)->main_iobase + HW_STATUS_REG); 2043 DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits)); 2044 if (board(dev)->layout == LAYOUT_4020) { 2045 if (readw(priv(dev)->main_iobase + 2046 ADC_WRITE_PNTR_REG)) 2047 break; 2048 } else { 2049 if (pipe_full_bits(bits)) 2050 break; 2051 } 2052 udelay(1); 2053 } 2054 DEBUG_PRINT(" looped %i times waiting for data\n", i); 2055 if (i == timeout) { 2056 comedi_error(dev, " analog input read insn timed out"); 2057 printk(" status 0x%x\n", bits); 2058 return -ETIME; 2059 } 2060 if (board(dev)->layout == LAYOUT_4020) 2061 data[n] = 2062 readl(priv(dev)->dio_counter_iobase + 2063 ADC_FIFO_REG) & 0xffff; 2064 else 2065 data[n] = 2066 readw(priv(dev)->main_iobase + PIPE1_READ_REG); 2067 } 2068 2069 return n; 2070} 2071 2072static int ai_config_calibration_source(struct comedi_device *dev, 2073 unsigned int *data) 2074{ 2075 unsigned int source = data[1]; 2076 int num_calibration_sources; 2077 2078 if (board(dev)->layout == LAYOUT_60XX) 2079 num_calibration_sources = 16; 2080 else 2081 num_calibration_sources = 8; 2082 if (source >= num_calibration_sources) { 2083 printk("invalid calibration source: %i\n", source); 2084 return -EINVAL; 2085 } 2086 2087 DEBUG_PRINT("setting calibration source to %i\n", source); 2088 priv(dev)->calibration_source = source; 2089 2090 return 2; 2091} 2092 2093static int ai_config_block_size(struct comedi_device *dev, unsigned int *data) 2094{ 2095 int fifo_size; 2096 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo; 2097 unsigned int block_size, requested_block_size; 2098 int retval; 2099 2100 requested_block_size = data[1]; 2101 2102 if (requested_block_size) { 2103 fifo_size = 2104 requested_block_size * fifo->num_segments / bytes_in_sample; 2105 2106 retval = set_ai_fifo_size(dev, fifo_size); 2107 if (retval < 0) 2108 return retval; 2109 2110 } 2111 2112 block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample; 2113 2114 data[1] = block_size; 2115 2116 return 2; 2117} 2118 2119static int ai_config_master_clock_4020(struct comedi_device *dev, 2120 unsigned int *data) 2121{ 2122 unsigned int divisor = data[4]; 2123 int retval = 0; 2124 2125 if (divisor < 2) { 2126 divisor = 2; 2127 retval = -EAGAIN; 2128 } 2129 2130 switch (data[1]) { 2131 case COMEDI_EV_SCAN_BEGIN: 2132 priv(dev)->ext_clock.divisor = divisor; 2133 priv(dev)->ext_clock.chanspec = data[2]; 2134 break; 2135 default: 2136 return -EINVAL; 2137 break; 2138 } 2139 2140 data[4] = divisor; 2141 2142 return retval ? retval : 5; 2143} 2144 2145/* XXX could add support for 60xx series */ 2146static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data) 2147{ 2148 2149 switch (board(dev)->layout) { 2150 case LAYOUT_4020: 2151 return ai_config_master_clock_4020(dev, data); 2152 break; 2153 default: 2154 return -EINVAL; 2155 break; 2156 } 2157 2158 return -EINVAL; 2159} 2160 2161static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s, 2162 struct comedi_insn *insn, unsigned int *data) 2163{ 2164 int id = data[0]; 2165 2166 switch (id) { 2167 case INSN_CONFIG_ALT_SOURCE: 2168 return ai_config_calibration_source(dev, data); 2169 break; 2170 case INSN_CONFIG_BLOCK_SIZE: 2171 return ai_config_block_size(dev, data); 2172 break; 2173 case INSN_CONFIG_TIMER_1: 2174 return ai_config_master_clock(dev, data); 2175 break; 2176 default: 2177 return -EINVAL; 2178 break; 2179 } 2180 return -EINVAL; 2181} 2182 2183static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 2184 struct comedi_cmd *cmd) 2185{ 2186 int err = 0; 2187 int tmp; 2188 unsigned int tmp_arg, tmp_arg2; 2189 int i; 2190 int aref; 2191 unsigned int triggers; 2192 2193 /* step 1: make sure trigger sources are trivially valid */ 2194 2195 tmp = cmd->start_src; 2196 cmd->start_src &= TRIG_NOW | TRIG_EXT; 2197 if (!cmd->start_src || tmp != cmd->start_src) 2198 err++; 2199 2200 tmp = cmd->scan_begin_src; 2201 triggers = TRIG_TIMER; 2202 if (board(dev)->layout == LAYOUT_4020) 2203 triggers |= TRIG_OTHER; 2204 else 2205 triggers |= TRIG_FOLLOW; 2206 cmd->scan_begin_src &= triggers; 2207 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 2208 err++; 2209 2210 tmp = cmd->convert_src; 2211 triggers = TRIG_TIMER; 2212 if (board(dev)->layout == LAYOUT_4020) 2213 triggers |= TRIG_NOW; 2214 else 2215 triggers |= TRIG_EXT; 2216 cmd->convert_src &= triggers; 2217 if (!cmd->convert_src || tmp != cmd->convert_src) 2218 err++; 2219 2220 tmp = cmd->scan_end_src; 2221 cmd->scan_end_src &= TRIG_COUNT; 2222 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 2223 err++; 2224 2225 tmp = cmd->stop_src; 2226 cmd->stop_src &= TRIG_COUNT | TRIG_EXT | TRIG_NONE; 2227 if (!cmd->stop_src || tmp != cmd->stop_src) 2228 err++; 2229 2230 if (err) 2231 return 1; 2232 2233 /* step 2: make sure trigger sources are unique and mutually compatible */ 2234 2235 /* uniqueness check */ 2236 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) 2237 err++; 2238 if (cmd->scan_begin_src != TRIG_TIMER && 2239 cmd->scan_begin_src != TRIG_OTHER && 2240 cmd->scan_begin_src != TRIG_FOLLOW) 2241 err++; 2242 if (cmd->convert_src != TRIG_TIMER && 2243 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW) 2244 err++; 2245 if (cmd->stop_src != TRIG_COUNT && 2246 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT) 2247 err++; 2248 2249 /* compatibility check */ 2250 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER) 2251 err++; 2252 if (cmd->stop_src != TRIG_COUNT && 2253 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT) 2254 err++; 2255 2256 if (err) 2257 return 2; 2258 2259 /* step 3: make sure arguments are trivially compatible */ 2260 2261 if (cmd->convert_src == TRIG_TIMER) { 2262 if (board(dev)->layout == LAYOUT_4020) { 2263 if (cmd->convert_arg) { 2264 cmd->convert_arg = 0; 2265 err++; 2266 } 2267 } else { 2268 if (cmd->convert_arg < board(dev)->ai_speed) { 2269 cmd->convert_arg = board(dev)->ai_speed; 2270 err++; 2271 } 2272 if (cmd->scan_begin_src == TRIG_TIMER) { 2273 /* if scans are timed faster than conversion rate allows */ 2274 if (cmd->convert_arg * cmd->chanlist_len > 2275 cmd->scan_begin_arg) { 2276 cmd->scan_begin_arg = 2277 cmd->convert_arg * 2278 cmd->chanlist_len; 2279 err++; 2280 } 2281 } 2282 } 2283 } 2284 2285 if (!cmd->chanlist_len) { 2286 cmd->chanlist_len = 1; 2287 err++; 2288 } 2289 if (cmd->scan_end_arg != cmd->chanlist_len) { 2290 cmd->scan_end_arg = cmd->chanlist_len; 2291 err++; 2292 } 2293 2294 switch (cmd->stop_src) { 2295 case TRIG_EXT: 2296 break; 2297 case TRIG_COUNT: 2298 if (!cmd->stop_arg) { 2299 cmd->stop_arg = 1; 2300 err++; 2301 } 2302 break; 2303 case TRIG_NONE: 2304 if (cmd->stop_arg != 0) { 2305 cmd->stop_arg = 0; 2306 err++; 2307 } 2308 break; 2309 default: 2310 break; 2311 } 2312 2313 if (err) 2314 return 3; 2315 2316 /* step 4: fix up any arguments */ 2317 2318 if (cmd->convert_src == TRIG_TIMER) { 2319 tmp_arg = cmd->convert_arg; 2320 tmp_arg2 = cmd->scan_begin_arg; 2321 check_adc_timing(dev, cmd); 2322 if (tmp_arg != cmd->convert_arg) 2323 err++; 2324 if (tmp_arg2 != cmd->scan_begin_arg) 2325 err++; 2326 } 2327 2328 if (err) 2329 return 4; 2330 2331 /* make sure user is doesn't change analog reference mid chanlist */ 2332 if (cmd->chanlist) { 2333 aref = CR_AREF(cmd->chanlist[0]); 2334 for (i = 1; i < cmd->chanlist_len; i++) { 2335 if (aref != CR_AREF(cmd->chanlist[i])) { 2336 comedi_error(dev, 2337 "all elements in chanlist must use the same analog reference"); 2338 err++; 2339 break; 2340 } 2341 } 2342 /* check 4020 chanlist */ 2343 if (board(dev)->layout == LAYOUT_4020) { 2344 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]); 2345 for (i = 1; i < cmd->chanlist_len; i++) { 2346 if (CR_CHAN(cmd->chanlist[i]) != 2347 first_channel + i) { 2348 comedi_error(dev, 2349 "chanlist must use consecutive channels"); 2350 err++; 2351 break; 2352 } 2353 } 2354 if (cmd->chanlist_len == 3) { 2355 comedi_error(dev, 2356 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels"); 2357 err++; 2358 } 2359 } 2360 } 2361 2362 if (err) 2363 return 5; 2364 2365 return 0; 2366} 2367 2368static int use_hw_sample_counter(struct comedi_cmd *cmd) 2369{ 2370/* disable for now until I work out a race */ 2371 return 0; 2372 2373 if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value) 2374 return 1; 2375 else 2376 return 0; 2377} 2378 2379static void setup_sample_counters(struct comedi_device *dev, 2380 struct comedi_cmd *cmd) 2381{ 2382 if (cmd->stop_src == TRIG_COUNT) { 2383 /* set software count */ 2384 priv(dev)->ai_count = cmd->stop_arg * cmd->chanlist_len; 2385 } 2386 /* load hardware conversion counter */ 2387 if (use_hw_sample_counter(cmd)) { 2388 writew(cmd->stop_arg & 0xffff, 2389 priv(dev)->main_iobase + ADC_COUNT_LOWER_REG); 2390 writew((cmd->stop_arg >> 16) & 0xff, 2391 priv(dev)->main_iobase + ADC_COUNT_UPPER_REG); 2392 } else { 2393 writew(1, priv(dev)->main_iobase + ADC_COUNT_LOWER_REG); 2394 } 2395} 2396 2397static inline unsigned int dma_transfer_size(struct comedi_device *dev) 2398{ 2399 unsigned int num_samples; 2400 2401 num_samples = 2402 priv(dev)->ai_fifo_segment_length * 2403 board(dev)->ai_fifo->sample_packing_ratio; 2404 if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t)) 2405 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t); 2406 2407 return num_samples; 2408} 2409 2410static void disable_ai_pacing(struct comedi_device *dev) 2411{ 2412 unsigned long flags; 2413 2414 disable_ai_interrupts(dev); 2415 2416 spin_lock_irqsave(&dev->spinlock, flags); 2417 priv(dev)->adc_control1_bits &= ~ADC_SW_GATE_BIT; 2418 writew(priv(dev)->adc_control1_bits, 2419 priv(dev)->main_iobase + ADC_CONTROL1_REG); 2420 spin_unlock_irqrestore(&dev->spinlock, flags); 2421 2422 /* disable pacing, triggering, etc */ 2423 writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT, 2424 priv(dev)->main_iobase + ADC_CONTROL0_REG); 2425} 2426 2427static void disable_ai_interrupts(struct comedi_device *dev) 2428{ 2429 unsigned long flags; 2430 2431 spin_lock_irqsave(&dev->spinlock, flags); 2432 priv(dev)->intr_enable_bits &= 2433 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT & 2434 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT & 2435 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK; 2436 writew(priv(dev)->intr_enable_bits, 2437 priv(dev)->main_iobase + INTR_ENABLE_REG); 2438 spin_unlock_irqrestore(&dev->spinlock, flags); 2439 2440 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits); 2441} 2442 2443static void enable_ai_interrupts(struct comedi_device *dev, 2444 const struct comedi_cmd *cmd) 2445{ 2446 uint32_t bits; 2447 unsigned long flags; 2448 2449 bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT | 2450 EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT; 2451 /* Use pio transfer and interrupt on end of conversion if TRIG_WAKE_EOS flag is set. */ 2452 if (cmd->flags & TRIG_WAKE_EOS) { 2453 /* 4020 doesn't support pio transfers except for fifo dregs */ 2454 if (board(dev)->layout != LAYOUT_4020) 2455 bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT; 2456 } 2457 spin_lock_irqsave(&dev->spinlock, flags); 2458 priv(dev)->intr_enable_bits |= bits; 2459 writew(priv(dev)->intr_enable_bits, 2460 priv(dev)->main_iobase + INTR_ENABLE_REG); 2461 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits); 2462 spin_unlock_irqrestore(&dev->spinlock, flags); 2463} 2464 2465static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev, 2466 const struct comedi_cmd *cmd) 2467{ 2468 /* supposed to load counter with desired divisor minus 3 */ 2469 return cmd->convert_arg / TIMER_BASE - 3; 2470} 2471 2472static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev, 2473 struct comedi_cmd *cmd) 2474{ 2475 uint32_t count; 2476 /* figure out how long we need to delay at end of scan */ 2477 switch (cmd->scan_begin_src) { 2478 case TRIG_TIMER: 2479 count = (cmd->scan_begin_arg - 2480 (cmd->convert_arg * (cmd->chanlist_len - 1))) 2481 / TIMER_BASE; 2482 break; 2483 case TRIG_FOLLOW: 2484 count = cmd->convert_arg / TIMER_BASE; 2485 break; 2486 default: 2487 return 0; 2488 break; 2489 } 2490 return count - 3; 2491} 2492 2493static uint32_t ai_convert_counter_4020(struct comedi_device *dev, 2494 struct comedi_cmd *cmd) 2495{ 2496 unsigned int divisor; 2497 2498 switch (cmd->scan_begin_src) { 2499 case TRIG_TIMER: 2500 divisor = cmd->scan_begin_arg / TIMER_BASE; 2501 break; 2502 case TRIG_OTHER: 2503 divisor = priv(dev)->ext_clock.divisor; 2504 break; 2505 default: /* should never happen */ 2506 comedi_error(dev, "bug! failed to set ai pacing!"); 2507 divisor = 1000; 2508 break; 2509 } 2510 2511 /* supposed to load counter with desired divisor minus 2 for 4020 */ 2512 return divisor - 2; 2513} 2514 2515static void select_master_clock_4020(struct comedi_device *dev, 2516 const struct comedi_cmd *cmd) 2517{ 2518 /* select internal/external master clock */ 2519 priv(dev)->hw_config_bits &= ~MASTER_CLOCK_4020_MASK; 2520 if (cmd->scan_begin_src == TRIG_OTHER) { 2521 int chanspec = priv(dev)->ext_clock.chanspec; 2522 2523 if (CR_CHAN(chanspec)) 2524 priv(dev)->hw_config_bits |= BNC_CLOCK_4020_BITS; 2525 else 2526 priv(dev)->hw_config_bits |= EXT_CLOCK_4020_BITS; 2527 } else { 2528 priv(dev)->hw_config_bits |= INTERNAL_CLOCK_4020_BITS; 2529 } 2530 writew(priv(dev)->hw_config_bits, 2531 priv(dev)->main_iobase + HW_CONFIG_REG); 2532} 2533 2534static void select_master_clock(struct comedi_device *dev, 2535 const struct comedi_cmd *cmd) 2536{ 2537 switch (board(dev)->layout) { 2538 case LAYOUT_4020: 2539 select_master_clock_4020(dev, cmd); 2540 break; 2541 default: 2542 break; 2543 } 2544} 2545 2546static inline void dma_start_sync(struct comedi_device *dev, 2547 unsigned int channel) 2548{ 2549 unsigned long flags; 2550 2551 /* spinlock for plx dma control/status reg */ 2552 spin_lock_irqsave(&dev->spinlock, flags); 2553 if (channel) 2554 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | 2555 PLX_CLEAR_DMA_INTR_BIT, 2556 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG); 2557 else 2558 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | 2559 PLX_CLEAR_DMA_INTR_BIT, 2560 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 2561 spin_unlock_irqrestore(&dev->spinlock, flags); 2562} 2563 2564static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd) 2565{ 2566 uint32_t convert_counter = 0, scan_counter = 0; 2567 2568 check_adc_timing(dev, cmd); 2569 2570 select_master_clock(dev, cmd); 2571 2572 if (board(dev)->layout == LAYOUT_4020) { 2573 convert_counter = ai_convert_counter_4020(dev, cmd); 2574 } else { 2575 convert_counter = ai_convert_counter_6xxx(dev, cmd); 2576 scan_counter = ai_scan_counter_6xxx(dev, cmd); 2577 } 2578 2579 /* load lower 16 bits of convert interval */ 2580 writew(convert_counter & 0xffff, 2581 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG); 2582 DEBUG_PRINT("convert counter 0x%x\n", convert_counter); 2583 /* load upper 8 bits of convert interval */ 2584 writew((convert_counter >> 16) & 0xff, 2585 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); 2586 /* load lower 16 bits of scan delay */ 2587 writew(scan_counter & 0xffff, 2588 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG); 2589 /* load upper 8 bits of scan delay */ 2590 writew((scan_counter >> 16) & 0xff, 2591 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG); 2592 DEBUG_PRINT("scan counter 0x%x\n", scan_counter); 2593} 2594 2595static int use_internal_queue_6xxx(const struct comedi_cmd *cmd) 2596{ 2597 int i; 2598 for (i = 0; i + 1 < cmd->chanlist_len; i++) { 2599 if (CR_CHAN(cmd->chanlist[i + 1]) != 2600 CR_CHAN(cmd->chanlist[i]) + 1) 2601 return 0; 2602 if (CR_RANGE(cmd->chanlist[i + 1]) != 2603 CR_RANGE(cmd->chanlist[i])) 2604 return 0; 2605 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i])) 2606 return 0; 2607 } 2608 return 1; 2609} 2610 2611static int setup_channel_queue(struct comedi_device *dev, 2612 const struct comedi_cmd *cmd) 2613{ 2614 unsigned short bits; 2615 int i; 2616 2617 if (board(dev)->layout != LAYOUT_4020) { 2618 if (use_internal_queue_6xxx(cmd)) { 2619 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT; 2620 writew(priv(dev)->hw_config_bits, 2621 priv(dev)->main_iobase + HW_CONFIG_REG); 2622 bits = 0; 2623 /* set channel */ 2624 bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0])); 2625 /* set gain */ 2626 bits |= ai_range_bits_6xxx(dev, 2627 CR_RANGE(cmd->chanlist[0])); 2628 /* set single-ended / differential */ 2629 bits |= se_diff_bit_6xxx(dev, 2630 CR_AREF(cmd->chanlist[0]) == 2631 AREF_DIFF); 2632 if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON) 2633 bits |= ADC_COMMON_BIT; 2634 /* set stop channel */ 2635 writew(adc_chan_bits 2636 (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])), 2637 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG); 2638 /* set start channel, and rest of settings */ 2639 writew(bits, 2640 priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG); 2641 } else { 2642 /* use external queue */ 2643 if (dev->write_subdev && dev->write_subdev->busy) { 2644 warn_external_queue(dev); 2645 return -EBUSY; 2646 } 2647 priv(dev)->hw_config_bits |= EXT_QUEUE_BIT; 2648 writew(priv(dev)->hw_config_bits, 2649 priv(dev)->main_iobase + HW_CONFIG_REG); 2650 /* clear DAC buffer to prevent weird interactions */ 2651 writew(0, 2652 priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG); 2653 /* clear queue pointer */ 2654 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG); 2655 /* load external queue */ 2656 for (i = 0; i < cmd->chanlist_len; i++) { 2657 bits = 0; 2658 /* set channel */ 2659 bits |= 2660 adc_chan_bits(CR_CHAN(cmd->chanlist[i])); 2661 /* set gain */ 2662 bits |= ai_range_bits_6xxx(dev, 2663 CR_RANGE(cmd-> 2664 chanlist 2665 [i])); 2666 /* set single-ended / differential */ 2667 bits |= se_diff_bit_6xxx(dev, 2668 CR_AREF(cmd-> 2669 chanlist[i]) == 2670 AREF_DIFF); 2671 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON) 2672 bits |= ADC_COMMON_BIT; 2673 /* mark end of queue */ 2674 if (i == cmd->chanlist_len - 1) 2675 bits |= QUEUE_EOSCAN_BIT | 2676 QUEUE_EOSEQ_BIT; 2677 writew(bits, 2678 priv(dev)->main_iobase + 2679 ADC_QUEUE_FIFO_REG); 2680 DEBUG_PRINT 2681 ("wrote 0x%x to external channel queue\n", 2682 bits); 2683 } 2684 /* doing a queue clear is not specified in board docs, 2685 * but required for reliable operation */ 2686 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG); 2687 /* prime queue holding register */ 2688 writew(0, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG); 2689 } 2690 } else { 2691 unsigned short old_cal_range_bits = 2692 priv(dev)->i2c_cal_range_bits; 2693 2694 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK; 2695 /* select BNC inputs */ 2696 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4); 2697 /* select ranges */ 2698 for (i = 0; i < cmd->chanlist_len; i++) { 2699 unsigned int channel = CR_CHAN(cmd->chanlist[i]); 2700 unsigned int range = CR_RANGE(cmd->chanlist[i]); 2701 2702 if (range == 0) 2703 priv(dev)->i2c_cal_range_bits |= 2704 attenuate_bit(channel); 2705 else 2706 priv(dev)->i2c_cal_range_bits &= 2707 ~attenuate_bit(channel); 2708 } 2709 /* update calibration/range i2c register only if necessary, as it is very slow */ 2710 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) { 2711 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits; 2712 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data, 2713 sizeof(i2c_data)); 2714 } 2715 } 2716 return 0; 2717} 2718 2719static inline void load_first_dma_descriptor(struct comedi_device *dev, 2720 unsigned int dma_channel, 2721 unsigned int descriptor_bits) 2722{ 2723 /* The transfer size, pci address, and local address registers 2724 * are supposedly unused during chained dma, 2725 * but I have found that left over values from last operation 2726 * occasionally cause problems with transfer of first dma 2727 * block. Initializing them to zero seems to fix the problem. */ 2728 if (dma_channel) { 2729 writel(0, 2730 priv(dev)->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG); 2731 writel(0, priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG); 2732 writel(0, 2733 priv(dev)->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG); 2734 writel(descriptor_bits, 2735 priv(dev)->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG); 2736 } else { 2737 writel(0, 2738 priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG); 2739 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG); 2740 writel(0, 2741 priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG); 2742 writel(descriptor_bits, 2743 priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG); 2744 } 2745} 2746 2747static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 2748{ 2749 struct comedi_async *async = s->async; 2750 struct comedi_cmd *cmd = &async->cmd; 2751 uint32_t bits; 2752 unsigned int i; 2753 unsigned long flags; 2754 int retval; 2755 2756 disable_ai_pacing(dev); 2757 abort_dma(dev, 1); 2758 2759 retval = setup_channel_queue(dev, cmd); 2760 if (retval < 0) 2761 return retval; 2762 2763 /* make sure internal calibration source is turned off */ 2764 writew(0, priv(dev)->main_iobase + CALIBRATION_REG); 2765 2766 set_ai_pacing(dev, cmd); 2767 2768 setup_sample_counters(dev, cmd); 2769 2770 enable_ai_interrupts(dev, cmd); 2771 2772 spin_lock_irqsave(&dev->spinlock, flags); 2773 /* set mode, allow conversions through software gate */ 2774 priv(dev)->adc_control1_bits |= ADC_SW_GATE_BIT; 2775 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT; 2776 if (board(dev)->layout != LAYOUT_4020) { 2777 priv(dev)->adc_control1_bits &= ~ADC_MODE_MASK; 2778 if (cmd->convert_src == TRIG_EXT) 2779 priv(dev)->adc_control1_bits |= adc_mode_bits(13); /* good old mode 13 */ 2780 else 2781 priv(dev)->adc_control1_bits |= adc_mode_bits(8); /* mode 8. What else could you need? */ 2782 } else { 2783 priv(dev)->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK; 2784 if (cmd->chanlist_len == 4) 2785 priv(dev)->adc_control1_bits |= FOUR_CHANNEL_4020_BITS; 2786 else if (cmd->chanlist_len == 2) 2787 priv(dev)->adc_control1_bits |= TWO_CHANNEL_4020_BITS; 2788 priv(dev)->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK; 2789 priv(dev)->adc_control1_bits |= 2790 adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0])); 2791 priv(dev)->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK; 2792 priv(dev)->adc_control1_bits |= 2793 adc_hi_chan_4020_bits(CR_CHAN 2794 (cmd-> 2795 chanlist[cmd->chanlist_len - 1])); 2796 } 2797 writew(priv(dev)->adc_control1_bits, 2798 priv(dev)->main_iobase + ADC_CONTROL1_REG); 2799 DEBUG_PRINT("control1 bits 0x%x\n", priv(dev)->adc_control1_bits); 2800 spin_unlock_irqrestore(&dev->spinlock, flags); 2801 2802 /* clear adc buffer */ 2803 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG); 2804 2805 if ((cmd->flags & TRIG_WAKE_EOS) == 0 || 2806 board(dev)->layout == LAYOUT_4020) { 2807 priv(dev)->ai_dma_index = 0; 2808 2809 /* set dma transfer size */ 2810 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) 2811 priv(dev)->ai_dma_desc[i].transfer_size = 2812 cpu_to_le32(dma_transfer_size(dev) * 2813 sizeof(uint16_t)); 2814 2815 /* give location of first dma descriptor */ 2816 load_first_dma_descriptor(dev, 1, 2817 priv(dev)->ai_dma_desc_bus_addr | 2818 PLX_DESC_IN_PCI_BIT | 2819 PLX_INTR_TERM_COUNT | 2820 PLX_XFER_LOCAL_TO_PCI); 2821 2822 dma_start_sync(dev, 1); 2823 } 2824 2825 if (board(dev)->layout == LAYOUT_4020) { 2826 /* set source for external triggers */ 2827 bits = 0; 2828 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg)) 2829 bits |= EXT_START_TRIG_BNC_BIT; 2830 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg)) 2831 bits |= EXT_STOP_TRIG_BNC_BIT; 2832 writew(bits, priv(dev)->main_iobase + DAQ_ATRIG_LOW_4020_REG); 2833 } 2834 2835 spin_lock_irqsave(&dev->spinlock, flags); 2836 2837 /* enable pacing, triggering, etc */ 2838 bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT; 2839 if (cmd->flags & TRIG_WAKE_EOS) 2840 bits |= ADC_DMA_DISABLE_BIT; 2841 /* set start trigger */ 2842 if (cmd->start_src == TRIG_EXT) { 2843 bits |= ADC_START_TRIG_EXT_BITS; 2844 if (cmd->start_arg & CR_INVERT) 2845 bits |= ADC_START_TRIG_FALLING_BIT; 2846 } else if (cmd->start_src == TRIG_NOW) 2847 bits |= ADC_START_TRIG_SOFT_BITS; 2848 if (use_hw_sample_counter(cmd)) 2849 bits |= ADC_SAMPLE_COUNTER_EN_BIT; 2850 writew(bits, priv(dev)->main_iobase + ADC_CONTROL0_REG); 2851 DEBUG_PRINT("control0 bits 0x%x\n", bits); 2852 2853 priv(dev)->ai_cmd_running = 1; 2854 2855 spin_unlock_irqrestore(&dev->spinlock, flags); 2856 2857 /* start aquisition */ 2858 if (cmd->start_src == TRIG_NOW) { 2859 writew(0, priv(dev)->main_iobase + ADC_START_REG); 2860 DEBUG_PRINT("soft trig\n"); 2861 } 2862 2863 return 0; 2864} 2865 2866/* read num_samples from 16 bit wide ai fifo */ 2867static void pio_drain_ai_fifo_16(struct comedi_device *dev) 2868{ 2869 struct comedi_subdevice *s = dev->read_subdev; 2870 struct comedi_async *async = s->async; 2871 struct comedi_cmd *cmd = &async->cmd; 2872 unsigned int i; 2873 uint16_t prepost_bits; 2874 int read_segment, read_index, write_segment, write_index; 2875 int num_samples; 2876 2877 do { 2878 /* get least significant 15 bits */ 2879 read_index = 2880 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff; 2881 write_index = 2882 readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff; 2883 /* Get most significant bits (grey code). Different boards use different code 2884 * so use a scheme that doesn't depend on encoding. This read must 2885 * occur after reading least significant 15 bits to avoid race 2886 * with fifo switching to next segment. */ 2887 prepost_bits = readw(priv(dev)->main_iobase + PREPOST_REG); 2888 2889 /* if read and write pointers are not on the same fifo segment, read to the 2890 * end of the read segment */ 2891 read_segment = adc_upper_read_ptr_code(prepost_bits); 2892 write_segment = adc_upper_write_ptr_code(prepost_bits); 2893 2894 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n", 2895 read_segment, write_segment, read_index, 2896 write_index); 2897 2898 if (read_segment != write_segment) 2899 num_samples = 2900 priv(dev)->ai_fifo_segment_length - read_index; 2901 else 2902 num_samples = write_index - read_index; 2903 2904 if (cmd->stop_src == TRIG_COUNT) { 2905 if (priv(dev)->ai_count == 0) 2906 break; 2907 if (num_samples > priv(dev)->ai_count) 2908 num_samples = priv(dev)->ai_count; 2909 2910 priv(dev)->ai_count -= num_samples; 2911 } 2912 2913 if (num_samples < 0) { 2914 printk(" cb_pcidas64: bug! num_samples < 0\n"); 2915 break; 2916 } 2917 2918 DEBUG_PRINT(" read %i samples from fifo\n", num_samples); 2919 2920 for (i = 0; i < num_samples; i++) { 2921 cfc_write_to_buffer(s, 2922 readw(priv(dev)->main_iobase + 2923 ADC_FIFO_REG)); 2924 } 2925 2926 } while (read_segment != write_segment); 2927} 2928 2929/* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers. 2930 * The pci-4020 hardware only supports 2931 * dma transfers (it only supports the use of pio for draining the last remaining 2932 * points from the fifo when a data aquisition operation has completed). 2933 */ 2934static void pio_drain_ai_fifo_32(struct comedi_device *dev) 2935{ 2936 struct comedi_subdevice *s = dev->read_subdev; 2937 struct comedi_async *async = s->async; 2938 struct comedi_cmd *cmd = &async->cmd; 2939 unsigned int i; 2940 unsigned int max_transfer = 100000; 2941 uint32_t fifo_data; 2942 int write_code = 2943 readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff; 2944 int read_code = 2945 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff; 2946 2947 if (cmd->stop_src == TRIG_COUNT) { 2948 if (max_transfer > priv(dev)->ai_count) 2949 max_transfer = priv(dev)->ai_count; 2950 2951 } 2952 for (i = 0; read_code != write_code && i < max_transfer;) { 2953 fifo_data = readl(priv(dev)->dio_counter_iobase + ADC_FIFO_REG); 2954 cfc_write_to_buffer(s, fifo_data & 0xffff); 2955 i++; 2956 if (i < max_transfer) { 2957 cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff); 2958 i++; 2959 } 2960 read_code = 2961 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff; 2962 } 2963 priv(dev)->ai_count -= i; 2964} 2965 2966/* empty fifo */ 2967static void pio_drain_ai_fifo(struct comedi_device *dev) 2968{ 2969 if (board(dev)->layout == LAYOUT_4020) 2970 pio_drain_ai_fifo_32(dev); 2971 else 2972 pio_drain_ai_fifo_16(dev); 2973} 2974 2975static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel) 2976{ 2977 struct comedi_async *async = dev->read_subdev->async; 2978 uint32_t next_transfer_addr; 2979 int j; 2980 int num_samples = 0; 2981 void *pci_addr_reg; 2982 2983 if (channel) 2984 pci_addr_reg = 2985 priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG; 2986 else 2987 pci_addr_reg = 2988 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG; 2989 2990 /* loop until we have read all the full buffers */ 2991 for (j = 0, next_transfer_addr = readl(pci_addr_reg); 2992 (next_transfer_addr < 2993 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index] 2994 || next_transfer_addr >= 2995 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index] + 2996 DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board(dev)); j++) { 2997 /* transfer data from dma buffer to comedi buffer */ 2998 num_samples = dma_transfer_size(dev); 2999 if (async->cmd.stop_src == TRIG_COUNT) { 3000 if (num_samples > priv(dev)->ai_count) 3001 num_samples = priv(dev)->ai_count; 3002 priv(dev)->ai_count -= num_samples; 3003 } 3004 cfc_write_array_to_buffer(dev->read_subdev, 3005 priv(dev)->ai_buffer[priv(dev)-> 3006 ai_dma_index], 3007 num_samples * sizeof(uint16_t)); 3008 priv(dev)->ai_dma_index = 3009 (priv(dev)->ai_dma_index + 3010 1) % ai_dma_ring_count(board(dev)); 3011 3012 DEBUG_PRINT("next buffer addr 0x%lx\n", 3013 (unsigned long)priv(dev)-> 3014 ai_buffer_bus_addr[priv(dev)->ai_dma_index]); 3015 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr); 3016 } 3017 /* XXX check for dma ring buffer overrun (use end-of-chain bit to mark last 3018 * unused buffer) */ 3019} 3020 3021void handle_ai_interrupt(struct comedi_device *dev, unsigned short status, 3022 unsigned int plx_status) 3023{ 3024 struct comedi_subdevice *s = dev->read_subdev; 3025 struct comedi_async *async = s->async; 3026 struct comedi_cmd *cmd = &async->cmd; 3027 uint8_t dma1_status; 3028 unsigned long flags; 3029 3030 /* check for fifo overrun */ 3031 if (status & ADC_OVERRUN_BIT) { 3032 comedi_error(dev, "fifo overrun"); 3033 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 3034 } 3035 /* spin lock makes sure noone else changes plx dma control reg */ 3036 spin_lock_irqsave(&dev->spinlock, flags); 3037 dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG); 3038 if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */ 3039 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT, 3040 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG); 3041 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status); 3042 3043 if (dma1_status & PLX_DMA_EN_BIT) 3044 drain_dma_buffers(dev, 1); 3045 3046 DEBUG_PRINT(" cleared dma ch1 interrupt\n"); 3047 } 3048 spin_unlock_irqrestore(&dev->spinlock, flags); 3049 3050 if (status & ADC_DONE_BIT) 3051 DEBUG_PRINT("adc done interrupt\n"); 3052 3053 /* drain fifo with pio */ 3054 if ((status & ADC_DONE_BIT) || 3055 ((cmd->flags & TRIG_WAKE_EOS) && 3056 (status & ADC_INTR_PENDING_BIT) && 3057 (board(dev)->layout != LAYOUT_4020))) { 3058 DEBUG_PRINT("pio fifo drain\n"); 3059 spin_lock_irqsave(&dev->spinlock, flags); 3060 if (priv(dev)->ai_cmd_running) { 3061 spin_unlock_irqrestore(&dev->spinlock, flags); 3062 pio_drain_ai_fifo(dev); 3063 } else 3064 spin_unlock_irqrestore(&dev->spinlock, flags); 3065 } 3066 /* if we are have all the data, then quit */ 3067 if ((cmd->stop_src == TRIG_COUNT && priv(dev)->ai_count <= 0) || 3068 (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) { 3069 async->events |= COMEDI_CB_EOA; 3070 } 3071 3072 cfc_handle_events(dev, s); 3073} 3074 3075static inline unsigned int prev_ao_dma_index(struct comedi_device *dev) 3076{ 3077 unsigned int buffer_index; 3078 3079 if (priv(dev)->ao_dma_index == 0) 3080 buffer_index = AO_DMA_RING_COUNT - 1; 3081 else 3082 buffer_index = priv(dev)->ao_dma_index - 1; 3083 return buffer_index; 3084} 3085 3086static int last_ao_dma_load_completed(struct comedi_device *dev) 3087{ 3088 unsigned int buffer_index; 3089 unsigned int transfer_address; 3090 unsigned short dma_status; 3091 3092 buffer_index = prev_ao_dma_index(dev); 3093 dma_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 3094 if ((dma_status & PLX_DMA_DONE_BIT) == 0) 3095 return 0; 3096 3097 transfer_address = 3098 readl(priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG); 3099 if (transfer_address != priv(dev)->ao_buffer_bus_addr[buffer_index]) 3100 return 0; 3101 3102 return 1; 3103} 3104 3105static int ao_stopped_by_error(struct comedi_device *dev, 3106 const struct comedi_cmd *cmd) 3107{ 3108 if (cmd->stop_src == TRIG_NONE) 3109 return 1; 3110 if (cmd->stop_src == TRIG_COUNT) { 3111 if (priv(dev)->ao_count) 3112 return 1; 3113 if (last_ao_dma_load_completed(dev) == 0) 3114 return 1; 3115 } 3116 return 0; 3117} 3118 3119static inline int ao_dma_needs_restart(struct comedi_device *dev, 3120 unsigned short dma_status) 3121{ 3122 if ((dma_status & PLX_DMA_DONE_BIT) == 0 || 3123 (dma_status & PLX_DMA_EN_BIT) == 0) 3124 return 0; 3125 if (last_ao_dma_load_completed(dev)) 3126 return 0; 3127 3128 return 1; 3129} 3130 3131static void restart_ao_dma(struct comedi_device *dev) 3132{ 3133 unsigned int dma_desc_bits; 3134 3135 dma_desc_bits = 3136 readl(priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG); 3137 dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT; 3138 DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits); 3139 load_first_dma_descriptor(dev, 0, dma_desc_bits); 3140 3141 dma_start_sync(dev, 0); 3142} 3143 3144static void handle_ao_interrupt(struct comedi_device *dev, 3145 unsigned short status, unsigned int plx_status) 3146{ 3147 struct comedi_subdevice *s = dev->write_subdev; 3148 struct comedi_async *async; 3149 struct comedi_cmd *cmd; 3150 uint8_t dma0_status; 3151 unsigned long flags; 3152 3153 /* board might not support ao, in which case write_subdev is NULL */ 3154 if (s == NULL) 3155 return; 3156 async = s->async; 3157 cmd = &async->cmd; 3158 3159 /* spin lock makes sure noone else changes plx dma control reg */ 3160 spin_lock_irqsave(&dev->spinlock, flags); 3161 dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 3162 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */ 3163 if ((dma0_status & PLX_DMA_EN_BIT) 3164 && !(dma0_status & PLX_DMA_DONE_BIT)) 3165 writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT, 3166 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 3167 else 3168 writeb(PLX_CLEAR_DMA_INTR_BIT, 3169 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 3170 spin_unlock_irqrestore(&dev->spinlock, flags); 3171 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status); 3172 if (dma0_status & PLX_DMA_EN_BIT) { 3173 load_ao_dma(dev, cmd); 3174 /* try to recover from dma end-of-chain event */ 3175 if (ao_dma_needs_restart(dev, dma0_status)) 3176 restart_ao_dma(dev); 3177 } 3178 DEBUG_PRINT(" cleared dma ch0 interrupt\n"); 3179 } else 3180 spin_unlock_irqrestore(&dev->spinlock, flags); 3181 3182 if ((status & DAC_DONE_BIT)) { 3183 async->events |= COMEDI_CB_EOA; 3184 if (ao_stopped_by_error(dev, cmd)) 3185 async->events |= COMEDI_CB_ERROR; 3186 DEBUG_PRINT("plx dma0 desc reg 0x%x\n", 3187 readl(priv(dev)->plx9080_iobase + 3188 PLX_DMA0_DESCRIPTOR_REG)); 3189 DEBUG_PRINT("plx dma0 address reg 0x%x\n", 3190 readl(priv(dev)->plx9080_iobase + 3191 PLX_DMA0_PCI_ADDRESS_REG)); 3192 } 3193 cfc_handle_events(dev, s); 3194} 3195 3196static irqreturn_t handle_interrupt(int irq, void *d) 3197{ 3198 struct comedi_device *dev = d; 3199 unsigned short status; 3200 uint32_t plx_status; 3201 uint32_t plx_bits; 3202 3203 plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG); 3204 status = readw(priv(dev)->main_iobase + HW_STATUS_REG); 3205 3206 DEBUG_PRINT("cb_pcidas64: hw status 0x%x ", status); 3207 DEBUG_PRINT("plx status 0x%x\n", plx_status); 3208 3209 /* an interrupt before all the postconfig stuff gets done could 3210 * cause a NULL dereference if we continue through the 3211 * interrupt handler */ 3212 if (dev->attached == 0) { 3213 DEBUG_PRINT("cb_pcidas64: premature interrupt, ignoring", 3214 status); 3215 return IRQ_HANDLED; 3216 } 3217 handle_ai_interrupt(dev, status, plx_status); 3218 handle_ao_interrupt(dev, status, plx_status); 3219 3220 /* clear possible plx9080 interrupt sources */ 3221 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */ 3222 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG); 3223 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG); 3224 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits); 3225 } 3226 3227 DEBUG_PRINT("exiting handler\n"); 3228 3229 return IRQ_HANDLED; 3230} 3231 3232void abort_dma(struct comedi_device *dev, unsigned int channel) 3233{ 3234 unsigned long flags; 3235 3236 /* spinlock for plx dma control/status reg */ 3237 spin_lock_irqsave(&dev->spinlock, flags); 3238 3239 plx9080_abort_dma(priv(dev)->plx9080_iobase, channel); 3240 3241 spin_unlock_irqrestore(&dev->spinlock, flags); 3242} 3243 3244static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 3245{ 3246 unsigned long flags; 3247 3248 spin_lock_irqsave(&dev->spinlock, flags); 3249 if (priv(dev)->ai_cmd_running == 0) { 3250 spin_unlock_irqrestore(&dev->spinlock, flags); 3251 return 0; 3252 } 3253 priv(dev)->ai_cmd_running = 0; 3254 spin_unlock_irqrestore(&dev->spinlock, flags); 3255 3256 disable_ai_pacing(dev); 3257 3258 abort_dma(dev, 1); 3259 3260 DEBUG_PRINT("ai canceled\n"); 3261 return 0; 3262} 3263 3264static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 3265 struct comedi_insn *insn, unsigned int *data) 3266{ 3267 int chan = CR_CHAN(insn->chanspec); 3268 int range = CR_RANGE(insn->chanspec); 3269 3270 /* do some initializing */ 3271 writew(0, priv(dev)->main_iobase + DAC_CONTROL0_REG); 3272 3273 /* set range */ 3274 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, chan, range); 3275 writew(priv(dev)->dac_control1_bits, 3276 priv(dev)->main_iobase + DAC_CONTROL1_REG); 3277 3278 /* write to channel */ 3279 if (board(dev)->layout == LAYOUT_4020) { 3280 writew(data[0] & 0xff, 3281 priv(dev)->main_iobase + dac_lsb_4020_reg(chan)); 3282 writew((data[0] >> 8) & 0xf, 3283 priv(dev)->main_iobase + dac_msb_4020_reg(chan)); 3284 } else { 3285 writew(data[0], priv(dev)->main_iobase + dac_convert_reg(chan)); 3286 } 3287 3288 /* remember output value */ 3289 priv(dev)->ao_value[chan] = data[0]; 3290 3291 return 1; 3292} 3293 3294static int ao_readback_insn(struct comedi_device *dev, 3295 struct comedi_subdevice *s, 3296 struct comedi_insn *insn, unsigned int *data) 3297{ 3298 data[0] = priv(dev)->ao_value[CR_CHAN(insn->chanspec)]; 3299 3300 return 1; 3301} 3302 3303static void set_dac_control0_reg(struct comedi_device *dev, 3304 const struct comedi_cmd *cmd) 3305{ 3306 unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT | 3307 WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT; 3308 3309 if (cmd->start_src == TRIG_EXT) { 3310 bits |= WAVEFORM_TRIG_EXT_BITS; 3311 if (cmd->start_arg & CR_INVERT) 3312 bits |= WAVEFORM_TRIG_FALLING_BIT; 3313 } else { 3314 bits |= WAVEFORM_TRIG_SOFT_BITS; 3315 } 3316 if (cmd->scan_begin_src == TRIG_EXT) { 3317 bits |= DAC_EXT_UPDATE_ENABLE_BIT; 3318 if (cmd->scan_begin_arg & CR_INVERT) 3319 bits |= DAC_EXT_UPDATE_FALLING_BIT; 3320 } 3321 writew(bits, priv(dev)->main_iobase + DAC_CONTROL0_REG); 3322} 3323 3324static void set_dac_control1_reg(struct comedi_device *dev, 3325 const struct comedi_cmd *cmd) 3326{ 3327 int i; 3328 3329 for (i = 0; i < cmd->chanlist_len; i++) { 3330 int channel, range; 3331 3332 channel = CR_CHAN(cmd->chanlist[i]); 3333 range = CR_RANGE(cmd->chanlist[i]); 3334 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, channel, 3335 range); 3336 } 3337 priv(dev)->dac_control1_bits |= DAC_SW_GATE_BIT; 3338 writew(priv(dev)->dac_control1_bits, 3339 priv(dev)->main_iobase + DAC_CONTROL1_REG); 3340} 3341 3342static void set_dac_select_reg(struct comedi_device *dev, 3343 const struct comedi_cmd *cmd) 3344{ 3345 uint16_t bits; 3346 unsigned int first_channel, last_channel; 3347 3348 first_channel = CR_CHAN(cmd->chanlist[0]); 3349 last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); 3350 if (last_channel < first_channel) 3351 comedi_error(dev, "bug! last ao channel < first ao channel"); 3352 3353 bits = (first_channel & 0x7) | (last_channel & 0x7) << 3; 3354 3355 writew(bits, priv(dev)->main_iobase + DAC_SELECT_REG); 3356} 3357 3358static void set_dac_interval_regs(struct comedi_device *dev, 3359 const struct comedi_cmd *cmd) 3360{ 3361 unsigned int divisor; 3362 3363 if (cmd->scan_begin_src != TRIG_TIMER) 3364 return; 3365 3366 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags); 3367 if (divisor > max_counter_value) { 3368 comedi_error(dev, "bug! ao divisor too big"); 3369 divisor = max_counter_value; 3370 } 3371 writew(divisor & 0xffff, 3372 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG); 3373 writew((divisor >> 16) & 0xff, 3374 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG); 3375} 3376 3377static unsigned int load_ao_dma_buffer(struct comedi_device *dev, 3378 const struct comedi_cmd *cmd) 3379{ 3380 unsigned int num_bytes, buffer_index, prev_buffer_index; 3381 unsigned int next_bits; 3382 3383 buffer_index = priv(dev)->ao_dma_index; 3384 prev_buffer_index = prev_ao_dma_index(dev); 3385 3386 DEBUG_PRINT("attempting to load ao buffer %i (0x%x)\n", buffer_index, 3387 priv(dev)->ao_buffer_bus_addr[buffer_index]); 3388 3389 num_bytes = comedi_buf_read_n_available(dev->write_subdev->async); 3390 if (num_bytes > DMA_BUFFER_SIZE) 3391 num_bytes = DMA_BUFFER_SIZE; 3392 if (cmd->stop_src == TRIG_COUNT && num_bytes > priv(dev)->ao_count) 3393 num_bytes = priv(dev)->ao_count; 3394 num_bytes -= num_bytes % bytes_in_sample; 3395 3396 if (num_bytes == 0) 3397 return 0; 3398 3399 DEBUG_PRINT("loading %i bytes\n", num_bytes); 3400 3401 num_bytes = cfc_read_array_from_buffer(dev->write_subdev, 3402 priv(dev)-> 3403 ao_buffer[buffer_index], 3404 num_bytes); 3405 priv(dev)->ao_dma_desc[buffer_index].transfer_size = 3406 cpu_to_le32(num_bytes); 3407 /* set end of chain bit so we catch underruns */ 3408 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[buffer_index].next); 3409 next_bits |= PLX_END_OF_CHAIN_BIT; 3410 priv(dev)->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits); 3411 /* clear end of chain bit on previous buffer now that we have set it 3412 * for the last buffer */ 3413 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[prev_buffer_index].next); 3414 next_bits &= ~PLX_END_OF_CHAIN_BIT; 3415 priv(dev)->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits); 3416 3417 priv(dev)->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT; 3418 priv(dev)->ao_count -= num_bytes; 3419 3420 return num_bytes; 3421} 3422 3423static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd) 3424{ 3425 unsigned int num_bytes; 3426 unsigned int next_transfer_addr; 3427 void *pci_addr_reg = 3428 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG; 3429 unsigned int buffer_index; 3430 3431 do { 3432 buffer_index = priv(dev)->ao_dma_index; 3433 /* don't overwrite data that hasn't been transferred yet */ 3434 next_transfer_addr = readl(pci_addr_reg); 3435 if (next_transfer_addr >= 3436 priv(dev)->ao_buffer_bus_addr[buffer_index] 3437 && next_transfer_addr < 3438 priv(dev)->ao_buffer_bus_addr[buffer_index] + 3439 DMA_BUFFER_SIZE) 3440 return; 3441 num_bytes = load_ao_dma_buffer(dev, cmd); 3442 } while (num_bytes >= DMA_BUFFER_SIZE); 3443} 3444 3445static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd) 3446{ 3447 unsigned int num_bytes; 3448 int i; 3449 3450 /* clear queue pointer too, since external queue has 3451 * weird interactions with ao fifo */ 3452 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG); 3453 writew(0, priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG); 3454 3455 num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample; 3456 if (cmd->stop_src == TRIG_COUNT && 3457 num_bytes / bytes_in_sample > priv(dev)->ao_count) 3458 num_bytes = priv(dev)->ao_count * bytes_in_sample; 3459 num_bytes = cfc_read_array_from_buffer(dev->write_subdev, 3460 priv(dev)->ao_bounce_buffer, 3461 num_bytes); 3462 for (i = 0; i < num_bytes / bytes_in_sample; i++) { 3463 writew(priv(dev)->ao_bounce_buffer[i], 3464 priv(dev)->main_iobase + DAC_FIFO_REG); 3465 } 3466 priv(dev)->ao_count -= num_bytes / bytes_in_sample; 3467 if (cmd->stop_src == TRIG_COUNT && priv(dev)->ao_count == 0) 3468 return 0; 3469 num_bytes = load_ao_dma_buffer(dev, cmd); 3470 if (num_bytes == 0) 3471 return -1; 3472 if (num_bytes >= DMA_BUFFER_SIZE) ; 3473 load_ao_dma(dev, cmd); 3474 3475 dma_start_sync(dev, 0); 3476 3477 return 0; 3478} 3479 3480static inline int external_ai_queue_in_use(struct comedi_device *dev) 3481{ 3482 if (dev->read_subdev->busy) 3483 return 0; 3484 if (board(dev)->layout == LAYOUT_4020) 3485 return 0; 3486 else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd)) 3487 return 0; 3488 return 1; 3489} 3490 3491static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 3492{ 3493 struct comedi_cmd *cmd = &s->async->cmd; 3494 3495 if (external_ai_queue_in_use(dev)) { 3496 warn_external_queue(dev); 3497 return -EBUSY; 3498 } 3499 /* disable analog output system during setup */ 3500 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG); 3501 3502 priv(dev)->ao_dma_index = 0; 3503 priv(dev)->ao_count = cmd->stop_arg * cmd->chanlist_len; 3504 3505 set_dac_select_reg(dev, cmd); 3506 set_dac_interval_regs(dev, cmd); 3507 load_first_dma_descriptor(dev, 0, priv(dev)->ao_dma_desc_bus_addr | 3508 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT); 3509 3510 set_dac_control1_reg(dev, cmd); 3511 s->async->inttrig = ao_inttrig; 3512 3513 return 0; 3514} 3515 3516static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 3517 unsigned int trig_num) 3518{ 3519 struct comedi_cmd *cmd = &s->async->cmd; 3520 int retval; 3521 3522 if (trig_num != 0) 3523 return -EINVAL; 3524 3525 retval = prep_ao_dma(dev, cmd); 3526 if (retval < 0) 3527 return -EPIPE; 3528 3529 set_dac_control0_reg(dev, cmd); 3530 3531 if (cmd->start_src == TRIG_INT) 3532 writew(0, priv(dev)->main_iobase + DAC_START_REG); 3533 3534 s->async->inttrig = NULL; 3535 3536 return 0; 3537} 3538 3539static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 3540 struct comedi_cmd *cmd) 3541{ 3542 int err = 0; 3543 int tmp; 3544 unsigned int tmp_arg; 3545 int i; 3546 3547 /* step 1: make sure trigger sources are trivially valid */ 3548 3549 tmp = cmd->start_src; 3550 cmd->start_src &= TRIG_INT | TRIG_EXT; 3551 if (!cmd->start_src || tmp != cmd->start_src) 3552 err++; 3553 3554 tmp = cmd->scan_begin_src; 3555 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; 3556 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 3557 err++; 3558 3559 tmp = cmd->convert_src; 3560 cmd->convert_src &= TRIG_NOW; 3561 if (!cmd->convert_src || tmp != cmd->convert_src) 3562 err++; 3563 3564 tmp = cmd->scan_end_src; 3565 cmd->scan_end_src &= TRIG_COUNT; 3566 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 3567 err++; 3568 3569 tmp = cmd->stop_src; 3570 cmd->stop_src &= TRIG_NONE; 3571 if (!cmd->stop_src || tmp != cmd->stop_src) 3572 err++; 3573 3574 if (err) 3575 return 1; 3576 3577 /* step 2: make sure trigger sources are unique and mutually compatible */ 3578 3579 /* uniqueness check */ 3580 if (cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT) 3581 err++; 3582 if (cmd->scan_begin_src != TRIG_TIMER && 3583 cmd->scan_begin_src != TRIG_EXT) 3584 err++; 3585 3586 /* compatibility check */ 3587 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER) 3588 err++; 3589 if (cmd->stop_src != TRIG_COUNT && 3590 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT) 3591 err++; 3592 3593 if (err) 3594 return 2; 3595 3596 /* step 3: make sure arguments are trivially compatible */ 3597 3598 if (cmd->scan_begin_src == TRIG_TIMER) { 3599 if (cmd->scan_begin_arg < board(dev)->ao_scan_speed) { 3600 cmd->scan_begin_arg = board(dev)->ao_scan_speed; 3601 err++; 3602 } 3603 if (get_ao_divisor(cmd->scan_begin_arg, 3604 cmd->flags) > max_counter_value) { 3605 cmd->scan_begin_arg = 3606 (max_counter_value + 2) * TIMER_BASE; 3607 err++; 3608 } 3609 } 3610 3611 if (!cmd->chanlist_len) { 3612 cmd->chanlist_len = 1; 3613 err++; 3614 } 3615 if (cmd->scan_end_arg != cmd->chanlist_len) { 3616 cmd->scan_end_arg = cmd->chanlist_len; 3617 err++; 3618 } 3619 3620 if (err) 3621 return 3; 3622 3623 /* step 4: fix up any arguments */ 3624 3625 if (cmd->scan_begin_src == TRIG_TIMER) { 3626 tmp_arg = cmd->scan_begin_arg; 3627 cmd->scan_begin_arg = 3628 get_divisor(cmd->scan_begin_arg, cmd->flags) * TIMER_BASE; 3629 if (tmp_arg != cmd->scan_begin_arg) 3630 err++; 3631 } 3632 3633 if (err) 3634 return 4; 3635 3636 if (cmd->chanlist) { 3637 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]); 3638 for (i = 1; i < cmd->chanlist_len; i++) { 3639 if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) { 3640 comedi_error(dev, 3641 "chanlist must use consecutive channels"); 3642 err++; 3643 break; 3644 } 3645 } 3646 } 3647 3648 if (err) 3649 return 5; 3650 3651 return 0; 3652} 3653 3654static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 3655{ 3656 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG); 3657 abort_dma(dev, 0); 3658 return 0; 3659} 3660 3661static int dio_callback(int dir, int port, int data, unsigned long iobase) 3662{ 3663 if (dir) { 3664 writeb(data, (void *)(iobase + port)); 3665 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port); 3666 return 0; 3667 } else { 3668 return readb((void *)(iobase + port)); 3669 } 3670} 3671 3672static int dio_callback_4020(int dir, int port, int data, unsigned long iobase) 3673{ 3674 if (dir) { 3675 writew(data, (void *)(iobase + 2 * port)); 3676 return 0; 3677 } else { 3678 return readw((void *)(iobase + 2 * port)); 3679 } 3680} 3681 3682static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s, 3683 struct comedi_insn *insn, unsigned int *data) 3684{ 3685 unsigned int bits; 3686 3687 bits = readb(priv(dev)->dio_counter_iobase + DI_REG); 3688 bits &= 0xf; 3689 data[1] = bits; 3690 data[0] = 0; 3691 3692 return 2; 3693} 3694 3695static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s, 3696 struct comedi_insn *insn, unsigned int *data) 3697{ 3698 data[0] &= 0xf; 3699 /* zero bits we are going to change */ 3700 s->state &= ~data[0]; 3701 /* set new bits */ 3702 s->state |= data[0] & data[1]; 3703 3704 writeb(s->state, priv(dev)->dio_counter_iobase + DO_REG); 3705 3706 data[1] = s->state; 3707 3708 return 2; 3709} 3710 3711static int dio_60xx_config_insn(struct comedi_device *dev, 3712 struct comedi_subdevice *s, 3713 struct comedi_insn *insn, unsigned int *data) 3714{ 3715 unsigned int mask; 3716 3717 mask = 1 << CR_CHAN(insn->chanspec); 3718 3719 switch (data[0]) { 3720 case INSN_CONFIG_DIO_INPUT: 3721 s->io_bits &= ~mask; 3722 break; 3723 case INSN_CONFIG_DIO_OUTPUT: 3724 s->io_bits |= mask; 3725 break; 3726 case INSN_CONFIG_DIO_QUERY: 3727 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT; 3728 return 2; 3729 default: 3730 return -EINVAL; 3731 } 3732 3733 writeb(s->io_bits, 3734 priv(dev)->dio_counter_iobase + DIO_DIRECTION_60XX_REG); 3735 3736 return 1; 3737} 3738 3739static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s, 3740 struct comedi_insn *insn, unsigned int *data) 3741{ 3742 if (data[0]) { 3743 s->state &= ~data[0]; 3744 s->state |= (data[0] & data[1]); 3745 writeb(s->state, 3746 priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG); 3747 } 3748 3749 data[1] = readb(priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG); 3750 3751 return 2; 3752} 3753 3754static void caldac_write(struct comedi_device *dev, unsigned int channel, 3755 unsigned int value) 3756{ 3757 priv(dev)->caldac_state[channel] = value; 3758 3759 switch (board(dev)->layout) { 3760 case LAYOUT_60XX: 3761 case LAYOUT_64XX: 3762 caldac_8800_write(dev, channel, value); 3763 break; 3764 case LAYOUT_4020: 3765 caldac_i2c_write(dev, channel, value); 3766 break; 3767 default: 3768 break; 3769 } 3770} 3771 3772static int calib_write_insn(struct comedi_device *dev, 3773 struct comedi_subdevice *s, 3774 struct comedi_insn *insn, unsigned int *data) 3775{ 3776 int channel = CR_CHAN(insn->chanspec); 3777 3778 /* return immediately if setting hasn't changed, since 3779 * programming these things is slow */ 3780 if (priv(dev)->caldac_state[channel] == data[0]) 3781 return 1; 3782 3783 caldac_write(dev, channel, data[0]); 3784 3785 return 1; 3786} 3787 3788static int calib_read_insn(struct comedi_device *dev, 3789 struct comedi_subdevice *s, struct comedi_insn *insn, 3790 unsigned int *data) 3791{ 3792 unsigned int channel = CR_CHAN(insn->chanspec); 3793 3794 data[0] = priv(dev)->caldac_state[channel]; 3795 3796 return 1; 3797} 3798 3799static void ad8402_write(struct comedi_device *dev, unsigned int channel, 3800 unsigned int value) 3801{ 3802 static const int bitstream_length = 10; 3803 unsigned int bit, register_bits; 3804 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff); 3805 static const int ad8402_udelay = 1; 3806 3807 priv(dev)->ad8402_state[channel] = value; 3808 3809 register_bits = SELECT_8402_64XX_BIT; 3810 udelay(ad8402_udelay); 3811 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG); 3812 3813 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { 3814 if (bitstream & bit) 3815 register_bits |= SERIAL_DATA_IN_BIT; 3816 else 3817 register_bits &= ~SERIAL_DATA_IN_BIT; 3818 udelay(ad8402_udelay); 3819 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG); 3820 udelay(ad8402_udelay); 3821 writew(register_bits | SERIAL_CLOCK_BIT, 3822 priv(dev)->main_iobase + CALIBRATION_REG); 3823 } 3824 3825 udelay(ad8402_udelay); 3826 writew(0, priv(dev)->main_iobase + CALIBRATION_REG); 3827} 3828 3829/* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */ 3830static int ad8402_write_insn(struct comedi_device *dev, 3831 struct comedi_subdevice *s, 3832 struct comedi_insn *insn, unsigned int *data) 3833{ 3834 int channel = CR_CHAN(insn->chanspec); 3835 3836 /* return immediately if setting hasn't changed, since 3837 * programming these things is slow */ 3838 if (priv(dev)->ad8402_state[channel] == data[0]) 3839 return 1; 3840 3841 priv(dev)->ad8402_state[channel] = data[0]; 3842 3843 ad8402_write(dev, channel, data[0]); 3844 3845 return 1; 3846} 3847 3848static int ad8402_read_insn(struct comedi_device *dev, 3849 struct comedi_subdevice *s, 3850 struct comedi_insn *insn, unsigned int *data) 3851{ 3852 unsigned int channel = CR_CHAN(insn->chanspec); 3853 3854 data[0] = priv(dev)->ad8402_state[channel]; 3855 3856 return 1; 3857} 3858 3859static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) 3860{ 3861 static const int bitstream_length = 11; 3862 static const int read_command = 0x6; 3863 unsigned int bitstream = (read_command << 8) | address; 3864 unsigned int bit; 3865 void *const plx_control_addr = 3866 priv(dev)->plx9080_iobase + PLX_CONTROL_REG; 3867 uint16_t value; 3868 static const int value_length = 16; 3869 static const int eeprom_udelay = 1; 3870 3871 udelay(eeprom_udelay); 3872 priv(dev)->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS; 3873 /* make sure we don't send anything to the i2c bus on 4020 */ 3874 priv(dev)->plx_control_bits |= CTL_USERO; 3875 writel(priv(dev)->plx_control_bits, plx_control_addr); 3876 /* activate serial eeprom */ 3877 udelay(eeprom_udelay); 3878 priv(dev)->plx_control_bits |= CTL_EE_CS; 3879 writel(priv(dev)->plx_control_bits, plx_control_addr); 3880 3881 /* write read command and desired memory address */ 3882 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { 3883 /* set bit to be written */ 3884 udelay(eeprom_udelay); 3885 if (bitstream & bit) 3886 priv(dev)->plx_control_bits |= CTL_EE_W; 3887 else 3888 priv(dev)->plx_control_bits &= ~CTL_EE_W; 3889 writel(priv(dev)->plx_control_bits, plx_control_addr); 3890 /* clock in bit */ 3891 udelay(eeprom_udelay); 3892 priv(dev)->plx_control_bits |= CTL_EE_CLK; 3893 writel(priv(dev)->plx_control_bits, plx_control_addr); 3894 udelay(eeprom_udelay); 3895 priv(dev)->plx_control_bits &= ~CTL_EE_CLK; 3896 writel(priv(dev)->plx_control_bits, plx_control_addr); 3897 } 3898 /* read back value from eeprom memory location */ 3899 value = 0; 3900 for (bit = 1 << (value_length - 1); bit; bit >>= 1) { 3901 /* clock out bit */ 3902 udelay(eeprom_udelay); 3903 priv(dev)->plx_control_bits |= CTL_EE_CLK; 3904 writel(priv(dev)->plx_control_bits, plx_control_addr); 3905 udelay(eeprom_udelay); 3906 priv(dev)->plx_control_bits &= ~CTL_EE_CLK; 3907 writel(priv(dev)->plx_control_bits, plx_control_addr); 3908 udelay(eeprom_udelay); 3909 if (readl(plx_control_addr) & CTL_EE_R) 3910 value |= bit; 3911 } 3912 3913 /* deactivate eeprom serial input */ 3914 udelay(eeprom_udelay); 3915 priv(dev)->plx_control_bits &= ~CTL_EE_CS; 3916 writel(priv(dev)->plx_control_bits, plx_control_addr); 3917 3918 return value; 3919} 3920 3921static int eeprom_read_insn(struct comedi_device *dev, 3922 struct comedi_subdevice *s, 3923 struct comedi_insn *insn, unsigned int *data) 3924{ 3925 data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec)); 3926 3927 return 1; 3928} 3929 3930/* utility function that rounds desired timing to an achievable time, and 3931 * sets cmd members appropriately. 3932 * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number 3933 */ 3934static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) 3935{ 3936 unsigned int convert_divisor = 0, scan_divisor; 3937 static const int min_convert_divisor = 3; 3938 static const int max_convert_divisor = 3939 max_counter_value + min_convert_divisor; 3940 static const int min_scan_divisor_4020 = 2; 3941 unsigned long long max_scan_divisor, min_scan_divisor; 3942 3943 if (cmd->convert_src == TRIG_TIMER) { 3944 if (board(dev)->layout == LAYOUT_4020) { 3945 cmd->convert_arg = 0; 3946 } else { 3947 convert_divisor = 3948 get_divisor(cmd->convert_arg, cmd->flags); 3949 if (convert_divisor > max_convert_divisor) 3950 convert_divisor = max_convert_divisor; 3951 if (convert_divisor < min_convert_divisor) 3952 convert_divisor = min_convert_divisor; 3953 cmd->convert_arg = convert_divisor * TIMER_BASE; 3954 } 3955 } else if (cmd->convert_src == TRIG_NOW) 3956 cmd->convert_arg = 0; 3957 3958 if (cmd->scan_begin_src == TRIG_TIMER) { 3959 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags); 3960 if (cmd->convert_src == TRIG_TIMER) { 3961 /* XXX check for integer overflows */ 3962 min_scan_divisor = convert_divisor * cmd->chanlist_len; 3963 max_scan_divisor = 3964 (convert_divisor * cmd->chanlist_len - 1) + 3965 max_counter_value; 3966 } else { 3967 min_scan_divisor = min_scan_divisor_4020; 3968 max_scan_divisor = max_counter_value + min_scan_divisor; 3969 } 3970 if (scan_divisor > max_scan_divisor) 3971 scan_divisor = max_scan_divisor; 3972 if (scan_divisor < min_scan_divisor) 3973 scan_divisor = min_scan_divisor; 3974 cmd->scan_begin_arg = scan_divisor * TIMER_BASE; 3975 } 3976 3977 return; 3978} 3979 3980/* Gets nearest achievable timing given master clock speed, does not 3981 * take into account possible minimum/maximum divisor values. Used 3982 * by other timing checking functions. */ 3983static unsigned int get_divisor(unsigned int ns, unsigned int flags) 3984{ 3985 unsigned int divisor; 3986 3987 switch (flags & TRIG_ROUND_MASK) { 3988 case TRIG_ROUND_UP: 3989 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE; 3990 break; 3991 case TRIG_ROUND_DOWN: 3992 divisor = ns / TIMER_BASE; 3993 break; 3994 case TRIG_ROUND_NEAREST: 3995 default: 3996 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE; 3997 break; 3998 } 3999 return divisor; 4000} 4001 4002static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags) 4003{ 4004 return get_divisor(ns, flags) - 2; 4005} 4006 4007/* adjusts the size of hardware fifo (which determines block size for dma xfers) */ 4008static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples) 4009{ 4010 unsigned int num_fifo_entries; 4011 int retval; 4012 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo; 4013 4014 num_fifo_entries = num_samples / fifo->sample_packing_ratio; 4015 4016 retval = set_ai_fifo_segment_length(dev, 4017 num_fifo_entries / 4018 fifo->num_segments); 4019 if (retval < 0) 4020 return retval; 4021 4022 num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio; 4023 4024 DEBUG_PRINT("set hardware fifo size to %i\n", num_samples); 4025 4026 return num_samples; 4027} 4028 4029/* query length of fifo */ 4030static unsigned int ai_fifo_size(struct comedi_device *dev) 4031{ 4032 return priv(dev)->ai_fifo_segment_length * 4033 board(dev)->ai_fifo->num_segments * 4034 board(dev)->ai_fifo->sample_packing_ratio; 4035} 4036 4037static int set_ai_fifo_segment_length(struct comedi_device *dev, 4038 unsigned int num_entries) 4039{ 4040 static const int increment_size = 0x100; 4041 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo; 4042 unsigned int num_increments; 4043 uint16_t bits; 4044 4045 if (num_entries < increment_size) 4046 num_entries = increment_size; 4047 if (num_entries > fifo->max_segment_length) 4048 num_entries = fifo->max_segment_length; 4049 4050 /* 1 == 256 entries, 2 == 512 entries, etc */ 4051 num_increments = (num_entries + increment_size / 2) / increment_size; 4052 4053 bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask; 4054 priv(dev)->fifo_size_bits &= ~fifo->fifo_size_reg_mask; 4055 priv(dev)->fifo_size_bits |= bits; 4056 writew(priv(dev)->fifo_size_bits, 4057 priv(dev)->main_iobase + FIFO_SIZE_REG); 4058 4059 priv(dev)->ai_fifo_segment_length = num_increments * increment_size; 4060 4061 DEBUG_PRINT("set hardware fifo segment length to %i\n", 4062 priv(dev)->ai_fifo_segment_length); 4063 4064 return priv(dev)->ai_fifo_segment_length; 4065} 4066 4067/* pci-6025 8800 caldac: 4068 * address 0 == dac channel 0 offset 4069 * address 1 == dac channel 0 gain 4070 * address 2 == dac channel 1 offset 4071 * address 3 == dac channel 1 gain 4072 * address 4 == fine adc offset 4073 * address 5 == coarse adc offset 4074 * address 6 == coarse adc gain 4075 * address 7 == fine adc gain 4076 */ 4077/* pci-6402/16 uses all 8 channels for dac: 4078 * address 0 == dac channel 0 fine gain 4079 * address 1 == dac channel 0 coarse gain 4080 * address 2 == dac channel 0 coarse offset 4081 * address 3 == dac channel 1 coarse offset 4082 * address 4 == dac channel 1 fine gain 4083 * address 5 == dac channel 1 coarse gain 4084 * address 6 == dac channel 0 fine offset 4085 * address 7 == dac channel 1 fine offset 4086*/ 4087 4088static int caldac_8800_write(struct comedi_device *dev, unsigned int address, 4089 uint8_t value) 4090{ 4091 static const int num_caldac_channels = 8; 4092 static const int bitstream_length = 11; 4093 unsigned int bitstream = ((address & 0x7) << 8) | value; 4094 unsigned int bit, register_bits; 4095 static const int caldac_8800_udelay = 1; 4096 4097 if (address >= num_caldac_channels) { 4098 comedi_error(dev, "illegal caldac channel"); 4099 return -1; 4100 } 4101 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { 4102 register_bits = 0; 4103 if (bitstream & bit) 4104 register_bits |= SERIAL_DATA_IN_BIT; 4105 udelay(caldac_8800_udelay); 4106 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG); 4107 register_bits |= SERIAL_CLOCK_BIT; 4108 udelay(caldac_8800_udelay); 4109 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG); 4110 } 4111 udelay(caldac_8800_udelay); 4112 writew(SELECT_8800_BIT, priv(dev)->main_iobase + CALIBRATION_REG); 4113 udelay(caldac_8800_udelay); 4114 writew(0, priv(dev)->main_iobase + CALIBRATION_REG); 4115 udelay(caldac_8800_udelay); 4116 return 0; 4117} 4118 4119/* 4020 caldacs */ 4120static int caldac_i2c_write(struct comedi_device *dev, 4121 unsigned int caldac_channel, unsigned int value) 4122{ 4123 uint8_t serial_bytes[3]; 4124 uint8_t i2c_addr; 4125 enum pointer_bits { 4126 /* manual has gain and offset bits switched */ 4127 OFFSET_0_2 = 0x1, 4128 GAIN_0_2 = 0x2, 4129 OFFSET_1_3 = 0x4, 4130 GAIN_1_3 = 0x8, 4131 }; 4132 enum data_bits { 4133 NOT_CLEAR_REGISTERS = 0x20, 4134 }; 4135 4136 switch (caldac_channel) { 4137 case 0: /* chan 0 offset */ 4138 i2c_addr = CALDAC0_I2C_ADDR; 4139 serial_bytes[0] = OFFSET_0_2; 4140 break; 4141 case 1: /* chan 1 offset */ 4142 i2c_addr = CALDAC0_I2C_ADDR; 4143 serial_bytes[0] = OFFSET_1_3; 4144 break; 4145 case 2: /* chan 2 offset */ 4146 i2c_addr = CALDAC1_I2C_ADDR; 4147 serial_bytes[0] = OFFSET_0_2; 4148 break; 4149 case 3: /* chan 3 offset */ 4150 i2c_addr = CALDAC1_I2C_ADDR; 4151 serial_bytes[0] = OFFSET_1_3; 4152 break; 4153 case 4: /* chan 0 gain */ 4154 i2c_addr = CALDAC0_I2C_ADDR; 4155 serial_bytes[0] = GAIN_0_2; 4156 break; 4157 case 5: /* chan 1 gain */ 4158 i2c_addr = CALDAC0_I2C_ADDR; 4159 serial_bytes[0] = GAIN_1_3; 4160 break; 4161 case 6: /* chan 2 gain */ 4162 i2c_addr = CALDAC1_I2C_ADDR; 4163 serial_bytes[0] = GAIN_0_2; 4164 break; 4165 case 7: /* chan 3 gain */ 4166 i2c_addr = CALDAC1_I2C_ADDR; 4167 serial_bytes[0] = GAIN_1_3; 4168 break; 4169 default: 4170 comedi_error(dev, "invalid caldac channel\n"); 4171 return -1; 4172 break; 4173 } 4174 serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf); 4175 serial_bytes[2] = value & 0xff; 4176 i2c_write(dev, i2c_addr, serial_bytes, 3); 4177 return 0; 4178} 4179 4180/* Their i2c requires a huge delay on setting clock or data high for some reason */ 4181static const int i2c_high_udelay = 1000; 4182static const int i2c_low_udelay = 10; 4183 4184/* set i2c data line high or low */ 4185static void i2c_set_sda(struct comedi_device *dev, int state) 4186{ 4187 static const int data_bit = CTL_EE_W; 4188 void *plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG; 4189 4190 if (state) { 4191 /* set data line high */ 4192 priv(dev)->plx_control_bits &= ~data_bit; 4193 writel(priv(dev)->plx_control_bits, plx_control_addr); 4194 udelay(i2c_high_udelay); 4195 } else { /* set data line low */ 4196 4197 priv(dev)->plx_control_bits |= data_bit; 4198 writel(priv(dev)->plx_control_bits, plx_control_addr); 4199 udelay(i2c_low_udelay); 4200 } 4201} 4202 4203/* set i2c clock line high or low */ 4204static void i2c_set_scl(struct comedi_device *dev, int state) 4205{ 4206 static const int clock_bit = CTL_USERO; 4207 void *plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG; 4208 4209 if (state) { 4210 /* set clock line high */ 4211 priv(dev)->plx_control_bits &= ~clock_bit; 4212 writel(priv(dev)->plx_control_bits, plx_control_addr); 4213 udelay(i2c_high_udelay); 4214 } else { /* set clock line low */ 4215 4216 priv(dev)->plx_control_bits |= clock_bit; 4217 writel(priv(dev)->plx_control_bits, plx_control_addr); 4218 udelay(i2c_low_udelay); 4219 } 4220} 4221 4222static void i2c_write_byte(struct comedi_device *dev, uint8_t byte) 4223{ 4224 uint8_t bit; 4225 unsigned int num_bits = 8; 4226 4227 DEBUG_PRINT("writing to i2c byte 0x%x\n", byte); 4228 4229 for (bit = 1 << (num_bits - 1); bit; bit >>= 1) { 4230 i2c_set_scl(dev, 0); 4231 if ((byte & bit)) 4232 i2c_set_sda(dev, 1); 4233 else 4234 i2c_set_sda(dev, 0); 4235 i2c_set_scl(dev, 1); 4236 } 4237} 4238 4239/* we can't really read the lines, so fake it */ 4240static int i2c_read_ack(struct comedi_device *dev) 4241{ 4242 i2c_set_scl(dev, 0); 4243 i2c_set_sda(dev, 1); 4244 i2c_set_scl(dev, 1); 4245 4246 return 0; /* return fake acknowledge bit */ 4247} 4248 4249/* send start bit */ 4250static void i2c_start(struct comedi_device *dev) 4251{ 4252 i2c_set_scl(dev, 1); 4253 i2c_set_sda(dev, 1); 4254 i2c_set_sda(dev, 0); 4255} 4256 4257/* send stop bit */ 4258static void i2c_stop(struct comedi_device *dev) 4259{ 4260 i2c_set_scl(dev, 0); 4261 i2c_set_sda(dev, 0); 4262 i2c_set_scl(dev, 1); 4263 i2c_set_sda(dev, 1); 4264} 4265 4266static void i2c_write(struct comedi_device *dev, unsigned int address, 4267 const uint8_t * data, unsigned int length) 4268{ 4269 unsigned int i; 4270 uint8_t bitstream; 4271 static const int read_bit = 0x1; 4272 4273/* XXX need mutex to prevent simultaneous attempts to access eeprom and i2c bus */ 4274 4275 /* make sure we dont send anything to eeprom */ 4276 priv(dev)->plx_control_bits &= ~CTL_EE_CS; 4277 4278 i2c_stop(dev); 4279 i2c_start(dev); 4280 4281 /* send address and write bit */ 4282 bitstream = (address << 1) & ~read_bit; 4283 i2c_write_byte(dev, bitstream); 4284 4285 /* get acknowledge */ 4286 if (i2c_read_ack(dev) != 0) { 4287 comedi_error(dev, "i2c write failed: no acknowledge"); 4288 i2c_stop(dev); 4289 return; 4290 } 4291 /* write data bytes */ 4292 for (i = 0; i < length; i++) { 4293 i2c_write_byte(dev, data[i]); 4294 if (i2c_read_ack(dev) != 0) { 4295 comedi_error(dev, "i2c write failed: no acknowledge"); 4296 i2c_stop(dev); 4297 return; 4298 } 4299 } 4300 i2c_stop(dev); 4301} 4302