cb_pcidas64.c revision d78678dad325b40258b8d38cf90b24e66d1e52e8
1/* 2 comedi/drivers/cb_pcidas64.c 3 This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS 4 64xx, 60xx, and 4020 cards. 5 6 Author: Frank Mori Hess <fmhess@users.sourceforge.net> 7 Copyright (C) 2001, 2002 Frank Mori Hess 8 9 Thanks also go to the following people: 10 11 Steve Rosenbluth, for providing the source code for 12 his pci-das6402 driver, and source code for working QNX pci-6402 13 drivers by Greg Laird and Mariusz Bogacz. None of the code was 14 used directly here, but it was useful as an additional source of 15 documentation on how to program the boards. 16 17 John Sims, for much testing and feedback on pcidas-4020 support. 18 19 COMEDI - Linux Control and Measurement Device Interface 20 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> 21 22 This program is free software; you can redistribute it and/or modify 23 it under the terms of the GNU General Public License as published by 24 the Free Software Foundation; either version 2 of the License, or 25 (at your option) any later version. 26 27 This program is distributed in the hope that it will be useful, 28 but WITHOUT ANY WARRANTY; without even the implied warranty of 29 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 GNU General Public License for more details. 31 32 You should have received a copy of the GNU General Public License 33 along with this program; if not, write to the Free Software 34 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 35 36************************************************************************/ 37 38/* 39 40Driver: cb_pcidas64 41Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series with the PLX 9080 PCI controller 42Author: Frank Mori Hess <fmhess@users.sourceforge.net> 43Status: works 44Updated: 2002-10-09 45Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64), 46 PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16, 47 PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR, 48 PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14, 49 PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014, 50 PCI-DAS6023, PCI-DAS6025, PCI-DAS6030, 51 PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034, 52 PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052, 53 PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12 54 55Configuration options: 56 [0] - PCI bus of device (optional) 57 [1] - PCI slot of device (optional) 58 59These boards may be autocalibrated with the comedi_calibrate utility. 60 61To select the bnc trigger input on the 4020 (instead of the dio input), 62specify a nonzero channel in the chanspec. If you wish to use an external 63master clock on the 4020, you may do so by setting the scan_begin_src 64to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn 65to configure the divisor to use for the external clock. 66 67Some devices are not identified because the PCI device IDs are not yet 68known. If you have such a board, please file a bug report at 69https://bugs.comedi.org. 70 71*/ 72 73/* 74 75TODO: 76 make it return error if user attempts an ai command that uses the 77 external queue, and an ao command simultaneously 78 user counter subdevice 79 there are a number of boards this driver will support when they are 80 fully released, but does not yet since the pci device id numbers 81 are not yet available. 82 support prescaled 100khz clock for slow pacing (not available on 6000 series?) 83 make ao fifo size adjustable like ai fifo 84*/ 85 86#include "../comedidev.h" 87#include <linux/delay.h> 88#include <linux/interrupt.h> 89#include <asm/system.h> 90 91#include "comedi_pci.h" 92#include "8253.h" 93#include "8255.h" 94#include "plx9080.h" 95#include "comedi_fc.h" 96 97#undef PCIDAS64_DEBUG /* disable debugging code */ 98/* #define PCIDAS64_DEBUG enable debugging code */ 99 100#ifdef PCIDAS64_DEBUG 101#define DEBUG_PRINT(format, args...) printk(format , ## args) 102#else 103#define DEBUG_PRINT(format, args...) 104#endif 105 106#define TIMER_BASE 25 /* 40MHz master clock */ 107#define PRESCALED_TIMER_BASE 10000 /* 100kHz 'prescaled' clock for slow acquisition, maybe I'll support this someday */ 108#define DMA_BUFFER_SIZE 0x1000 109 110#define PCI_VENDOR_ID_COMPUTERBOARDS 0x1307 111 112/* maximum value that can be loaded into board's 24-bit counters*/ 113static const int max_counter_value = 0xffffff; 114 115/* PCI-DAS64xxx base addresses */ 116 117/* indices of base address regions */ 118enum base_address_regions { 119 PLX9080_BADDRINDEX = 0, 120 MAIN_BADDRINDEX = 2, 121 DIO_COUNTER_BADDRINDEX = 3, 122}; 123 124/* priv(dev)->main_iobase registers */ 125enum write_only_registers { 126 INTR_ENABLE_REG = 0x0, /* interrupt enable register */ 127 HW_CONFIG_REG = 0x2, /* hardware config register */ 128 DAQ_SYNC_REG = 0xc, 129 DAQ_ATRIG_LOW_4020_REG = 0xc, 130 ADC_CONTROL0_REG = 0x10, /* adc control register 0 */ 131 ADC_CONTROL1_REG = 0x12, /* adc control register 1 */ 132 CALIBRATION_REG = 0x14, 133 ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16, /* lower 16 bits of adc sample interval counter */ 134 ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18, /* upper 8 bits of adc sample interval counter */ 135 ADC_DELAY_INTERVAL_LOWER_REG = 0x1a, /* lower 16 bits of delay interval counter */ 136 ADC_DELAY_INTERVAL_UPPER_REG = 0x1c, /* upper 8 bits of delay interval counter */ 137 ADC_COUNT_LOWER_REG = 0x1e, /* lower 16 bits of hardware conversion/scan counter */ 138 ADC_COUNT_UPPER_REG = 0x20, /* upper 8 bits of hardware conversion/scan counter */ 139 ADC_START_REG = 0x22, /* software trigger to start acquisition */ 140 ADC_CONVERT_REG = 0x24, /* initiates single conversion */ 141 ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */ 142 ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */ 143 ADC_BUFFER_CLEAR_REG = 0x2a, 144 ADC_QUEUE_HIGH_REG = 0x2c, /* high channel for internal queue, use adc_chan_bits() inline above */ 145 DAC_CONTROL0_REG = 0x50, /* dac control register 0 */ 146 DAC_CONTROL1_REG = 0x52, /* dac control register 0 */ 147 DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54, /* lower 16 bits of dac sample interval counter */ 148 DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56, /* upper 8 bits of dac sample interval counter */ 149 DAC_SELECT_REG = 0x60, 150 DAC_START_REG = 0x64, 151 DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */ 152}; 153static inline unsigned int dac_convert_reg(unsigned int channel) 154{ 155 return 0x70 + (2 * (channel & 0x1)); 156} 157 158static inline unsigned int dac_lsb_4020_reg(unsigned int channel) 159{ 160 return 0x70 + (4 * (channel & 0x1)); 161} 162 163static inline unsigned int dac_msb_4020_reg(unsigned int channel) 164{ 165 return 0x72 + (4 * (channel & 0x1)); 166} 167 168enum read_only_registers { 169 HW_STATUS_REG = 0x0, /* hardware status register, reading this apparently clears pending interrupts as well */ 170 PIPE1_READ_REG = 0x4, 171 ADC_READ_PNTR_REG = 0x8, 172 LOWER_XFER_REG = 0x10, 173 ADC_WRITE_PNTR_REG = 0xc, 174 PREPOST_REG = 0x14, 175}; 176 177enum read_write_registers { 178 I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */ 179 ADC_QUEUE_FIFO_REG = 0x100, /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */ 180 ADC_FIFO_REG = 0x200, /* adc data fifo */ 181 DAC_FIFO_REG = 0x300, /* dac data fifo, has weird interactions with external channel queue */ 182}; 183 184/* priv(dev)->dio_counter_iobase registers */ 185enum dio_counter_registers { 186 DIO_8255_OFFSET = 0x0, 187 DO_REG = 0x20, 188 DI_REG = 0x28, 189 DIO_DIRECTION_60XX_REG = 0x40, 190 DIO_DATA_60XX_REG = 0x48, 191}; 192 193/* bit definitions for write-only registers */ 194 195enum intr_enable_contents { 196 ADC_INTR_SRC_MASK = 0x3, /* bits that set adc interrupt source */ 197 ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quater full */ 198 ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */ 199 ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */ 200 ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence (probably wont use this it's pretty fancy) */ 201 EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */ 202 EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done interrupt */ 203 DAC_INTR_SRC_MASK = 0x30, 204 DAC_INTR_QEMPTY_BITS = 0x0, 205 DAC_INTR_HIGH_CHAN_BITS = 0x10, 206 EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */ 207 EN_DAC_DONE_INTR_BIT = 0x80, 208 EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */ 209 EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */ 210 EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */ 211 EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */ 212 EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */ 213}; 214 215enum hw_config_contents { 216 MASTER_CLOCK_4020_MASK = 0x3, /* bits that specify master clock source for 4020 */ 217 INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock for 4020 */ 218 BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */ 219 EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */ 220 EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue (more versatile than internal queue) */ 221 SLOW_DAC_BIT = 0x400, /* use 225 nanosec strobe when loading dac instead of 50 nanosec */ 222 HW_CONFIG_DUMMY_BITS = 0x2000, /* bit with unknown function yet given as default value in pci-das64 manual */ 223 DMA_CH_SELECT_BIT = 0x8000, /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */ 224 FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */ 225 DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */ 226 DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */ 227}; 228#define DAC_FIFO_SIZE 0x2000 229 230enum daq_atrig_low_4020_contents { 231 EXT_AGATE_BNC_BIT = 0x8000, /* use trig/ext clk bnc input for analog gate signal */ 232 EXT_STOP_TRIG_BNC_BIT = 0x4000, /* use trig/ext clk bnc input for external stop trigger signal */ 233 EXT_START_TRIG_BNC_BIT = 0x2000, /* use trig/ext clk bnc input for external start trigger signal */ 234}; 235static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold) 236{ 237 return threshold & 0xfff; 238} 239 240enum adc_control0_contents { 241 ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */ 242 ADC_SOFT_GATE_BITS = 0x1, /* software gate */ 243 ADC_EXT_GATE_BITS = 0x2, /* external digital gate */ 244 ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */ 245 ADC_GATE_LEVEL_BIT = 0x4, /* level-sensitive gate (for digital) */ 246 ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */ 247 ADC_START_TRIG_SOFT_BITS = 0x10, 248 ADC_START_TRIG_EXT_BITS = 0x20, 249 ADC_START_TRIG_ANALOG_BITS = 0x30, 250 ADC_START_TRIG_MASK = 0x30, 251 ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */ 252 ADC_EXT_CONV_FALLING_BIT = 0x800, /* external pacing uses falling edge */ 253 ADC_SAMPLE_COUNTER_EN_BIT = 0x1000, /* enable hardware scan counter */ 254 ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */ 255 ADC_ENABLE_BIT = 0x8000, /* master adc enable */ 256}; 257 258enum adc_control1_contents { 259 ADC_QUEUE_CONFIG_BIT = 0x1, /* should be set for boards with > 16 channels */ 260 CONVERT_POLARITY_BIT = 0x10, 261 EOC_POLARITY_BIT = 0x20, 262 ADC_SW_GATE_BIT = 0x40, /* software gate of adc */ 263 ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */ 264 RETRIGGER_BIT = 0x800, 265 ADC_LO_CHANNEL_4020_MASK = 0x300, 266 ADC_HI_CHANNEL_4020_MASK = 0xc00, 267 TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */ 268 FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */ 269 CHANNEL_MODE_4020_MASK = 0x3000, 270 ADC_MODE_MASK = 0xf000, 271}; 272static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel) 273{ 274 return (channel & 0x3) << 8; 275}; 276 277static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel) 278{ 279 return (channel & 0x3) << 10; 280}; 281 282static inline uint16_t adc_mode_bits(unsigned int mode) 283{ 284 return (mode & 0xf) << 12; 285}; 286 287enum calibration_contents { 288 SELECT_8800_BIT = 0x1, 289 SELECT_8402_64XX_BIT = 0x2, 290 SELECT_1590_60XX_BIT = 0x2, 291 CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */ 292 SERIAL_DATA_IN_BIT = 0x80, 293 SERIAL_CLOCK_BIT = 0x100, 294 CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */ 295 CAL_GAIN_BIT = 0x800, 296}; 297/* calibration sources for 6025 are: 298 * 0 : ground 299 * 1 : 10V 300 * 2 : 5V 301 * 3 : 0.5V 302 * 4 : 0.05V 303 * 5 : ground 304 * 6 : dac channel 0 305 * 7 : dac channel 1 306 */ 307static inline uint16_t adc_src_bits(unsigned int source) 308{ 309 return (source & 0xf) << 3; 310}; 311 312static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel) 313{ 314 return (channel & 0x3) << 8; 315}; 316 317enum adc_queue_load_contents { 318 UNIP_BIT = 0x800, /* unipolar/bipolar bit */ 319 ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */ 320 ADC_COMMON_BIT = 0x2000, /* non-referenced single-ended (common-mode input) */ 321 QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */ 322 QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */ 323}; 324static inline uint16_t adc_chan_bits(unsigned int channel) 325{ 326 return channel & 0x3f; 327}; 328 329enum dac_control0_contents { 330 DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */ 331 DAC_CYCLIC_STOP_BIT = 0x4000, 332 DAC_WAVEFORM_MODE_BIT = 0x100, 333 DAC_EXT_UPDATE_FALLING_BIT = 0x80, 334 DAC_EXT_UPDATE_ENABLE_BIT = 0x40, 335 WAVEFORM_TRIG_MASK = 0x30, 336 WAVEFORM_TRIG_DISABLED_BITS = 0x0, 337 WAVEFORM_TRIG_SOFT_BITS = 0x10, 338 WAVEFORM_TRIG_EXT_BITS = 0x20, 339 WAVEFORM_TRIG_ADC1_BITS = 0x30, 340 WAVEFORM_TRIG_FALLING_BIT = 0x8, 341 WAVEFORM_GATE_LEVEL_BIT = 0x4, 342 WAVEFORM_GATE_ENABLE_BIT = 0x2, 343 WAVEFORM_GATE_SELECT_BIT = 0x1, 344}; 345 346enum dac_control1_contents { 347 DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */ 348 DAC1_EXT_REF_BIT = 0x200, 349 DAC0_EXT_REF_BIT = 0x100, 350 DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */ 351 DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */ 352 DAC_SW_GATE_BIT = 0x20, 353 DAC1_UNIPOLAR_BIT = 0x8, 354 DAC0_UNIPOLAR_BIT = 0x2, 355}; 356 357/* bit definitions for read-only registers */ 358enum hw_status_contents { 359 DAC_UNDERRUN_BIT = 0x1, 360 ADC_OVERRUN_BIT = 0x2, 361 DAC_ACTIVE_BIT = 0x4, 362 ADC_ACTIVE_BIT = 0x8, 363 DAC_INTR_PENDING_BIT = 0x10, 364 ADC_INTR_PENDING_BIT = 0x20, 365 DAC_DONE_BIT = 0x40, 366 ADC_DONE_BIT = 0x80, 367 EXT_INTR_PENDING_BIT = 0x100, 368 ADC_STOP_BIT = 0x200, 369}; 370static inline uint16_t pipe_full_bits(uint16_t hw_status_bits) 371{ 372 return (hw_status_bits >> 10) & 0x3; 373}; 374 375static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits) 376{ 377 return (prepost_bits >> 6) & 0x3; 378} 379 380static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits) 381{ 382 return (prepost_bits >> 12) & 0x3; 383} 384 385static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits) 386{ 387 return (prepost_bits >> 14) & 0x3; 388} 389 390/* I2C addresses for 4020 */ 391enum i2c_addresses { 392 RANGE_CAL_I2C_ADDR = 0x20, 393 CALDAC0_I2C_ADDR = 0xc, 394 CALDAC1_I2C_ADDR = 0xd, 395}; 396 397enum range_cal_i2c_contents { 398 ADC_SRC_4020_MASK = 0x70, /* bits that set what source the adc converter measures */ 399 BNC_TRIG_THRESHOLD_0V_BIT = 0x80, /* make bnc trig/ext clock threshold 0V instead of 2.5V */ 400}; 401static inline uint8_t adc_src_4020_bits(unsigned int source) 402{ 403 return (source << 4) & ADC_SRC_4020_MASK; 404}; 405 406static inline uint8_t attenuate_bit(unsigned int channel) 407{ 408 /* attenuate channel (+-5V input range) */ 409 return 1 << (channel & 0x3); 410}; 411 412/* analog input ranges for 64xx boards */ 413static const struct comedi_lrange ai_ranges_64xx = { 414 8, 415 { 416 BIP_RANGE(10), 417 BIP_RANGE(5), 418 BIP_RANGE(2.5), 419 BIP_RANGE(1.25), 420 UNI_RANGE(10), 421 UNI_RANGE(5), 422 UNI_RANGE(2.5), 423 UNI_RANGE(1.25) 424 } 425}; 426 427/* analog input ranges for 60xx boards */ 428static const struct comedi_lrange ai_ranges_60xx = { 429 4, 430 { 431 BIP_RANGE(10), 432 BIP_RANGE(5), 433 BIP_RANGE(0.5), 434 BIP_RANGE(0.05), 435 } 436}; 437 438/* analog input ranges for 6030, etc boards */ 439static const struct comedi_lrange ai_ranges_6030 = { 440 14, 441 { 442 BIP_RANGE(10), 443 BIP_RANGE(5), 444 BIP_RANGE(2), 445 BIP_RANGE(1), 446 BIP_RANGE(0.5), 447 BIP_RANGE(0.2), 448 BIP_RANGE(0.1), 449 UNI_RANGE(10), 450 UNI_RANGE(5), 451 UNI_RANGE(2), 452 UNI_RANGE(1), 453 UNI_RANGE(0.5), 454 UNI_RANGE(0.2), 455 UNI_RANGE(0.1), 456 } 457}; 458 459/* analog input ranges for 6052, etc boards */ 460static const struct comedi_lrange ai_ranges_6052 = { 461 15, 462 { 463 BIP_RANGE(10), 464 BIP_RANGE(5), 465 BIP_RANGE(2.5), 466 BIP_RANGE(1), 467 BIP_RANGE(0.5), 468 BIP_RANGE(0.25), 469 BIP_RANGE(0.1), 470 BIP_RANGE(0.05), 471 UNI_RANGE(10), 472 UNI_RANGE(5), 473 UNI_RANGE(2), 474 UNI_RANGE(1), 475 UNI_RANGE(0.5), 476 UNI_RANGE(0.2), 477 UNI_RANGE(0.1), 478 } 479}; 480 481/* analog input ranges for 4020 board */ 482static const struct comedi_lrange ai_ranges_4020 = { 483 2, 484 { 485 BIP_RANGE(5), 486 BIP_RANGE(1), 487 } 488}; 489 490/* analog output ranges */ 491static const struct comedi_lrange ao_ranges_64xx = { 492 4, 493 { 494 BIP_RANGE(5), 495 BIP_RANGE(10), 496 UNI_RANGE(5), 497 UNI_RANGE(10), 498 } 499}; 500 501static const int ao_range_code_64xx[] = { 502 0x0, 503 0x1, 504 0x2, 505 0x3, 506}; 507 508static const struct comedi_lrange ao_ranges_60xx = { 509 1, 510 { 511 BIP_RANGE(10), 512 } 513}; 514 515static const int ao_range_code_60xx[] = { 516 0x0, 517}; 518 519static const struct comedi_lrange ao_ranges_6030 = { 520 2, 521 { 522 BIP_RANGE(10), 523 UNI_RANGE(10), 524 } 525}; 526 527static const int ao_range_code_6030[] = { 528 0x0, 529 0x2, 530}; 531 532static const struct comedi_lrange ao_ranges_4020 = { 533 2, 534 { 535 BIP_RANGE(5), 536 BIP_RANGE(10), 537 } 538}; 539 540static const int ao_range_code_4020[] = { 541 0x1, 542 0x0, 543}; 544 545enum register_layout { 546 LAYOUT_60XX, 547 LAYOUT_64XX, 548 LAYOUT_4020, 549}; 550 551struct hw_fifo_info { 552 unsigned int num_segments; 553 unsigned int max_segment_length; 554 unsigned int sample_packing_ratio; 555 uint16_t fifo_size_reg_mask; 556}; 557 558struct pcidas64_board { 559 const char *name; 560 int device_id; /* pci device id */ 561 int ai_se_chans; /* number of ai inputs in single-ended mode */ 562 int ai_bits; /* analog input resolution */ 563 int ai_speed; /* fastest conversion period in ns */ 564 const struct comedi_lrange *ai_range_table; 565 int ao_nchan; /* number of analog out channels */ 566 int ao_bits; /* analog output resolution */ 567 int ao_scan_speed; /* analog output speed (for a scan, not conversion) */ 568 const struct comedi_lrange *ao_range_table; 569 const int *ao_range_code; 570 const struct hw_fifo_info *const ai_fifo; 571 enum register_layout layout; /* different board families have slightly different registers */ 572 unsigned has_8255:1; 573}; 574 575static const struct hw_fifo_info ai_fifo_4020 = { 576 .num_segments = 2, 577 .max_segment_length = 0x8000, 578 .sample_packing_ratio = 2, 579 .fifo_size_reg_mask = 0x7f, 580}; 581 582static const struct hw_fifo_info ai_fifo_64xx = { 583 .num_segments = 4, 584 .max_segment_length = 0x800, 585 .sample_packing_ratio = 1, 586 .fifo_size_reg_mask = 0x3f, 587}; 588 589static const struct hw_fifo_info ai_fifo_60xx = { 590 .num_segments = 4, 591 .max_segment_length = 0x800, 592 .sample_packing_ratio = 1, 593 .fifo_size_reg_mask = 0x7f, 594}; 595 596/* maximum number of dma transfers we will chain together into a ring 597 * (and the maximum number of dma buffers we maintain) */ 598#define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE) 599#define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE) 600#define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE) 601static inline unsigned int ai_dma_ring_count(struct pcidas64_board *board) 602{ 603 if (board->layout == LAYOUT_4020) 604 return MAX_AI_DMA_RING_COUNT; 605 else 606 return MIN_AI_DMA_RING_COUNT; 607} 608 609static const int bytes_in_sample = 2; 610 611static const struct pcidas64_board pcidas64_boards[] = { 612 { 613 .name = "pci-das6402/16", 614 .device_id = 0x1d, 615 .ai_se_chans = 64, 616 .ai_bits = 16, 617 .ai_speed = 5000, 618 .ao_nchan = 2, 619 .ao_bits = 16, 620 .ao_scan_speed = 10000, 621 .layout = LAYOUT_64XX, 622 .ai_range_table = &ai_ranges_64xx, 623 .ao_range_table = &ao_ranges_64xx, 624 .ao_range_code = ao_range_code_64xx, 625 .ai_fifo = &ai_fifo_64xx, 626 .has_8255 = 1, 627 }, 628 { 629 .name = "pci-das6402/12", /* XXX check */ 630 .device_id = 0x1e, 631 .ai_se_chans = 64, 632 .ai_bits = 12, 633 .ai_speed = 5000, 634 .ao_nchan = 2, 635 .ao_bits = 12, 636 .ao_scan_speed = 10000, 637 .layout = LAYOUT_64XX, 638 .ai_range_table = &ai_ranges_64xx, 639 .ao_range_table = &ao_ranges_64xx, 640 .ao_range_code = ao_range_code_64xx, 641 .ai_fifo = &ai_fifo_64xx, 642 .has_8255 = 1, 643 }, 644 { 645 .name = "pci-das64/m1/16", 646 .device_id = 0x35, 647 .ai_se_chans = 64, 648 .ai_bits = 16, 649 .ai_speed = 1000, 650 .ao_nchan = 2, 651 .ao_bits = 16, 652 .ao_scan_speed = 10000, 653 .layout = LAYOUT_64XX, 654 .ai_range_table = &ai_ranges_64xx, 655 .ao_range_table = &ao_ranges_64xx, 656 .ao_range_code = ao_range_code_64xx, 657 .ai_fifo = &ai_fifo_64xx, 658 .has_8255 = 1, 659 }, 660 { 661 .name = "pci-das64/m2/16", 662 .device_id = 0x36, 663 .ai_se_chans = 64, 664 .ai_bits = 16, 665 .ai_speed = 500, 666 .ao_nchan = 2, 667 .ao_bits = 16, 668 .ao_scan_speed = 10000, 669 .layout = LAYOUT_64XX, 670 .ai_range_table = &ai_ranges_64xx, 671 .ao_range_table = &ao_ranges_64xx, 672 .ao_range_code = ao_range_code_64xx, 673 .ai_fifo = &ai_fifo_64xx, 674 .has_8255 = 1, 675 }, 676 { 677 .name = "pci-das64/m3/16", 678 .device_id = 0x37, 679 .ai_se_chans = 64, 680 .ai_bits = 16, 681 .ai_speed = 333, 682 .ao_nchan = 2, 683 .ao_bits = 16, 684 .ao_scan_speed = 10000, 685 .layout = LAYOUT_64XX, 686 .ai_range_table = &ai_ranges_64xx, 687 .ao_range_table = &ao_ranges_64xx, 688 .ao_range_code = ao_range_code_64xx, 689 .ai_fifo = &ai_fifo_64xx, 690 .has_8255 = 1, 691 }, 692 { 693 .name = "pci-das6013", 694 .device_id = 0x78, 695 .ai_se_chans = 16, 696 .ai_bits = 16, 697 .ai_speed = 5000, 698 .ao_nchan = 0, 699 .ao_bits = 16, 700 .layout = LAYOUT_60XX, 701 .ai_range_table = &ai_ranges_60xx, 702 .ao_range_table = &ao_ranges_60xx, 703 .ao_range_code = ao_range_code_60xx, 704 .ai_fifo = &ai_fifo_60xx, 705 .has_8255 = 0, 706 }, 707 { 708 .name = "pci-das6014", 709 .device_id = 0x79, 710 .ai_se_chans = 16, 711 .ai_bits = 16, 712 .ai_speed = 5000, 713 .ao_nchan = 2, 714 .ao_bits = 16, 715 .ao_scan_speed = 100000, 716 .layout = LAYOUT_60XX, 717 .ai_range_table = &ai_ranges_60xx, 718 .ao_range_table = &ao_ranges_60xx, 719 .ao_range_code = ao_range_code_60xx, 720 .ai_fifo = &ai_fifo_60xx, 721 .has_8255 = 0, 722 }, 723 { 724 .name = "pci-das6023", 725 .device_id = 0x5d, 726 .ai_se_chans = 16, 727 .ai_bits = 12, 728 .ai_speed = 5000, 729 .ao_nchan = 0, 730 .ao_scan_speed = 100000, 731 .layout = LAYOUT_60XX, 732 .ai_range_table = &ai_ranges_60xx, 733 .ao_range_table = &ao_ranges_60xx, 734 .ao_range_code = ao_range_code_60xx, 735 .ai_fifo = &ai_fifo_60xx, 736 .has_8255 = 1, 737 }, 738 { 739 .name = "pci-das6025", 740 .device_id = 0x5e, 741 .ai_se_chans = 16, 742 .ai_bits = 12, 743 .ai_speed = 5000, 744 .ao_nchan = 2, 745 .ao_bits = 12, 746 .ao_scan_speed = 100000, 747 .layout = LAYOUT_60XX, 748 .ai_range_table = &ai_ranges_60xx, 749 .ao_range_table = &ao_ranges_60xx, 750 .ao_range_code = ao_range_code_60xx, 751 .ai_fifo = &ai_fifo_60xx, 752 .has_8255 = 1, 753 }, 754 { 755 .name = "pci-das6030", 756 .device_id = 0x5f, 757 .ai_se_chans = 16, 758 .ai_bits = 16, 759 .ai_speed = 10000, 760 .ao_nchan = 2, 761 .ao_bits = 16, 762 .ao_scan_speed = 10000, 763 .layout = LAYOUT_60XX, 764 .ai_range_table = &ai_ranges_6030, 765 .ao_range_table = &ao_ranges_6030, 766 .ao_range_code = ao_range_code_6030, 767 .ai_fifo = &ai_fifo_60xx, 768 .has_8255 = 0, 769 }, 770 { 771 .name = "pci-das6031", 772 .device_id = 0x60, 773 .ai_se_chans = 64, 774 .ai_bits = 16, 775 .ai_speed = 10000, 776 .ao_nchan = 2, 777 .ao_bits = 16, 778 .ao_scan_speed = 10000, 779 .layout = LAYOUT_60XX, 780 .ai_range_table = &ai_ranges_6030, 781 .ao_range_table = &ao_ranges_6030, 782 .ao_range_code = ao_range_code_6030, 783 .ai_fifo = &ai_fifo_60xx, 784 .has_8255 = 0, 785 }, 786 { 787 .name = "pci-das6032", 788 .device_id = 0x61, 789 .ai_se_chans = 16, 790 .ai_bits = 16, 791 .ai_speed = 10000, 792 .ao_nchan = 0, 793 .layout = LAYOUT_60XX, 794 .ai_range_table = &ai_ranges_6030, 795 .ai_fifo = &ai_fifo_60xx, 796 .has_8255 = 0, 797 }, 798 { 799 .name = "pci-das6033", 800 .device_id = 0x62, 801 .ai_se_chans = 64, 802 .ai_bits = 16, 803 .ai_speed = 10000, 804 .ao_nchan = 0, 805 .layout = LAYOUT_60XX, 806 .ai_range_table = &ai_ranges_6030, 807 .ai_fifo = &ai_fifo_60xx, 808 .has_8255 = 0, 809 }, 810 { 811 .name = "pci-das6034", 812 .device_id = 0x63, 813 .ai_se_chans = 16, 814 .ai_bits = 16, 815 .ai_speed = 5000, 816 .ao_nchan = 0, 817 .ao_scan_speed = 0, 818 .layout = LAYOUT_60XX, 819 .ai_range_table = &ai_ranges_60xx, 820 .ai_fifo = &ai_fifo_60xx, 821 .has_8255 = 0, 822 }, 823 { 824 .name = "pci-das6035", 825 .device_id = 0x64, 826 .ai_se_chans = 16, 827 .ai_bits = 16, 828 .ai_speed = 5000, 829 .ao_nchan = 2, 830 .ao_bits = 12, 831 .ao_scan_speed = 100000, 832 .layout = LAYOUT_60XX, 833 .ai_range_table = &ai_ranges_60xx, 834 .ao_range_table = &ao_ranges_60xx, 835 .ao_range_code = ao_range_code_60xx, 836 .ai_fifo = &ai_fifo_60xx, 837 .has_8255 = 0, 838 }, 839 { 840 .name = "pci-das6036", 841 .device_id = 0x6f, 842 .ai_se_chans = 16, 843 .ai_bits = 16, 844 .ai_speed = 5000, 845 .ao_nchan = 2, 846 .ao_bits = 16, 847 .ao_scan_speed = 100000, 848 .layout = LAYOUT_60XX, 849 .ai_range_table = &ai_ranges_60xx, 850 .ao_range_table = &ao_ranges_60xx, 851 .ao_range_code = ao_range_code_60xx, 852 .ai_fifo = &ai_fifo_60xx, 853 .has_8255 = 0, 854 }, 855 { 856 .name = "pci-das6040", 857 .device_id = 0x65, 858 .ai_se_chans = 16, 859 .ai_bits = 12, 860 .ai_speed = 2000, 861 .ao_nchan = 2, 862 .ao_bits = 12, 863 .ao_scan_speed = 1000, 864 .layout = LAYOUT_60XX, 865 .ai_range_table = &ai_ranges_6052, 866 .ao_range_table = &ao_ranges_6030, 867 .ao_range_code = ao_range_code_6030, 868 .ai_fifo = &ai_fifo_60xx, 869 .has_8255 = 0, 870 }, 871 { 872 .name = "pci-das6052", 873 .device_id = 0x66, 874 .ai_se_chans = 16, 875 .ai_bits = 16, 876 .ai_speed = 3333, 877 .ao_nchan = 2, 878 .ao_bits = 16, 879 .ao_scan_speed = 3333, 880 .layout = LAYOUT_60XX, 881 .ai_range_table = &ai_ranges_6052, 882 .ao_range_table = &ao_ranges_6030, 883 .ao_range_code = ao_range_code_6030, 884 .ai_fifo = &ai_fifo_60xx, 885 .has_8255 = 0, 886 }, 887 { 888 .name = "pci-das6070", 889 .device_id = 0x67, 890 .ai_se_chans = 16, 891 .ai_bits = 12, 892 .ai_speed = 800, 893 .ao_nchan = 2, 894 .ao_bits = 12, 895 .ao_scan_speed = 1000, 896 .layout = LAYOUT_60XX, 897 .ai_range_table = &ai_ranges_6052, 898 .ao_range_table = &ao_ranges_6030, 899 .ao_range_code = ao_range_code_6030, 900 .ai_fifo = &ai_fifo_60xx, 901 .has_8255 = 0, 902 }, 903 { 904 .name = "pci-das6071", 905 .device_id = 0x68, 906 .ai_se_chans = 64, 907 .ai_bits = 12, 908 .ai_speed = 800, 909 .ao_nchan = 2, 910 .ao_bits = 12, 911 .ao_scan_speed = 1000, 912 .layout = LAYOUT_60XX, 913 .ai_range_table = &ai_ranges_6052, 914 .ao_range_table = &ao_ranges_6030, 915 .ao_range_code = ao_range_code_6030, 916 .ai_fifo = &ai_fifo_60xx, 917 .has_8255 = 0, 918 }, 919 { 920 .name = "pci-das4020/12", 921 .device_id = 0x52, 922 .ai_se_chans = 4, 923 .ai_bits = 12, 924 .ai_speed = 50, 925 .ao_bits = 12, 926 .ao_nchan = 2, 927 .ao_scan_speed = 0, /* no hardware pacing on ao */ 928 .layout = LAYOUT_4020, 929 .ai_range_table = &ai_ranges_4020, 930 .ao_range_table = &ao_ranges_4020, 931 .ao_range_code = ao_range_code_4020, 932 .ai_fifo = &ai_fifo_4020, 933 .has_8255 = 1, 934 }, 935#if 0 936 { 937 .name = "pci-das6402/16/jr", 938 .device_id = 0 /* XXX, */ 939 .ai_se_chans = 64, 940 .ai_bits = 16, 941 .ai_speed = 5000, 942 .ao_nchan = 0, 943 .ao_scan_speed = 10000, 944 .layout = LAYOUT_64XX, 945 .ai_range_table = &ai_ranges_64xx, 946 .ai_fifo = ai_fifo_64xx, 947 .has_8255 = 1, 948 }, 949 { 950 .name = "pci-das64/m1/16/jr", 951 .device_id = 0 /* XXX, */ 952 .ai_se_chans = 64, 953 .ai_bits = 16, 954 .ai_speed = 1000, 955 .ao_nchan = 0, 956 .ao_scan_speed = 10000, 957 .layout = LAYOUT_64XX, 958 .ai_range_table = &ai_ranges_64xx, 959 .ai_fifo = ai_fifo_64xx, 960 .has_8255 = 1, 961 }, 962 { 963 .name = "pci-das64/m2/16/jr", 964 .device_id = 0 /* XXX, */ 965 .ai_se_chans = 64, 966 .ai_bits = 16, 967 .ai_speed = 500, 968 .ao_nchan = 0, 969 .ao_scan_speed = 10000, 970 .layout = LAYOUT_64XX, 971 .ai_range_table = &ai_ranges_64xx, 972 .ai_fifo = ai_fifo_64xx, 973 .has_8255 = 1, 974 }, 975 { 976 .name = "pci-das64/m3/16/jr", 977 .device_id = 0 /* XXX, */ 978 .ai_se_chans = 64, 979 .ai_bits = 16, 980 .ai_speed = 333, 981 .ao_nchan = 0, 982 .ao_scan_speed = 10000, 983 .layout = LAYOUT_64XX, 984 .ai_range_table = &ai_ranges_64xx, 985 .ai_fifo = ai_fifo_64xx, 986 .has_8255 = 1, 987 }, 988 { 989 .name = "pci-das64/m1/14", 990 .device_id = 0, /* XXX */ 991 .ai_se_chans = 64, 992 .ai_bits = 14, 993 .ai_speed = 1000, 994 .ao_nchan = 2, 995 .ao_scan_speed = 10000, 996 .layout = LAYOUT_64XX, 997 .ai_range_table = &ai_ranges_64xx, 998 .ai_fifo = ai_fifo_64xx, 999 .has_8255 = 1, 1000 }, 1001 { 1002 .name = "pci-das64/m2/14", 1003 .device_id = 0, /* XXX */ 1004 .ai_se_chans = 64, 1005 .ai_bits = 14, 1006 .ai_speed = 500, 1007 .ao_nchan = 2, 1008 .ao_scan_speed = 10000, 1009 .layout = LAYOUT_64XX, 1010 .ai_range_table = &ai_ranges_64xx, 1011 .ai_fifo = ai_fifo_64xx, 1012 .has_8255 = 1, 1013 }, 1014 { 1015 .name = "pci-das64/m3/14", 1016 .device_id = 0, /* XXX */ 1017 .ai_se_chans = 64, 1018 .ai_bits = 14, 1019 .ai_speed = 333, 1020 .ao_nchan = 2, 1021 .ao_scan_speed = 10000, 1022 .layout = LAYOUT_64XX, 1023 .ai_range_table = &ai_ranges_64xx, 1024 .ai_fifo = ai_fifo_64xx, 1025 .has_8255 = 1, 1026 }, 1027#endif 1028}; 1029 1030static DEFINE_PCI_DEVICE_TABLE(pcidas64_pci_table) = { 1031 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001d) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001e) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0035) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0036) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0037) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0052) }, 1037 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005d) }, 1038 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005e) }, 1039 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005f) }, 1040 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0061) }, 1041 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0062) }, 1042 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0063) }, 1043 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0064) }, 1044 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0066) }, 1045 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0067) }, 1046 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0068) }, 1047 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x006f) }, 1048 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0078) }, 1049 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0079) }, 1050 { 0 } 1051}; 1052 1053MODULE_DEVICE_TABLE(pci, pcidas64_pci_table); 1054 1055static inline struct pcidas64_board *board(const struct comedi_device *dev) 1056{ 1057 return (struct pcidas64_board *)dev->board_ptr; 1058} 1059 1060static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev, 1061 int use_differential) 1062{ 1063 if ((board(dev)->layout == LAYOUT_64XX && !use_differential) || 1064 (board(dev)->layout == LAYOUT_60XX && use_differential)) 1065 return ADC_SE_DIFF_BIT; 1066 else 1067 return 0; 1068}; 1069 1070struct ext_clock_info { 1071 unsigned int divisor; /* master clock divisor to use for scans with external master clock */ 1072 unsigned int chanspec; /* chanspec for master clock input when used as scan begin src */ 1073}; 1074 1075/* this structure is for data unique to this hardware driver. */ 1076struct pcidas64_private { 1077 1078 struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */ 1079 /* base addresses (physical) */ 1080 resource_size_t plx9080_phys_iobase; 1081 resource_size_t main_phys_iobase; 1082 resource_size_t dio_counter_phys_iobase; 1083 /* base addresses (ioremapped) */ 1084 void __iomem *plx9080_iobase; 1085 void __iomem *main_iobase; 1086 void __iomem *dio_counter_iobase; 1087 /* local address (used by dma controller) */ 1088 uint32_t local0_iobase; 1089 uint32_t local1_iobase; 1090 volatile unsigned int ai_count; /* number of analog input samples remaining */ 1091 uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT]; /* dma buffers for analog input */ 1092 dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT]; /* physical addresses of ai dma buffers */ 1093 struct plx_dma_desc *ai_dma_desc; /* array of ai dma descriptors read by plx9080, allocated to get proper alignment */ 1094 dma_addr_t ai_dma_desc_bus_addr; /* physical address of ai dma descriptor array */ 1095 volatile unsigned int ai_dma_index; /* index of the ai dma descriptor/buffer that is currently being used */ 1096 uint16_t *ao_buffer[AO_DMA_RING_COUNT]; /* dma buffers for analog output */ 1097 dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT]; /* physical addresses of ao dma buffers */ 1098 struct plx_dma_desc *ao_dma_desc; 1099 dma_addr_t ao_dma_desc_bus_addr; 1100 volatile unsigned int ao_dma_index; /* keeps track of buffer where the next ao sample should go */ 1101 volatile unsigned long ao_count; /* number of analog output samples remaining */ 1102 volatile unsigned int ao_value[2]; /* remember what the analog outputs are set to, to allow readback */ 1103 unsigned int hw_revision; /* stc chip hardware revision number */ 1104 volatile unsigned int intr_enable_bits; /* last bits sent to INTR_ENABLE_REG register */ 1105 volatile uint16_t adc_control1_bits; /* last bits sent to ADC_CONTROL1_REG register */ 1106 volatile uint16_t fifo_size_bits; /* last bits sent to FIFO_SIZE_REG register */ 1107 volatile uint16_t hw_config_bits; /* last bits sent to HW_CONFIG_REG register */ 1108 volatile uint16_t dac_control1_bits; 1109 volatile uint32_t plx_control_bits; /* last bits written to plx9080 control register */ 1110 volatile uint32_t plx_intcsr_bits; /* last bits written to plx interrupt control and status register */ 1111 volatile int calibration_source; /* index of calibration source readable through ai ch0 */ 1112 volatile uint8_t i2c_cal_range_bits; /* bits written to i2c calibration/range register */ 1113 volatile unsigned int ext_trig_falling; /* configure digital triggers to trigger on falling edge */ 1114 /* states of various devices stored to enable read-back */ 1115 unsigned int ad8402_state[2]; 1116 unsigned int caldac_state[8]; 1117 volatile short ai_cmd_running; 1118 unsigned int ai_fifo_segment_length; 1119 struct ext_clock_info ext_clock; 1120 short ao_bounce_buffer[DAC_FIFO_SIZE]; 1121}; 1122 1123/* inline function that makes it easier to 1124 * access the private structure. 1125 */ 1126static inline struct pcidas64_private *priv(struct comedi_device *dev) 1127{ 1128 return dev->private; 1129} 1130 1131/* 1132 * The comedi_driver structure tells the Comedi core module 1133 * which functions to call to configure/deconfigure (attach/detach) 1134 * the board, and also about the kernel module that contains 1135 * the device code. 1136 */ 1137static int attach(struct comedi_device *dev, struct comedi_devconfig *it); 1138static int detach(struct comedi_device *dev); 1139static struct comedi_driver driver_cb_pcidas = { 1140 .driver_name = "cb_pcidas64", 1141 .module = THIS_MODULE, 1142 .attach = attach, 1143 .detach = detach, 1144}; 1145 1146static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1147 struct comedi_insn *insn, unsigned int *data); 1148static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s, 1149 struct comedi_insn *insn, unsigned int *data); 1150static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 1151 struct comedi_insn *insn, unsigned int *data); 1152static int ao_readback_insn(struct comedi_device *dev, 1153 struct comedi_subdevice *s, 1154 struct comedi_insn *insn, unsigned int *data); 1155static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 1156static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 1157 struct comedi_cmd *cmd); 1158static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 1159static int ao_inttrig(struct comedi_device *dev, 1160 struct comedi_subdevice *subdev, unsigned int trig_num); 1161static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 1162 struct comedi_cmd *cmd); 1163static irqreturn_t handle_interrupt(int irq, void *d); 1164static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 1165static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 1166static int dio_callback(int dir, int port, int data, unsigned long arg); 1167static int dio_callback_4020(int dir, int port, int data, unsigned long arg); 1168static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s, 1169 struct comedi_insn *insn, unsigned int *data); 1170static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s, 1171 struct comedi_insn *insn, unsigned int *data); 1172static int dio_60xx_config_insn(struct comedi_device *dev, 1173 struct comedi_subdevice *s, 1174 struct comedi_insn *insn, unsigned int *data); 1175static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s, 1176 struct comedi_insn *insn, unsigned int *data); 1177static int calib_read_insn(struct comedi_device *dev, 1178 struct comedi_subdevice *s, struct comedi_insn *insn, 1179 unsigned int *data); 1180static int calib_write_insn(struct comedi_device *dev, 1181 struct comedi_subdevice *s, 1182 struct comedi_insn *insn, unsigned int *data); 1183static int ad8402_read_insn(struct comedi_device *dev, 1184 struct comedi_subdevice *s, 1185 struct comedi_insn *insn, unsigned int *data); 1186static void ad8402_write(struct comedi_device *dev, unsigned int channel, 1187 unsigned int value); 1188static int ad8402_write_insn(struct comedi_device *dev, 1189 struct comedi_subdevice *s, 1190 struct comedi_insn *insn, unsigned int *data); 1191static int eeprom_read_insn(struct comedi_device *dev, 1192 struct comedi_subdevice *s, 1193 struct comedi_insn *insn, unsigned int *data); 1194static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd); 1195static unsigned int get_divisor(unsigned int ns, unsigned int flags); 1196static void i2c_write(struct comedi_device *dev, unsigned int address, 1197 const uint8_t * data, unsigned int length); 1198static void caldac_write(struct comedi_device *dev, unsigned int channel, 1199 unsigned int value); 1200static int caldac_8800_write(struct comedi_device *dev, unsigned int address, 1201 uint8_t value); 1202/* static int dac_1590_write(struct comedi_device *dev, unsigned int dac_a, unsigned int dac_b); */ 1203static int caldac_i2c_write(struct comedi_device *dev, 1204 unsigned int caldac_channel, unsigned int value); 1205static void abort_dma(struct comedi_device *dev, unsigned int channel); 1206static void disable_plx_interrupts(struct comedi_device *dev); 1207static int set_ai_fifo_size(struct comedi_device *dev, 1208 unsigned int num_samples); 1209static unsigned int ai_fifo_size(struct comedi_device *dev); 1210static int set_ai_fifo_segment_length(struct comedi_device *dev, 1211 unsigned int num_entries); 1212static void disable_ai_pacing(struct comedi_device *dev); 1213static void disable_ai_interrupts(struct comedi_device *dev); 1214static void enable_ai_interrupts(struct comedi_device *dev, 1215 const struct comedi_cmd *cmd); 1216static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags); 1217static void load_ao_dma(struct comedi_device *dev, 1218 const struct comedi_cmd *cmd); 1219 1220static int __devinit driver_cb_pcidas_pci_probe(struct pci_dev *dev, 1221 const struct pci_device_id *ent) 1222{ 1223 return comedi_pci_auto_config(dev, driver_cb_pcidas.driver_name); 1224} 1225 1226static void __devexit driver_cb_pcidas_pci_remove(struct pci_dev *dev) 1227{ 1228 comedi_pci_auto_unconfig(dev); 1229} 1230 1231static struct pci_driver driver_cb_pcidas_pci_driver = { 1232 .id_table = pcidas64_pci_table, 1233 .probe = &driver_cb_pcidas_pci_probe, 1234 .remove = __devexit_p(&driver_cb_pcidas_pci_remove) 1235}; 1236 1237static int __init driver_cb_pcidas_init_module(void) 1238{ 1239 int retval; 1240 1241 retval = comedi_driver_register(&driver_cb_pcidas); 1242 if (retval < 0) 1243 return retval; 1244 1245 driver_cb_pcidas_pci_driver.name = (char *)driver_cb_pcidas.driver_name; 1246 return pci_register_driver(&driver_cb_pcidas_pci_driver); 1247} 1248 1249static void __exit driver_cb_pcidas_cleanup_module(void) 1250{ 1251 pci_unregister_driver(&driver_cb_pcidas_pci_driver); 1252 comedi_driver_unregister(&driver_cb_pcidas); 1253} 1254 1255module_init(driver_cb_pcidas_init_module); 1256module_exit(driver_cb_pcidas_cleanup_module); 1257 1258static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev, 1259 unsigned int range_index) 1260{ 1261 const struct comedi_krange *range = 1262 &board(dev)->ai_range_table->range[range_index]; 1263 unsigned int bits = 0; 1264 1265 switch (range->max) { 1266 case 10000000: 1267 bits = 0x000; 1268 break; 1269 case 5000000: 1270 bits = 0x100; 1271 break; 1272 case 2000000: 1273 case 2500000: 1274 bits = 0x200; 1275 break; 1276 case 1000000: 1277 case 1250000: 1278 bits = 0x300; 1279 break; 1280 case 500000: 1281 bits = 0x400; 1282 break; 1283 case 200000: 1284 case 250000: 1285 bits = 0x500; 1286 break; 1287 case 100000: 1288 bits = 0x600; 1289 break; 1290 case 50000: 1291 bits = 0x700; 1292 break; 1293 default: 1294 comedi_error(dev, "bug! in ai_range_bits_6xxx"); 1295 break; 1296 } 1297 if (range->min == 0) 1298 bits += 0x900; 1299 return bits; 1300} 1301 1302static unsigned int hw_revision(const struct comedi_device *dev, 1303 uint16_t hw_status_bits) 1304{ 1305 if (board(dev)->layout == LAYOUT_4020) 1306 return (hw_status_bits >> 13) & 0x7; 1307 1308 return (hw_status_bits >> 12) & 0xf; 1309} 1310 1311static void set_dac_range_bits(struct comedi_device *dev, 1312 volatile uint16_t * bits, unsigned int channel, 1313 unsigned int range) 1314{ 1315 unsigned int code = board(dev)->ao_range_code[range]; 1316 1317 if (channel > 1) 1318 comedi_error(dev, "bug! bad channel?"); 1319 if (code & ~0x3) 1320 comedi_error(dev, "bug! bad range code?"); 1321 1322 *bits &= ~(0x3 << (2 * channel)); 1323 *bits |= code << (2 * channel); 1324}; 1325 1326static inline int ao_cmd_is_supported(const struct pcidas64_board *board) 1327{ 1328 return board->ao_nchan && board->layout != LAYOUT_4020; 1329} 1330 1331/* initialize plx9080 chip */ 1332static void init_plx9080(struct comedi_device *dev) 1333{ 1334 uint32_t bits; 1335 void __iomem *plx_iobase = priv(dev)->plx9080_iobase; 1336 1337 priv(dev)->plx_control_bits = 1338 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG); 1339 1340 /* plx9080 dump */ 1341 DEBUG_PRINT(" plx interrupt status 0x%x\n", 1342 readl(plx_iobase + PLX_INTRCS_REG)); 1343 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG)); 1344 DEBUG_PRINT(" plx control reg 0x%x\n", priv(dev)->plx_control_bits); 1345 DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n", 1346 readl(plx_iobase + PLX_MARB_REG)); 1347 DEBUG_PRINT(" plx region0 reg 0x%x\n", 1348 readl(plx_iobase + PLX_REGION0_REG)); 1349 DEBUG_PRINT(" plx region1 reg 0x%x\n", 1350 readl(plx_iobase + PLX_REGION1_REG)); 1351 1352 DEBUG_PRINT(" plx revision 0x%x\n", 1353 readl(plx_iobase + PLX_REVISION_REG)); 1354 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n", 1355 readl(plx_iobase + PLX_DMA0_MODE_REG)); 1356 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n", 1357 readl(plx_iobase + PLX_DMA1_MODE_REG)); 1358 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n", 1359 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG)); 1360 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n", 1361 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG)); 1362 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n", 1363 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG)); 1364 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n", 1365 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG)); 1366 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n", 1367 readb(plx_iobase + PLX_DMA0_CS_REG)); 1368 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n", 1369 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG)); 1370 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG)); 1371 1372#ifdef __BIG_ENDIAN 1373 bits = BIGEND_DMA0 | BIGEND_DMA1; 1374#else 1375 bits = 0; 1376#endif 1377 writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG); 1378 1379 disable_plx_interrupts(dev); 1380 1381 abort_dma(dev, 0); 1382 abort_dma(dev, 1); 1383 1384 /* configure dma0 mode */ 1385 bits = 0; 1386 /* enable ready input, not sure if this is necessary */ 1387 bits |= PLX_DMA_EN_READYIN_BIT; 1388 /* enable bterm, not sure if this is necessary */ 1389 bits |= PLX_EN_BTERM_BIT; 1390 /* enable dma chaining */ 1391 bits |= PLX_EN_CHAIN_BIT; 1392 /* enable interrupt on dma done (probably don't need this, since chain never finishes) */ 1393 bits |= PLX_EN_DMA_DONE_INTR_BIT; 1394 /* don't increment local address during transfers (we are transferring from a fixed fifo register) */ 1395 bits |= PLX_LOCAL_ADDR_CONST_BIT; 1396 /* route dma interrupt to pci bus */ 1397 bits |= PLX_DMA_INTR_PCI_BIT; 1398 /* enable demand mode */ 1399 bits |= PLX_DEMAND_MODE_BIT; 1400 /* enable local burst mode */ 1401 bits |= PLX_DMA_LOCAL_BURST_EN_BIT; 1402 /* 4020 uses 32 bit dma */ 1403 if (board(dev)->layout == LAYOUT_4020) { 1404 bits |= PLX_LOCAL_BUS_32_WIDE_BITS; 1405 } else { /* localspace0 bus is 16 bits wide */ 1406 bits |= PLX_LOCAL_BUS_16_WIDE_BITS; 1407 } 1408 writel(bits, plx_iobase + PLX_DMA1_MODE_REG); 1409 if (ao_cmd_is_supported(board(dev))) 1410 writel(bits, plx_iobase + PLX_DMA0_MODE_REG); 1411 1412 /* enable interrupts on plx 9080 */ 1413 priv(dev)->plx_intcsr_bits |= 1414 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE | 1415 ICS_DMA0_E | ICS_DMA1_E; 1416 writel(priv(dev)->plx_intcsr_bits, 1417 priv(dev)->plx9080_iobase + PLX_INTRCS_REG); 1418} 1419 1420/* Allocate and initialize the subdevice structures. 1421 */ 1422static int setup_subdevices(struct comedi_device *dev) 1423{ 1424 struct comedi_subdevice *s; 1425 void __iomem *dio_8255_iobase; 1426 int i; 1427 1428 if (alloc_subdevices(dev, 10) < 0) 1429 return -ENOMEM; 1430 1431 s = dev->subdevices + 0; 1432 /* analog input subdevice */ 1433 dev->read_subdev = s; 1434 s->type = COMEDI_SUBD_AI; 1435 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ; 1436 if (board(dev)->layout == LAYOUT_60XX) 1437 s->subdev_flags |= SDF_COMMON | SDF_DIFF; 1438 else if (board(dev)->layout == LAYOUT_64XX) 1439 s->subdev_flags |= SDF_DIFF; 1440 /* XXX Number of inputs in differential mode is ignored */ 1441 s->n_chan = board(dev)->ai_se_chans; 1442 s->len_chanlist = 0x2000; 1443 s->maxdata = (1 << board(dev)->ai_bits) - 1; 1444 s->range_table = board(dev)->ai_range_table; 1445 s->insn_read = ai_rinsn; 1446 s->insn_config = ai_config_insn; 1447 s->do_cmd = ai_cmd; 1448 s->do_cmdtest = ai_cmdtest; 1449 s->cancel = ai_cancel; 1450 if (board(dev)->layout == LAYOUT_4020) { 1451 uint8_t data; 1452 /* set adc to read from inputs (not internal calibration sources) */ 1453 priv(dev)->i2c_cal_range_bits = adc_src_4020_bits(4); 1454 /* set channels to +-5 volt input ranges */ 1455 for (i = 0; i < s->n_chan; i++) 1456 priv(dev)->i2c_cal_range_bits |= attenuate_bit(i); 1457 data = priv(dev)->i2c_cal_range_bits; 1458 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data)); 1459 } 1460 1461 /* analog output subdevice */ 1462 s = dev->subdevices + 1; 1463 if (board(dev)->ao_nchan) { 1464 s->type = COMEDI_SUBD_AO; 1465 s->subdev_flags = 1466 SDF_READABLE | SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE; 1467 s->n_chan = board(dev)->ao_nchan; 1468 s->maxdata = (1 << board(dev)->ao_bits) - 1; 1469 s->range_table = board(dev)->ao_range_table; 1470 s->insn_read = ao_readback_insn; 1471 s->insn_write = ao_winsn; 1472 if (ao_cmd_is_supported(board(dev))) { 1473 dev->write_subdev = s; 1474 s->do_cmdtest = ao_cmdtest; 1475 s->do_cmd = ao_cmd; 1476 s->len_chanlist = board(dev)->ao_nchan; 1477 s->cancel = ao_cancel; 1478 } 1479 } else { 1480 s->type = COMEDI_SUBD_UNUSED; 1481 } 1482 1483 /* digital input */ 1484 s = dev->subdevices + 2; 1485 if (board(dev)->layout == LAYOUT_64XX) { 1486 s->type = COMEDI_SUBD_DI; 1487 s->subdev_flags = SDF_READABLE; 1488 s->n_chan = 4; 1489 s->maxdata = 1; 1490 s->range_table = &range_digital; 1491 s->insn_bits = di_rbits; 1492 } else 1493 s->type = COMEDI_SUBD_UNUSED; 1494 1495 /* digital output */ 1496 if (board(dev)->layout == LAYOUT_64XX) { 1497 s = dev->subdevices + 3; 1498 s->type = COMEDI_SUBD_DO; 1499 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 1500 s->n_chan = 4; 1501 s->maxdata = 1; 1502 s->range_table = &range_digital; 1503 s->insn_bits = do_wbits; 1504 } else 1505 s->type = COMEDI_SUBD_UNUSED; 1506 1507 /* 8255 */ 1508 s = dev->subdevices + 4; 1509 if (board(dev)->has_8255) { 1510 if (board(dev)->layout == LAYOUT_4020) { 1511 dio_8255_iobase = 1512 priv(dev)->main_iobase + I8255_4020_REG; 1513 subdev_8255_init(dev, s, dio_callback_4020, 1514 (unsigned long)dio_8255_iobase); 1515 } else { 1516 dio_8255_iobase = 1517 priv(dev)->dio_counter_iobase + DIO_8255_OFFSET; 1518 subdev_8255_init(dev, s, dio_callback, 1519 (unsigned long)dio_8255_iobase); 1520 } 1521 } else 1522 s->type = COMEDI_SUBD_UNUSED; 1523 1524 /* 8 channel dio for 60xx */ 1525 s = dev->subdevices + 5; 1526 if (board(dev)->layout == LAYOUT_60XX) { 1527 s->type = COMEDI_SUBD_DIO; 1528 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 1529 s->n_chan = 8; 1530 s->maxdata = 1; 1531 s->range_table = &range_digital; 1532 s->insn_config = dio_60xx_config_insn; 1533 s->insn_bits = dio_60xx_wbits; 1534 } else 1535 s->type = COMEDI_SUBD_UNUSED; 1536 1537 /* caldac */ 1538 s = dev->subdevices + 6; 1539 s->type = COMEDI_SUBD_CALIB; 1540 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 1541 s->n_chan = 8; 1542 if (board(dev)->layout == LAYOUT_4020) 1543 s->maxdata = 0xfff; 1544 else 1545 s->maxdata = 0xff; 1546 s->insn_read = calib_read_insn; 1547 s->insn_write = calib_write_insn; 1548 for (i = 0; i < s->n_chan; i++) 1549 caldac_write(dev, i, s->maxdata / 2); 1550 1551 /* 2 channel ad8402 potentiometer */ 1552 s = dev->subdevices + 7; 1553 if (board(dev)->layout == LAYOUT_64XX) { 1554 s->type = COMEDI_SUBD_CALIB; 1555 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 1556 s->n_chan = 2; 1557 s->insn_read = ad8402_read_insn; 1558 s->insn_write = ad8402_write_insn; 1559 s->maxdata = 0xff; 1560 for (i = 0; i < s->n_chan; i++) 1561 ad8402_write(dev, i, s->maxdata / 2); 1562 } else 1563 s->type = COMEDI_SUBD_UNUSED; 1564 1565 /* serial EEPROM, if present */ 1566 s = dev->subdevices + 8; 1567 if (readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) { 1568 s->type = COMEDI_SUBD_MEMORY; 1569 s->subdev_flags = SDF_READABLE | SDF_INTERNAL; 1570 s->n_chan = 128; 1571 s->maxdata = 0xffff; 1572 s->insn_read = eeprom_read_insn; 1573 } else 1574 s->type = COMEDI_SUBD_UNUSED; 1575 1576 /* user counter subd XXX */ 1577 s = dev->subdevices + 9; 1578 s->type = COMEDI_SUBD_UNUSED; 1579 1580 return 0; 1581} 1582 1583static void disable_plx_interrupts(struct comedi_device *dev) 1584{ 1585 priv(dev)->plx_intcsr_bits = 0; 1586 writel(priv(dev)->plx_intcsr_bits, 1587 priv(dev)->plx9080_iobase + PLX_INTRCS_REG); 1588} 1589 1590static void init_stc_registers(struct comedi_device *dev) 1591{ 1592 uint16_t bits; 1593 unsigned long flags; 1594 1595 spin_lock_irqsave(&dev->spinlock, flags); 1596 1597 /* bit should be set for 6025, although docs say boards with <= 16 chans should be cleared XXX */ 1598 if (1) 1599 priv(dev)->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT; 1600 writew(priv(dev)->adc_control1_bits, 1601 priv(dev)->main_iobase + ADC_CONTROL1_REG); 1602 1603 /* 6402/16 manual says this register must be initialized to 0xff? */ 1604 writew(0xff, priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); 1605 1606 bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT; 1607 if (board(dev)->layout == LAYOUT_4020) 1608 bits |= INTERNAL_CLOCK_4020_BITS; 1609 priv(dev)->hw_config_bits |= bits; 1610 writew(priv(dev)->hw_config_bits, 1611 priv(dev)->main_iobase + HW_CONFIG_REG); 1612 1613 writew(0, priv(dev)->main_iobase + DAQ_SYNC_REG); 1614 writew(0, priv(dev)->main_iobase + CALIBRATION_REG); 1615 1616 spin_unlock_irqrestore(&dev->spinlock, flags); 1617 1618 /* set fifos to maximum size */ 1619 priv(dev)->fifo_size_bits |= DAC_FIFO_BITS; 1620 set_ai_fifo_segment_length(dev, 1621 board(dev)->ai_fifo->max_segment_length); 1622 1623 priv(dev)->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT; 1624 priv(dev)->intr_enable_bits = /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */ 1625 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT; 1626 writew(priv(dev)->intr_enable_bits, 1627 priv(dev)->main_iobase + INTR_ENABLE_REG); 1628 1629 disable_ai_pacing(dev); 1630}; 1631 1632static int alloc_and_init_dma_members(struct comedi_device *dev) 1633{ 1634 int i; 1635 1636 /* alocate pci dma buffers */ 1637 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) { 1638 priv(dev)->ai_buffer[i] = 1639 pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE, 1640 &priv(dev)->ai_buffer_bus_addr[i]); 1641 if (priv(dev)->ai_buffer[i] == NULL) 1642 return -ENOMEM; 1643 1644 } 1645 for (i = 0; i < AO_DMA_RING_COUNT; i++) { 1646 if (ao_cmd_is_supported(board(dev))) { 1647 priv(dev)->ao_buffer[i] = 1648 pci_alloc_consistent(priv(dev)->hw_dev, 1649 DMA_BUFFER_SIZE, 1650 &priv(dev)-> 1651 ao_buffer_bus_addr[i]); 1652 if (priv(dev)->ao_buffer[i] == NULL) 1653 return -ENOMEM; 1654 1655 } 1656 } 1657 /* allocate dma descriptors */ 1658 priv(dev)->ai_dma_desc = 1659 pci_alloc_consistent(priv(dev)->hw_dev, 1660 sizeof(struct plx_dma_desc) * 1661 ai_dma_ring_count(board(dev)), 1662 &priv(dev)->ai_dma_desc_bus_addr); 1663 if (priv(dev)->ai_dma_desc == NULL) 1664 return -ENOMEM; 1665 1666 DEBUG_PRINT("ai dma descriptors start at bus addr 0x%x\n", 1667 priv(dev)->ai_dma_desc_bus_addr); 1668 if (ao_cmd_is_supported(board(dev))) { 1669 priv(dev)->ao_dma_desc = 1670 pci_alloc_consistent(priv(dev)->hw_dev, 1671 sizeof(struct plx_dma_desc) * 1672 AO_DMA_RING_COUNT, 1673 &priv(dev)->ao_dma_desc_bus_addr); 1674 if (priv(dev)->ao_dma_desc == NULL) 1675 return -ENOMEM; 1676 1677 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%x\n", 1678 priv(dev)->ao_dma_desc_bus_addr); 1679 } 1680 /* initialize dma descriptors */ 1681 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) { 1682 priv(dev)->ai_dma_desc[i].pci_start_addr = 1683 cpu_to_le32(priv(dev)->ai_buffer_bus_addr[i]); 1684 if (board(dev)->layout == LAYOUT_4020) 1685 priv(dev)->ai_dma_desc[i].local_start_addr = 1686 cpu_to_le32(priv(dev)->local1_iobase + 1687 ADC_FIFO_REG); 1688 else 1689 priv(dev)->ai_dma_desc[i].local_start_addr = 1690 cpu_to_le32(priv(dev)->local0_iobase + 1691 ADC_FIFO_REG); 1692 priv(dev)->ai_dma_desc[i].transfer_size = cpu_to_le32(0); 1693 priv(dev)->ai_dma_desc[i].next = 1694 cpu_to_le32((priv(dev)->ai_dma_desc_bus_addr + ((i + 1695 1) % 1696 ai_dma_ring_count 1697 (board 1698 (dev))) * 1699 sizeof(priv(dev)->ai_dma_desc[0])) | 1700 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT | 1701 PLX_XFER_LOCAL_TO_PCI); 1702 } 1703 if (ao_cmd_is_supported(board(dev))) { 1704 for (i = 0; i < AO_DMA_RING_COUNT; i++) { 1705 priv(dev)->ao_dma_desc[i].pci_start_addr = 1706 cpu_to_le32(priv(dev)->ao_buffer_bus_addr[i]); 1707 priv(dev)->ao_dma_desc[i].local_start_addr = 1708 cpu_to_le32(priv(dev)->local0_iobase + 1709 DAC_FIFO_REG); 1710 priv(dev)->ao_dma_desc[i].transfer_size = 1711 cpu_to_le32(0); 1712 priv(dev)->ao_dma_desc[i].next = 1713 cpu_to_le32((priv(dev)->ao_dma_desc_bus_addr + 1714 ((i + 1) % (AO_DMA_RING_COUNT)) * 1715 sizeof(priv(dev)->ao_dma_desc[0])) | 1716 PLX_DESC_IN_PCI_BIT | 1717 PLX_INTR_TERM_COUNT); 1718 } 1719 } 1720 return 0; 1721} 1722 1723static inline void warn_external_queue(struct comedi_device *dev) 1724{ 1725 comedi_error(dev, 1726 "AO command and AI external channel queue cannot be used simultaneously."); 1727 comedi_error(dev, 1728 "Use internal AI channel queue (channels must be consecutive and use same range/aref)"); 1729} 1730 1731/* 1732 * Attach is called by the Comedi core to configure the driver 1733 * for a particular board. 1734 */ 1735static int attach(struct comedi_device *dev, struct comedi_devconfig *it) 1736{ 1737 struct pci_dev *pcidev = NULL; 1738 int index; 1739 uint32_t local_range, local_decode; 1740 int retval; 1741 1742/* 1743 * Allocate the private structure area. 1744 */ 1745 if (alloc_private(dev, sizeof(struct pcidas64_private)) < 0) 1746 return -ENOMEM; 1747 1748/* 1749 * Probe the device to determine what device in the series it is. 1750 */ 1751 1752 for_each_pci_dev(pcidev) { 1753 /* is it not a computer boards card? */ 1754 if (pcidev->vendor != PCI_VENDOR_ID_COMPUTERBOARDS) 1755 continue; 1756 /* loop through cards supported by this driver */ 1757 for (index = 0; index < ARRAY_SIZE(pcidas64_boards); index++) { 1758 if (pcidas64_boards[index].device_id != pcidev->device) 1759 continue; 1760 /* was a particular bus/slot requested? */ 1761 if (it->options[0] || it->options[1]) { 1762 /* are we on the wrong bus/slot? */ 1763 if (pcidev->bus->number != it->options[0] || 1764 PCI_SLOT(pcidev->devfn) != it->options[1]) { 1765 continue; 1766 } 1767 } 1768 priv(dev)->hw_dev = pcidev; 1769 dev->board_ptr = pcidas64_boards + index; 1770 break; 1771 } 1772 if (dev->board_ptr) 1773 break; 1774 } 1775 1776 if (dev->board_ptr == NULL) { 1777 printk 1778 ("No supported ComputerBoards/MeasurementComputing card found\n"); 1779 return -EIO; 1780 } 1781 1782 dev_dbg(dev->hw_dev, "Found %s on bus %i, slot %i\n", board(dev)->name, 1783 pcidev->bus->number, PCI_SLOT(pcidev->devfn)); 1784 1785 if (comedi_pci_enable(pcidev, driver_cb_pcidas.driver_name)) { 1786 dev_warn(dev->hw_dev, "failed to enable PCI device and request regions\n"); 1787 return -EIO; 1788 } 1789 pci_set_master(pcidev); 1790 1791 /* Initialize dev->board_name */ 1792 dev->board_name = board(dev)->name; 1793 1794 priv(dev)->plx9080_phys_iobase = 1795 pci_resource_start(pcidev, PLX9080_BADDRINDEX); 1796 priv(dev)->main_phys_iobase = 1797 pci_resource_start(pcidev, MAIN_BADDRINDEX); 1798 priv(dev)->dio_counter_phys_iobase = 1799 pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX); 1800 1801 /* remap, won't work with 2.0 kernels but who cares */ 1802 priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase, 1803 pci_resource_len(pcidev, 1804 PLX9080_BADDRINDEX)); 1805 priv(dev)->main_iobase = 1806 ioremap(priv(dev)->main_phys_iobase, 1807 pci_resource_len(pcidev, MAIN_BADDRINDEX)); 1808 priv(dev)->dio_counter_iobase = 1809 ioremap(priv(dev)->dio_counter_phys_iobase, 1810 pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX)); 1811 1812 if (!priv(dev)->plx9080_iobase || !priv(dev)->main_iobase 1813 || !priv(dev)->dio_counter_iobase) { 1814 dev_warn(dev->hw_dev, "failed to remap io memory\n"); 1815 return -ENOMEM; 1816 } 1817 1818 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase); 1819 DEBUG_PRINT(" main remapped to 0x%p\n", priv(dev)->main_iobase); 1820 DEBUG_PRINT(" diocounter remapped to 0x%p\n", 1821 priv(dev)->dio_counter_iobase); 1822 1823 /* figure out what local addresses are */ 1824 local_range = 1825 readl(priv(dev)->plx9080_iobase + PLX_LAS0RNG_REG) & LRNG_MEM_MASK; 1826 local_decode = 1827 readl(priv(dev)->plx9080_iobase + 1828 PLX_LAS0MAP_REG) & local_range & LMAP_MEM_MASK; 1829 priv(dev)->local0_iobase = 1830 ((uint32_t) priv(dev)->main_phys_iobase & ~local_range) | 1831 local_decode; 1832 local_range = 1833 readl(priv(dev)->plx9080_iobase + PLX_LAS1RNG_REG) & LRNG_MEM_MASK; 1834 local_decode = 1835 readl(priv(dev)->plx9080_iobase + 1836 PLX_LAS1MAP_REG) & local_range & LMAP_MEM_MASK; 1837 priv(dev)->local1_iobase = 1838 ((uint32_t) priv(dev)->dio_counter_phys_iobase & ~local_range) | 1839 local_decode; 1840 1841 DEBUG_PRINT(" local 0 io addr 0x%x\n", priv(dev)->local0_iobase); 1842 DEBUG_PRINT(" local 1 io addr 0x%x\n", priv(dev)->local1_iobase); 1843 1844 retval = alloc_and_init_dma_members(dev); 1845 if (retval < 0) 1846 return retval; 1847 1848 priv(dev)->hw_revision = 1849 hw_revision(dev, readw(priv(dev)->main_iobase + HW_STATUS_REG)); 1850 dev_dbg(dev->hw_dev, "stc hardware revision %i\n", 1851 priv(dev)->hw_revision); 1852 init_plx9080(dev); 1853 init_stc_registers(dev); 1854 /* get irq */ 1855 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED, 1856 "cb_pcidas64", dev)) { 1857 dev_dbg(dev->hw_dev, "unable to allocate irq %u\n", 1858 pcidev->irq); 1859 return -EINVAL; 1860 } 1861 dev->irq = pcidev->irq; 1862 dev_dbg(dev->hw_dev, "irq %u\n", dev->irq); 1863 1864 retval = setup_subdevices(dev); 1865 if (retval < 0) 1866 return retval; 1867 1868 1869 return 0; 1870} 1871 1872/* 1873 * _detach is called to deconfigure a device. It should deallocate 1874 * resources. 1875 * This function is also called when _attach() fails, so it should be 1876 * careful not to release resources that were not necessarily 1877 * allocated by _attach(). dev->private and dev->subdevices are 1878 * deallocated automatically by the core. 1879 */ 1880static int detach(struct comedi_device *dev) 1881{ 1882 unsigned int i; 1883 1884 printk("comedi%d: cb_pcidas: remove\n", dev->minor); 1885 1886 if (dev->irq) 1887 free_irq(dev->irq, dev); 1888 if (priv(dev)) { 1889 if (priv(dev)->hw_dev) { 1890 if (priv(dev)->plx9080_iobase) { 1891 disable_plx_interrupts(dev); 1892 iounmap(priv(dev)->plx9080_iobase); 1893 } 1894 if (priv(dev)->main_iobase) 1895 iounmap(priv(dev)->main_iobase); 1896 if (priv(dev)->dio_counter_iobase) 1897 iounmap(priv(dev)->dio_counter_iobase); 1898 /* free pci dma buffers */ 1899 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) { 1900 if (priv(dev)->ai_buffer[i]) 1901 pci_free_consistent(priv(dev)->hw_dev, 1902 DMA_BUFFER_SIZE, 1903 priv(dev)-> 1904 ai_buffer[i], 1905 priv 1906 (dev)->ai_buffer_bus_addr 1907 [i]); 1908 } 1909 for (i = 0; i < AO_DMA_RING_COUNT; i++) { 1910 if (priv(dev)->ao_buffer[i]) 1911 pci_free_consistent(priv(dev)->hw_dev, 1912 DMA_BUFFER_SIZE, 1913 priv(dev)-> 1914 ao_buffer[i], 1915 priv 1916 (dev)->ao_buffer_bus_addr 1917 [i]); 1918 } 1919 /* free dma descriptors */ 1920 if (priv(dev)->ai_dma_desc) 1921 pci_free_consistent(priv(dev)->hw_dev, 1922 sizeof(struct plx_dma_desc) 1923 * 1924 ai_dma_ring_count(board 1925 (dev)), 1926 priv(dev)->ai_dma_desc, 1927 priv(dev)-> 1928 ai_dma_desc_bus_addr); 1929 if (priv(dev)->ao_dma_desc) 1930 pci_free_consistent(priv(dev)->hw_dev, 1931 sizeof(struct plx_dma_desc) 1932 * AO_DMA_RING_COUNT, 1933 priv(dev)->ao_dma_desc, 1934 priv(dev)-> 1935 ao_dma_desc_bus_addr); 1936 if (priv(dev)->main_phys_iobase) 1937 comedi_pci_disable(priv(dev)->hw_dev); 1938 1939 pci_dev_put(priv(dev)->hw_dev); 1940 } 1941 } 1942 if (dev->subdevices) 1943 subdev_8255_cleanup(dev, dev->subdevices + 4); 1944 1945 return 0; 1946} 1947 1948static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1949 struct comedi_insn *insn, unsigned int *data) 1950{ 1951 unsigned int bits = 0, n, i; 1952 unsigned int channel, range, aref; 1953 unsigned long flags; 1954 static const int timeout = 100; 1955 1956 DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec); 1957 channel = CR_CHAN(insn->chanspec); 1958 range = CR_RANGE(insn->chanspec); 1959 aref = CR_AREF(insn->chanspec); 1960 1961 /* disable card's analog input interrupt sources and pacing */ 1962 /* 4020 generates dac done interrupts even though they are disabled */ 1963 disable_ai_pacing(dev); 1964 1965 spin_lock_irqsave(&dev->spinlock, flags); 1966 if (insn->chanspec & CR_ALT_FILTER) 1967 priv(dev)->adc_control1_bits |= ADC_DITHER_BIT; 1968 else 1969 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT; 1970 writew(priv(dev)->adc_control1_bits, 1971 priv(dev)->main_iobase + ADC_CONTROL1_REG); 1972 spin_unlock_irqrestore(&dev->spinlock, flags); 1973 1974 if (board(dev)->layout != LAYOUT_4020) { 1975 /* use internal queue */ 1976 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT; 1977 writew(priv(dev)->hw_config_bits, 1978 priv(dev)->main_iobase + HW_CONFIG_REG); 1979 1980 /* ALT_SOURCE is internal calibration reference */ 1981 if (insn->chanspec & CR_ALT_SOURCE) { 1982 unsigned int cal_en_bit; 1983 1984 DEBUG_PRINT("reading calibration source\n"); 1985 if (board(dev)->layout == LAYOUT_60XX) 1986 cal_en_bit = CAL_EN_60XX_BIT; 1987 else 1988 cal_en_bit = CAL_EN_64XX_BIT; 1989 /* select internal reference source to connect to channel 0 */ 1990 writew(cal_en_bit | 1991 adc_src_bits(priv(dev)->calibration_source), 1992 priv(dev)->main_iobase + CALIBRATION_REG); 1993 } else { 1994 /* make sure internal calibration source is turned off */ 1995 writew(0, priv(dev)->main_iobase + CALIBRATION_REG); 1996 } 1997 /* load internal queue */ 1998 bits = 0; 1999 /* set gain */ 2000 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec)); 2001 /* set single-ended / differential */ 2002 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF); 2003 if (aref == AREF_COMMON) 2004 bits |= ADC_COMMON_BIT; 2005 bits |= adc_chan_bits(channel); 2006 /* set stop channel */ 2007 writew(adc_chan_bits(channel), 2008 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG); 2009 /* set start channel, and rest of settings */ 2010 writew(bits, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG); 2011 } else { 2012 uint8_t old_cal_range_bits = priv(dev)->i2c_cal_range_bits; 2013 2014 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK; 2015 if (insn->chanspec & CR_ALT_SOURCE) { 2016 DEBUG_PRINT("reading calibration source\n"); 2017 priv(dev)->i2c_cal_range_bits |= 2018 adc_src_4020_bits(priv(dev)->calibration_source); 2019 } else { /* select BNC inputs */ 2020 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4); 2021 } 2022 /* select range */ 2023 if (range == 0) 2024 priv(dev)->i2c_cal_range_bits |= attenuate_bit(channel); 2025 else 2026 priv(dev)->i2c_cal_range_bits &= 2027 ~attenuate_bit(channel); 2028 /* update calibration/range i2c register only if necessary, as it is very slow */ 2029 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) { 2030 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits; 2031 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data, 2032 sizeof(i2c_data)); 2033 } 2034 2035 /* 4020 manual asks that sample interval register to be set before writing to convert register. 2036 * Using somewhat arbitrary setting of 4 master clock ticks = 0.1 usec */ 2037 writew(0, 2038 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); 2039 writew(2, 2040 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG); 2041 } 2042 2043 for (n = 0; n < insn->n; n++) { 2044 2045 /* clear adc buffer (inside loop for 4020 sake) */ 2046 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG); 2047 2048 /* trigger conversion, bits sent only matter for 4020 */ 2049 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)), 2050 priv(dev)->main_iobase + ADC_CONVERT_REG); 2051 2052 /* wait for data */ 2053 for (i = 0; i < timeout; i++) { 2054 bits = readw(priv(dev)->main_iobase + HW_STATUS_REG); 2055 DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits)); 2056 if (board(dev)->layout == LAYOUT_4020) { 2057 if (readw(priv(dev)->main_iobase + 2058 ADC_WRITE_PNTR_REG)) 2059 break; 2060 } else { 2061 if (pipe_full_bits(bits)) 2062 break; 2063 } 2064 udelay(1); 2065 } 2066 DEBUG_PRINT(" looped %i times waiting for data\n", i); 2067 if (i == timeout) { 2068 comedi_error(dev, " analog input read insn timed out"); 2069 printk(" status 0x%x\n", bits); 2070 return -ETIME; 2071 } 2072 if (board(dev)->layout == LAYOUT_4020) 2073 data[n] = 2074 readl(priv(dev)->dio_counter_iobase + 2075 ADC_FIFO_REG) & 0xffff; 2076 else 2077 data[n] = 2078 readw(priv(dev)->main_iobase + PIPE1_READ_REG); 2079 } 2080 2081 return n; 2082} 2083 2084static int ai_config_calibration_source(struct comedi_device *dev, 2085 unsigned int *data) 2086{ 2087 unsigned int source = data[1]; 2088 int num_calibration_sources; 2089 2090 if (board(dev)->layout == LAYOUT_60XX) 2091 num_calibration_sources = 16; 2092 else 2093 num_calibration_sources = 8; 2094 if (source >= num_calibration_sources) { 2095 printk("invalid calibration source: %i\n", source); 2096 return -EINVAL; 2097 } 2098 2099 DEBUG_PRINT("setting calibration source to %i\n", source); 2100 priv(dev)->calibration_source = source; 2101 2102 return 2; 2103} 2104 2105static int ai_config_block_size(struct comedi_device *dev, unsigned int *data) 2106{ 2107 int fifo_size; 2108 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo; 2109 unsigned int block_size, requested_block_size; 2110 int retval; 2111 2112 requested_block_size = data[1]; 2113 2114 if (requested_block_size) { 2115 fifo_size = 2116 requested_block_size * fifo->num_segments / bytes_in_sample; 2117 2118 retval = set_ai_fifo_size(dev, fifo_size); 2119 if (retval < 0) 2120 return retval; 2121 2122 } 2123 2124 block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample; 2125 2126 data[1] = block_size; 2127 2128 return 2; 2129} 2130 2131static int ai_config_master_clock_4020(struct comedi_device *dev, 2132 unsigned int *data) 2133{ 2134 unsigned int divisor = data[4]; 2135 int retval = 0; 2136 2137 if (divisor < 2) { 2138 divisor = 2; 2139 retval = -EAGAIN; 2140 } 2141 2142 switch (data[1]) { 2143 case COMEDI_EV_SCAN_BEGIN: 2144 priv(dev)->ext_clock.divisor = divisor; 2145 priv(dev)->ext_clock.chanspec = data[2]; 2146 break; 2147 default: 2148 return -EINVAL; 2149 break; 2150 } 2151 2152 data[4] = divisor; 2153 2154 return retval ? retval : 5; 2155} 2156 2157/* XXX could add support for 60xx series */ 2158static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data) 2159{ 2160 2161 switch (board(dev)->layout) { 2162 case LAYOUT_4020: 2163 return ai_config_master_clock_4020(dev, data); 2164 break; 2165 default: 2166 return -EINVAL; 2167 break; 2168 } 2169 2170 return -EINVAL; 2171} 2172 2173static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s, 2174 struct comedi_insn *insn, unsigned int *data) 2175{ 2176 int id = data[0]; 2177 2178 switch (id) { 2179 case INSN_CONFIG_ALT_SOURCE: 2180 return ai_config_calibration_source(dev, data); 2181 break; 2182 case INSN_CONFIG_BLOCK_SIZE: 2183 return ai_config_block_size(dev, data); 2184 break; 2185 case INSN_CONFIG_TIMER_1: 2186 return ai_config_master_clock(dev, data); 2187 break; 2188 default: 2189 return -EINVAL; 2190 break; 2191 } 2192 return -EINVAL; 2193} 2194 2195static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 2196 struct comedi_cmd *cmd) 2197{ 2198 int err = 0; 2199 int tmp; 2200 unsigned int tmp_arg, tmp_arg2; 2201 int i; 2202 int aref; 2203 unsigned int triggers; 2204 2205 /* step 1: make sure trigger sources are trivially valid */ 2206 2207 tmp = cmd->start_src; 2208 cmd->start_src &= TRIG_NOW | TRIG_EXT; 2209 if (!cmd->start_src || tmp != cmd->start_src) 2210 err++; 2211 2212 tmp = cmd->scan_begin_src; 2213 triggers = TRIG_TIMER; 2214 if (board(dev)->layout == LAYOUT_4020) 2215 triggers |= TRIG_OTHER; 2216 else 2217 triggers |= TRIG_FOLLOW; 2218 cmd->scan_begin_src &= triggers; 2219 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 2220 err++; 2221 2222 tmp = cmd->convert_src; 2223 triggers = TRIG_TIMER; 2224 if (board(dev)->layout == LAYOUT_4020) 2225 triggers |= TRIG_NOW; 2226 else 2227 triggers |= TRIG_EXT; 2228 cmd->convert_src &= triggers; 2229 if (!cmd->convert_src || tmp != cmd->convert_src) 2230 err++; 2231 2232 tmp = cmd->scan_end_src; 2233 cmd->scan_end_src &= TRIG_COUNT; 2234 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 2235 err++; 2236 2237 tmp = cmd->stop_src; 2238 cmd->stop_src &= TRIG_COUNT | TRIG_EXT | TRIG_NONE; 2239 if (!cmd->stop_src || tmp != cmd->stop_src) 2240 err++; 2241 2242 if (err) 2243 return 1; 2244 2245 /* step 2: make sure trigger sources are unique and mutually compatible */ 2246 2247 /* uniqueness check */ 2248 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) 2249 err++; 2250 if (cmd->scan_begin_src != TRIG_TIMER && 2251 cmd->scan_begin_src != TRIG_OTHER && 2252 cmd->scan_begin_src != TRIG_FOLLOW) 2253 err++; 2254 if (cmd->convert_src != TRIG_TIMER && 2255 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW) 2256 err++; 2257 if (cmd->stop_src != TRIG_COUNT && 2258 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT) 2259 err++; 2260 2261 /* compatibility check */ 2262 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER) 2263 err++; 2264 if (cmd->stop_src != TRIG_COUNT && 2265 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT) 2266 err++; 2267 2268 if (err) 2269 return 2; 2270 2271 /* step 3: make sure arguments are trivially compatible */ 2272 2273 if (cmd->convert_src == TRIG_TIMER) { 2274 if (board(dev)->layout == LAYOUT_4020) { 2275 if (cmd->convert_arg) { 2276 cmd->convert_arg = 0; 2277 err++; 2278 } 2279 } else { 2280 if (cmd->convert_arg < board(dev)->ai_speed) { 2281 cmd->convert_arg = board(dev)->ai_speed; 2282 err++; 2283 } 2284 if (cmd->scan_begin_src == TRIG_TIMER) { 2285 /* if scans are timed faster than conversion rate allows */ 2286 if (cmd->convert_arg * cmd->chanlist_len > 2287 cmd->scan_begin_arg) { 2288 cmd->scan_begin_arg = 2289 cmd->convert_arg * 2290 cmd->chanlist_len; 2291 err++; 2292 } 2293 } 2294 } 2295 } 2296 2297 if (!cmd->chanlist_len) { 2298 cmd->chanlist_len = 1; 2299 err++; 2300 } 2301 if (cmd->scan_end_arg != cmd->chanlist_len) { 2302 cmd->scan_end_arg = cmd->chanlist_len; 2303 err++; 2304 } 2305 2306 switch (cmd->stop_src) { 2307 case TRIG_EXT: 2308 break; 2309 case TRIG_COUNT: 2310 if (!cmd->stop_arg) { 2311 cmd->stop_arg = 1; 2312 err++; 2313 } 2314 break; 2315 case TRIG_NONE: 2316 if (cmd->stop_arg != 0) { 2317 cmd->stop_arg = 0; 2318 err++; 2319 } 2320 break; 2321 default: 2322 break; 2323 } 2324 2325 if (err) 2326 return 3; 2327 2328 /* step 4: fix up any arguments */ 2329 2330 if (cmd->convert_src == TRIG_TIMER) { 2331 tmp_arg = cmd->convert_arg; 2332 tmp_arg2 = cmd->scan_begin_arg; 2333 check_adc_timing(dev, cmd); 2334 if (tmp_arg != cmd->convert_arg) 2335 err++; 2336 if (tmp_arg2 != cmd->scan_begin_arg) 2337 err++; 2338 } 2339 2340 if (err) 2341 return 4; 2342 2343 /* make sure user is doesn't change analog reference mid chanlist */ 2344 if (cmd->chanlist) { 2345 aref = CR_AREF(cmd->chanlist[0]); 2346 for (i = 1; i < cmd->chanlist_len; i++) { 2347 if (aref != CR_AREF(cmd->chanlist[i])) { 2348 comedi_error(dev, 2349 "all elements in chanlist must use the same analog reference"); 2350 err++; 2351 break; 2352 } 2353 } 2354 /* check 4020 chanlist */ 2355 if (board(dev)->layout == LAYOUT_4020) { 2356 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]); 2357 for (i = 1; i < cmd->chanlist_len; i++) { 2358 if (CR_CHAN(cmd->chanlist[i]) != 2359 first_channel + i) { 2360 comedi_error(dev, 2361 "chanlist must use consecutive channels"); 2362 err++; 2363 break; 2364 } 2365 } 2366 if (cmd->chanlist_len == 3) { 2367 comedi_error(dev, 2368 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels"); 2369 err++; 2370 } 2371 } 2372 } 2373 2374 if (err) 2375 return 5; 2376 2377 return 0; 2378} 2379 2380static int use_hw_sample_counter(struct comedi_cmd *cmd) 2381{ 2382/* disable for now until I work out a race */ 2383 return 0; 2384 2385 if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value) 2386 return 1; 2387 else 2388 return 0; 2389} 2390 2391static void setup_sample_counters(struct comedi_device *dev, 2392 struct comedi_cmd *cmd) 2393{ 2394 if (cmd->stop_src == TRIG_COUNT) { 2395 /* set software count */ 2396 priv(dev)->ai_count = cmd->stop_arg * cmd->chanlist_len; 2397 } 2398 /* load hardware conversion counter */ 2399 if (use_hw_sample_counter(cmd)) { 2400 writew(cmd->stop_arg & 0xffff, 2401 priv(dev)->main_iobase + ADC_COUNT_LOWER_REG); 2402 writew((cmd->stop_arg >> 16) & 0xff, 2403 priv(dev)->main_iobase + ADC_COUNT_UPPER_REG); 2404 } else { 2405 writew(1, priv(dev)->main_iobase + ADC_COUNT_LOWER_REG); 2406 } 2407} 2408 2409static inline unsigned int dma_transfer_size(struct comedi_device *dev) 2410{ 2411 unsigned int num_samples; 2412 2413 num_samples = 2414 priv(dev)->ai_fifo_segment_length * 2415 board(dev)->ai_fifo->sample_packing_ratio; 2416 if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t)) 2417 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t); 2418 2419 return num_samples; 2420} 2421 2422static void disable_ai_pacing(struct comedi_device *dev) 2423{ 2424 unsigned long flags; 2425 2426 disable_ai_interrupts(dev); 2427 2428 spin_lock_irqsave(&dev->spinlock, flags); 2429 priv(dev)->adc_control1_bits &= ~ADC_SW_GATE_BIT; 2430 writew(priv(dev)->adc_control1_bits, 2431 priv(dev)->main_iobase + ADC_CONTROL1_REG); 2432 spin_unlock_irqrestore(&dev->spinlock, flags); 2433 2434 /* disable pacing, triggering, etc */ 2435 writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT, 2436 priv(dev)->main_iobase + ADC_CONTROL0_REG); 2437} 2438 2439static void disable_ai_interrupts(struct comedi_device *dev) 2440{ 2441 unsigned long flags; 2442 2443 spin_lock_irqsave(&dev->spinlock, flags); 2444 priv(dev)->intr_enable_bits &= 2445 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT & 2446 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT & 2447 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK; 2448 writew(priv(dev)->intr_enable_bits, 2449 priv(dev)->main_iobase + INTR_ENABLE_REG); 2450 spin_unlock_irqrestore(&dev->spinlock, flags); 2451 2452 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits); 2453} 2454 2455static void enable_ai_interrupts(struct comedi_device *dev, 2456 const struct comedi_cmd *cmd) 2457{ 2458 uint32_t bits; 2459 unsigned long flags; 2460 2461 bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT | 2462 EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT; 2463 /* Use pio transfer and interrupt on end of conversion if TRIG_WAKE_EOS flag is set. */ 2464 if (cmd->flags & TRIG_WAKE_EOS) { 2465 /* 4020 doesn't support pio transfers except for fifo dregs */ 2466 if (board(dev)->layout != LAYOUT_4020) 2467 bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT; 2468 } 2469 spin_lock_irqsave(&dev->spinlock, flags); 2470 priv(dev)->intr_enable_bits |= bits; 2471 writew(priv(dev)->intr_enable_bits, 2472 priv(dev)->main_iobase + INTR_ENABLE_REG); 2473 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits); 2474 spin_unlock_irqrestore(&dev->spinlock, flags); 2475} 2476 2477static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev, 2478 const struct comedi_cmd *cmd) 2479{ 2480 /* supposed to load counter with desired divisor minus 3 */ 2481 return cmd->convert_arg / TIMER_BASE - 3; 2482} 2483 2484static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev, 2485 struct comedi_cmd *cmd) 2486{ 2487 uint32_t count; 2488 /* figure out how long we need to delay at end of scan */ 2489 switch (cmd->scan_begin_src) { 2490 case TRIG_TIMER: 2491 count = (cmd->scan_begin_arg - 2492 (cmd->convert_arg * (cmd->chanlist_len - 1))) 2493 / TIMER_BASE; 2494 break; 2495 case TRIG_FOLLOW: 2496 count = cmd->convert_arg / TIMER_BASE; 2497 break; 2498 default: 2499 return 0; 2500 break; 2501 } 2502 return count - 3; 2503} 2504 2505static uint32_t ai_convert_counter_4020(struct comedi_device *dev, 2506 struct comedi_cmd *cmd) 2507{ 2508 unsigned int divisor; 2509 2510 switch (cmd->scan_begin_src) { 2511 case TRIG_TIMER: 2512 divisor = cmd->scan_begin_arg / TIMER_BASE; 2513 break; 2514 case TRIG_OTHER: 2515 divisor = priv(dev)->ext_clock.divisor; 2516 break; 2517 default: /* should never happen */ 2518 comedi_error(dev, "bug! failed to set ai pacing!"); 2519 divisor = 1000; 2520 break; 2521 } 2522 2523 /* supposed to load counter with desired divisor minus 2 for 4020 */ 2524 return divisor - 2; 2525} 2526 2527static void select_master_clock_4020(struct comedi_device *dev, 2528 const struct comedi_cmd *cmd) 2529{ 2530 /* select internal/external master clock */ 2531 priv(dev)->hw_config_bits &= ~MASTER_CLOCK_4020_MASK; 2532 if (cmd->scan_begin_src == TRIG_OTHER) { 2533 int chanspec = priv(dev)->ext_clock.chanspec; 2534 2535 if (CR_CHAN(chanspec)) 2536 priv(dev)->hw_config_bits |= BNC_CLOCK_4020_BITS; 2537 else 2538 priv(dev)->hw_config_bits |= EXT_CLOCK_4020_BITS; 2539 } else { 2540 priv(dev)->hw_config_bits |= INTERNAL_CLOCK_4020_BITS; 2541 } 2542 writew(priv(dev)->hw_config_bits, 2543 priv(dev)->main_iobase + HW_CONFIG_REG); 2544} 2545 2546static void select_master_clock(struct comedi_device *dev, 2547 const struct comedi_cmd *cmd) 2548{ 2549 switch (board(dev)->layout) { 2550 case LAYOUT_4020: 2551 select_master_clock_4020(dev, cmd); 2552 break; 2553 default: 2554 break; 2555 } 2556} 2557 2558static inline void dma_start_sync(struct comedi_device *dev, 2559 unsigned int channel) 2560{ 2561 unsigned long flags; 2562 2563 /* spinlock for plx dma control/status reg */ 2564 spin_lock_irqsave(&dev->spinlock, flags); 2565 if (channel) 2566 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | 2567 PLX_CLEAR_DMA_INTR_BIT, 2568 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG); 2569 else 2570 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | 2571 PLX_CLEAR_DMA_INTR_BIT, 2572 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 2573 spin_unlock_irqrestore(&dev->spinlock, flags); 2574} 2575 2576static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd) 2577{ 2578 uint32_t convert_counter = 0, scan_counter = 0; 2579 2580 check_adc_timing(dev, cmd); 2581 2582 select_master_clock(dev, cmd); 2583 2584 if (board(dev)->layout == LAYOUT_4020) { 2585 convert_counter = ai_convert_counter_4020(dev, cmd); 2586 } else { 2587 convert_counter = ai_convert_counter_6xxx(dev, cmd); 2588 scan_counter = ai_scan_counter_6xxx(dev, cmd); 2589 } 2590 2591 /* load lower 16 bits of convert interval */ 2592 writew(convert_counter & 0xffff, 2593 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG); 2594 DEBUG_PRINT("convert counter 0x%x\n", convert_counter); 2595 /* load upper 8 bits of convert interval */ 2596 writew((convert_counter >> 16) & 0xff, 2597 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG); 2598 /* load lower 16 bits of scan delay */ 2599 writew(scan_counter & 0xffff, 2600 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG); 2601 /* load upper 8 bits of scan delay */ 2602 writew((scan_counter >> 16) & 0xff, 2603 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG); 2604 DEBUG_PRINT("scan counter 0x%x\n", scan_counter); 2605} 2606 2607static int use_internal_queue_6xxx(const struct comedi_cmd *cmd) 2608{ 2609 int i; 2610 for (i = 0; i + 1 < cmd->chanlist_len; i++) { 2611 if (CR_CHAN(cmd->chanlist[i + 1]) != 2612 CR_CHAN(cmd->chanlist[i]) + 1) 2613 return 0; 2614 if (CR_RANGE(cmd->chanlist[i + 1]) != 2615 CR_RANGE(cmd->chanlist[i])) 2616 return 0; 2617 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i])) 2618 return 0; 2619 } 2620 return 1; 2621} 2622 2623static int setup_channel_queue(struct comedi_device *dev, 2624 const struct comedi_cmd *cmd) 2625{ 2626 unsigned short bits; 2627 int i; 2628 2629 if (board(dev)->layout != LAYOUT_4020) { 2630 if (use_internal_queue_6xxx(cmd)) { 2631 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT; 2632 writew(priv(dev)->hw_config_bits, 2633 priv(dev)->main_iobase + HW_CONFIG_REG); 2634 bits = 0; 2635 /* set channel */ 2636 bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0])); 2637 /* set gain */ 2638 bits |= ai_range_bits_6xxx(dev, 2639 CR_RANGE(cmd->chanlist[0])); 2640 /* set single-ended / differential */ 2641 bits |= se_diff_bit_6xxx(dev, 2642 CR_AREF(cmd->chanlist[0]) == 2643 AREF_DIFF); 2644 if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON) 2645 bits |= ADC_COMMON_BIT; 2646 /* set stop channel */ 2647 writew(adc_chan_bits 2648 (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])), 2649 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG); 2650 /* set start channel, and rest of settings */ 2651 writew(bits, 2652 priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG); 2653 } else { 2654 /* use external queue */ 2655 if (dev->write_subdev && dev->write_subdev->busy) { 2656 warn_external_queue(dev); 2657 return -EBUSY; 2658 } 2659 priv(dev)->hw_config_bits |= EXT_QUEUE_BIT; 2660 writew(priv(dev)->hw_config_bits, 2661 priv(dev)->main_iobase + HW_CONFIG_REG); 2662 /* clear DAC buffer to prevent weird interactions */ 2663 writew(0, 2664 priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG); 2665 /* clear queue pointer */ 2666 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG); 2667 /* load external queue */ 2668 for (i = 0; i < cmd->chanlist_len; i++) { 2669 bits = 0; 2670 /* set channel */ 2671 bits |= 2672 adc_chan_bits(CR_CHAN(cmd->chanlist[i])); 2673 /* set gain */ 2674 bits |= ai_range_bits_6xxx(dev, 2675 CR_RANGE(cmd-> 2676 chanlist 2677 [i])); 2678 /* set single-ended / differential */ 2679 bits |= se_diff_bit_6xxx(dev, 2680 CR_AREF(cmd-> 2681 chanlist[i]) == 2682 AREF_DIFF); 2683 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON) 2684 bits |= ADC_COMMON_BIT; 2685 /* mark end of queue */ 2686 if (i == cmd->chanlist_len - 1) 2687 bits |= QUEUE_EOSCAN_BIT | 2688 QUEUE_EOSEQ_BIT; 2689 writew(bits, 2690 priv(dev)->main_iobase + 2691 ADC_QUEUE_FIFO_REG); 2692 DEBUG_PRINT 2693 ("wrote 0x%x to external channel queue\n", 2694 bits); 2695 } 2696 /* doing a queue clear is not specified in board docs, 2697 * but required for reliable operation */ 2698 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG); 2699 /* prime queue holding register */ 2700 writew(0, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG); 2701 } 2702 } else { 2703 unsigned short old_cal_range_bits = 2704 priv(dev)->i2c_cal_range_bits; 2705 2706 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK; 2707 /* select BNC inputs */ 2708 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4); 2709 /* select ranges */ 2710 for (i = 0; i < cmd->chanlist_len; i++) { 2711 unsigned int channel = CR_CHAN(cmd->chanlist[i]); 2712 unsigned int range = CR_RANGE(cmd->chanlist[i]); 2713 2714 if (range == 0) 2715 priv(dev)->i2c_cal_range_bits |= 2716 attenuate_bit(channel); 2717 else 2718 priv(dev)->i2c_cal_range_bits &= 2719 ~attenuate_bit(channel); 2720 } 2721 /* update calibration/range i2c register only if necessary, as it is very slow */ 2722 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) { 2723 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits; 2724 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data, 2725 sizeof(i2c_data)); 2726 } 2727 } 2728 return 0; 2729} 2730 2731static inline void load_first_dma_descriptor(struct comedi_device *dev, 2732 unsigned int dma_channel, 2733 unsigned int descriptor_bits) 2734{ 2735 /* The transfer size, pci address, and local address registers 2736 * are supposedly unused during chained dma, 2737 * but I have found that left over values from last operation 2738 * occasionally cause problems with transfer of first dma 2739 * block. Initializing them to zero seems to fix the problem. */ 2740 if (dma_channel) { 2741 writel(0, 2742 priv(dev)->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG); 2743 writel(0, priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG); 2744 writel(0, 2745 priv(dev)->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG); 2746 writel(descriptor_bits, 2747 priv(dev)->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG); 2748 } else { 2749 writel(0, 2750 priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG); 2751 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG); 2752 writel(0, 2753 priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG); 2754 writel(descriptor_bits, 2755 priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG); 2756 } 2757} 2758 2759static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 2760{ 2761 struct comedi_async *async = s->async; 2762 struct comedi_cmd *cmd = &async->cmd; 2763 uint32_t bits; 2764 unsigned int i; 2765 unsigned long flags; 2766 int retval; 2767 2768 disable_ai_pacing(dev); 2769 abort_dma(dev, 1); 2770 2771 retval = setup_channel_queue(dev, cmd); 2772 if (retval < 0) 2773 return retval; 2774 2775 /* make sure internal calibration source is turned off */ 2776 writew(0, priv(dev)->main_iobase + CALIBRATION_REG); 2777 2778 set_ai_pacing(dev, cmd); 2779 2780 setup_sample_counters(dev, cmd); 2781 2782 enable_ai_interrupts(dev, cmd); 2783 2784 spin_lock_irqsave(&dev->spinlock, flags); 2785 /* set mode, allow conversions through software gate */ 2786 priv(dev)->adc_control1_bits |= ADC_SW_GATE_BIT; 2787 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT; 2788 if (board(dev)->layout != LAYOUT_4020) { 2789 priv(dev)->adc_control1_bits &= ~ADC_MODE_MASK; 2790 if (cmd->convert_src == TRIG_EXT) 2791 priv(dev)->adc_control1_bits |= adc_mode_bits(13); /* good old mode 13 */ 2792 else 2793 priv(dev)->adc_control1_bits |= adc_mode_bits(8); /* mode 8. What else could you need? */ 2794 } else { 2795 priv(dev)->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK; 2796 if (cmd->chanlist_len == 4) 2797 priv(dev)->adc_control1_bits |= FOUR_CHANNEL_4020_BITS; 2798 else if (cmd->chanlist_len == 2) 2799 priv(dev)->adc_control1_bits |= TWO_CHANNEL_4020_BITS; 2800 priv(dev)->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK; 2801 priv(dev)->adc_control1_bits |= 2802 adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0])); 2803 priv(dev)->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK; 2804 priv(dev)->adc_control1_bits |= 2805 adc_hi_chan_4020_bits(CR_CHAN 2806 (cmd-> 2807 chanlist[cmd->chanlist_len - 1])); 2808 } 2809 writew(priv(dev)->adc_control1_bits, 2810 priv(dev)->main_iobase + ADC_CONTROL1_REG); 2811 DEBUG_PRINT("control1 bits 0x%x\n", priv(dev)->adc_control1_bits); 2812 spin_unlock_irqrestore(&dev->spinlock, flags); 2813 2814 /* clear adc buffer */ 2815 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG); 2816 2817 if ((cmd->flags & TRIG_WAKE_EOS) == 0 || 2818 board(dev)->layout == LAYOUT_4020) { 2819 priv(dev)->ai_dma_index = 0; 2820 2821 /* set dma transfer size */ 2822 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) 2823 priv(dev)->ai_dma_desc[i].transfer_size = 2824 cpu_to_le32(dma_transfer_size(dev) * 2825 sizeof(uint16_t)); 2826 2827 /* give location of first dma descriptor */ 2828 load_first_dma_descriptor(dev, 1, 2829 priv(dev)->ai_dma_desc_bus_addr | 2830 PLX_DESC_IN_PCI_BIT | 2831 PLX_INTR_TERM_COUNT | 2832 PLX_XFER_LOCAL_TO_PCI); 2833 2834 dma_start_sync(dev, 1); 2835 } 2836 2837 if (board(dev)->layout == LAYOUT_4020) { 2838 /* set source for external triggers */ 2839 bits = 0; 2840 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg)) 2841 bits |= EXT_START_TRIG_BNC_BIT; 2842 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg)) 2843 bits |= EXT_STOP_TRIG_BNC_BIT; 2844 writew(bits, priv(dev)->main_iobase + DAQ_ATRIG_LOW_4020_REG); 2845 } 2846 2847 spin_lock_irqsave(&dev->spinlock, flags); 2848 2849 /* enable pacing, triggering, etc */ 2850 bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT; 2851 if (cmd->flags & TRIG_WAKE_EOS) 2852 bits |= ADC_DMA_DISABLE_BIT; 2853 /* set start trigger */ 2854 if (cmd->start_src == TRIG_EXT) { 2855 bits |= ADC_START_TRIG_EXT_BITS; 2856 if (cmd->start_arg & CR_INVERT) 2857 bits |= ADC_START_TRIG_FALLING_BIT; 2858 } else if (cmd->start_src == TRIG_NOW) 2859 bits |= ADC_START_TRIG_SOFT_BITS; 2860 if (use_hw_sample_counter(cmd)) 2861 bits |= ADC_SAMPLE_COUNTER_EN_BIT; 2862 writew(bits, priv(dev)->main_iobase + ADC_CONTROL0_REG); 2863 DEBUG_PRINT("control0 bits 0x%x\n", bits); 2864 2865 priv(dev)->ai_cmd_running = 1; 2866 2867 spin_unlock_irqrestore(&dev->spinlock, flags); 2868 2869 /* start acquisition */ 2870 if (cmd->start_src == TRIG_NOW) { 2871 writew(0, priv(dev)->main_iobase + ADC_START_REG); 2872 DEBUG_PRINT("soft trig\n"); 2873 } 2874 2875 return 0; 2876} 2877 2878/* read num_samples from 16 bit wide ai fifo */ 2879static void pio_drain_ai_fifo_16(struct comedi_device *dev) 2880{ 2881 struct comedi_subdevice *s = dev->read_subdev; 2882 struct comedi_async *async = s->async; 2883 struct comedi_cmd *cmd = &async->cmd; 2884 unsigned int i; 2885 uint16_t prepost_bits; 2886 int read_segment, read_index, write_segment, write_index; 2887 int num_samples; 2888 2889 do { 2890 /* get least significant 15 bits */ 2891 read_index = 2892 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff; 2893 write_index = 2894 readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff; 2895 /* Get most significant bits (grey code). Different boards use different code 2896 * so use a scheme that doesn't depend on encoding. This read must 2897 * occur after reading least significant 15 bits to avoid race 2898 * with fifo switching to next segment. */ 2899 prepost_bits = readw(priv(dev)->main_iobase + PREPOST_REG); 2900 2901 /* if read and write pointers are not on the same fifo segment, read to the 2902 * end of the read segment */ 2903 read_segment = adc_upper_read_ptr_code(prepost_bits); 2904 write_segment = adc_upper_write_ptr_code(prepost_bits); 2905 2906 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n", 2907 read_segment, write_segment, read_index, 2908 write_index); 2909 2910 if (read_segment != write_segment) 2911 num_samples = 2912 priv(dev)->ai_fifo_segment_length - read_index; 2913 else 2914 num_samples = write_index - read_index; 2915 2916 if (cmd->stop_src == TRIG_COUNT) { 2917 if (priv(dev)->ai_count == 0) 2918 break; 2919 if (num_samples > priv(dev)->ai_count) 2920 num_samples = priv(dev)->ai_count; 2921 2922 priv(dev)->ai_count -= num_samples; 2923 } 2924 2925 if (num_samples < 0) { 2926 printk(" cb_pcidas64: bug! num_samples < 0\n"); 2927 break; 2928 } 2929 2930 DEBUG_PRINT(" read %i samples from fifo\n", num_samples); 2931 2932 for (i = 0; i < num_samples; i++) { 2933 cfc_write_to_buffer(s, 2934 readw(priv(dev)->main_iobase + 2935 ADC_FIFO_REG)); 2936 } 2937 2938 } while (read_segment != write_segment); 2939} 2940 2941/* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers. 2942 * The pci-4020 hardware only supports 2943 * dma transfers (it only supports the use of pio for draining the last remaining 2944 * points from the fifo when a data acquisition operation has completed). 2945 */ 2946static void pio_drain_ai_fifo_32(struct comedi_device *dev) 2947{ 2948 struct comedi_subdevice *s = dev->read_subdev; 2949 struct comedi_async *async = s->async; 2950 struct comedi_cmd *cmd = &async->cmd; 2951 unsigned int i; 2952 unsigned int max_transfer = 100000; 2953 uint32_t fifo_data; 2954 int write_code = 2955 readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff; 2956 int read_code = 2957 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff; 2958 2959 if (cmd->stop_src == TRIG_COUNT) { 2960 if (max_transfer > priv(dev)->ai_count) 2961 max_transfer = priv(dev)->ai_count; 2962 2963 } 2964 for (i = 0; read_code != write_code && i < max_transfer;) { 2965 fifo_data = readl(priv(dev)->dio_counter_iobase + ADC_FIFO_REG); 2966 cfc_write_to_buffer(s, fifo_data & 0xffff); 2967 i++; 2968 if (i < max_transfer) { 2969 cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff); 2970 i++; 2971 } 2972 read_code = 2973 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff; 2974 } 2975 priv(dev)->ai_count -= i; 2976} 2977 2978/* empty fifo */ 2979static void pio_drain_ai_fifo(struct comedi_device *dev) 2980{ 2981 if (board(dev)->layout == LAYOUT_4020) 2982 pio_drain_ai_fifo_32(dev); 2983 else 2984 pio_drain_ai_fifo_16(dev); 2985} 2986 2987static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel) 2988{ 2989 struct comedi_async *async = dev->read_subdev->async; 2990 uint32_t next_transfer_addr; 2991 int j; 2992 int num_samples = 0; 2993 void __iomem *pci_addr_reg; 2994 2995 if (channel) 2996 pci_addr_reg = 2997 priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG; 2998 else 2999 pci_addr_reg = 3000 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG; 3001 3002 /* loop until we have read all the full buffers */ 3003 for (j = 0, next_transfer_addr = readl(pci_addr_reg); 3004 (next_transfer_addr < 3005 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index] 3006 || next_transfer_addr >= 3007 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index] + 3008 DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board(dev)); j++) { 3009 /* transfer data from dma buffer to comedi buffer */ 3010 num_samples = dma_transfer_size(dev); 3011 if (async->cmd.stop_src == TRIG_COUNT) { 3012 if (num_samples > priv(dev)->ai_count) 3013 num_samples = priv(dev)->ai_count; 3014 priv(dev)->ai_count -= num_samples; 3015 } 3016 cfc_write_array_to_buffer(dev->read_subdev, 3017 priv(dev)->ai_buffer[priv(dev)-> 3018 ai_dma_index], 3019 num_samples * sizeof(uint16_t)); 3020 priv(dev)->ai_dma_index = 3021 (priv(dev)->ai_dma_index + 3022 1) % ai_dma_ring_count(board(dev)); 3023 3024 DEBUG_PRINT("next buffer addr 0x%lx\n", 3025 (unsigned long)priv(dev)-> 3026 ai_buffer_bus_addr[priv(dev)->ai_dma_index]); 3027 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr); 3028 } 3029 /* XXX check for dma ring buffer overrun (use end-of-chain bit to mark last 3030 * unused buffer) */ 3031} 3032 3033static void handle_ai_interrupt(struct comedi_device *dev, 3034 unsigned short status, 3035 unsigned int plx_status) 3036{ 3037 struct comedi_subdevice *s = dev->read_subdev; 3038 struct comedi_async *async = s->async; 3039 struct comedi_cmd *cmd = &async->cmd; 3040 uint8_t dma1_status; 3041 unsigned long flags; 3042 3043 /* check for fifo overrun */ 3044 if (status & ADC_OVERRUN_BIT) { 3045 comedi_error(dev, "fifo overrun"); 3046 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 3047 } 3048 /* spin lock makes sure no one else changes plx dma control reg */ 3049 spin_lock_irqsave(&dev->spinlock, flags); 3050 dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG); 3051 if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */ 3052 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT, 3053 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG); 3054 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status); 3055 3056 if (dma1_status & PLX_DMA_EN_BIT) 3057 drain_dma_buffers(dev, 1); 3058 3059 DEBUG_PRINT(" cleared dma ch1 interrupt\n"); 3060 } 3061 spin_unlock_irqrestore(&dev->spinlock, flags); 3062 3063 if (status & ADC_DONE_BIT) 3064 DEBUG_PRINT("adc done interrupt\n"); 3065 3066 /* drain fifo with pio */ 3067 if ((status & ADC_DONE_BIT) || 3068 ((cmd->flags & TRIG_WAKE_EOS) && 3069 (status & ADC_INTR_PENDING_BIT) && 3070 (board(dev)->layout != LAYOUT_4020))) { 3071 DEBUG_PRINT("pio fifo drain\n"); 3072 spin_lock_irqsave(&dev->spinlock, flags); 3073 if (priv(dev)->ai_cmd_running) { 3074 spin_unlock_irqrestore(&dev->spinlock, flags); 3075 pio_drain_ai_fifo(dev); 3076 } else 3077 spin_unlock_irqrestore(&dev->spinlock, flags); 3078 } 3079 /* if we are have all the data, then quit */ 3080 if ((cmd->stop_src == TRIG_COUNT && (int)priv(dev)->ai_count <= 0) || 3081 (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) { 3082 async->events |= COMEDI_CB_EOA; 3083 } 3084 3085 cfc_handle_events(dev, s); 3086} 3087 3088static inline unsigned int prev_ao_dma_index(struct comedi_device *dev) 3089{ 3090 unsigned int buffer_index; 3091 3092 if (priv(dev)->ao_dma_index == 0) 3093 buffer_index = AO_DMA_RING_COUNT - 1; 3094 else 3095 buffer_index = priv(dev)->ao_dma_index - 1; 3096 return buffer_index; 3097} 3098 3099static int last_ao_dma_load_completed(struct comedi_device *dev) 3100{ 3101 unsigned int buffer_index; 3102 unsigned int transfer_address; 3103 unsigned short dma_status; 3104 3105 buffer_index = prev_ao_dma_index(dev); 3106 dma_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 3107 if ((dma_status & PLX_DMA_DONE_BIT) == 0) 3108 return 0; 3109 3110 transfer_address = 3111 readl(priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG); 3112 if (transfer_address != priv(dev)->ao_buffer_bus_addr[buffer_index]) 3113 return 0; 3114 3115 return 1; 3116} 3117 3118static int ao_stopped_by_error(struct comedi_device *dev, 3119 const struct comedi_cmd *cmd) 3120{ 3121 if (cmd->stop_src == TRIG_NONE) 3122 return 1; 3123 if (cmd->stop_src == TRIG_COUNT) { 3124 if (priv(dev)->ao_count) 3125 return 1; 3126 if (last_ao_dma_load_completed(dev) == 0) 3127 return 1; 3128 } 3129 return 0; 3130} 3131 3132static inline int ao_dma_needs_restart(struct comedi_device *dev, 3133 unsigned short dma_status) 3134{ 3135 if ((dma_status & PLX_DMA_DONE_BIT) == 0 || 3136 (dma_status & PLX_DMA_EN_BIT) == 0) 3137 return 0; 3138 if (last_ao_dma_load_completed(dev)) 3139 return 0; 3140 3141 return 1; 3142} 3143 3144static void restart_ao_dma(struct comedi_device *dev) 3145{ 3146 unsigned int dma_desc_bits; 3147 3148 dma_desc_bits = 3149 readl(priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG); 3150 dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT; 3151 DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits); 3152 load_first_dma_descriptor(dev, 0, dma_desc_bits); 3153 3154 dma_start_sync(dev, 0); 3155} 3156 3157static void handle_ao_interrupt(struct comedi_device *dev, 3158 unsigned short status, unsigned int plx_status) 3159{ 3160 struct comedi_subdevice *s = dev->write_subdev; 3161 struct comedi_async *async; 3162 struct comedi_cmd *cmd; 3163 uint8_t dma0_status; 3164 unsigned long flags; 3165 3166 /* board might not support ao, in which case write_subdev is NULL */ 3167 if (s == NULL) 3168 return; 3169 async = s->async; 3170 cmd = &async->cmd; 3171 3172 /* spin lock makes sure no one else changes plx dma control reg */ 3173 spin_lock_irqsave(&dev->spinlock, flags); 3174 dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 3175 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */ 3176 if ((dma0_status & PLX_DMA_EN_BIT) 3177 && !(dma0_status & PLX_DMA_DONE_BIT)) 3178 writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT, 3179 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 3180 else 3181 writeb(PLX_CLEAR_DMA_INTR_BIT, 3182 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 3183 spin_unlock_irqrestore(&dev->spinlock, flags); 3184 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status); 3185 if (dma0_status & PLX_DMA_EN_BIT) { 3186 load_ao_dma(dev, cmd); 3187 /* try to recover from dma end-of-chain event */ 3188 if (ao_dma_needs_restart(dev, dma0_status)) 3189 restart_ao_dma(dev); 3190 } 3191 DEBUG_PRINT(" cleared dma ch0 interrupt\n"); 3192 } else 3193 spin_unlock_irqrestore(&dev->spinlock, flags); 3194 3195 if ((status & DAC_DONE_BIT)) { 3196 async->events |= COMEDI_CB_EOA; 3197 if (ao_stopped_by_error(dev, cmd)) 3198 async->events |= COMEDI_CB_ERROR; 3199 DEBUG_PRINT("plx dma0 desc reg 0x%x\n", 3200 readl(priv(dev)->plx9080_iobase + 3201 PLX_DMA0_DESCRIPTOR_REG)); 3202 DEBUG_PRINT("plx dma0 address reg 0x%x\n", 3203 readl(priv(dev)->plx9080_iobase + 3204 PLX_DMA0_PCI_ADDRESS_REG)); 3205 } 3206 cfc_handle_events(dev, s); 3207} 3208 3209static irqreturn_t handle_interrupt(int irq, void *d) 3210{ 3211 struct comedi_device *dev = d; 3212 unsigned short status; 3213 uint32_t plx_status; 3214 uint32_t plx_bits; 3215 3216 plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG); 3217 status = readw(priv(dev)->main_iobase + HW_STATUS_REG); 3218 3219 DEBUG_PRINT("cb_pcidas64: hw status 0x%x ", status); 3220 DEBUG_PRINT("plx status 0x%x\n", plx_status); 3221 3222 /* an interrupt before all the postconfig stuff gets done could 3223 * cause a NULL dereference if we continue through the 3224 * interrupt handler */ 3225 if (dev->attached == 0) { 3226 DEBUG_PRINT("cb_pcidas64: premature interrupt, ignoring", 3227 status); 3228 return IRQ_HANDLED; 3229 } 3230 handle_ai_interrupt(dev, status, plx_status); 3231 handle_ao_interrupt(dev, status, plx_status); 3232 3233 /* clear possible plx9080 interrupt sources */ 3234 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */ 3235 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG); 3236 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG); 3237 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits); 3238 } 3239 3240 DEBUG_PRINT("exiting handler\n"); 3241 3242 return IRQ_HANDLED; 3243} 3244 3245static void abort_dma(struct comedi_device *dev, unsigned int channel) 3246{ 3247 unsigned long flags; 3248 3249 /* spinlock for plx dma control/status reg */ 3250 spin_lock_irqsave(&dev->spinlock, flags); 3251 3252 plx9080_abort_dma(priv(dev)->plx9080_iobase, channel); 3253 3254 spin_unlock_irqrestore(&dev->spinlock, flags); 3255} 3256 3257static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 3258{ 3259 unsigned long flags; 3260 3261 spin_lock_irqsave(&dev->spinlock, flags); 3262 if (priv(dev)->ai_cmd_running == 0) { 3263 spin_unlock_irqrestore(&dev->spinlock, flags); 3264 return 0; 3265 } 3266 priv(dev)->ai_cmd_running = 0; 3267 spin_unlock_irqrestore(&dev->spinlock, flags); 3268 3269 disable_ai_pacing(dev); 3270 3271 abort_dma(dev, 1); 3272 3273 DEBUG_PRINT("ai canceled\n"); 3274 return 0; 3275} 3276 3277static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 3278 struct comedi_insn *insn, unsigned int *data) 3279{ 3280 int chan = CR_CHAN(insn->chanspec); 3281 int range = CR_RANGE(insn->chanspec); 3282 3283 /* do some initializing */ 3284 writew(0, priv(dev)->main_iobase + DAC_CONTROL0_REG); 3285 3286 /* set range */ 3287 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, chan, range); 3288 writew(priv(dev)->dac_control1_bits, 3289 priv(dev)->main_iobase + DAC_CONTROL1_REG); 3290 3291 /* write to channel */ 3292 if (board(dev)->layout == LAYOUT_4020) { 3293 writew(data[0] & 0xff, 3294 priv(dev)->main_iobase + dac_lsb_4020_reg(chan)); 3295 writew((data[0] >> 8) & 0xf, 3296 priv(dev)->main_iobase + dac_msb_4020_reg(chan)); 3297 } else { 3298 writew(data[0], priv(dev)->main_iobase + dac_convert_reg(chan)); 3299 } 3300 3301 /* remember output value */ 3302 priv(dev)->ao_value[chan] = data[0]; 3303 3304 return 1; 3305} 3306 3307static int ao_readback_insn(struct comedi_device *dev, 3308 struct comedi_subdevice *s, 3309 struct comedi_insn *insn, unsigned int *data) 3310{ 3311 data[0] = priv(dev)->ao_value[CR_CHAN(insn->chanspec)]; 3312 3313 return 1; 3314} 3315 3316static void set_dac_control0_reg(struct comedi_device *dev, 3317 const struct comedi_cmd *cmd) 3318{ 3319 unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT | 3320 WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT; 3321 3322 if (cmd->start_src == TRIG_EXT) { 3323 bits |= WAVEFORM_TRIG_EXT_BITS; 3324 if (cmd->start_arg & CR_INVERT) 3325 bits |= WAVEFORM_TRIG_FALLING_BIT; 3326 } else { 3327 bits |= WAVEFORM_TRIG_SOFT_BITS; 3328 } 3329 if (cmd->scan_begin_src == TRIG_EXT) { 3330 bits |= DAC_EXT_UPDATE_ENABLE_BIT; 3331 if (cmd->scan_begin_arg & CR_INVERT) 3332 bits |= DAC_EXT_UPDATE_FALLING_BIT; 3333 } 3334 writew(bits, priv(dev)->main_iobase + DAC_CONTROL0_REG); 3335} 3336 3337static void set_dac_control1_reg(struct comedi_device *dev, 3338 const struct comedi_cmd *cmd) 3339{ 3340 int i; 3341 3342 for (i = 0; i < cmd->chanlist_len; i++) { 3343 int channel, range; 3344 3345 channel = CR_CHAN(cmd->chanlist[i]); 3346 range = CR_RANGE(cmd->chanlist[i]); 3347 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, channel, 3348 range); 3349 } 3350 priv(dev)->dac_control1_bits |= DAC_SW_GATE_BIT; 3351 writew(priv(dev)->dac_control1_bits, 3352 priv(dev)->main_iobase + DAC_CONTROL1_REG); 3353} 3354 3355static void set_dac_select_reg(struct comedi_device *dev, 3356 const struct comedi_cmd *cmd) 3357{ 3358 uint16_t bits; 3359 unsigned int first_channel, last_channel; 3360 3361 first_channel = CR_CHAN(cmd->chanlist[0]); 3362 last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); 3363 if (last_channel < first_channel) 3364 comedi_error(dev, "bug! last ao channel < first ao channel"); 3365 3366 bits = (first_channel & 0x7) | (last_channel & 0x7) << 3; 3367 3368 writew(bits, priv(dev)->main_iobase + DAC_SELECT_REG); 3369} 3370 3371static void set_dac_interval_regs(struct comedi_device *dev, 3372 const struct comedi_cmd *cmd) 3373{ 3374 unsigned int divisor; 3375 3376 if (cmd->scan_begin_src != TRIG_TIMER) 3377 return; 3378 3379 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags); 3380 if (divisor > max_counter_value) { 3381 comedi_error(dev, "bug! ao divisor too big"); 3382 divisor = max_counter_value; 3383 } 3384 writew(divisor & 0xffff, 3385 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG); 3386 writew((divisor >> 16) & 0xff, 3387 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG); 3388} 3389 3390static unsigned int load_ao_dma_buffer(struct comedi_device *dev, 3391 const struct comedi_cmd *cmd) 3392{ 3393 unsigned int num_bytes, buffer_index, prev_buffer_index; 3394 unsigned int next_bits; 3395 3396 buffer_index = priv(dev)->ao_dma_index; 3397 prev_buffer_index = prev_ao_dma_index(dev); 3398 3399 DEBUG_PRINT("attempting to load ao buffer %i (0x%x)\n", buffer_index, 3400 priv(dev)->ao_buffer_bus_addr[buffer_index]); 3401 3402 num_bytes = comedi_buf_read_n_available(dev->write_subdev->async); 3403 if (num_bytes > DMA_BUFFER_SIZE) 3404 num_bytes = DMA_BUFFER_SIZE; 3405 if (cmd->stop_src == TRIG_COUNT && num_bytes > priv(dev)->ao_count) 3406 num_bytes = priv(dev)->ao_count; 3407 num_bytes -= num_bytes % bytes_in_sample; 3408 3409 if (num_bytes == 0) 3410 return 0; 3411 3412 DEBUG_PRINT("loading %i bytes\n", num_bytes); 3413 3414 num_bytes = cfc_read_array_from_buffer(dev->write_subdev, 3415 priv(dev)-> 3416 ao_buffer[buffer_index], 3417 num_bytes); 3418 priv(dev)->ao_dma_desc[buffer_index].transfer_size = 3419 cpu_to_le32(num_bytes); 3420 /* set end of chain bit so we catch underruns */ 3421 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[buffer_index].next); 3422 next_bits |= PLX_END_OF_CHAIN_BIT; 3423 priv(dev)->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits); 3424 /* clear end of chain bit on previous buffer now that we have set it 3425 * for the last buffer */ 3426 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[prev_buffer_index].next); 3427 next_bits &= ~PLX_END_OF_CHAIN_BIT; 3428 priv(dev)->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits); 3429 3430 priv(dev)->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT; 3431 priv(dev)->ao_count -= num_bytes; 3432 3433 return num_bytes; 3434} 3435 3436static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd) 3437{ 3438 unsigned int num_bytes; 3439 unsigned int next_transfer_addr; 3440 void __iomem *pci_addr_reg = 3441 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG; 3442 unsigned int buffer_index; 3443 3444 do { 3445 buffer_index = priv(dev)->ao_dma_index; 3446 /* don't overwrite data that hasn't been transferred yet */ 3447 next_transfer_addr = readl(pci_addr_reg); 3448 if (next_transfer_addr >= 3449 priv(dev)->ao_buffer_bus_addr[buffer_index] 3450 && next_transfer_addr < 3451 priv(dev)->ao_buffer_bus_addr[buffer_index] + 3452 DMA_BUFFER_SIZE) 3453 return; 3454 num_bytes = load_ao_dma_buffer(dev, cmd); 3455 } while (num_bytes >= DMA_BUFFER_SIZE); 3456} 3457 3458static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd) 3459{ 3460 unsigned int num_bytes; 3461 int i; 3462 3463 /* clear queue pointer too, since external queue has 3464 * weird interactions with ao fifo */ 3465 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG); 3466 writew(0, priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG); 3467 3468 num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample; 3469 if (cmd->stop_src == TRIG_COUNT && 3470 num_bytes / bytes_in_sample > priv(dev)->ao_count) 3471 num_bytes = priv(dev)->ao_count * bytes_in_sample; 3472 num_bytes = cfc_read_array_from_buffer(dev->write_subdev, 3473 priv(dev)->ao_bounce_buffer, 3474 num_bytes); 3475 for (i = 0; i < num_bytes / bytes_in_sample; i++) { 3476 writew(priv(dev)->ao_bounce_buffer[i], 3477 priv(dev)->main_iobase + DAC_FIFO_REG); 3478 } 3479 priv(dev)->ao_count -= num_bytes / bytes_in_sample; 3480 if (cmd->stop_src == TRIG_COUNT && priv(dev)->ao_count == 0) 3481 return 0; 3482 num_bytes = load_ao_dma_buffer(dev, cmd); 3483 if (num_bytes == 0) 3484 return -1; 3485 if (num_bytes >= DMA_BUFFER_SIZE) ; 3486 load_ao_dma(dev, cmd); 3487 3488 dma_start_sync(dev, 0); 3489 3490 return 0; 3491} 3492 3493static inline int external_ai_queue_in_use(struct comedi_device *dev) 3494{ 3495 if (dev->read_subdev->busy) 3496 return 0; 3497 if (board(dev)->layout == LAYOUT_4020) 3498 return 0; 3499 else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd)) 3500 return 0; 3501 return 1; 3502} 3503 3504static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 3505{ 3506 struct comedi_cmd *cmd = &s->async->cmd; 3507 3508 if (external_ai_queue_in_use(dev)) { 3509 warn_external_queue(dev); 3510 return -EBUSY; 3511 } 3512 /* disable analog output system during setup */ 3513 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG); 3514 3515 priv(dev)->ao_dma_index = 0; 3516 priv(dev)->ao_count = cmd->stop_arg * cmd->chanlist_len; 3517 3518 set_dac_select_reg(dev, cmd); 3519 set_dac_interval_regs(dev, cmd); 3520 load_first_dma_descriptor(dev, 0, priv(dev)->ao_dma_desc_bus_addr | 3521 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT); 3522 3523 set_dac_control1_reg(dev, cmd); 3524 s->async->inttrig = ao_inttrig; 3525 3526 return 0; 3527} 3528 3529static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 3530 unsigned int trig_num) 3531{ 3532 struct comedi_cmd *cmd = &s->async->cmd; 3533 int retval; 3534 3535 if (trig_num != 0) 3536 return -EINVAL; 3537 3538 retval = prep_ao_dma(dev, cmd); 3539 if (retval < 0) 3540 return -EPIPE; 3541 3542 set_dac_control0_reg(dev, cmd); 3543 3544 if (cmd->start_src == TRIG_INT) 3545 writew(0, priv(dev)->main_iobase + DAC_START_REG); 3546 3547 s->async->inttrig = NULL; 3548 3549 return 0; 3550} 3551 3552static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 3553 struct comedi_cmd *cmd) 3554{ 3555 int err = 0; 3556 int tmp; 3557 unsigned int tmp_arg; 3558 int i; 3559 3560 /* step 1: make sure trigger sources are trivially valid */ 3561 3562 tmp = cmd->start_src; 3563 cmd->start_src &= TRIG_INT | TRIG_EXT; 3564 if (!cmd->start_src || tmp != cmd->start_src) 3565 err++; 3566 3567 tmp = cmd->scan_begin_src; 3568 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; 3569 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 3570 err++; 3571 3572 tmp = cmd->convert_src; 3573 cmd->convert_src &= TRIG_NOW; 3574 if (!cmd->convert_src || tmp != cmd->convert_src) 3575 err++; 3576 3577 tmp = cmd->scan_end_src; 3578 cmd->scan_end_src &= TRIG_COUNT; 3579 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 3580 err++; 3581 3582 tmp = cmd->stop_src; 3583 cmd->stop_src &= TRIG_NONE; 3584 if (!cmd->stop_src || tmp != cmd->stop_src) 3585 err++; 3586 3587 if (err) 3588 return 1; 3589 3590 /* step 2: make sure trigger sources are unique and mutually compatible */ 3591 3592 /* uniqueness check */ 3593 if (cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT) 3594 err++; 3595 if (cmd->scan_begin_src != TRIG_TIMER && 3596 cmd->scan_begin_src != TRIG_EXT) 3597 err++; 3598 3599 /* compatibility check */ 3600 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER) 3601 err++; 3602 if (cmd->stop_src != TRIG_COUNT && 3603 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT) 3604 err++; 3605 3606 if (err) 3607 return 2; 3608 3609 /* step 3: make sure arguments are trivially compatible */ 3610 3611 if (cmd->scan_begin_src == TRIG_TIMER) { 3612 if (cmd->scan_begin_arg < board(dev)->ao_scan_speed) { 3613 cmd->scan_begin_arg = board(dev)->ao_scan_speed; 3614 err++; 3615 } 3616 if (get_ao_divisor(cmd->scan_begin_arg, 3617 cmd->flags) > max_counter_value) { 3618 cmd->scan_begin_arg = 3619 (max_counter_value + 2) * TIMER_BASE; 3620 err++; 3621 } 3622 } 3623 3624 if (!cmd->chanlist_len) { 3625 cmd->chanlist_len = 1; 3626 err++; 3627 } 3628 if (cmd->scan_end_arg != cmd->chanlist_len) { 3629 cmd->scan_end_arg = cmd->chanlist_len; 3630 err++; 3631 } 3632 3633 if (err) 3634 return 3; 3635 3636 /* step 4: fix up any arguments */ 3637 3638 if (cmd->scan_begin_src == TRIG_TIMER) { 3639 tmp_arg = cmd->scan_begin_arg; 3640 cmd->scan_begin_arg = 3641 get_divisor(cmd->scan_begin_arg, cmd->flags) * TIMER_BASE; 3642 if (tmp_arg != cmd->scan_begin_arg) 3643 err++; 3644 } 3645 3646 if (err) 3647 return 4; 3648 3649 if (cmd->chanlist) { 3650 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]); 3651 for (i = 1; i < cmd->chanlist_len; i++) { 3652 if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) { 3653 comedi_error(dev, 3654 "chanlist must use consecutive channels"); 3655 err++; 3656 break; 3657 } 3658 } 3659 } 3660 3661 if (err) 3662 return 5; 3663 3664 return 0; 3665} 3666 3667static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 3668{ 3669 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG); 3670 abort_dma(dev, 0); 3671 return 0; 3672} 3673 3674static int dio_callback(int dir, int port, int data, unsigned long arg) 3675{ 3676 void __iomem *iobase = (void __iomem *)arg; 3677 if (dir) { 3678 writeb(data, iobase + port); 3679 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port); 3680 return 0; 3681 } else { 3682 return readb(iobase + port); 3683 } 3684} 3685 3686static int dio_callback_4020(int dir, int port, int data, unsigned long arg) 3687{ 3688 void __iomem *iobase = (void __iomem *)arg; 3689 if (dir) { 3690 writew(data, iobase + 2 * port); 3691 return 0; 3692 } else { 3693 return readw(iobase + 2 * port); 3694 } 3695} 3696 3697static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s, 3698 struct comedi_insn *insn, unsigned int *data) 3699{ 3700 unsigned int bits; 3701 3702 bits = readb(priv(dev)->dio_counter_iobase + DI_REG); 3703 bits &= 0xf; 3704 data[1] = bits; 3705 data[0] = 0; 3706 3707 return 2; 3708} 3709 3710static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s, 3711 struct comedi_insn *insn, unsigned int *data) 3712{ 3713 data[0] &= 0xf; 3714 /* zero bits we are going to change */ 3715 s->state &= ~data[0]; 3716 /* set new bits */ 3717 s->state |= data[0] & data[1]; 3718 3719 writeb(s->state, priv(dev)->dio_counter_iobase + DO_REG); 3720 3721 data[1] = s->state; 3722 3723 return 2; 3724} 3725 3726static int dio_60xx_config_insn(struct comedi_device *dev, 3727 struct comedi_subdevice *s, 3728 struct comedi_insn *insn, unsigned int *data) 3729{ 3730 unsigned int mask; 3731 3732 mask = 1 << CR_CHAN(insn->chanspec); 3733 3734 switch (data[0]) { 3735 case INSN_CONFIG_DIO_INPUT: 3736 s->io_bits &= ~mask; 3737 break; 3738 case INSN_CONFIG_DIO_OUTPUT: 3739 s->io_bits |= mask; 3740 break; 3741 case INSN_CONFIG_DIO_QUERY: 3742 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT; 3743 return 2; 3744 default: 3745 return -EINVAL; 3746 } 3747 3748 writeb(s->io_bits, 3749 priv(dev)->dio_counter_iobase + DIO_DIRECTION_60XX_REG); 3750 3751 return 1; 3752} 3753 3754static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s, 3755 struct comedi_insn *insn, unsigned int *data) 3756{ 3757 if (data[0]) { 3758 s->state &= ~data[0]; 3759 s->state |= (data[0] & data[1]); 3760 writeb(s->state, 3761 priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG); 3762 } 3763 3764 data[1] = readb(priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG); 3765 3766 return 2; 3767} 3768 3769static void caldac_write(struct comedi_device *dev, unsigned int channel, 3770 unsigned int value) 3771{ 3772 priv(dev)->caldac_state[channel] = value; 3773 3774 switch (board(dev)->layout) { 3775 case LAYOUT_60XX: 3776 case LAYOUT_64XX: 3777 caldac_8800_write(dev, channel, value); 3778 break; 3779 case LAYOUT_4020: 3780 caldac_i2c_write(dev, channel, value); 3781 break; 3782 default: 3783 break; 3784 } 3785} 3786 3787static int calib_write_insn(struct comedi_device *dev, 3788 struct comedi_subdevice *s, 3789 struct comedi_insn *insn, unsigned int *data) 3790{ 3791 int channel = CR_CHAN(insn->chanspec); 3792 3793 /* return immediately if setting hasn't changed, since 3794 * programming these things is slow */ 3795 if (priv(dev)->caldac_state[channel] == data[0]) 3796 return 1; 3797 3798 caldac_write(dev, channel, data[0]); 3799 3800 return 1; 3801} 3802 3803static int calib_read_insn(struct comedi_device *dev, 3804 struct comedi_subdevice *s, struct comedi_insn *insn, 3805 unsigned int *data) 3806{ 3807 unsigned int channel = CR_CHAN(insn->chanspec); 3808 3809 data[0] = priv(dev)->caldac_state[channel]; 3810 3811 return 1; 3812} 3813 3814static void ad8402_write(struct comedi_device *dev, unsigned int channel, 3815 unsigned int value) 3816{ 3817 static const int bitstream_length = 10; 3818 unsigned int bit, register_bits; 3819 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff); 3820 static const int ad8402_udelay = 1; 3821 3822 priv(dev)->ad8402_state[channel] = value; 3823 3824 register_bits = SELECT_8402_64XX_BIT; 3825 udelay(ad8402_udelay); 3826 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG); 3827 3828 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { 3829 if (bitstream & bit) 3830 register_bits |= SERIAL_DATA_IN_BIT; 3831 else 3832 register_bits &= ~SERIAL_DATA_IN_BIT; 3833 udelay(ad8402_udelay); 3834 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG); 3835 udelay(ad8402_udelay); 3836 writew(register_bits | SERIAL_CLOCK_BIT, 3837 priv(dev)->main_iobase + CALIBRATION_REG); 3838 } 3839 3840 udelay(ad8402_udelay); 3841 writew(0, priv(dev)->main_iobase + CALIBRATION_REG); 3842} 3843 3844/* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */ 3845static int ad8402_write_insn(struct comedi_device *dev, 3846 struct comedi_subdevice *s, 3847 struct comedi_insn *insn, unsigned int *data) 3848{ 3849 int channel = CR_CHAN(insn->chanspec); 3850 3851 /* return immediately if setting hasn't changed, since 3852 * programming these things is slow */ 3853 if (priv(dev)->ad8402_state[channel] == data[0]) 3854 return 1; 3855 3856 priv(dev)->ad8402_state[channel] = data[0]; 3857 3858 ad8402_write(dev, channel, data[0]); 3859 3860 return 1; 3861} 3862 3863static int ad8402_read_insn(struct comedi_device *dev, 3864 struct comedi_subdevice *s, 3865 struct comedi_insn *insn, unsigned int *data) 3866{ 3867 unsigned int channel = CR_CHAN(insn->chanspec); 3868 3869 data[0] = priv(dev)->ad8402_state[channel]; 3870 3871 return 1; 3872} 3873 3874static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) 3875{ 3876 static const int bitstream_length = 11; 3877 static const int read_command = 0x6; 3878 unsigned int bitstream = (read_command << 8) | address; 3879 unsigned int bit; 3880 void __iomem * const plx_control_addr = 3881 priv(dev)->plx9080_iobase + PLX_CONTROL_REG; 3882 uint16_t value; 3883 static const int value_length = 16; 3884 static const int eeprom_udelay = 1; 3885 3886 udelay(eeprom_udelay); 3887 priv(dev)->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS; 3888 /* make sure we don't send anything to the i2c bus on 4020 */ 3889 priv(dev)->plx_control_bits |= CTL_USERO; 3890 writel(priv(dev)->plx_control_bits, plx_control_addr); 3891 /* activate serial eeprom */ 3892 udelay(eeprom_udelay); 3893 priv(dev)->plx_control_bits |= CTL_EE_CS; 3894 writel(priv(dev)->plx_control_bits, plx_control_addr); 3895 3896 /* write read command and desired memory address */ 3897 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { 3898 /* set bit to be written */ 3899 udelay(eeprom_udelay); 3900 if (bitstream & bit) 3901 priv(dev)->plx_control_bits |= CTL_EE_W; 3902 else 3903 priv(dev)->plx_control_bits &= ~CTL_EE_W; 3904 writel(priv(dev)->plx_control_bits, plx_control_addr); 3905 /* clock in bit */ 3906 udelay(eeprom_udelay); 3907 priv(dev)->plx_control_bits |= CTL_EE_CLK; 3908 writel(priv(dev)->plx_control_bits, plx_control_addr); 3909 udelay(eeprom_udelay); 3910 priv(dev)->plx_control_bits &= ~CTL_EE_CLK; 3911 writel(priv(dev)->plx_control_bits, plx_control_addr); 3912 } 3913 /* read back value from eeprom memory location */ 3914 value = 0; 3915 for (bit = 1 << (value_length - 1); bit; bit >>= 1) { 3916 /* clock out bit */ 3917 udelay(eeprom_udelay); 3918 priv(dev)->plx_control_bits |= CTL_EE_CLK; 3919 writel(priv(dev)->plx_control_bits, plx_control_addr); 3920 udelay(eeprom_udelay); 3921 priv(dev)->plx_control_bits &= ~CTL_EE_CLK; 3922 writel(priv(dev)->plx_control_bits, plx_control_addr); 3923 udelay(eeprom_udelay); 3924 if (readl(plx_control_addr) & CTL_EE_R) 3925 value |= bit; 3926 } 3927 3928 /* deactivate eeprom serial input */ 3929 udelay(eeprom_udelay); 3930 priv(dev)->plx_control_bits &= ~CTL_EE_CS; 3931 writel(priv(dev)->plx_control_bits, plx_control_addr); 3932 3933 return value; 3934} 3935 3936static int eeprom_read_insn(struct comedi_device *dev, 3937 struct comedi_subdevice *s, 3938 struct comedi_insn *insn, unsigned int *data) 3939{ 3940 data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec)); 3941 3942 return 1; 3943} 3944 3945/* utility function that rounds desired timing to an achievable time, and 3946 * sets cmd members appropriately. 3947 * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number 3948 */ 3949static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) 3950{ 3951 unsigned int convert_divisor = 0, scan_divisor; 3952 static const int min_convert_divisor = 3; 3953 static const int max_convert_divisor = 3954 max_counter_value + min_convert_divisor; 3955 static const int min_scan_divisor_4020 = 2; 3956 unsigned long long max_scan_divisor, min_scan_divisor; 3957 3958 if (cmd->convert_src == TRIG_TIMER) { 3959 if (board(dev)->layout == LAYOUT_4020) { 3960 cmd->convert_arg = 0; 3961 } else { 3962 convert_divisor = 3963 get_divisor(cmd->convert_arg, cmd->flags); 3964 if (convert_divisor > max_convert_divisor) 3965 convert_divisor = max_convert_divisor; 3966 if (convert_divisor < min_convert_divisor) 3967 convert_divisor = min_convert_divisor; 3968 cmd->convert_arg = convert_divisor * TIMER_BASE; 3969 } 3970 } else if (cmd->convert_src == TRIG_NOW) 3971 cmd->convert_arg = 0; 3972 3973 if (cmd->scan_begin_src == TRIG_TIMER) { 3974 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags); 3975 if (cmd->convert_src == TRIG_TIMER) { 3976 /* XXX check for integer overflows */ 3977 min_scan_divisor = convert_divisor * cmd->chanlist_len; 3978 max_scan_divisor = 3979 (convert_divisor * cmd->chanlist_len - 1) + 3980 max_counter_value; 3981 } else { 3982 min_scan_divisor = min_scan_divisor_4020; 3983 max_scan_divisor = max_counter_value + min_scan_divisor; 3984 } 3985 if (scan_divisor > max_scan_divisor) 3986 scan_divisor = max_scan_divisor; 3987 if (scan_divisor < min_scan_divisor) 3988 scan_divisor = min_scan_divisor; 3989 cmd->scan_begin_arg = scan_divisor * TIMER_BASE; 3990 } 3991 3992 return; 3993} 3994 3995/* Gets nearest achievable timing given master clock speed, does not 3996 * take into account possible minimum/maximum divisor values. Used 3997 * by other timing checking functions. */ 3998static unsigned int get_divisor(unsigned int ns, unsigned int flags) 3999{ 4000 unsigned int divisor; 4001 4002 switch (flags & TRIG_ROUND_MASK) { 4003 case TRIG_ROUND_UP: 4004 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE; 4005 break; 4006 case TRIG_ROUND_DOWN: 4007 divisor = ns / TIMER_BASE; 4008 break; 4009 case TRIG_ROUND_NEAREST: 4010 default: 4011 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE; 4012 break; 4013 } 4014 return divisor; 4015} 4016 4017static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags) 4018{ 4019 return get_divisor(ns, flags) - 2; 4020} 4021 4022/* adjusts the size of hardware fifo (which determines block size for dma xfers) */ 4023static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples) 4024{ 4025 unsigned int num_fifo_entries; 4026 int retval; 4027 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo; 4028 4029 num_fifo_entries = num_samples / fifo->sample_packing_ratio; 4030 4031 retval = set_ai_fifo_segment_length(dev, 4032 num_fifo_entries / 4033 fifo->num_segments); 4034 if (retval < 0) 4035 return retval; 4036 4037 num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio; 4038 4039 DEBUG_PRINT("set hardware fifo size to %i\n", num_samples); 4040 4041 return num_samples; 4042} 4043 4044/* query length of fifo */ 4045static unsigned int ai_fifo_size(struct comedi_device *dev) 4046{ 4047 return priv(dev)->ai_fifo_segment_length * 4048 board(dev)->ai_fifo->num_segments * 4049 board(dev)->ai_fifo->sample_packing_ratio; 4050} 4051 4052static int set_ai_fifo_segment_length(struct comedi_device *dev, 4053 unsigned int num_entries) 4054{ 4055 static const int increment_size = 0x100; 4056 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo; 4057 unsigned int num_increments; 4058 uint16_t bits; 4059 4060 if (num_entries < increment_size) 4061 num_entries = increment_size; 4062 if (num_entries > fifo->max_segment_length) 4063 num_entries = fifo->max_segment_length; 4064 4065 /* 1 == 256 entries, 2 == 512 entries, etc */ 4066 num_increments = (num_entries + increment_size / 2) / increment_size; 4067 4068 bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask; 4069 priv(dev)->fifo_size_bits &= ~fifo->fifo_size_reg_mask; 4070 priv(dev)->fifo_size_bits |= bits; 4071 writew(priv(dev)->fifo_size_bits, 4072 priv(dev)->main_iobase + FIFO_SIZE_REG); 4073 4074 priv(dev)->ai_fifo_segment_length = num_increments * increment_size; 4075 4076 DEBUG_PRINT("set hardware fifo segment length to %i\n", 4077 priv(dev)->ai_fifo_segment_length); 4078 4079 return priv(dev)->ai_fifo_segment_length; 4080} 4081 4082/* pci-6025 8800 caldac: 4083 * address 0 == dac channel 0 offset 4084 * address 1 == dac channel 0 gain 4085 * address 2 == dac channel 1 offset 4086 * address 3 == dac channel 1 gain 4087 * address 4 == fine adc offset 4088 * address 5 == coarse adc offset 4089 * address 6 == coarse adc gain 4090 * address 7 == fine adc gain 4091 */ 4092/* pci-6402/16 uses all 8 channels for dac: 4093 * address 0 == dac channel 0 fine gain 4094 * address 1 == dac channel 0 coarse gain 4095 * address 2 == dac channel 0 coarse offset 4096 * address 3 == dac channel 1 coarse offset 4097 * address 4 == dac channel 1 fine gain 4098 * address 5 == dac channel 1 coarse gain 4099 * address 6 == dac channel 0 fine offset 4100 * address 7 == dac channel 1 fine offset 4101*/ 4102 4103static int caldac_8800_write(struct comedi_device *dev, unsigned int address, 4104 uint8_t value) 4105{ 4106 static const int num_caldac_channels = 8; 4107 static const int bitstream_length = 11; 4108 unsigned int bitstream = ((address & 0x7) << 8) | value; 4109 unsigned int bit, register_bits; 4110 static const int caldac_8800_udelay = 1; 4111 4112 if (address >= num_caldac_channels) { 4113 comedi_error(dev, "illegal caldac channel"); 4114 return -1; 4115 } 4116 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { 4117 register_bits = 0; 4118 if (bitstream & bit) 4119 register_bits |= SERIAL_DATA_IN_BIT; 4120 udelay(caldac_8800_udelay); 4121 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG); 4122 register_bits |= SERIAL_CLOCK_BIT; 4123 udelay(caldac_8800_udelay); 4124 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG); 4125 } 4126 udelay(caldac_8800_udelay); 4127 writew(SELECT_8800_BIT, priv(dev)->main_iobase + CALIBRATION_REG); 4128 udelay(caldac_8800_udelay); 4129 writew(0, priv(dev)->main_iobase + CALIBRATION_REG); 4130 udelay(caldac_8800_udelay); 4131 return 0; 4132} 4133 4134/* 4020 caldacs */ 4135static int caldac_i2c_write(struct comedi_device *dev, 4136 unsigned int caldac_channel, unsigned int value) 4137{ 4138 uint8_t serial_bytes[3]; 4139 uint8_t i2c_addr; 4140 enum pointer_bits { 4141 /* manual has gain and offset bits switched */ 4142 OFFSET_0_2 = 0x1, 4143 GAIN_0_2 = 0x2, 4144 OFFSET_1_3 = 0x4, 4145 GAIN_1_3 = 0x8, 4146 }; 4147 enum data_bits { 4148 NOT_CLEAR_REGISTERS = 0x20, 4149 }; 4150 4151 switch (caldac_channel) { 4152 case 0: /* chan 0 offset */ 4153 i2c_addr = CALDAC0_I2C_ADDR; 4154 serial_bytes[0] = OFFSET_0_2; 4155 break; 4156 case 1: /* chan 1 offset */ 4157 i2c_addr = CALDAC0_I2C_ADDR; 4158 serial_bytes[0] = OFFSET_1_3; 4159 break; 4160 case 2: /* chan 2 offset */ 4161 i2c_addr = CALDAC1_I2C_ADDR; 4162 serial_bytes[0] = OFFSET_0_2; 4163 break; 4164 case 3: /* chan 3 offset */ 4165 i2c_addr = CALDAC1_I2C_ADDR; 4166 serial_bytes[0] = OFFSET_1_3; 4167 break; 4168 case 4: /* chan 0 gain */ 4169 i2c_addr = CALDAC0_I2C_ADDR; 4170 serial_bytes[0] = GAIN_0_2; 4171 break; 4172 case 5: /* chan 1 gain */ 4173 i2c_addr = CALDAC0_I2C_ADDR; 4174 serial_bytes[0] = GAIN_1_3; 4175 break; 4176 case 6: /* chan 2 gain */ 4177 i2c_addr = CALDAC1_I2C_ADDR; 4178 serial_bytes[0] = GAIN_0_2; 4179 break; 4180 case 7: /* chan 3 gain */ 4181 i2c_addr = CALDAC1_I2C_ADDR; 4182 serial_bytes[0] = GAIN_1_3; 4183 break; 4184 default: 4185 comedi_error(dev, "invalid caldac channel\n"); 4186 return -1; 4187 break; 4188 } 4189 serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf); 4190 serial_bytes[2] = value & 0xff; 4191 i2c_write(dev, i2c_addr, serial_bytes, 3); 4192 return 0; 4193} 4194 4195/* Their i2c requires a huge delay on setting clock or data high for some reason */ 4196static const int i2c_high_udelay = 1000; 4197static const int i2c_low_udelay = 10; 4198 4199/* set i2c data line high or low */ 4200static void i2c_set_sda(struct comedi_device *dev, int state) 4201{ 4202 static const int data_bit = CTL_EE_W; 4203 void __iomem *plx_control_addr = priv(dev)->plx9080_iobase + 4204 PLX_CONTROL_REG; 4205 4206 if (state) { 4207 /* set data line high */ 4208 priv(dev)->plx_control_bits &= ~data_bit; 4209 writel(priv(dev)->plx_control_bits, plx_control_addr); 4210 udelay(i2c_high_udelay); 4211 } else { /* set data line low */ 4212 4213 priv(dev)->plx_control_bits |= data_bit; 4214 writel(priv(dev)->plx_control_bits, plx_control_addr); 4215 udelay(i2c_low_udelay); 4216 } 4217} 4218 4219/* set i2c clock line high or low */ 4220static void i2c_set_scl(struct comedi_device *dev, int state) 4221{ 4222 static const int clock_bit = CTL_USERO; 4223 void __iomem *plx_control_addr = priv(dev)->plx9080_iobase + 4224 PLX_CONTROL_REG; 4225 4226 if (state) { 4227 /* set clock line high */ 4228 priv(dev)->plx_control_bits &= ~clock_bit; 4229 writel(priv(dev)->plx_control_bits, plx_control_addr); 4230 udelay(i2c_high_udelay); 4231 } else { /* set clock line low */ 4232 4233 priv(dev)->plx_control_bits |= clock_bit; 4234 writel(priv(dev)->plx_control_bits, plx_control_addr); 4235 udelay(i2c_low_udelay); 4236 } 4237} 4238 4239static void i2c_write_byte(struct comedi_device *dev, uint8_t byte) 4240{ 4241 uint8_t bit; 4242 unsigned int num_bits = 8; 4243 4244 DEBUG_PRINT("writing to i2c byte 0x%x\n", byte); 4245 4246 for (bit = 1 << (num_bits - 1); bit; bit >>= 1) { 4247 i2c_set_scl(dev, 0); 4248 if ((byte & bit)) 4249 i2c_set_sda(dev, 1); 4250 else 4251 i2c_set_sda(dev, 0); 4252 i2c_set_scl(dev, 1); 4253 } 4254} 4255 4256/* we can't really read the lines, so fake it */ 4257static int i2c_read_ack(struct comedi_device *dev) 4258{ 4259 i2c_set_scl(dev, 0); 4260 i2c_set_sda(dev, 1); 4261 i2c_set_scl(dev, 1); 4262 4263 return 0; /* return fake acknowledge bit */ 4264} 4265 4266/* send start bit */ 4267static void i2c_start(struct comedi_device *dev) 4268{ 4269 i2c_set_scl(dev, 1); 4270 i2c_set_sda(dev, 1); 4271 i2c_set_sda(dev, 0); 4272} 4273 4274/* send stop bit */ 4275static void i2c_stop(struct comedi_device *dev) 4276{ 4277 i2c_set_scl(dev, 0); 4278 i2c_set_sda(dev, 0); 4279 i2c_set_scl(dev, 1); 4280 i2c_set_sda(dev, 1); 4281} 4282 4283static void i2c_write(struct comedi_device *dev, unsigned int address, 4284 const uint8_t * data, unsigned int length) 4285{ 4286 unsigned int i; 4287 uint8_t bitstream; 4288 static const int read_bit = 0x1; 4289 4290/* XXX need mutex to prevent simultaneous attempts to access eeprom and i2c bus */ 4291 4292 /* make sure we dont send anything to eeprom */ 4293 priv(dev)->plx_control_bits &= ~CTL_EE_CS; 4294 4295 i2c_stop(dev); 4296 i2c_start(dev); 4297 4298 /* send address and write bit */ 4299 bitstream = (address << 1) & ~read_bit; 4300 i2c_write_byte(dev, bitstream); 4301 4302 /* get acknowledge */ 4303 if (i2c_read_ack(dev) != 0) { 4304 comedi_error(dev, "i2c write failed: no acknowledge"); 4305 i2c_stop(dev); 4306 return; 4307 } 4308 /* write data bytes */ 4309 for (i = 0; i < length; i++) { 4310 i2c_write_byte(dev, data[i]); 4311 if (i2c_read_ack(dev) != 0) { 4312 comedi_error(dev, "i2c write failed: no acknowledge"); 4313 i2c_stop(dev); 4314 return; 4315 } 4316 } 4317 i2c_stop(dev); 4318} 4319 4320MODULE_AUTHOR("Comedi http://www.comedi.org"); 4321MODULE_DESCRIPTION("Comedi low-level driver"); 4322MODULE_LICENSE("GPL"); 4323