gsc_hpdi.c revision 25985edcedea6396277003854657b5f3cb31a628
1/* 2 comedi/drivers/gsc_hpdi.c 3 This is a driver for the General Standards Corporation High 4 Speed Parallel Digital Interface rs485 boards. 5 6 Author: Frank Mori Hess <fmhess@users.sourceforge.net> 7 Copyright (C) 2003 Coherent Imaging Systems 8 9 COMEDI - Linux Control and Measurement Device Interface 10 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> 11 12 This program is free software; you can redistribute it and/or modify 13 it under the terms of the GNU General Public License as published by 14 the Free Software Foundation; either version 2 of the License, or 15 (at your option) any later version. 16 17 This program is distributed in the hope that it will be useful, 18 but WITHOUT ANY WARRANTY; without even the implied warranty of 19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 GNU General Public License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with this program; if not, write to the Free Software 24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 26************************************************************************/ 27 28/* 29 30Driver: gsc_hpdi 31Description: General Standards Corporation High 32 Speed Parallel Digital Interface rs485 boards 33Author: Frank Mori Hess <fmhess@users.sourceforge.net> 34Status: only receive mode works, transmit not supported 35Updated: 2003-02-20 36Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi), 37 PMC-HPDI32 38 39Configuration options: 40 [0] - PCI bus of device (optional) 41 [1] - PCI slot of device (optional) 42 43There are some additional hpdi models available from GSC for which 44support could be added to this driver. 45 46*/ 47 48#include <linux/interrupt.h> 49#include "../comedidev.h" 50#include <linux/delay.h> 51 52#include "comedi_pci.h" 53#include "plx9080.h" 54#include "comedi_fc.h" 55 56static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it); 57static int hpdi_detach(struct comedi_device *dev); 58static void abort_dma(struct comedi_device *dev, unsigned int channel); 59static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 60static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s, 61 struct comedi_cmd *cmd); 62static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 63static irqreturn_t handle_interrupt(int irq, void *d); 64static int dio_config_block_size(struct comedi_device *dev, unsigned int *data); 65 66#undef HPDI_DEBUG /* disable debugging messages */ 67/* #define HPDI_DEBUG enable debugging code */ 68 69#ifdef HPDI_DEBUG 70#define DEBUG_PRINT(format, args...) printk(format , ## args) 71#else 72#define DEBUG_PRINT(format, args...) 73#endif 74 75#define TIMER_BASE 50 /* 20MHz master clock */ 76#define DMA_BUFFER_SIZE 0x10000 77#define NUM_DMA_BUFFERS 4 78#define NUM_DMA_DESCRIPTORS 256 79 80/* indices of base address regions */ 81enum base_address_regions { 82 PLX9080_BADDRINDEX = 0, 83 HPDI_BADDRINDEX = 2, 84}; 85 86enum hpdi_registers { 87 FIRMWARE_REV_REG = 0x0, 88 BOARD_CONTROL_REG = 0x4, 89 BOARD_STATUS_REG = 0x8, 90 TX_PROG_ALMOST_REG = 0xc, 91 RX_PROG_ALMOST_REG = 0x10, 92 FEATURES_REG = 0x14, 93 FIFO_REG = 0x18, 94 TX_STATUS_COUNT_REG = 0x1c, 95 TX_LINE_VALID_COUNT_REG = 0x20, 96 TX_LINE_INVALID_COUNT_REG = 0x24, 97 RX_STATUS_COUNT_REG = 0x28, 98 RX_LINE_COUNT_REG = 0x2c, 99 INTERRUPT_CONTROL_REG = 0x30, 100 INTERRUPT_STATUS_REG = 0x34, 101 TX_CLOCK_DIVIDER_REG = 0x38, 102 TX_FIFO_SIZE_REG = 0x40, 103 RX_FIFO_SIZE_REG = 0x44, 104 TX_FIFO_WORDS_REG = 0x48, 105 RX_FIFO_WORDS_REG = 0x4c, 106 INTERRUPT_EDGE_LEVEL_REG = 0x50, 107 INTERRUPT_POLARITY_REG = 0x54, 108}; 109 110int command_channel_valid(unsigned int channel) 111{ 112 if (channel == 0 || channel > 6) { 113 printk(KERN_WARNING 114 "gsc_hpdi: bug! invalid cable command channel\n"); 115 return 0; 116 } 117 return 1; 118} 119 120/* bit definitions */ 121 122enum firmware_revision_bits { 123 FEATURES_REG_PRESENT_BIT = 0x8000, 124}; 125int firmware_revision(uint32_t fwr_bits) 126{ 127 return fwr_bits & 0xff; 128} 129 130int pcb_revision(uint32_t fwr_bits) 131{ 132 return (fwr_bits >> 8) & 0xff; 133} 134 135int hpdi_subid(uint32_t fwr_bits) 136{ 137 return (fwr_bits >> 16) & 0xff; 138} 139 140enum board_control_bits { 141 BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */ 142 TX_FIFO_RESET_BIT = 0x2, 143 RX_FIFO_RESET_BIT = 0x4, 144 TX_ENABLE_BIT = 0x10, 145 RX_ENABLE_BIT = 0x20, 146 DEMAND_DMA_DIRECTION_TX_BIT = 0x40, 147 /* for ch 0, ch 1 can only transmit (when present) */ 148 LINE_VALID_ON_STATUS_VALID_BIT = 0x80, 149 START_TX_BIT = 0x10, 150 CABLE_THROTTLE_ENABLE_BIT = 0x20, 151 TEST_MODE_ENABLE_BIT = 0x80000000, 152}; 153uint32_t command_discrete_output_bits(unsigned int channel, int output, 154 int output_value) 155{ 156 uint32_t bits = 0; 157 158 if (command_channel_valid(channel) == 0) 159 return 0; 160 if (output) { 161 bits |= 0x1 << (16 + channel); 162 if (output_value) 163 bits |= 0x1 << (24 + channel); 164 } else 165 bits |= 0x1 << (24 + channel); 166 167 return bits; 168} 169 170enum board_status_bits { 171 COMMAND_LINE_STATUS_MASK = 0x7f, 172 TX_IN_PROGRESS_BIT = 0x80, 173 TX_NOT_EMPTY_BIT = 0x100, 174 TX_NOT_ALMOST_EMPTY_BIT = 0x200, 175 TX_NOT_ALMOST_FULL_BIT = 0x400, 176 TX_NOT_FULL_BIT = 0x800, 177 RX_NOT_EMPTY_BIT = 0x1000, 178 RX_NOT_ALMOST_EMPTY_BIT = 0x2000, 179 RX_NOT_ALMOST_FULL_BIT = 0x4000, 180 RX_NOT_FULL_BIT = 0x8000, 181 BOARD_JUMPER0_INSTALLED_BIT = 0x10000, 182 BOARD_JUMPER1_INSTALLED_BIT = 0x20000, 183 TX_OVERRUN_BIT = 0x200000, 184 RX_UNDERRUN_BIT = 0x400000, 185 RX_OVERRUN_BIT = 0x800000, 186}; 187 188uint32_t almost_full_bits(unsigned int num_words) 189{ 190/* XXX need to add or subtract one? */ 191 return (num_words << 16) & 0xff0000; 192} 193 194uint32_t almost_empty_bits(unsigned int num_words) 195{ 196 return num_words & 0xffff; 197} 198 199unsigned int almost_full_num_words(uint32_t bits) 200{ 201/* XXX need to add or subtract one? */ 202 return (bits >> 16) & 0xffff; 203} 204 205unsigned int almost_empty_num_words(uint32_t bits) 206{ 207 return bits & 0xffff; 208} 209 210enum features_bits { 211 FIFO_SIZE_PRESENT_BIT = 0x1, 212 FIFO_WORDS_PRESENT_BIT = 0x2, 213 LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4, 214 GPIO_SUPPORTED_BIT = 0x8, 215 PLX_DMA_CH1_SUPPORTED_BIT = 0x10, 216 OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20, 217}; 218 219enum interrupt_sources { 220 FRAME_VALID_START_INTR = 0, 221 FRAME_VALID_END_INTR = 1, 222 TX_FIFO_EMPTY_INTR = 8, 223 TX_FIFO_ALMOST_EMPTY_INTR = 9, 224 TX_FIFO_ALMOST_FULL_INTR = 10, 225 TX_FIFO_FULL_INTR = 11, 226 RX_EMPTY_INTR = 12, 227 RX_ALMOST_EMPTY_INTR = 13, 228 RX_ALMOST_FULL_INTR = 14, 229 RX_FULL_INTR = 15, 230}; 231int command_intr_source(unsigned int channel) 232{ 233 if (command_channel_valid(channel) == 0) 234 channel = 1; 235 return channel + 1; 236} 237 238uint32_t intr_bit(int interrupt_source) 239{ 240 return 0x1 << interrupt_source; 241} 242 243uint32_t tx_clock_divisor_bits(unsigned int divisor) 244{ 245 return divisor & 0xff; 246} 247 248unsigned int fifo_size(uint32_t fifo_size_bits) 249{ 250 return fifo_size_bits & 0xfffff; 251} 252 253unsigned int fifo_words(uint32_t fifo_words_bits) 254{ 255 return fifo_words_bits & 0xfffff; 256} 257 258uint32_t intr_edge_bit(int interrupt_source) 259{ 260 return 0x1 << interrupt_source; 261} 262 263uint32_t intr_active_high_bit(int interrupt_source) 264{ 265 return 0x1 << interrupt_source; 266} 267 268struct hpdi_board { 269 270 char *name; 271 int device_id; /* pci device id */ 272 int subdevice_id; /* pci subdevice id */ 273}; 274 275static const struct hpdi_board hpdi_boards[] = { 276 { 277 .name = "pci-hpdi32", 278 .device_id = PCI_DEVICE_ID_PLX_9080, 279 .subdevice_id = 0x2400, 280 }, 281#if 0 282 { 283 .name = "pxi-hpdi32", 284 .device_id = 0x9656, 285 .subdevice_id = 0x2705, 286 }, 287#endif 288}; 289 290static DEFINE_PCI_DEVICE_TABLE(hpdi_pci_table) = { 291 { 292 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX, 293 0x2400, 0, 0, 0}, { 294 0} 295}; 296 297MODULE_DEVICE_TABLE(pci, hpdi_pci_table); 298 299static inline struct hpdi_board *board(const struct comedi_device *dev) 300{ 301 return (struct hpdi_board *)dev->board_ptr; 302} 303 304struct hpdi_private { 305 306 struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */ 307 /* base addresses (physical) */ 308 resource_size_t plx9080_phys_iobase; 309 resource_size_t hpdi_phys_iobase; 310 /* base addresses (ioremapped) */ 311 void *plx9080_iobase; 312 void *hpdi_iobase; 313 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */ 314 /* physical addresses of dma buffers */ 315 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS]; 316 /* array of dma descriptors read by plx9080, allocated to get proper 317 * alignment */ 318 struct plx_dma_desc *dma_desc; 319 /* physical address of dma descriptor array */ 320 dma_addr_t dma_desc_phys_addr; 321 unsigned int num_dma_descriptors; 322 /* pointer to start of buffers indexed by descriptor */ 323 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS]; 324 /* index of the dma descriptor that is currently being used */ 325 volatile unsigned int dma_desc_index; 326 unsigned int tx_fifo_size; 327 unsigned int rx_fifo_size; 328 volatile unsigned long dio_count; 329 /* software copies of values written to hpdi registers */ 330 volatile uint32_t bits[24]; 331 /* number of bytes at which to generate COMEDI_CB_BLOCK events */ 332 volatile unsigned int block_size; 333 unsigned dio_config_output:1; 334}; 335 336static inline struct hpdi_private *priv(struct comedi_device *dev) 337{ 338 return dev->private; 339} 340 341static struct comedi_driver driver_hpdi = { 342 .driver_name = "gsc_hpdi", 343 .module = THIS_MODULE, 344 .attach = hpdi_attach, 345 .detach = hpdi_detach, 346}; 347 348static int __devinit driver_hpdi_pci_probe(struct pci_dev *dev, 349 const struct pci_device_id *ent) 350{ 351 return comedi_pci_auto_config(dev, driver_hpdi.driver_name); 352} 353 354static void __devexit driver_hpdi_pci_remove(struct pci_dev *dev) 355{ 356 comedi_pci_auto_unconfig(dev); 357} 358 359static struct pci_driver driver_hpdi_pci_driver = { 360 .id_table = hpdi_pci_table, 361 .probe = &driver_hpdi_pci_probe, 362 .remove = __devexit_p(&driver_hpdi_pci_remove) 363}; 364 365static int __init driver_hpdi_init_module(void) 366{ 367 int retval; 368 369 retval = comedi_driver_register(&driver_hpdi); 370 if (retval < 0) 371 return retval; 372 373 driver_hpdi_pci_driver.name = (char *)driver_hpdi.driver_name; 374 return pci_register_driver(&driver_hpdi_pci_driver); 375} 376 377static void __exit driver_hpdi_cleanup_module(void) 378{ 379 pci_unregister_driver(&driver_hpdi_pci_driver); 380 comedi_driver_unregister(&driver_hpdi); 381} 382 383module_init(driver_hpdi_init_module); 384module_exit(driver_hpdi_cleanup_module); 385 386static int dio_config_insn(struct comedi_device *dev, 387 struct comedi_subdevice *s, struct comedi_insn *insn, 388 unsigned int *data) 389{ 390 switch (data[0]) { 391 case INSN_CONFIG_DIO_OUTPUT: 392 priv(dev)->dio_config_output = 1; 393 return insn->n; 394 break; 395 case INSN_CONFIG_DIO_INPUT: 396 priv(dev)->dio_config_output = 0; 397 return insn->n; 398 break; 399 case INSN_CONFIG_DIO_QUERY: 400 data[1] = 401 priv(dev)->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT; 402 return insn->n; 403 break; 404 case INSN_CONFIG_BLOCK_SIZE: 405 return dio_config_block_size(dev, data); 406 break; 407 default: 408 break; 409 } 410 411 return -EINVAL; 412} 413 414static void disable_plx_interrupts(struct comedi_device *dev) 415{ 416 writel(0, priv(dev)->plx9080_iobase + PLX_INTRCS_REG); 417} 418 419/* initialize plx9080 chip */ 420static void init_plx9080(struct comedi_device *dev) 421{ 422 uint32_t bits; 423 void *plx_iobase = priv(dev)->plx9080_iobase; 424 425 /* plx9080 dump */ 426 DEBUG_PRINT(" plx interrupt status 0x%x\n", 427 readl(plx_iobase + PLX_INTRCS_REG)); 428 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG)); 429 DEBUG_PRINT(" plx control reg 0x%x\n", 430 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG)); 431 432 DEBUG_PRINT(" plx revision 0x%x\n", 433 readl(plx_iobase + PLX_REVISION_REG)); 434 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n", 435 readl(plx_iobase + PLX_DMA0_MODE_REG)); 436 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n", 437 readl(plx_iobase + PLX_DMA1_MODE_REG)); 438 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n", 439 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG)); 440 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n", 441 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG)); 442 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n", 443 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG)); 444 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n", 445 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG)); 446 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n", 447 readb(plx_iobase + PLX_DMA0_CS_REG)); 448 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n", 449 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG)); 450 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG)); 451#ifdef __BIG_ENDIAN 452 bits = BIGEND_DMA0 | BIGEND_DMA1; 453#else 454 bits = 0; 455#endif 456 writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG); 457 458 disable_plx_interrupts(dev); 459 460 abort_dma(dev, 0); 461 abort_dma(dev, 1); 462 463 /* configure dma0 mode */ 464 bits = 0; 465 /* enable ready input */ 466 bits |= PLX_DMA_EN_READYIN_BIT; 467 /* enable dma chaining */ 468 bits |= PLX_EN_CHAIN_BIT; 469 /* enable interrupt on dma done 470 * (probably don't need this, since chain never finishes) */ 471 bits |= PLX_EN_DMA_DONE_INTR_BIT; 472 /* don't increment local address during transfers 473 * (we are transferring from a fixed fifo register) */ 474 bits |= PLX_LOCAL_ADDR_CONST_BIT; 475 /* route dma interrupt to pci bus */ 476 bits |= PLX_DMA_INTR_PCI_BIT; 477 /* enable demand mode */ 478 bits |= PLX_DEMAND_MODE_BIT; 479 /* enable local burst mode */ 480 bits |= PLX_DMA_LOCAL_BURST_EN_BIT; 481 bits |= PLX_LOCAL_BUS_32_WIDE_BITS; 482 writel(bits, plx_iobase + PLX_DMA0_MODE_REG); 483} 484 485/* Allocate and initialize the subdevice structures. 486 */ 487static int setup_subdevices(struct comedi_device *dev) 488{ 489 struct comedi_subdevice *s; 490 491 if (alloc_subdevices(dev, 1) < 0) 492 return -ENOMEM; 493 494 s = dev->subdevices + 0; 495 /* analog input subdevice */ 496 dev->read_subdev = s; 497/* dev->write_subdev = s; */ 498 s->type = COMEDI_SUBD_DIO; 499 s->subdev_flags = 500 SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ; 501 s->n_chan = 32; 502 s->len_chanlist = 32; 503 s->maxdata = 1; 504 s->range_table = &range_digital; 505 s->insn_config = dio_config_insn; 506 s->do_cmd = hpdi_cmd; 507 s->do_cmdtest = hpdi_cmd_test; 508 s->cancel = hpdi_cancel; 509 510 return 0; 511} 512 513static int init_hpdi(struct comedi_device *dev) 514{ 515 uint32_t plx_intcsr_bits; 516 517 writel(BOARD_RESET_BIT, priv(dev)->hpdi_iobase + BOARD_CONTROL_REG); 518 udelay(10); 519 520 writel(almost_empty_bits(32) | almost_full_bits(32), 521 priv(dev)->hpdi_iobase + RX_PROG_ALMOST_REG); 522 writel(almost_empty_bits(32) | almost_full_bits(32), 523 priv(dev)->hpdi_iobase + TX_PROG_ALMOST_REG); 524 525 priv(dev)->tx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase + 526 TX_FIFO_SIZE_REG)); 527 priv(dev)->rx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase + 528 RX_FIFO_SIZE_REG)); 529 530 writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG); 531 532 /* enable interrupts */ 533 plx_intcsr_bits = 534 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE | 535 ICS_DMA0_E; 536 writel(plx_intcsr_bits, priv(dev)->plx9080_iobase + PLX_INTRCS_REG); 537 538 return 0; 539} 540 541/* setup dma descriptors so a link completes every 'transfer_size' bytes */ 542static int setup_dma_descriptors(struct comedi_device *dev, 543 unsigned int transfer_size) 544{ 545 unsigned int buffer_index, buffer_offset; 546 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT | 547 PLX_XFER_LOCAL_TO_PCI; 548 unsigned int i; 549 550 if (transfer_size > DMA_BUFFER_SIZE) 551 transfer_size = DMA_BUFFER_SIZE; 552 transfer_size -= transfer_size % sizeof(uint32_t); 553 if (transfer_size == 0) 554 return -1; 555 556 DEBUG_PRINT(" transfer_size %i\n", transfer_size); 557 DEBUG_PRINT(" descriptors at 0x%lx\n", 558 (unsigned long)priv(dev)->dma_desc_phys_addr); 559 560 buffer_offset = 0; 561 buffer_index = 0; 562 for (i = 0; i < NUM_DMA_DESCRIPTORS && 563 buffer_index < NUM_DMA_BUFFERS; i++) { 564 priv(dev)->dma_desc[i].pci_start_addr = 565 cpu_to_le32(priv(dev)->dio_buffer_phys_addr[buffer_index] + 566 buffer_offset); 567 priv(dev)->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG); 568 priv(dev)->dma_desc[i].transfer_size = 569 cpu_to_le32(transfer_size); 570 priv(dev)->dma_desc[i].next = 571 cpu_to_le32((priv(dev)->dma_desc_phys_addr + (i + 572 1) * 573 sizeof(priv(dev)->dma_desc[0])) | next_bits); 574 575 priv(dev)->desc_dio_buffer[i] = 576 priv(dev)->dio_buffer[buffer_index] + 577 (buffer_offset / sizeof(uint32_t)); 578 579 buffer_offset += transfer_size; 580 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) { 581 buffer_offset = 0; 582 buffer_index++; 583 } 584 585 DEBUG_PRINT(" desc %i\n", i); 586 DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n", 587 priv(dev)->desc_dio_buffer[i], 588 (unsigned long)priv(dev)->dma_desc[i]. 589 pci_start_addr); 590 DEBUG_PRINT(" next 0x%lx\n", 591 (unsigned long)priv(dev)->dma_desc[i].next); 592 } 593 priv(dev)->num_dma_descriptors = i; 594 /* fix last descriptor to point back to first */ 595 priv(dev)->dma_desc[i - 1].next = 596 cpu_to_le32(priv(dev)->dma_desc_phys_addr | next_bits); 597 DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1, 598 (unsigned long)priv(dev)->dma_desc[i - 1].next); 599 600 priv(dev)->block_size = transfer_size; 601 602 return transfer_size; 603} 604 605static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it) 606{ 607 struct pci_dev *pcidev; 608 int i; 609 int retval; 610 611 printk(KERN_WARNING "comedi%d: gsc_hpdi\n", dev->minor); 612 613 if (alloc_private(dev, sizeof(struct hpdi_private)) < 0) 614 return -ENOMEM; 615 616 pcidev = NULL; 617 for (i = 0; i < ARRAY_SIZE(hpdi_boards) && 618 dev->board_ptr == NULL; i++) { 619 do { 620 pcidev = pci_get_subsys(PCI_VENDOR_ID_PLX, 621 hpdi_boards[i].device_id, 622 PCI_VENDOR_ID_PLX, 623 hpdi_boards[i].subdevice_id, 624 pcidev); 625 /* was a particular bus/slot requested? */ 626 if (it->options[0] || it->options[1]) { 627 /* are we on the wrong bus/slot? */ 628 if (pcidev->bus->number != it->options[0] || 629 PCI_SLOT(pcidev->devfn) != it->options[1]) 630 continue; 631 } 632 if (pcidev) { 633 priv(dev)->hw_dev = pcidev; 634 dev->board_ptr = hpdi_boards + i; 635 break; 636 } 637 } while (pcidev != NULL); 638 } 639 if (dev->board_ptr == NULL) { 640 printk(KERN_WARNING "gsc_hpdi: no hpdi card found\n"); 641 return -EIO; 642 } 643 644 printk(KERN_WARNING 645 "gsc_hpdi: found %s on bus %i, slot %i\n", board(dev)->name, 646 pcidev->bus->number, PCI_SLOT(pcidev->devfn)); 647 648 if (comedi_pci_enable(pcidev, driver_hpdi.driver_name)) { 649 printk(KERN_WARNING 650 " failed enable PCI device and request regions\n"); 651 return -EIO; 652 } 653 pci_set_master(pcidev); 654 655 /* Initialize dev->board_name */ 656 dev->board_name = board(dev)->name; 657 658 priv(dev)->plx9080_phys_iobase = 659 pci_resource_start(pcidev, PLX9080_BADDRINDEX); 660 priv(dev)->hpdi_phys_iobase = 661 pci_resource_start(pcidev, HPDI_BADDRINDEX); 662 663 /* remap, won't work with 2.0 kernels but who cares */ 664 priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase, 665 pci_resource_len(pcidev, 666 PLX9080_BADDRINDEX)); 667 priv(dev)->hpdi_iobase = 668 ioremap(priv(dev)->hpdi_phys_iobase, 669 pci_resource_len(pcidev, HPDI_BADDRINDEX)); 670 if (!priv(dev)->plx9080_iobase || !priv(dev)->hpdi_iobase) { 671 printk(KERN_WARNING " failed to remap io memory\n"); 672 return -ENOMEM; 673 } 674 675 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase); 676 DEBUG_PRINT(" hpdi remapped to 0x%p\n", priv(dev)->hpdi_iobase); 677 678 init_plx9080(dev); 679 680 /* get irq */ 681 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED, 682 driver_hpdi.driver_name, dev)) { 683 printk(KERN_WARNING 684 " unable to allocate irq %u\n", pcidev->irq); 685 return -EINVAL; 686 } 687 dev->irq = pcidev->irq; 688 689 printk(KERN_WARNING " irq %u\n", dev->irq); 690 691 /* alocate pci dma buffers */ 692 for (i = 0; i < NUM_DMA_BUFFERS; i++) { 693 priv(dev)->dio_buffer[i] = 694 pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE, 695 &priv(dev)->dio_buffer_phys_addr[i]); 696 DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n", 697 priv(dev)->dio_buffer[i], 698 (unsigned long)priv(dev)->dio_buffer_phys_addr[i]); 699 } 700 /* allocate dma descriptors */ 701 priv(dev)->dma_desc = pci_alloc_consistent(priv(dev)->hw_dev, 702 sizeof(struct plx_dma_desc) * 703 NUM_DMA_DESCRIPTORS, 704 &priv(dev)-> 705 dma_desc_phys_addr); 706 if (priv(dev)->dma_desc_phys_addr & 0xf) { 707 printk(KERN_WARNING 708 " dma descriptors not quad-word aligned (bug)\n"); 709 return -EIO; 710 } 711 712 retval = setup_dma_descriptors(dev, 0x1000); 713 if (retval < 0) 714 return retval; 715 716 retval = setup_subdevices(dev); 717 if (retval < 0) 718 return retval; 719 720 return init_hpdi(dev); 721} 722 723static int hpdi_detach(struct comedi_device *dev) 724{ 725 unsigned int i; 726 727 printk(KERN_WARNING "comedi%d: gsc_hpdi: remove\n", dev->minor); 728 729 if (dev->irq) 730 free_irq(dev->irq, dev); 731 if ((priv(dev)) && (priv(dev)->hw_dev)) { 732 if (priv(dev)->plx9080_iobase) { 733 disable_plx_interrupts(dev); 734 iounmap((void *)priv(dev)->plx9080_iobase); 735 } 736 if (priv(dev)->hpdi_iobase) 737 iounmap((void *)priv(dev)->hpdi_iobase); 738 /* free pci dma buffers */ 739 for (i = 0; i < NUM_DMA_BUFFERS; i++) { 740 if (priv(dev)->dio_buffer[i]) 741 pci_free_consistent(priv(dev)->hw_dev, 742 DMA_BUFFER_SIZE, 743 priv(dev)-> 744 dio_buffer[i], 745 priv 746 (dev)->dio_buffer_phys_addr 747 [i]); 748 } 749 /* free dma descriptors */ 750 if (priv(dev)->dma_desc) 751 pci_free_consistent(priv(dev)->hw_dev, 752 sizeof(struct plx_dma_desc) 753 * NUM_DMA_DESCRIPTORS, 754 priv(dev)->dma_desc, 755 priv(dev)-> 756 dma_desc_phys_addr); 757 if (priv(dev)->hpdi_phys_iobase) 758 comedi_pci_disable(priv(dev)->hw_dev); 759 pci_dev_put(priv(dev)->hw_dev); 760 } 761 return 0; 762} 763 764static int dio_config_block_size(struct comedi_device *dev, unsigned int *data) 765{ 766 unsigned int requested_block_size; 767 int retval; 768 769 requested_block_size = data[1]; 770 771 retval = setup_dma_descriptors(dev, requested_block_size); 772 if (retval < 0) 773 return retval; 774 775 data[1] = retval; 776 777 return 2; 778} 779 780static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s, 781 struct comedi_cmd *cmd) 782{ 783 int err = 0; 784 int tmp; 785 int i; 786 787 /* step 1: make sure trigger sources are trivially valid */ 788 789 tmp = cmd->start_src; 790 cmd->start_src &= TRIG_NOW; 791 if (!cmd->start_src || tmp != cmd->start_src) 792 err++; 793 794 tmp = cmd->scan_begin_src; 795 cmd->scan_begin_src &= TRIG_EXT; 796 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 797 err++; 798 799 tmp = cmd->convert_src; 800 cmd->convert_src &= TRIG_NOW; 801 if (!cmd->convert_src || tmp != cmd->convert_src) 802 err++; 803 804 tmp = cmd->scan_end_src; 805 cmd->scan_end_src &= TRIG_COUNT; 806 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 807 err++; 808 809 tmp = cmd->stop_src; 810 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 811 if (!cmd->stop_src || tmp != cmd->stop_src) 812 err++; 813 814 if (err) 815 return 1; 816 817 /* step 2: make sure trigger sources are unique and mutually 818 * compatible */ 819 820 /* uniqueness check */ 821 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 822 err++; 823 824 if (err) 825 return 2; 826 827 /* step 3: make sure arguments are trivially compatible */ 828 829 if (!cmd->chanlist_len) { 830 cmd->chanlist_len = 32; 831 err++; 832 } 833 if (cmd->scan_end_arg != cmd->chanlist_len) { 834 cmd->scan_end_arg = cmd->chanlist_len; 835 err++; 836 } 837 838 switch (cmd->stop_src) { 839 case TRIG_COUNT: 840 if (!cmd->stop_arg) { 841 cmd->stop_arg = 1; 842 err++; 843 } 844 break; 845 case TRIG_NONE: 846 if (cmd->stop_arg != 0) { 847 cmd->stop_arg = 0; 848 err++; 849 } 850 break; 851 default: 852 break; 853 } 854 855 if (err) 856 return 3; 857 858 /* step 4: fix up any arguments */ 859 860 if (err) 861 return 4; 862 863 if (!cmd->chanlist) 864 return 0; 865 866 for (i = 1; i < cmd->chanlist_len; i++) { 867 if (CR_CHAN(cmd->chanlist[i]) != i) { 868 /* XXX could support 8 or 16 channels */ 869 comedi_error(dev, 870 "chanlist must be ch 0 to 31 in order"); 871 err++; 872 break; 873 } 874 } 875 876 if (err) 877 return 5; 878 879 return 0; 880} 881 882static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s, 883 struct comedi_cmd *cmd) 884{ 885 if (priv(dev)->dio_config_output) 886 return -EINVAL; 887 else 888 return di_cmd_test(dev, s, cmd); 889} 890 891static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits, 892 unsigned int offset) 893{ 894 writel(bits | priv(dev)->bits[offset / sizeof(uint32_t)], 895 priv(dev)->hpdi_iobase + offset); 896} 897 898static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 899{ 900 uint32_t bits; 901 unsigned long flags; 902 struct comedi_async *async = s->async; 903 struct comedi_cmd *cmd = &async->cmd; 904 905 hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG); 906 907 DEBUG_PRINT("hpdi: in di_cmd\n"); 908 909 abort_dma(dev, 0); 910 911 priv(dev)->dma_desc_index = 0; 912 913 /* These register are supposedly unused during chained dma, 914 * but I have found that left over values from last operation 915 * occasionally cause problems with transfer of first dma 916 * block. Initializing them to zero seems to fix the problem. */ 917 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG); 918 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG); 919 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG); 920 /* give location of first dma descriptor */ 921 bits = 922 priv(dev)->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT | 923 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI; 924 writel(bits, priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG); 925 926 /* spinlock for plx dma control/status reg */ 927 spin_lock_irqsave(&dev->spinlock, flags); 928 /* enable dma transfer */ 929 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT, 930 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 931 spin_unlock_irqrestore(&dev->spinlock, flags); 932 933 if (cmd->stop_src == TRIG_COUNT) 934 priv(dev)->dio_count = cmd->stop_arg; 935 else 936 priv(dev)->dio_count = 1; 937 938 /* clear over/under run status flags */ 939 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, 940 priv(dev)->hpdi_iobase + BOARD_STATUS_REG); 941 /* enable interrupts */ 942 writel(intr_bit(RX_FULL_INTR), 943 priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG); 944 945 DEBUG_PRINT("hpdi: starting rx\n"); 946 hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG); 947 948 return 0; 949} 950 951static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 952{ 953 if (priv(dev)->dio_config_output) 954 return -EINVAL; 955 else 956 return di_cmd(dev, s); 957} 958 959static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel) 960{ 961 struct comedi_async *async = dev->read_subdev->async; 962 uint32_t next_transfer_addr; 963 int j; 964 int num_samples = 0; 965 void *pci_addr_reg; 966 967 if (channel) 968 pci_addr_reg = 969 priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG; 970 else 971 pci_addr_reg = 972 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG; 973 974 /* loop until we have read all the full buffers */ 975 j = 0; 976 for (next_transfer_addr = readl(pci_addr_reg); 977 (next_transfer_addr < 978 le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index]. 979 pci_start_addr) 980 || next_transfer_addr >= 981 le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index]. 982 pci_start_addr) + priv(dev)->block_size) 983 && j < priv(dev)->num_dma_descriptors; j++) { 984 /* transfer data from dma buffer to comedi buffer */ 985 num_samples = priv(dev)->block_size / sizeof(uint32_t); 986 if (async->cmd.stop_src == TRIG_COUNT) { 987 if (num_samples > priv(dev)->dio_count) 988 num_samples = priv(dev)->dio_count; 989 priv(dev)->dio_count -= num_samples; 990 } 991 cfc_write_array_to_buffer(dev->read_subdev, 992 priv(dev)->desc_dio_buffer[priv(dev)-> 993 dma_desc_index], 994 num_samples * sizeof(uint32_t)); 995 priv(dev)->dma_desc_index++; 996 priv(dev)->dma_desc_index %= priv(dev)->num_dma_descriptors; 997 998 DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long) 999 priv(dev)->dma_desc[priv(dev)->dma_desc_index]. 1000 next); 1001 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr); 1002 } 1003 /* XXX check for buffer overrun somehow */ 1004} 1005 1006static irqreturn_t handle_interrupt(int irq, void *d) 1007{ 1008 struct comedi_device *dev = d; 1009 struct comedi_subdevice *s = dev->read_subdev; 1010 struct comedi_async *async = s->async; 1011 uint32_t hpdi_intr_status, hpdi_board_status; 1012 uint32_t plx_status; 1013 uint32_t plx_bits; 1014 uint8_t dma0_status, dma1_status; 1015 unsigned long flags; 1016 1017 if (!dev->attached) 1018 return IRQ_NONE; 1019 1020 plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG); 1021 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0) 1022 return IRQ_NONE; 1023 1024 hpdi_intr_status = readl(priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG); 1025 hpdi_board_status = readl(priv(dev)->hpdi_iobase + BOARD_STATUS_REG); 1026 1027 async->events = 0; 1028 1029 if (hpdi_intr_status) { 1030 DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status); 1031 writel(hpdi_intr_status, 1032 priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG); 1033 } 1034 /* spin lock makes sure no one else changes plx dma control reg */ 1035 spin_lock_irqsave(&dev->spinlock, flags); 1036 dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 1037 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */ 1038 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT, 1039 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG); 1040 1041 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status); 1042 if (dma0_status & PLX_DMA_EN_BIT) 1043 drain_dma_buffers(dev, 0); 1044 DEBUG_PRINT(" cleared dma ch0 interrupt\n"); 1045 } 1046 spin_unlock_irqrestore(&dev->spinlock, flags); 1047 1048 /* spin lock makes sure no one else changes plx dma control reg */ 1049 spin_lock_irqsave(&dev->spinlock, flags); 1050 dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG); 1051 if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */ 1052 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT, 1053 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG); 1054 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status); 1055 1056 DEBUG_PRINT(" cleared dma ch1 interrupt\n"); 1057 } 1058 spin_unlock_irqrestore(&dev->spinlock, flags); 1059 1060 /* clear possible plx9080 interrupt sources */ 1061 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */ 1062 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG); 1063 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG); 1064 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits); 1065 } 1066 1067 if (hpdi_board_status & RX_OVERRUN_BIT) { 1068 comedi_error(dev, "rx fifo overrun"); 1069 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 1070 DEBUG_PRINT("dma0_status 0x%x\n", 1071 (int)readb(priv(dev)->plx9080_iobase + 1072 PLX_DMA0_CS_REG)); 1073 } 1074 1075 if (hpdi_board_status & RX_UNDERRUN_BIT) { 1076 comedi_error(dev, "rx fifo underrun"); 1077 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 1078 } 1079 1080 if (priv(dev)->dio_count == 0) 1081 async->events |= COMEDI_CB_EOA; 1082 1083 DEBUG_PRINT("board status 0x%x, ", hpdi_board_status); 1084 DEBUG_PRINT("plx status 0x%x\n", plx_status); 1085 if (async->events) 1086 DEBUG_PRINT(" events 0x%x\n", async->events); 1087 1088 cfc_handle_events(dev, s); 1089 1090 return IRQ_HANDLED; 1091} 1092 1093static void abort_dma(struct comedi_device *dev, unsigned int channel) 1094{ 1095 unsigned long flags; 1096 1097 /* spinlock for plx dma control/status reg */ 1098 spin_lock_irqsave(&dev->spinlock, flags); 1099 1100 plx9080_abort_dma(priv(dev)->plx9080_iobase, channel); 1101 1102 spin_unlock_irqrestore(&dev->spinlock, flags); 1103} 1104 1105static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 1106{ 1107 hpdi_writel(dev, 0, BOARD_CONTROL_REG); 1108 1109 writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG); 1110 1111 abort_dma(dev, 0); 1112 1113 return 0; 1114} 1115 1116MODULE_AUTHOR("Comedi http://www.comedi.org"); 1117MODULE_DESCRIPTION("Comedi low-level driver"); 1118MODULE_LICENSE("GPL"); 1119