me4000.h revision 0c18e8c046b5ec21e9e0b458807db260309a8f5d
1/* 2 me4000.h 3 Register descriptions and defines for the ME-4000 board family 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1998-9 David A. Schleef <ds@schleef.org> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 22*/ 23 24#ifndef _ME4000_H_ 25#define _ME4000_H_ 26 27/*============================================================================= 28 Debug section 29 ===========================================================================*/ 30 31#undef ME4000_CALL_DEBUG /* Debug function entry and exit */ 32#undef ME4000_PORT_DEBUG /* Debug port access */ 33#undef ME4000_ISR_DEBUG /* Debug the interrupt service routine */ 34#undef ME4000_DEBUG /* General purpose debug masseges */ 35 36#ifdef ME4000_CALL_DEBUG 37#undef CALL_PDEBUG 38#define CALL_PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args) 39#else 40# define CALL_PDEBUG(fmt, args...) /* no debugging, do nothing */ 41#endif 42 43#ifdef ME4000_PORT_DEBUG 44#undef PORT_PDEBUG 45#define PORT_PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args) 46#else 47#define PORT_PDEBUG(fmt, args...) /* no debugging, do nothing */ 48#endif 49 50#ifdef ME4000_ISR_DEBUG 51#undef ISR_PDEBUG 52#define ISR_PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args) 53#else 54#define ISR_PDEBUG(fmt, args...) /* no debugging, do nothing */ 55#endif 56 57#ifdef ME4000_DEBUG 58#undef PDEBUG 59#define PDEBUG(fmt, args...) printk(KERN_DEBUG"comedi%d: me4000: " fmt, dev->minor, ##args) 60#else 61#define PDEBUG(fmt, args...) /* no debugging, do nothing */ 62#endif 63 64/*============================================================================= 65 PCI vendor and device IDs 66 ===========================================================================*/ 67 68#define PCI_VENDOR_ID_MEILHAUS 0x1402 69 70#define PCI_DEVICE_ID_MEILHAUS_ME4650 0x4650 /* Low Cost version */ 71 72#define PCI_DEVICE_ID_MEILHAUS_ME4660 0x4660 /* Standard version */ 73#define PCI_DEVICE_ID_MEILHAUS_ME4660I 0x4661 /* Isolated version */ 74#define PCI_DEVICE_ID_MEILHAUS_ME4660S 0x4662 /* Standard version with Sample and Hold */ 75#define PCI_DEVICE_ID_MEILHAUS_ME4660IS 0x4663 /* Isolated version with Sample and Hold */ 76 77#define PCI_DEVICE_ID_MEILHAUS_ME4670 0x4670 /* Standard version */ 78#define PCI_DEVICE_ID_MEILHAUS_ME4670I 0x4671 /* Isolated version */ 79#define PCI_DEVICE_ID_MEILHAUS_ME4670S 0x4672 /* Standard version with Sample and Hold */ 80#define PCI_DEVICE_ID_MEILHAUS_ME4670IS 0x4673 /* Isolated version with Sample and Hold */ 81 82#define PCI_DEVICE_ID_MEILHAUS_ME4680 0x4680 /* Standard version */ 83#define PCI_DEVICE_ID_MEILHAUS_ME4680I 0x4681 /* Isolated version */ 84#define PCI_DEVICE_ID_MEILHAUS_ME4680S 0x4682 /* Standard version with Sample and Hold */ 85#define PCI_DEVICE_ID_MEILHAUS_ME4680IS 0x4683 /* Isolated version with Sample and Hold */ 86 87/*============================================================================= 88 ME-4000 base register offsets 89 ===========================================================================*/ 90 91#define ME4000_AO_00_CTRL_REG 0x00 /* R/W */ 92#define ME4000_AO_00_STATUS_REG 0x04 /* R/_ */ 93#define ME4000_AO_00_FIFO_REG 0x08 /* _/W */ 94#define ME4000_AO_00_SINGLE_REG 0x0C /* R/W */ 95#define ME4000_AO_00_TIMER_REG 0x10 /* _/W */ 96 97#define ME4000_AO_01_CTRL_REG 0x18 /* R/W */ 98#define ME4000_AO_01_STATUS_REG 0x1C /* R/_ */ 99#define ME4000_AO_01_FIFO_REG 0x20 /* _/W */ 100#define ME4000_AO_01_SINGLE_REG 0x24 /* R/W */ 101#define ME4000_AO_01_TIMER_REG 0x28 /* _/W */ 102 103#define ME4000_AO_02_CTRL_REG 0x30 /* R/W */ 104#define ME4000_AO_02_STATUS_REG 0x34 /* R/_ */ 105#define ME4000_AO_02_FIFO_REG 0x38 /* _/W */ 106#define ME4000_AO_02_SINGLE_REG 0x3C /* R/W */ 107#define ME4000_AO_02_TIMER_REG 0x40 /* _/W */ 108 109#define ME4000_AO_03_CTRL_REG 0x48 /* R/W */ 110#define ME4000_AO_03_STATUS_REG 0x4C /* R/_ */ 111#define ME4000_AO_03_FIFO_REG 0x50 /* _/W */ 112#define ME4000_AO_03_SINGLE_REG 0x54 /* R/W */ 113#define ME4000_AO_03_TIMER_REG 0x58 /* _/W */ 114 115#define ME4000_AI_CTRL_REG 0x74 /* _/W */ 116#define ME4000_AI_STATUS_REG 0x74 /* R/_ */ 117#define ME4000_AI_CHANNEL_LIST_REG 0x78 /* _/W */ 118#define ME4000_AI_DATA_REG 0x7C /* R/_ */ 119#define ME4000_AI_CHAN_TIMER_REG 0x80 /* _/W */ 120#define ME4000_AI_CHAN_PRE_TIMER_REG 0x84 /* _/W */ 121#define ME4000_AI_SCAN_TIMER_LOW_REG 0x88 /* _/W */ 122#define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8C /* _/W */ 123#define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90 /* _/W */ 124#define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94 /* _/W */ 125#define ME4000_AI_START_REG 0x98 /* R/_ */ 126 127#define ME4000_IRQ_STATUS_REG 0x9C /* R/_ */ 128 129#define ME4000_DIO_PORT_0_REG 0xA0 /* R/W */ 130#define ME4000_DIO_PORT_1_REG 0xA4 /* R/W */ 131#define ME4000_DIO_PORT_2_REG 0xA8 /* R/W */ 132#define ME4000_DIO_PORT_3_REG 0xAC /* R/W */ 133#define ME4000_DIO_DIR_REG 0xB0 /* R/W */ 134 135#define ME4000_AO_LOADSETREG_XX 0xB4 /* R/W */ 136 137#define ME4000_DIO_CTRL_REG 0xB8 /* R/W */ 138 139#define ME4000_AO_DEMUX_ADJUST_REG 0xBC /* -/W */ 140 141#define ME4000_AI_SAMPLE_COUNTER_REG 0xC0 /* _/W */ 142 143/*============================================================================= 144 Value to adjust Demux 145 ===========================================================================*/ 146 147#define ME4000_AO_DEMUX_ADJUST_VALUE 0x4C 148 149/*============================================================================= 150 Counter base register offsets 151 ===========================================================================*/ 152 153#define ME4000_CNT_COUNTER_0_REG 0x00 154#define ME4000_CNT_COUNTER_1_REG 0x01 155#define ME4000_CNT_COUNTER_2_REG 0x02 156#define ME4000_CNT_CTRL_REG 0x03 157 158/*============================================================================= 159 PLX base register offsets 160 ===========================================================================*/ 161 162#define PLX_INTCSR 0x4C /* Interrupt control and status register */ 163#define PLX_ICR 0x50 /* Initialization control register */ 164 165/*============================================================================= 166 Bits for the PLX_ICSR register 167 ===========================================================================*/ 168 169#define PLX_INTCSR_LOCAL_INT1_EN 0x01 /* If set, local interrupt 1 is enabled (r/w) */ 170#define PLX_INTCSR_LOCAL_INT1_POL 0x02 /* If set, local interrupt 1 polarity is active high (r/w) */ 171#define PLX_INTCSR_LOCAL_INT1_STATE 0x04 /* If set, local interrupt 1 is active (r/_) */ 172#define PLX_INTCSR_LOCAL_INT2_EN 0x08 /* If set, local interrupt 2 is enabled (r/w) */ 173#define PLX_INTCSR_LOCAL_INT2_POL 0x10 /* If set, local interrupt 2 polarity is active high (r/w) */ 174#define PLX_INTCSR_LOCAL_INT2_STATE 0x20 /* If set, local interrupt 2 is active (r/_) */ 175#define PLX_INTCSR_PCI_INT_EN 0x40 /* If set, PCI interrupt is enabled (r/w) */ 176#define PLX_INTCSR_SOFT_INT 0x80 /* If set, a software interrupt is generated (r/w) */ 177 178/*============================================================================= 179 Bits for the PLX_ICR register 180 ===========================================================================*/ 181 182#define PLX_ICR_BIT_EEPROM_CLOCK_SET 0x01000000 183#define PLX_ICR_BIT_EEPROM_CHIP_SELECT 0x02000000 184#define PLX_ICR_BIT_EEPROM_WRITE 0x04000000 185#define PLX_ICR_BIT_EEPROM_READ 0x08000000 186#define PLX_ICR_BIT_EEPROM_VALID 0x10000000 187 188#define PLX_ICR_MASK_EEPROM 0x1F000000 189 190#define EEPROM_DELAY 1 191 192/*============================================================================= 193 Bits for the ME4000_AO_CTRL_REG register 194 ===========================================================================*/ 195 196#define ME4000_AO_CTRL_BIT_MODE_0 0x001 197#define ME4000_AO_CTRL_BIT_MODE_1 0x002 198#define ME4000_AO_CTRL_MASK_MODE 0x003 199#define ME4000_AO_CTRL_BIT_STOP 0x004 200#define ME4000_AO_CTRL_BIT_ENABLE_FIFO 0x008 201#define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG 0x010 202#define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE 0x020 203#define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP 0x080 204#define ME4000_AO_CTRL_BIT_ENABLE_DO 0x100 205#define ME4000_AO_CTRL_BIT_ENABLE_IRQ 0x200 206#define ME4000_AO_CTRL_BIT_RESET_IRQ 0x400 207 208/*============================================================================= 209 Bits for the ME4000_AO_STATUS_REG register 210 ===========================================================================*/ 211 212#define ME4000_AO_STATUS_BIT_FSM 0x01 213#define ME4000_AO_STATUS_BIT_FF 0x02 214#define ME4000_AO_STATUS_BIT_HF 0x04 215#define ME4000_AO_STATUS_BIT_EF 0x08 216 217/*============================================================================= 218 Bits for the ME4000_AI_CTRL_REG register 219 ===========================================================================*/ 220 221#define ME4000_AI_CTRL_BIT_MODE_0 0x00000001 222#define ME4000_AI_CTRL_BIT_MODE_1 0x00000002 223#define ME4000_AI_CTRL_BIT_MODE_2 0x00000004 224#define ME4000_AI_CTRL_BIT_SAMPLE_HOLD 0x00000008 225#define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP 0x00000010 226#define ME4000_AI_CTRL_BIT_STOP 0x00000020 227#define ME4000_AI_CTRL_BIT_CHANNEL_FIFO 0x00000040 228#define ME4000_AI_CTRL_BIT_DATA_FIFO 0x00000080 229#define ME4000_AI_CTRL_BIT_FULLSCALE 0x00000100 230#define ME4000_AI_CTRL_BIT_OFFSET 0x00000200 231#define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG 0x00000400 232#define ME4000_AI_CTRL_BIT_EX_TRIG 0x00000800 233#define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING 0x00001000 234#define ME4000_AI_CTRL_BIT_EX_IRQ 0x00002000 235#define ME4000_AI_CTRL_BIT_EX_IRQ_RESET 0x00004000 236#define ME4000_AI_CTRL_BIT_LE_IRQ 0x00008000 237#define ME4000_AI_CTRL_BIT_LE_IRQ_RESET 0x00010000 238#define ME4000_AI_CTRL_BIT_HF_IRQ 0x00020000 239#define ME4000_AI_CTRL_BIT_HF_IRQ_RESET 0x00040000 240#define ME4000_AI_CTRL_BIT_SC_IRQ 0x00080000 241#define ME4000_AI_CTRL_BIT_SC_IRQ_RESET 0x00100000 242#define ME4000_AI_CTRL_BIT_SC_RELOAD 0x00200000 243#define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH 0x80000000 244 245/*============================================================================= 246 Bits for the ME4000_AI_STATUS_REG register 247 ===========================================================================*/ 248 249#define ME4000_AI_STATUS_BIT_EF_CHANNEL 0x00400000 250#define ME4000_AI_STATUS_BIT_HF_CHANNEL 0x00800000 251#define ME4000_AI_STATUS_BIT_FF_CHANNEL 0x01000000 252#define ME4000_AI_STATUS_BIT_EF_DATA 0x02000000 253#define ME4000_AI_STATUS_BIT_HF_DATA 0x04000000 254#define ME4000_AI_STATUS_BIT_FF_DATA 0x08000000 255#define ME4000_AI_STATUS_BIT_LE 0x10000000 256#define ME4000_AI_STATUS_BIT_FSM 0x20000000 257 258/*============================================================================= 259 Bits for the ME4000_IRQ_STATUS_REG register 260 ===========================================================================*/ 261 262#define ME4000_IRQ_STATUS_BIT_EX 0x01 263#define ME4000_IRQ_STATUS_BIT_LE 0x02 264#define ME4000_IRQ_STATUS_BIT_AI_HF 0x04 265#define ME4000_IRQ_STATUS_BIT_AO_0_HF 0x08 266#define ME4000_IRQ_STATUS_BIT_AO_1_HF 0x10 267#define ME4000_IRQ_STATUS_BIT_AO_2_HF 0x20 268#define ME4000_IRQ_STATUS_BIT_AO_3_HF 0x40 269#define ME4000_IRQ_STATUS_BIT_SC 0x80 270 271/*============================================================================= 272 Bits for the ME4000_DIO_CTRL_REG register 273 ===========================================================================*/ 274 275#define ME4000_DIO_CTRL_BIT_MODE_0 0x0001 276#define ME4000_DIO_CTRL_BIT_MODE_1 0x0002 277#define ME4000_DIO_CTRL_BIT_MODE_2 0x0004 278#define ME4000_DIO_CTRL_BIT_MODE_3 0x0008 279#define ME4000_DIO_CTRL_BIT_MODE_4 0x0010 280#define ME4000_DIO_CTRL_BIT_MODE_5 0x0020 281#define ME4000_DIO_CTRL_BIT_MODE_6 0x0040 282#define ME4000_DIO_CTRL_BIT_MODE_7 0x0080 283 284#define ME4000_DIO_CTRL_BIT_FUNCTION_0 0x0100 285#define ME4000_DIO_CTRL_BIT_FUNCTION_1 0x0200 286 287#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 0x0400 288#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 0x0800 289#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 0x1000 290#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 0x2000 291 292/*============================================================================= 293 Information about the hardware capabilities 294 ===========================================================================*/ 295 296struct me4000_ao_info { 297 int count; 298 int fifo_count; 299}; 300 301struct me4000_ai_info { 302 int count; 303 int sh_count; 304 int diff_count; 305 int ex_trig_analog; 306}; 307 308typedef struct me4000_dio_info { 309 int count; 310} me4000_dio_info_t; 311 312typedef struct me4000_cnt_info { 313 int count; 314} me4000_cnt_info_t; 315 316typedef struct me4000_board { 317 const char *name; 318 unsigned short device_id; 319 struct me4000_ao_info ao; 320 struct me4000_ai_info ai; 321 me4000_dio_info_t dio; 322 me4000_cnt_info_t cnt; 323} me4000_board_t; 324 325#define thisboard ((const me4000_board_t *)dev->board_ptr) 326 327/*============================================================================= 328 Global board and subdevice information structures 329 ===========================================================================*/ 330 331typedef struct me4000_ao_context { 332 int irq; 333 334 unsigned long mirror; /* Store the last written value */ 335 336 unsigned long ctrl_reg; 337 unsigned long status_reg; 338 unsigned long fifo_reg; 339 unsigned long single_reg; 340 unsigned long timer_reg; 341 unsigned long irq_status_reg; 342 unsigned long preload_reg; 343} me4000_ao_context_t; 344 345typedef struct me4000_ai_context { 346 int irq; 347 348 unsigned long ctrl_reg; 349 unsigned long status_reg; 350 unsigned long channel_list_reg; 351 unsigned long data_reg; 352 unsigned long chan_timer_reg; 353 unsigned long chan_pre_timer_reg; 354 unsigned long scan_timer_low_reg; 355 unsigned long scan_timer_high_reg; 356 unsigned long scan_pre_timer_low_reg; 357 unsigned long scan_pre_timer_high_reg; 358 unsigned long start_reg; 359 unsigned long irq_status_reg; 360 unsigned long sample_counter_reg; 361} me4000_ai_context_t; 362 363typedef struct me4000_dio_context { 364 unsigned long dir_reg; 365 unsigned long ctrl_reg; 366 unsigned long port_0_reg; 367 unsigned long port_1_reg; 368 unsigned long port_2_reg; 369 unsigned long port_3_reg; 370} me4000_dio_context_t; 371 372typedef struct me4000_cnt_context { 373 unsigned long ctrl_reg; 374 unsigned long counter_0_reg; 375 unsigned long counter_1_reg; 376 unsigned long counter_2_reg; 377} me4000_cnt_context_t; 378 379typedef struct me4000_info { 380 unsigned long plx_regbase; /* PLX configuration space base address */ 381 unsigned long me4000_regbase; /* Base address of the ME4000 */ 382 unsigned long timer_regbase; /* Base address of the timer circuit */ 383 unsigned long program_regbase; /* Base address to set the program pin for the xilinx */ 384 385 unsigned long plx_regbase_size; /* PLX register set space */ 386 unsigned long me4000_regbase_size; /* ME4000 register set space */ 387 unsigned long timer_regbase_size; /* Timer circuit register set space */ 388 unsigned long program_regbase_size; /* Size of program base address of the ME4000 */ 389 390 unsigned int serial_no; /* Serial number of the board */ 391 unsigned char hw_revision; /* Hardware revision of the board */ 392 unsigned short vendor_id; /* Meilhaus vendor id */ 393 unsigned short device_id; /* Device id */ 394 395 struct pci_dev *pci_dev_p; /* General PCI information */ 396 397 unsigned int irq; /* IRQ assigned from the PCI BIOS */ 398 399 struct me4000_ai_context ai_context; /* Analog input specific context */ 400 struct me4000_ao_context ao_context[4]; /* Vector with analog output specific context */ 401 struct me4000_dio_context dio_context; /* Digital I/O specific context */ 402 struct me4000_cnt_context cnt_context; /* Counter specific context */ 403} me4000_info_t; 404 405#define info ((me4000_info_t *)dev->private) 406 407/*----------------------------------------------------------------------------- 408 Defines for analog input 409 ----------------------------------------------------------------------------*/ 410 411/* General stuff */ 412#define ME4000_AI_FIFO_COUNT 2048 413 414#define ME4000_AI_MIN_TICKS 66 415#define ME4000_AI_MIN_SAMPLE_TIME 2000 /* Minimum sample time [ns] */ 416#define ME4000_AI_BASE_FREQUENCY (unsigned int) 33E6 417 418/* Channel list defines and masks */ 419#define ME4000_AI_CHANNEL_LIST_COUNT 1024 420 421#define ME4000_AI_LIST_INPUT_SINGLE_ENDED 0x000 422#define ME4000_AI_LIST_INPUT_DIFFERENTIAL 0x020 423 424#define ME4000_AI_LIST_RANGE_BIPOLAR_10 0x000 425#define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 0x040 426#define ME4000_AI_LIST_RANGE_UNIPOLAR_10 0x080 427#define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 0x0C0 428 429#define ME4000_AI_LIST_LAST_ENTRY 0x100 430 431/*----------------------------------------------------------------------------- 432 Defines for counters 433 ----------------------------------------------------------------------------*/ 434 435#define ME4000_CNT_COUNTER_0 0x00 436#define ME4000_CNT_COUNTER_1 0x40 437#define ME4000_CNT_COUNTER_2 0x80 438 439#define ME4000_CNT_MODE_0 0x00 /* Change state if zero crossing */ 440#define ME4000_CNT_MODE_1 0x02 /* Retriggerable One-Shot */ 441#define ME4000_CNT_MODE_2 0x04 /* Asymmetrical divider */ 442#define ME4000_CNT_MODE_3 0x06 /* Symmetrical divider */ 443#define ME4000_CNT_MODE_4 0x08 /* Counter start by software trigger */ 444#define ME4000_CNT_MODE_5 0x0A /* Counter start by hardware trigger */ 445 446#endif 447