mite.c revision 0a85b6f0ab0d2edb0d41b32697111ce0e4f43496
1/* 2 comedi/drivers/mite.c 3 Hardware driver for NI Mite PCI interface chip 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 22*/ 23 24/* 25 The PCI-MIO E series driver was originally written by 26 Tomasz Motylewski <...>, and ported to comedi by ds. 27 28 References for specifications: 29 30 321747b.pdf Register Level Programmer Manual (obsolete) 31 321747c.pdf Register Level Programmer Manual (new) 32 DAQ-STC reference manual 33 34 Other possibly relevant info: 35 36 320517c.pdf User manual (obsolete) 37 320517f.pdf User manual (new) 38 320889a.pdf delete 39 320906c.pdf maximum signal ratings 40 321066a.pdf about 16x 41 321791a.pdf discontinuation of at-mio-16e-10 rev. c 42 321808a.pdf about at-mio-16e-10 rev P 43 321837a.pdf discontinuation of at-mio-16de-10 rev d 44 321838a.pdf about at-mio-16de-10 rev N 45 46 ISSUES: 47 48*/ 49 50/* #define USE_KMALLOC */ 51 52#include "mite.h" 53 54#include "comedi_fc.h" 55#include "comedi_pci.h" 56#include "../comedidev.h" 57 58#include <asm/system.h> 59 60#define PCI_MITE_SIZE 4096 61#define PCI_DAQ_SIZE 4096 62#define PCI_DAQ_SIZE_660X 8192 63 64MODULE_LICENSE("GPL"); 65 66struct mite_struct *mite_devices; 67 68#define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK))) 69 70void mite_init(void) 71{ 72 struct pci_dev *pcidev; 73 struct mite_struct *mite; 74 75 for (pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL); 76 pcidev != NULL; 77 pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pcidev)) { 78 if (pcidev->vendor == PCI_VENDOR_ID_NATINST) { 79 unsigned i; 80 81 mite = kzalloc(sizeof(*mite), GFP_KERNEL); 82 if (!mite) { 83 printk("mite: allocation failed\n"); 84 pci_dev_put(pcidev); 85 return; 86 } 87 spin_lock_init(&mite->lock); 88 mite->pcidev = pci_dev_get(pcidev); 89 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) { 90 mite->channels[i].mite = mite; 91 mite->channels[i].channel = i; 92 mite->channels[i].done = 1; 93 } 94 mite->next = mite_devices; 95 mite_devices = mite; 96 } 97 } 98} 99 100static void dump_chip_signature(u32 csigr_bits) 101{ 102 printk 103 ("mite: version = %i, type = %i, mite mode = %i, interface mode = %i\n", 104 mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits), 105 mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits)); 106 printk 107 ("mite: num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n", 108 mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits), 109 mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits)); 110} 111 112unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel) 113{ 114 unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel)); 115 unsigned empty_count = (fcr_bits >> 16) & 0xff; 116 unsigned full_count = fcr_bits & 0xff; 117 return empty_count + full_count; 118} 119 120int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1) 121{ 122 unsigned long length; 123 resource_size_t addr; 124 int i; 125 u32 csigr_bits; 126 unsigned unknown_dma_burst_bits; 127 128 if (comedi_pci_enable(mite->pcidev, "mite")) { 129 printk("error enabling mite and requesting io regions\n"); 130 return -EIO; 131 } 132 pci_set_master(mite->pcidev); 133 134 addr = pci_resource_start(mite->pcidev, 0); 135 mite->mite_phys_addr = addr; 136 mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE); 137 if (!mite->mite_io_addr) { 138 printk("failed to remap mite io memory address\n"); 139 return -ENOMEM; 140 } 141 printk("MITE:0x%08llx mapped to %p ", 142 (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr); 143 144 addr = pci_resource_start(mite->pcidev, 1); 145 mite->daq_phys_addr = addr; 146 length = pci_resource_len(mite->pcidev, 1); 147 /* In case of a 660x board, DAQ size is 8k instead of 4k (see as shown by lspci output) */ 148 mite->daq_io_addr = ioremap(mite->daq_phys_addr, length); 149 if (!mite->daq_io_addr) { 150 printk("failed to remap daq io memory address\n"); 151 return -ENOMEM; 152 } 153 printk("DAQ:0x%08llx mapped to %p\n", 154 (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr); 155 156 if (use_iodwbsr_1) { 157 writel(0, mite->mite_io_addr + MITE_IODWBSR); 158 printk("mite: using I/O Window Base Size register 1\n"); 159 writel(mite->daq_phys_addr | WENAB | 160 MITE_IODWBSR_1_WSIZE_bits(length), 161 mite->mite_io_addr + MITE_IODWBSR_1); 162 writel(0, mite->mite_io_addr + MITE_IODWCR_1); 163 } else { 164 writel(mite->daq_phys_addr | WENAB, 165 mite->mite_io_addr + MITE_IODWBSR); 166 } 167 /* make sure dma bursts work. I got this from running a bus analyzer 168 on a pxi-6281 and a pxi-6713. 6713 powered up with register value 169 of 0x61f and bursts worked. 6281 powered up with register value of 170 0x1f and bursts didn't work. The NI windows driver reads the register, 171 then does a bitwise-or of 0x600 with it and writes it back. 172 */ 173 unknown_dma_burst_bits = 174 readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG); 175 unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS; 176 writel(unknown_dma_burst_bits, 177 mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG); 178 179 csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR); 180 mite->num_channels = mite_csigr_dmac(csigr_bits); 181 if (mite->num_channels > MAX_MITE_DMA_CHANNELS) { 182 printk 183 ("mite: bug? chip claims to have %i dma channels. Setting to %i.\n", 184 mite->num_channels, MAX_MITE_DMA_CHANNELS); 185 mite->num_channels = MAX_MITE_DMA_CHANNELS; 186 } 187 dump_chip_signature(csigr_bits); 188 for (i = 0; i < mite->num_channels; i++) { 189 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i)); 190 /* disable interrupts */ 191 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | 192 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | 193 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, 194 mite->mite_io_addr + MITE_CHCR(i)); 195 } 196 mite->fifo_size = mite_fifo_size(mite, 0); 197 printk("mite: fifo size is %i.\n", mite->fifo_size); 198 mite->used = 1; 199 200 return 0; 201} 202 203int mite_setup(struct mite_struct *mite) 204{ 205 return mite_setup2(mite, 0); 206} 207 208void mite_cleanup(void) 209{ 210 struct mite_struct *mite, *next; 211 212 for (mite = mite_devices; mite; mite = next) { 213 pci_dev_put(mite->pcidev); 214 next = mite->next; 215 kfree(mite); 216 } 217} 218 219void mite_unsetup(struct mite_struct *mite) 220{ 221 /* unsigned long offset, start, length; */ 222 223 if (!mite) 224 return; 225 226 if (mite->mite_io_addr) { 227 iounmap(mite->mite_io_addr); 228 mite->mite_io_addr = NULL; 229 } 230 if (mite->daq_io_addr) { 231 iounmap(mite->daq_io_addr); 232 mite->daq_io_addr = NULL; 233 } 234 if (mite->mite_phys_addr) { 235 comedi_pci_disable(mite->pcidev); 236 mite->mite_phys_addr = 0; 237 } 238 239 mite->used = 0; 240} 241 242void mite_list_devices(void) 243{ 244 struct mite_struct *mite, *next; 245 246 printk("Available NI device IDs:"); 247 if (mite_devices) 248 for (mite = mite_devices; mite; mite = next) { 249 next = mite->next; 250 printk(" 0x%04x", mite_device_id(mite)); 251 if (mite->used) 252 printk("(used)"); 253 } 254 printk("\n"); 255 256} 257 258struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite, 259 struct 260 mite_dma_descriptor_ring 261 *ring, unsigned min_channel, 262 unsigned max_channel) 263{ 264 int i; 265 unsigned long flags; 266 struct mite_channel *channel = NULL; 267 268 /* spin lock so mite_release_channel can be called safely from interrupts */ 269 spin_lock_irqsave(&mite->lock, flags); 270 for (i = min_channel; i <= max_channel; ++i) { 271 if (mite->channel_allocated[i] == 0) { 272 mite->channel_allocated[i] = 1; 273 channel = &mite->channels[i]; 274 channel->ring = ring; 275 break; 276 } 277 } 278 spin_unlock_irqrestore(&mite->lock, flags); 279 return channel; 280} 281 282void mite_release_channel(struct mite_channel *mite_chan) 283{ 284 struct mite_struct *mite = mite_chan->mite; 285 unsigned long flags; 286 287 /* spin lock to prevent races with mite_request_channel */ 288 spin_lock_irqsave(&mite->lock, flags); 289 if (mite->channel_allocated[mite_chan->channel]) { 290 mite_dma_disarm(mite_chan); 291 mite_dma_reset(mite_chan); 292/* disable all channel's interrupts (do it after disarm/reset so 293MITE_CHCR reg isn't changed while dma is still active!) */ 294 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | 295 CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE | 296 CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | 297 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, 298 mite->mite_io_addr + MITE_CHCR(mite_chan->channel)); 299 mite->channel_allocated[mite_chan->channel] = 0; 300 mite_chan->ring = NULL; 301 mmiowb(); 302 } 303 spin_unlock_irqrestore(&mite->lock, flags); 304} 305 306void mite_dma_arm(struct mite_channel *mite_chan) 307{ 308 struct mite_struct *mite = mite_chan->mite; 309 int chor; 310 unsigned long flags; 311 312 MDPRINTK("mite_dma_arm ch%i\n", channel); 313 /* memory barrier is intended to insure any twiddling with the buffer 314 is done before writing to the mite to arm dma transfer */ 315 smp_mb(); 316 /* arm */ 317 chor = CHOR_START; 318 spin_lock_irqsave(&mite->lock, flags); 319 mite_chan->done = 0; 320 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 321 mmiowb(); 322 spin_unlock_irqrestore(&mite->lock, flags); 323/* mite_dma_tcr(mite, channel); */ 324} 325 326/**************************************/ 327 328int mite_buf_change(struct mite_dma_descriptor_ring *ring, 329 struct comedi_async *async) 330{ 331 unsigned int n_links; 332 int i; 333 334 if (ring->descriptors) { 335 dma_free_coherent(ring->hw_dev, 336 ring->n_links * 337 sizeof(struct mite_dma_descriptor), 338 ring->descriptors, 339 ring->descriptors_dma_addr); 340 } 341 ring->descriptors = NULL; 342 ring->descriptors_dma_addr = 0; 343 ring->n_links = 0; 344 345 if (async->prealloc_bufsz == 0) 346 return 0; 347 348 n_links = async->prealloc_bufsz >> PAGE_SHIFT; 349 350 MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links); 351 352 ring->descriptors = 353 dma_alloc_coherent(ring->hw_dev, 354 n_links * sizeof(struct mite_dma_descriptor), 355 &ring->descriptors_dma_addr, GFP_KERNEL); 356 if (!ring->descriptors) { 357 printk("mite: ring buffer allocation failed\n"); 358 return -ENOMEM; 359 } 360 ring->n_links = n_links; 361 362 for (i = 0; i < n_links; i++) { 363 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE); 364 ring->descriptors[i].addr = 365 cpu_to_le32(async->buf_page_list[i].dma_addr); 366 ring->descriptors[i].next = 367 cpu_to_le32(ring->descriptors_dma_addr + (i + 368 1) * 369 sizeof(struct mite_dma_descriptor)); 370 } 371 ring->descriptors[n_links - 1].next = 372 cpu_to_le32(ring->descriptors_dma_addr); 373 /* barrier is meant to insure that all the writes to the dma descriptors 374 have completed before the dma controller is commanded to read them */ 375 smp_wmb(); 376 return 0; 377} 378 379void mite_prep_dma(struct mite_channel *mite_chan, 380 unsigned int num_device_bits, unsigned int num_memory_bits) 381{ 382 unsigned int chor, chcr, mcr, dcr, lkcr; 383 struct mite_struct *mite = mite_chan->mite; 384 385 MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel); 386 387 /* reset DMA and FIFO */ 388 chor = CHOR_DMARESET | CHOR_FRESET; 389 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 390 391 /* short link chaining mode */ 392 chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE | 393 CHCR_BURSTEN; 394 /* 395 * Link Complete Interrupt: interrupt every time a link 396 * in MITE_RING is completed. This can generate a lot of 397 * extra interrupts, but right now we update the values 398 * of buf_int_ptr and buf_int_count at each interrupt. A 399 * better method is to poll the MITE before each user 400 * "read()" to calculate the number of bytes available. 401 */ 402 chcr |= CHCR_SET_LC_IE; 403 if (num_memory_bits == 32 && num_device_bits == 16) { 404 /* Doing a combined 32 and 16 bit byteswap gets the 16 bit samples into the fifo in the right order. 405 Tested doing 32 bit memory to 16 bit device transfers to the analog out of a pxi-6281, 406 which has mite version = 1, type = 4. This also works for dma reads from the counters 407 on e-series boards. */ 408 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY; 409 } 410 if (mite_chan->dir == COMEDI_INPUT) 411 chcr |= CHCR_DEV_TO_MEM; 412 413 writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel)); 414 415 /* to/from memory */ 416 mcr = CR_RL(64) | CR_ASEQUP; 417 switch (num_memory_bits) { 418 case 8: 419 mcr |= CR_PSIZE8; 420 break; 421 case 16: 422 mcr |= CR_PSIZE16; 423 break; 424 case 32: 425 mcr |= CR_PSIZE32; 426 break; 427 default: 428 printk("mite: bug! invalid mem bit width for dma transfer\n"); 429 break; 430 } 431 writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel)); 432 433 /* from/to device */ 434 dcr = CR_RL(64) | CR_ASEQUP; 435 dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel); 436 switch (num_device_bits) { 437 case 8: 438 dcr |= CR_PSIZE8; 439 break; 440 case 16: 441 dcr |= CR_PSIZE16; 442 break; 443 case 32: 444 dcr |= CR_PSIZE32; 445 break; 446 default: 447 printk("mite: bug! invalid dev bit width for dma transfer\n"); 448 break; 449 } 450 writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel)); 451 452 /* reset the DAR */ 453 writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel)); 454 455 /* the link is 32bits */ 456 lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32; 457 writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel)); 458 459 /* starting address for link chaining */ 460 writel(mite_chan->ring->descriptors_dma_addr, 461 mite->mite_io_addr + MITE_LKAR(mite_chan->channel)); 462 463 MDPRINTK("exit mite_prep_dma\n"); 464} 465 466u32 mite_device_bytes_transferred(struct mite_channel *mite_chan) 467{ 468 struct mite_struct *mite = mite_chan->mite; 469 return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel)); 470} 471 472u32 mite_bytes_in_transit(struct mite_channel * mite_chan) 473{ 474 struct mite_struct *mite = mite_chan->mite; 475 return readl(mite->mite_io_addr + 476 MITE_FCR(mite_chan->channel)) & 0x000000FF; 477} 478 479/* returns lower bound for number of bytes transferred from device to memory */ 480u32 mite_bytes_written_to_memory_lb(struct mite_channel * mite_chan) 481{ 482 u32 device_byte_count; 483 484 device_byte_count = mite_device_bytes_transferred(mite_chan); 485 return device_byte_count - mite_bytes_in_transit(mite_chan); 486} 487 488/* returns upper bound for number of bytes transferred from device to memory */ 489u32 mite_bytes_written_to_memory_ub(struct mite_channel * mite_chan) 490{ 491 u32 in_transit_count; 492 493 in_transit_count = mite_bytes_in_transit(mite_chan); 494 return mite_device_bytes_transferred(mite_chan) - in_transit_count; 495} 496 497/* returns lower bound for number of bytes read from memory for transfer to device */ 498u32 mite_bytes_read_from_memory_lb(struct mite_channel * mite_chan) 499{ 500 u32 device_byte_count; 501 502 device_byte_count = mite_device_bytes_transferred(mite_chan); 503 return device_byte_count + mite_bytes_in_transit(mite_chan); 504} 505 506/* returns upper bound for number of bytes read from memory for transfer to device */ 507u32 mite_bytes_read_from_memory_ub(struct mite_channel * mite_chan) 508{ 509 u32 in_transit_count; 510 511 in_transit_count = mite_bytes_in_transit(mite_chan); 512 return mite_device_bytes_transferred(mite_chan) + in_transit_count; 513} 514 515unsigned mite_dma_tcr(struct mite_channel *mite_chan) 516{ 517 struct mite_struct *mite = mite_chan->mite; 518 int tcr; 519 int lkar; 520 521 lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel)); 522 tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel)); 523 MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel, 524 lkar, tcr); 525 526 return tcr; 527} 528 529void mite_dma_disarm(struct mite_channel *mite_chan) 530{ 531 struct mite_struct *mite = mite_chan->mite; 532 unsigned chor; 533 534 /* disarm */ 535 chor = CHOR_ABORT; 536 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 537} 538 539int mite_sync_input_dma(struct mite_channel *mite_chan, 540 struct comedi_async *async) 541{ 542 int count; 543 unsigned int nbytes, old_alloc_count; 544 const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice); 545 546 old_alloc_count = async->buf_write_alloc_count; 547 /* write alloc as much as we can */ 548 comedi_buf_write_alloc(async, async->prealloc_bufsz); 549 550 nbytes = mite_bytes_written_to_memory_lb(mite_chan); 551 if ((int)(mite_bytes_written_to_memory_ub(mite_chan) - 552 old_alloc_count) > 0) { 553 printk("mite: DMA overwrite of free area\n"); 554 async->events |= COMEDI_CB_OVERFLOW; 555 return -1; 556 } 557 558 count = nbytes - async->buf_write_count; 559 /* it's possible count will be negative due to 560 * conservative value returned by mite_bytes_written_to_memory_lb */ 561 if (count <= 0) 562 return 0; 563 564 comedi_buf_write_free(async, count); 565 566 async->scan_progress += count; 567 if (async->scan_progress >= bytes_per_scan) { 568 async->scan_progress %= bytes_per_scan; 569 async->events |= COMEDI_CB_EOS; 570 } 571 async->events |= COMEDI_CB_BLOCK; 572 return 0; 573} 574 575int mite_sync_output_dma(struct mite_channel *mite_chan, 576 struct comedi_async *async) 577{ 578 int count; 579 u32 nbytes_ub, nbytes_lb; 580 unsigned int old_alloc_count; 581 u32 stop_count = 582 async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice); 583 584 old_alloc_count = async->buf_read_alloc_count; 585 /* read alloc as much as we can */ 586 comedi_buf_read_alloc(async, async->prealloc_bufsz); 587 nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan); 588 if (async->cmd.stop_src == TRIG_COUNT && 589 (int)(nbytes_lb - stop_count) > 0) 590 nbytes_lb = stop_count; 591 nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan); 592 if (async->cmd.stop_src == TRIG_COUNT && 593 (int)(nbytes_ub - stop_count) > 0) 594 nbytes_ub = stop_count; 595 if ((int)(nbytes_ub - old_alloc_count) > 0) { 596 printk("mite: DMA underrun\n"); 597 async->events |= COMEDI_CB_OVERFLOW; 598 return -1; 599 } 600 count = nbytes_lb - async->buf_read_count; 601 if (count <= 0) 602 return 0; 603 604 if (count) { 605 comedi_buf_read_free(async, count); 606 async->events |= COMEDI_CB_BLOCK; 607 } 608 return 0; 609} 610 611unsigned mite_get_status(struct mite_channel *mite_chan) 612{ 613 struct mite_struct *mite = mite_chan->mite; 614 unsigned status; 615 unsigned long flags; 616 617 spin_lock_irqsave(&mite->lock, flags); 618 status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel)); 619 if (status & CHSR_DONE) { 620 mite_chan->done = 1; 621 writel(CHOR_CLRDONE, 622 mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 623 } 624 mmiowb(); 625 spin_unlock_irqrestore(&mite->lock, flags); 626 return status; 627} 628 629int mite_done(struct mite_channel *mite_chan) 630{ 631 struct mite_struct *mite = mite_chan->mite; 632 unsigned long flags; 633 int done; 634 635 mite_get_status(mite_chan); 636 spin_lock_irqsave(&mite->lock, flags); 637 done = mite_chan->done; 638 spin_unlock_irqrestore(&mite->lock, flags); 639 return done; 640} 641 642#ifdef DEBUG_MITE 643 644static void mite_decode(char **bit_str, unsigned int bits); 645 646/* names of bits in mite registers */ 647 648static const char *const mite_CHOR_strings[] = { 649 "start", "cont", "stop", "abort", 650 "freset", "clrlc", "clrrb", "clrdone", 651 "clr_lpause", "set_lpause", "clr_send_tc", 652 "set_send_tc", "12", "13", "14", 653 "15", "16", "17", "18", 654 "19", "20", "21", "22", 655 "23", "24", "25", "26", 656 "27", "28", "29", "30", 657 "dmareset", 658}; 659 660static const char *const mite_CHCR_strings[] = { 661 "continue", "ringbuff", "2", "3", 662 "4", "5", "6", "7", 663 "8", "9", "10", "11", 664 "12", "13", "bursten", "fifodis", 665 "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie", 666 "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie", 667 "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie", 668 "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie", 669}; 670 671static const char *const mite_MCR_strings[] = { 672 "amdevice", "1", "2", "3", 673 "4", "5", "portio", "portvxi", 674 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11", 675 "12", "13", "blocken", "berhand", 676 "reqsintlim/reqs0", "reqs1", "reqs2", "rd32", 677 "rd512", "rl1", "rl2", "rl8", 678 "24", "25", "26", "27", 679 "28", "29", "30", "stopen", 680}; 681 682static const char *const mite_DCR_strings[] = { 683 "amdevice", "1", "2", "3", 684 "4", "5", "portio", "portvxi", 685 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2", 686 "aseqxp8", "13", "blocken", "berhand", 687 "reqsintlim", "reqs1", "reqs2", "rd32", 688 "rd512", "rl1", "rl2", "rl8", 689 "23", "24", "25", "27", 690 "28", "wsdevc", "wsdevs", "rwdevpack", 691}; 692 693static const char *const mite_LKCR_strings[] = { 694 "amdevice", "1", "2", "3", 695 "4", "5", "portio", "portvxi", 696 "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown", 697 "12", "13", "14", "berhand", 698 "16", "17", "18", "rd32", 699 "rd512", "rl1", "rl2", "rl8", 700 "24", "25", "26", "27", 701 "28", "29", "30", "chngend", 702}; 703 704static const char *const mite_CHSR_strings[] = { 705 "d.err0", "d.err1", "m.err0", "m.err1", 706 "l.err0", "l.err1", "drq0", "drq1", 707 "end", "xferr", "operr0", "operr1", 708 "stops", "habort", "sabort", "error", 709 "16", "conts_rb", "18", "linkc", 710 "20", "drdy", "22", "mrdy", 711 "24", "done", "26", "sars", 712 "28", "lpauses", "30", "int", 713}; 714 715void mite_dump_regs(struct mite_channel *mite_chan) 716{ 717 unsigned long mite_io_addr = 718 (unsigned long)mite_chan->mite->mite_io_addr; 719 unsigned long addr = 0; 720 unsigned long temp = 0; 721 722 printk("mite_dump_regs ch%i\n", mite_chan->channel); 723 printk("mite address is =0x%08lx\n", mite_io_addr); 724 725 addr = mite_io_addr + MITE_CHOR(channel); 726 printk("mite status[CHOR]at 0x%08lx =0x%08lx\n", addr, temp = 727 readl(addr)); 728 mite_decode(mite_CHOR_strings, temp); 729 addr = mite_io_addr + MITE_CHCR(channel); 730 printk("mite status[CHCR]at 0x%08lx =0x%08lx\n", addr, temp = 731 readl(addr)); 732 mite_decode(mite_CHCR_strings, temp); 733 addr = mite_io_addr + MITE_TCR(channel); 734 printk("mite status[TCR] at 0x%08lx =0x%08x\n", addr, readl(addr)); 735 addr = mite_io_addr + MITE_MCR(channel); 736 printk("mite status[MCR] at 0x%08lx =0x%08lx\n", addr, temp = 737 readl(addr)); 738 mite_decode(mite_MCR_strings, temp); 739 740 addr = mite_io_addr + MITE_MAR(channel); 741 printk("mite status[MAR] at 0x%08lx =0x%08x\n", addr, readl(addr)); 742 addr = mite_io_addr + MITE_DCR(channel); 743 printk("mite status[DCR] at 0x%08lx =0x%08lx\n", addr, temp = 744 readl(addr)); 745 mite_decode(mite_DCR_strings, temp); 746 addr = mite_io_addr + MITE_DAR(channel); 747 printk("mite status[DAR] at 0x%08lx =0x%08x\n", addr, readl(addr)); 748 addr = mite_io_addr + MITE_LKCR(channel); 749 printk("mite status[LKCR]at 0x%08lx =0x%08lx\n", addr, temp = 750 readl(addr)); 751 mite_decode(mite_LKCR_strings, temp); 752 addr = mite_io_addr + MITE_LKAR(channel); 753 printk("mite status[LKAR]at 0x%08lx =0x%08x\n", addr, readl(addr)); 754 755 addr = mite_io_addr + MITE_CHSR(channel); 756 printk("mite status[CHSR]at 0x%08lx =0x%08lx\n", addr, temp = 757 readl(addr)); 758 mite_decode(mite_CHSR_strings, temp); 759 addr = mite_io_addr + MITE_FCR(channel); 760 printk("mite status[FCR] at 0x%08lx =0x%08x\n\n", addr, readl(addr)); 761} 762 763static void mite_decode(char **bit_str, unsigned int bits) 764{ 765 int i; 766 767 for (i = 31; i >= 0; i--) { 768 if (bits & (1 << i)) 769 printk(" %s", bit_str[i]); 770 } 771 printk("\n"); 772} 773#endif 774 775#ifdef MODULE 776int __init init_module(void) 777{ 778 mite_init(); 779 mite_list_devices(); 780 781 return 0; 782} 783 784void __exit cleanup_module(void) 785{ 786 mite_cleanup(); 787} 788 789EXPORT_SYMBOL(mite_dma_tcr); 790EXPORT_SYMBOL(mite_dma_arm); 791EXPORT_SYMBOL(mite_dma_disarm); 792EXPORT_SYMBOL(mite_sync_input_dma); 793EXPORT_SYMBOL(mite_sync_output_dma); 794EXPORT_SYMBOL(mite_setup); 795EXPORT_SYMBOL(mite_setup2); 796EXPORT_SYMBOL(mite_unsetup); 797#if 0 798EXPORT_SYMBOL(mite_kvmem_segment_load); 799EXPORT_SYMBOL(mite_ll_from_kvmem); 800EXPORT_SYMBOL(mite_setregs); 801#endif 802EXPORT_SYMBOL(mite_devices); 803EXPORT_SYMBOL(mite_list_devices); 804EXPORT_SYMBOL(mite_request_channel_in_range); 805EXPORT_SYMBOL(mite_release_channel); 806EXPORT_SYMBOL(mite_prep_dma); 807EXPORT_SYMBOL(mite_buf_change); 808EXPORT_SYMBOL(mite_bytes_written_to_memory_lb); 809EXPORT_SYMBOL(mite_bytes_written_to_memory_ub); 810EXPORT_SYMBOL(mite_bytes_read_from_memory_lb); 811EXPORT_SYMBOL(mite_bytes_read_from_memory_ub); 812EXPORT_SYMBOL(mite_bytes_in_transit); 813EXPORT_SYMBOL(mite_get_status); 814EXPORT_SYMBOL(mite_done); 815#ifdef DEBUG_MITE 816EXPORT_SYMBOL(mite_decode); 817EXPORT_SYMBOL(mite_dump_regs); 818#endif 819 820#endif 821