mite.c revision 9ffc93f203c18a70623f21950f1dd473c9ec48cd
1/* 2 comedi/drivers/mite.c 3 Hardware driver for NI Mite PCI interface chip 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 22*/ 23 24/* 25 The PCI-MIO E series driver was originally written by 26 Tomasz Motylewski <...>, and ported to comedi by ds. 27 28 References for specifications: 29 30 321747b.pdf Register Level Programmer Manual (obsolete) 31 321747c.pdf Register Level Programmer Manual (new) 32 DAQ-STC reference manual 33 34 Other possibly relevant info: 35 36 320517c.pdf User manual (obsolete) 37 320517f.pdf User manual (new) 38 320889a.pdf delete 39 320906c.pdf maximum signal ratings 40 321066a.pdf about 16x 41 321791a.pdf discontinuation of at-mio-16e-10 rev. c 42 321808a.pdf about at-mio-16e-10 rev P 43 321837a.pdf discontinuation of at-mio-16de-10 rev d 44 321838a.pdf about at-mio-16de-10 rev N 45 46 ISSUES: 47 48*/ 49 50/* #define USE_KMALLOC */ 51 52#include "mite.h" 53 54#include "comedi_fc.h" 55#include "comedi_pci.h" 56#include "../comedidev.h" 57 58 59#define PCI_MITE_SIZE 4096 60#define PCI_DAQ_SIZE 4096 61#define PCI_DAQ_SIZE_660X 8192 62 63struct mite_struct *mite_devices; 64EXPORT_SYMBOL(mite_devices); 65 66#define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK))) 67 68void mite_init(void) 69{ 70 struct pci_dev *pcidev = NULL; 71 struct mite_struct *mite; 72 73 for_each_pci_dev(pcidev) { 74 if (pcidev->vendor == PCI_VENDOR_ID_NI) { 75 unsigned i; 76 77 mite = kzalloc(sizeof(*mite), GFP_KERNEL); 78 if (!mite) { 79 printk(KERN_ERR "mite: allocation failed\n"); 80 pci_dev_put(pcidev); 81 return; 82 } 83 spin_lock_init(&mite->lock); 84 mite->pcidev = pci_dev_get(pcidev); 85 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) { 86 mite->channels[i].mite = mite; 87 mite->channels[i].channel = i; 88 mite->channels[i].done = 1; 89 } 90 mite->next = mite_devices; 91 mite_devices = mite; 92 } 93 } 94} 95 96static void dump_chip_signature(u32 csigr_bits) 97{ 98 printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i," 99 "interface mode = %i\n", 100 mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits), 101 mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits)); 102 printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i," 103 "wins = %i, iowins = %i\n", 104 mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits), 105 mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits)); 106} 107 108unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel) 109{ 110 unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel)); 111 unsigned empty_count = (fcr_bits >> 16) & 0xff; 112 unsigned full_count = fcr_bits & 0xff; 113 return empty_count + full_count; 114} 115 116int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1) 117{ 118 unsigned long length; 119 resource_size_t addr; 120 int i; 121 u32 csigr_bits; 122 unsigned unknown_dma_burst_bits; 123 124 if (comedi_pci_enable(mite->pcidev, "mite")) { 125 printk(KERN_ERR "error enabling mite and requesting io regions\n"); 126 return -EIO; 127 } 128 pci_set_master(mite->pcidev); 129 130 addr = pci_resource_start(mite->pcidev, 0); 131 mite->mite_phys_addr = addr; 132 mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE); 133 if (!mite->mite_io_addr) { 134 printk(KERN_ERR "Failed to remap mite io memory address\n"); 135 return -ENOMEM; 136 } 137 printk(KERN_INFO "MITE:0x%08llx mapped to %p ", 138 (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr); 139 140 addr = pci_resource_start(mite->pcidev, 1); 141 mite->daq_phys_addr = addr; 142 length = pci_resource_len(mite->pcidev, 1); 143 /* 144 * In case of a 660x board, DAQ size is 8k instead of 4k 145 * (see as shown by lspci output) 146 */ 147 mite->daq_io_addr = ioremap(mite->daq_phys_addr, length); 148 if (!mite->daq_io_addr) { 149 printk(KERN_ERR "Failed to remap daq io memory address\n"); 150 return -ENOMEM; 151 } 152 printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n", 153 (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr); 154 155 if (use_iodwbsr_1) { 156 writel(0, mite->mite_io_addr + MITE_IODWBSR); 157 printk(KERN_INFO "mite: using I/O Window Base Size register 1\n"); 158 writel(mite->daq_phys_addr | WENAB | 159 MITE_IODWBSR_1_WSIZE_bits(length), 160 mite->mite_io_addr + MITE_IODWBSR_1); 161 writel(0, mite->mite_io_addr + MITE_IODWCR_1); 162 } else { 163 writel(mite->daq_phys_addr | WENAB, 164 mite->mite_io_addr + MITE_IODWBSR); 165 } 166 /* 167 * make sure dma bursts work. I got this from running a bus analyzer 168 * on a pxi-6281 and a pxi-6713. 6713 powered up with register value 169 * of 0x61f and bursts worked. 6281 powered up with register value of 170 * 0x1f and bursts didn't work. The NI windows driver reads the 171 * register, then does a bitwise-or of 0x600 with it and writes it back. 172 */ 173 unknown_dma_burst_bits = 174 readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG); 175 unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS; 176 writel(unknown_dma_burst_bits, 177 mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG); 178 179 csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR); 180 mite->num_channels = mite_csigr_dmac(csigr_bits); 181 if (mite->num_channels > MAX_MITE_DMA_CHANNELS) { 182 printk(KERN_WARNING "mite: bug? chip claims to have %i dma " 183 "channels. Setting to %i.\n", 184 mite->num_channels, MAX_MITE_DMA_CHANNELS); 185 mite->num_channels = MAX_MITE_DMA_CHANNELS; 186 } 187 dump_chip_signature(csigr_bits); 188 for (i = 0; i < mite->num_channels; i++) { 189 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i)); 190 /* disable interrupts */ 191 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | 192 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | 193 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, 194 mite->mite_io_addr + MITE_CHCR(i)); 195 } 196 mite->fifo_size = mite_fifo_size(mite, 0); 197 printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size); 198 mite->used = 1; 199 200 return 0; 201} 202EXPORT_SYMBOL(mite_setup2); 203 204int mite_setup(struct mite_struct *mite) 205{ 206 return mite_setup2(mite, 0); 207} 208EXPORT_SYMBOL(mite_setup); 209 210void mite_cleanup(void) 211{ 212 struct mite_struct *mite, *next; 213 214 for (mite = mite_devices; mite; mite = next) { 215 pci_dev_put(mite->pcidev); 216 next = mite->next; 217 kfree(mite); 218 } 219} 220 221void mite_unsetup(struct mite_struct *mite) 222{ 223 /* unsigned long offset, start, length; */ 224 225 if (!mite) 226 return; 227 228 if (mite->mite_io_addr) { 229 iounmap(mite->mite_io_addr); 230 mite->mite_io_addr = NULL; 231 } 232 if (mite->daq_io_addr) { 233 iounmap(mite->daq_io_addr); 234 mite->daq_io_addr = NULL; 235 } 236 if (mite->mite_phys_addr) { 237 comedi_pci_disable(mite->pcidev); 238 mite->mite_phys_addr = 0; 239 } 240 241 mite->used = 0; 242} 243EXPORT_SYMBOL(mite_unsetup); 244 245void mite_list_devices(void) 246{ 247 struct mite_struct *mite, *next; 248 249 printk(KERN_INFO "Available NI device IDs:"); 250 if (mite_devices) 251 for (mite = mite_devices; mite; mite = next) { 252 next = mite->next; 253 printk(KERN_INFO " 0x%04x", mite_device_id(mite)); 254 if (mite->used) 255 printk(KERN_INFO "(used)"); 256 } 257 printk(KERN_INFO "\n"); 258} 259EXPORT_SYMBOL(mite_list_devices); 260 261struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite, 262 struct 263 mite_dma_descriptor_ring 264 *ring, unsigned min_channel, 265 unsigned max_channel) 266{ 267 int i; 268 unsigned long flags; 269 struct mite_channel *channel = NULL; 270 271 /* spin lock so mite_release_channel can be called safely 272 * from interrupts 273 */ 274 spin_lock_irqsave(&mite->lock, flags); 275 for (i = min_channel; i <= max_channel; ++i) { 276 if (mite->channel_allocated[i] == 0) { 277 mite->channel_allocated[i] = 1; 278 channel = &mite->channels[i]; 279 channel->ring = ring; 280 break; 281 } 282 } 283 spin_unlock_irqrestore(&mite->lock, flags); 284 return channel; 285} 286EXPORT_SYMBOL(mite_request_channel_in_range); 287 288void mite_release_channel(struct mite_channel *mite_chan) 289{ 290 struct mite_struct *mite = mite_chan->mite; 291 unsigned long flags; 292 293 /* spin lock to prevent races with mite_request_channel */ 294 spin_lock_irqsave(&mite->lock, flags); 295 if (mite->channel_allocated[mite_chan->channel]) { 296 mite_dma_disarm(mite_chan); 297 mite_dma_reset(mite_chan); 298 /* 299 * disable all channel's interrupts (do it after disarm/reset so 300 * MITE_CHCR reg isn't changed while dma is still active!) 301 */ 302 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | 303 CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE | 304 CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | 305 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, 306 mite->mite_io_addr + MITE_CHCR(mite_chan->channel)); 307 mite->channel_allocated[mite_chan->channel] = 0; 308 mite_chan->ring = NULL; 309 mmiowb(); 310 } 311 spin_unlock_irqrestore(&mite->lock, flags); 312} 313EXPORT_SYMBOL(mite_release_channel); 314 315void mite_dma_arm(struct mite_channel *mite_chan) 316{ 317 struct mite_struct *mite = mite_chan->mite; 318 int chor; 319 unsigned long flags; 320 321 MDPRINTK("mite_dma_arm ch%i\n", channel); 322 /* 323 * memory barrier is intended to insure any twiddling with the buffer 324 * is done before writing to the mite to arm dma transfer 325 */ 326 smp_mb(); 327 /* arm */ 328 chor = CHOR_START; 329 spin_lock_irqsave(&mite->lock, flags); 330 mite_chan->done = 0; 331 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 332 mmiowb(); 333 spin_unlock_irqrestore(&mite->lock, flags); 334/* mite_dma_tcr(mite, channel); */ 335} 336EXPORT_SYMBOL(mite_dma_arm); 337 338/**************************************/ 339 340int mite_buf_change(struct mite_dma_descriptor_ring *ring, 341 struct comedi_async *async) 342{ 343 unsigned int n_links; 344 int i; 345 346 if (ring->descriptors) { 347 dma_free_coherent(ring->hw_dev, 348 ring->n_links * 349 sizeof(struct mite_dma_descriptor), 350 ring->descriptors, 351 ring->descriptors_dma_addr); 352 } 353 ring->descriptors = NULL; 354 ring->descriptors_dma_addr = 0; 355 ring->n_links = 0; 356 357 if (async->prealloc_bufsz == 0) 358 return 0; 359 360 n_links = async->prealloc_bufsz >> PAGE_SHIFT; 361 362 MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links); 363 364 ring->descriptors = 365 dma_alloc_coherent(ring->hw_dev, 366 n_links * sizeof(struct mite_dma_descriptor), 367 &ring->descriptors_dma_addr, GFP_KERNEL); 368 if (!ring->descriptors) { 369 printk(KERN_ERR "mite: ring buffer allocation failed\n"); 370 return -ENOMEM; 371 } 372 ring->n_links = n_links; 373 374 for (i = 0; i < n_links; i++) { 375 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE); 376 ring->descriptors[i].addr = 377 cpu_to_le32(async->buf_page_list[i].dma_addr); 378 ring->descriptors[i].next = 379 cpu_to_le32(ring->descriptors_dma_addr + (i + 380 1) * 381 sizeof(struct mite_dma_descriptor)); 382 } 383 ring->descriptors[n_links - 1].next = 384 cpu_to_le32(ring->descriptors_dma_addr); 385 /* 386 * barrier is meant to insure that all the writes to the dma descriptors 387 * have completed before the dma controller is commanded to read them 388 */ 389 smp_wmb(); 390 return 0; 391} 392EXPORT_SYMBOL(mite_buf_change); 393 394void mite_prep_dma(struct mite_channel *mite_chan, 395 unsigned int num_device_bits, unsigned int num_memory_bits) 396{ 397 unsigned int chor, chcr, mcr, dcr, lkcr; 398 struct mite_struct *mite = mite_chan->mite; 399 400 MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel); 401 402 /* reset DMA and FIFO */ 403 chor = CHOR_DMARESET | CHOR_FRESET; 404 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 405 406 /* short link chaining mode */ 407 chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE | 408 CHCR_BURSTEN; 409 /* 410 * Link Complete Interrupt: interrupt every time a link 411 * in MITE_RING is completed. This can generate a lot of 412 * extra interrupts, but right now we update the values 413 * of buf_int_ptr and buf_int_count at each interrupt. A 414 * better method is to poll the MITE before each user 415 * "read()" to calculate the number of bytes available. 416 */ 417 chcr |= CHCR_SET_LC_IE; 418 if (num_memory_bits == 32 && num_device_bits == 16) { 419 /* 420 * Doing a combined 32 and 16 bit byteswap gets the 16 bit 421 * samples into the fifo in the right order. Tested doing 32 bit 422 * memory to 16 bit device transfers to the analog out of a 423 * pxi-6281, which has mite version = 1, type = 4. This also 424 * works for dma reads from the counters on e-series boards. 425 */ 426 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY; 427 } 428 if (mite_chan->dir == COMEDI_INPUT) 429 chcr |= CHCR_DEV_TO_MEM; 430 431 writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel)); 432 433 /* to/from memory */ 434 mcr = CR_RL(64) | CR_ASEQUP; 435 switch (num_memory_bits) { 436 case 8: 437 mcr |= CR_PSIZE8; 438 break; 439 case 16: 440 mcr |= CR_PSIZE16; 441 break; 442 case 32: 443 mcr |= CR_PSIZE32; 444 break; 445 default: 446 printk(KERN_WARNING "mite: bug! invalid mem bit width for dma " 447 "transfer\n"); 448 break; 449 } 450 writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel)); 451 452 /* from/to device */ 453 dcr = CR_RL(64) | CR_ASEQUP; 454 dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel); 455 switch (num_device_bits) { 456 case 8: 457 dcr |= CR_PSIZE8; 458 break; 459 case 16: 460 dcr |= CR_PSIZE16; 461 break; 462 case 32: 463 dcr |= CR_PSIZE32; 464 break; 465 default: 466 printk(KERN_WARNING "mite: bug! invalid dev bit width for dma " 467 "transfer\n"); 468 break; 469 } 470 writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel)); 471 472 /* reset the DAR */ 473 writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel)); 474 475 /* the link is 32bits */ 476 lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32; 477 writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel)); 478 479 /* starting address for link chaining */ 480 writel(mite_chan->ring->descriptors_dma_addr, 481 mite->mite_io_addr + MITE_LKAR(mite_chan->channel)); 482 483 MDPRINTK("exit mite_prep_dma\n"); 484} 485EXPORT_SYMBOL(mite_prep_dma); 486 487u32 mite_device_bytes_transferred(struct mite_channel *mite_chan) 488{ 489 struct mite_struct *mite = mite_chan->mite; 490 return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel)); 491} 492 493u32 mite_bytes_in_transit(struct mite_channel *mite_chan) 494{ 495 struct mite_struct *mite = mite_chan->mite; 496 return readl(mite->mite_io_addr + 497 MITE_FCR(mite_chan->channel)) & 0x000000FF; 498} 499EXPORT_SYMBOL(mite_bytes_in_transit); 500 501/* returns lower bound for number of bytes transferred from device to memory */ 502u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan) 503{ 504 u32 device_byte_count; 505 506 device_byte_count = mite_device_bytes_transferred(mite_chan); 507 return device_byte_count - mite_bytes_in_transit(mite_chan); 508} 509EXPORT_SYMBOL(mite_bytes_written_to_memory_lb); 510 511/* returns upper bound for number of bytes transferred from device to memory */ 512u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan) 513{ 514 u32 in_transit_count; 515 516 in_transit_count = mite_bytes_in_transit(mite_chan); 517 return mite_device_bytes_transferred(mite_chan) - in_transit_count; 518} 519EXPORT_SYMBOL(mite_bytes_written_to_memory_ub); 520 521/* returns lower bound for number of bytes read from memory to device */ 522u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan) 523{ 524 u32 device_byte_count; 525 526 device_byte_count = mite_device_bytes_transferred(mite_chan); 527 return device_byte_count + mite_bytes_in_transit(mite_chan); 528} 529EXPORT_SYMBOL(mite_bytes_read_from_memory_lb); 530 531/* returns upper bound for number of bytes read from memory to device */ 532u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan) 533{ 534 u32 in_transit_count; 535 536 in_transit_count = mite_bytes_in_transit(mite_chan); 537 return mite_device_bytes_transferred(mite_chan) + in_transit_count; 538} 539EXPORT_SYMBOL(mite_bytes_read_from_memory_ub); 540 541unsigned mite_dma_tcr(struct mite_channel *mite_chan) 542{ 543 struct mite_struct *mite = mite_chan->mite; 544 int tcr; 545 int lkar; 546 547 lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel)); 548 tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel)); 549 MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel, 550 lkar, tcr); 551 552 return tcr; 553} 554EXPORT_SYMBOL(mite_dma_tcr); 555 556void mite_dma_disarm(struct mite_channel *mite_chan) 557{ 558 struct mite_struct *mite = mite_chan->mite; 559 unsigned chor; 560 561 /* disarm */ 562 chor = CHOR_ABORT; 563 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 564} 565EXPORT_SYMBOL(mite_dma_disarm); 566 567int mite_sync_input_dma(struct mite_channel *mite_chan, 568 struct comedi_async *async) 569{ 570 int count; 571 unsigned int nbytes, old_alloc_count; 572 const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice); 573 574 old_alloc_count = async->buf_write_alloc_count; 575 /* write alloc as much as we can */ 576 comedi_buf_write_alloc(async, async->prealloc_bufsz); 577 578 nbytes = mite_bytes_written_to_memory_lb(mite_chan); 579 if ((int)(mite_bytes_written_to_memory_ub(mite_chan) - 580 old_alloc_count) > 0) { 581 printk("mite: DMA overwrite of free area\n"); 582 async->events |= COMEDI_CB_OVERFLOW; 583 return -1; 584 } 585 586 count = nbytes - async->buf_write_count; 587 /* it's possible count will be negative due to 588 * conservative value returned by mite_bytes_written_to_memory_lb */ 589 if (count <= 0) 590 return 0; 591 592 comedi_buf_write_free(async, count); 593 594 async->scan_progress += count; 595 if (async->scan_progress >= bytes_per_scan) { 596 async->scan_progress %= bytes_per_scan; 597 async->events |= COMEDI_CB_EOS; 598 } 599 async->events |= COMEDI_CB_BLOCK; 600 return 0; 601} 602EXPORT_SYMBOL(mite_sync_input_dma); 603 604int mite_sync_output_dma(struct mite_channel *mite_chan, 605 struct comedi_async *async) 606{ 607 int count; 608 u32 nbytes_ub, nbytes_lb; 609 unsigned int old_alloc_count; 610 u32 stop_count = 611 async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice); 612 613 old_alloc_count = async->buf_read_alloc_count; 614 /* read alloc as much as we can */ 615 comedi_buf_read_alloc(async, async->prealloc_bufsz); 616 nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan); 617 if (async->cmd.stop_src == TRIG_COUNT && 618 (int)(nbytes_lb - stop_count) > 0) 619 nbytes_lb = stop_count; 620 nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan); 621 if (async->cmd.stop_src == TRIG_COUNT && 622 (int)(nbytes_ub - stop_count) > 0) 623 nbytes_ub = stop_count; 624 if ((int)(nbytes_ub - old_alloc_count) > 0) { 625 printk(KERN_ERR "mite: DMA underrun\n"); 626 async->events |= COMEDI_CB_OVERFLOW; 627 return -1; 628 } 629 count = nbytes_lb - async->buf_read_count; 630 if (count <= 0) 631 return 0; 632 633 if (count) { 634 comedi_buf_read_free(async, count); 635 async->events |= COMEDI_CB_BLOCK; 636 } 637 return 0; 638} 639EXPORT_SYMBOL(mite_sync_output_dma); 640 641unsigned mite_get_status(struct mite_channel *mite_chan) 642{ 643 struct mite_struct *mite = mite_chan->mite; 644 unsigned status; 645 unsigned long flags; 646 647 spin_lock_irqsave(&mite->lock, flags); 648 status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel)); 649 if (status & CHSR_DONE) { 650 mite_chan->done = 1; 651 writel(CHOR_CLRDONE, 652 mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 653 } 654 mmiowb(); 655 spin_unlock_irqrestore(&mite->lock, flags); 656 return status; 657} 658EXPORT_SYMBOL(mite_get_status); 659 660int mite_done(struct mite_channel *mite_chan) 661{ 662 struct mite_struct *mite = mite_chan->mite; 663 unsigned long flags; 664 int done; 665 666 mite_get_status(mite_chan); 667 spin_lock_irqsave(&mite->lock, flags); 668 done = mite_chan->done; 669 spin_unlock_irqrestore(&mite->lock, flags); 670 return done; 671} 672EXPORT_SYMBOL(mite_done); 673 674#ifdef DEBUG_MITE 675 676static void mite_decode(char **bit_str, unsigned int bits); 677 678/* names of bits in mite registers */ 679 680static const char *const mite_CHOR_strings[] = { 681 "start", "cont", "stop", "abort", 682 "freset", "clrlc", "clrrb", "clrdone", 683 "clr_lpause", "set_lpause", "clr_send_tc", 684 "set_send_tc", "12", "13", "14", 685 "15", "16", "17", "18", 686 "19", "20", "21", "22", 687 "23", "24", "25", "26", 688 "27", "28", "29", "30", 689 "dmareset", 690}; 691 692static const char *const mite_CHCR_strings[] = { 693 "continue", "ringbuff", "2", "3", 694 "4", "5", "6", "7", 695 "8", "9", "10", "11", 696 "12", "13", "bursten", "fifodis", 697 "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie", 698 "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie", 699 "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie", 700 "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie", 701}; 702 703static const char *const mite_MCR_strings[] = { 704 "amdevice", "1", "2", "3", 705 "4", "5", "portio", "portvxi", 706 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11", 707 "12", "13", "blocken", "berhand", 708 "reqsintlim/reqs0", "reqs1", "reqs2", "rd32", 709 "rd512", "rl1", "rl2", "rl8", 710 "24", "25", "26", "27", 711 "28", "29", "30", "stopen", 712}; 713 714static const char *const mite_DCR_strings[] = { 715 "amdevice", "1", "2", "3", 716 "4", "5", "portio", "portvxi", 717 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2", 718 "aseqxp8", "13", "blocken", "berhand", 719 "reqsintlim", "reqs1", "reqs2", "rd32", 720 "rd512", "rl1", "rl2", "rl8", 721 "23", "24", "25", "27", 722 "28", "wsdevc", "wsdevs", "rwdevpack", 723}; 724 725static const char *const mite_LKCR_strings[] = { 726 "amdevice", "1", "2", "3", 727 "4", "5", "portio", "portvxi", 728 "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown", 729 "12", "13", "14", "berhand", 730 "16", "17", "18", "rd32", 731 "rd512", "rl1", "rl2", "rl8", 732 "24", "25", "26", "27", 733 "28", "29", "30", "chngend", 734}; 735 736static const char *const mite_CHSR_strings[] = { 737 "d.err0", "d.err1", "m.err0", "m.err1", 738 "l.err0", "l.err1", "drq0", "drq1", 739 "end", "xferr", "operr0", "operr1", 740 "stops", "habort", "sabort", "error", 741 "16", "conts_rb", "18", "linkc", 742 "20", "drdy", "22", "mrdy", 743 "24", "done", "26", "sars", 744 "28", "lpauses", "30", "int", 745}; 746 747void mite_dump_regs(struct mite_channel *mite_chan) 748{ 749 unsigned long mite_io_addr = 750 (unsigned long)mite_chan->mite->mite_io_addr; 751 unsigned long addr = 0; 752 unsigned long temp = 0; 753 754 printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel); 755 printk(KERN_DEBUG "mite address is =0x%08lx\n", mite_io_addr); 756 757 addr = mite_io_addr + MITE_CHOR(channel); 758 printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr, 759 temp = readl(addr)); 760 mite_decode(mite_CHOR_strings, temp); 761 addr = mite_io_addr + MITE_CHCR(channel); 762 printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr, 763 temp = readl(addr)); 764 mite_decode(mite_CHCR_strings, temp); 765 addr = mite_io_addr + MITE_TCR(channel); 766 printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr, 767 readl(addr)); 768 addr = mite_io_addr + MITE_MCR(channel); 769 printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr, 770 temp = readl(addr)); 771 mite_decode(mite_MCR_strings, temp); 772 773 addr = mite_io_addr + MITE_MAR(channel); 774 printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr, 775 readl(addr)); 776 addr = mite_io_addr + MITE_DCR(channel); 777 printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr, 778 temp = readl(addr)); 779 mite_decode(mite_DCR_strings, temp); 780 addr = mite_io_addr + MITE_DAR(channel); 781 printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr, 782 readl(addr)); 783 addr = mite_io_addr + MITE_LKCR(channel); 784 printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr, 785 temp = readl(addr)); 786 mite_decode(mite_LKCR_strings, temp); 787 addr = mite_io_addr + MITE_LKAR(channel); 788 printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr, 789 readl(addr)); 790 addr = mite_io_addr + MITE_CHSR(channel); 791 printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr, 792 temp = readl(addr)); 793 mite_decode(mite_CHSR_strings, temp); 794 addr = mite_io_addr + MITE_FCR(channel); 795 printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr, 796 readl(addr)); 797} 798EXPORT_SYMBOL(mite_dump_regs); 799 800static void mite_decode(char **bit_str, unsigned int bits) 801{ 802 int i; 803 804 for (i = 31; i >= 0; i--) { 805 if (bits & (1 << i)) 806 printk(KERN_DEBUG " %s", bit_str[i]); 807 } 808 printk(KERN_DEBUG "\n"); 809} 810EXPORT_SYMBOL(mite_decode); 811#endif 812 813#ifdef MODULE 814int __init init_module(void) 815{ 816 mite_init(); 817 mite_list_devices(); 818 819 return 0; 820} 821 822void __exit cleanup_module(void) 823{ 824 mite_cleanup(); 825} 826#endif 827 828MODULE_AUTHOR("Comedi http://www.comedi.org"); 829MODULE_DESCRIPTION("Comedi low-level driver"); 830MODULE_LICENSE("GPL"); 831