mite.c revision e473e9120b0a2d7252aca1ed9db5adadee36c0fa
1/* 2 comedi/drivers/mite.c 3 Hardware driver for NI Mite PCI interface chip 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 22*/ 23 24/* 25 The PCI-MIO E series driver was originally written by 26 Tomasz Motylewski <...>, and ported to comedi by ds. 27 28 References for specifications: 29 30 321747b.pdf Register Level Programmer Manual (obsolete) 31 321747c.pdf Register Level Programmer Manual (new) 32 DAQ-STC reference manual 33 34 Other possibly relevant info: 35 36 320517c.pdf User manual (obsolete) 37 320517f.pdf User manual (new) 38 320889a.pdf delete 39 320906c.pdf maximum signal ratings 40 321066a.pdf about 16x 41 321791a.pdf discontinuation of at-mio-16e-10 rev. c 42 321808a.pdf about at-mio-16e-10 rev P 43 321837a.pdf discontinuation of at-mio-16de-10 rev d 44 321838a.pdf about at-mio-16de-10 rev N 45 46 ISSUES: 47 48*/ 49 50/* #define USE_KMALLOC */ 51 52#include "mite.h" 53 54#include "comedi_fc.h" 55#include "comedi_pci.h" 56#include "../comedidev.h" 57 58#include <asm/system.h> 59 60#define PCI_MITE_SIZE 4096 61#define PCI_DAQ_SIZE 4096 62#define PCI_DAQ_SIZE_660X 8192 63 64MODULE_LICENSE("GPL"); 65 66struct mite_struct *mite_devices = NULL; 67 68#define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK))) 69 70void mite_init(void) 71{ 72 struct pci_dev *pcidev; 73 struct mite_struct *mite; 74 75 for (pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL); 76 pcidev != NULL; 77 pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pcidev)) { 78 if (pcidev->vendor == PCI_VENDOR_ID_NATINST) { 79 unsigned i; 80 81 mite = kzalloc(sizeof(*mite), GFP_KERNEL); 82 if (!mite) { 83 printk("mite: allocation failed\n"); 84 pci_dev_put(pcidev); 85 return; 86 } 87 spin_lock_init(&mite->lock); 88 mite->pcidev = pci_dev_get(pcidev); 89 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) { 90 mite->channels[i].mite = mite; 91 mite->channels[i].channel = i; 92 mite->channels[i].done = 1; 93 } 94 mite->next = mite_devices; 95 mite_devices = mite; 96 } 97 } 98} 99 100static void dump_chip_signature(u32 csigr_bits) 101{ 102 printk("mite: version = %i, type = %i, mite mode = %i, interface mode = %i\n", mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits), mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits)); 103 printk("mite: num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n", mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits), mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits)); 104} 105 106unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel) 107{ 108 unsigned fcr_bits = readl(mite->mite_io_addr + 109 MITE_FCR(channel)); 110 unsigned empty_count = (fcr_bits >> 16) & 0xff; 111 unsigned full_count = fcr_bits & 0xff; 112 return empty_count + full_count; 113} 114 115int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1) 116{ 117 unsigned long length; 118 resource_size_t addr; 119 int i; 120 u32 csigr_bits; 121 unsigned unknown_dma_burst_bits; 122 123 if (comedi_pci_enable(mite->pcidev, "mite")) { 124 printk("error enabling mite and requesting io regions\n"); 125 return -EIO; 126 } 127 pci_set_master(mite->pcidev); 128 129 addr = pci_resource_start(mite->pcidev, 0); 130 mite->mite_phys_addr = addr; 131 mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE); 132 if (!mite->mite_io_addr) { 133 printk("failed to remap mite io memory address\n"); 134 return -ENOMEM; 135 } 136 printk("MITE:0x%08llx mapped to %p ", 137 (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr); 138 139 addr = pci_resource_start(mite->pcidev, 1); 140 mite->daq_phys_addr = addr; 141 length = pci_resource_len(mite->pcidev, 1); 142 /* In case of a 660x board, DAQ size is 8k instead of 4k (see as shown by lspci output) */ 143 mite->daq_io_addr = ioremap(mite->daq_phys_addr, length); 144 if (!mite->daq_io_addr) { 145 printk("failed to remap daq io memory address\n"); 146 return -ENOMEM; 147 } 148 printk("DAQ:0x%08llx mapped to %p\n", 149 (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr); 150 151 if (use_iodwbsr_1) { 152 writel(0, mite->mite_io_addr + MITE_IODWBSR); 153 printk("mite: using I/O Window Base Size register 1\n"); 154 writel(mite-> 155 daq_phys_addr | WENAB | 156 MITE_IODWBSR_1_WSIZE_bits(length), 157 mite->mite_io_addr + MITE_IODWBSR_1); 158 writel(0, mite->mite_io_addr + MITE_IODWCR_1); 159 } else { 160 writel(mite->daq_phys_addr | WENAB, 161 mite->mite_io_addr + MITE_IODWBSR); 162 } 163 /* make sure dma bursts work. I got this from running a bus analyzer 164 on a pxi-6281 and a pxi-6713. 6713 powered up with register value 165 of 0x61f and bursts worked. 6281 powered up with register value of 166 0x1f and bursts didn't work. The NI windows driver reads the register, 167 then does a bitwise-or of 0x600 with it and writes it back. 168 */ 169 unknown_dma_burst_bits = 170 readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG); 171 unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS; 172 writel(unknown_dma_burst_bits, 173 mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG); 174 175 csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR); 176 mite->num_channels = mite_csigr_dmac(csigr_bits); 177 if (mite->num_channels > MAX_MITE_DMA_CHANNELS) { 178 printk("mite: bug? chip claims to have %i dma channels. Setting to %i.\n", mite->num_channels, MAX_MITE_DMA_CHANNELS); 179 mite->num_channels = MAX_MITE_DMA_CHANNELS; 180 } 181 dump_chip_signature(csigr_bits); 182 for (i = 0; i < mite->num_channels; i++) { 183 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i)); 184 /* disable interrupts */ 185 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | 186 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | 187 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, 188 mite->mite_io_addr + MITE_CHCR(i)); 189 } 190 mite->fifo_size = mite_fifo_size(mite, 0); 191 printk("mite: fifo size is %i.\n", mite->fifo_size); 192 mite->used = 1; 193 194 return 0; 195} 196 197int mite_setup(struct mite_struct *mite) 198{ 199 return mite_setup2(mite, 0); 200} 201 202void mite_cleanup(void) 203{ 204 struct mite_struct *mite, *next; 205 206 for (mite = mite_devices; mite; mite = next) { 207 pci_dev_put(mite->pcidev); 208 next = mite->next; 209 kfree(mite); 210 } 211} 212 213void mite_unsetup(struct mite_struct *mite) 214{ 215 /* unsigned long offset, start, length; */ 216 217 if (!mite) 218 return; 219 220 if (mite->mite_io_addr) { 221 iounmap(mite->mite_io_addr); 222 mite->mite_io_addr = NULL; 223 } 224 if (mite->daq_io_addr) { 225 iounmap(mite->daq_io_addr); 226 mite->daq_io_addr = NULL; 227 } 228 if (mite->mite_phys_addr) { 229 comedi_pci_disable(mite->pcidev); 230 mite->mite_phys_addr = 0; 231 } 232 233 mite->used = 0; 234} 235 236void mite_list_devices(void) 237{ 238 struct mite_struct *mite, *next; 239 240 printk("Available NI device IDs:"); 241 if (mite_devices) 242 for (mite = mite_devices; mite; mite = next) { 243 next = mite->next; 244 printk(" 0x%04x", mite_device_id(mite)); 245 if (mite->used) 246 printk("(used)"); 247 } 248 printk("\n"); 249 250} 251 252struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite, 253 struct mite_dma_descriptor_ring *ring, unsigned min_channel, 254 unsigned max_channel) 255{ 256 int i; 257 unsigned long flags; 258 struct mite_channel *channel = NULL; 259 260 /* spin lock so mite_release_channel can be called safely from interrupts */ 261 comedi_spin_lock_irqsave(&mite->lock, flags); 262 for (i = min_channel; i <= max_channel; ++i) { 263 if (mite->channel_allocated[i] == 0) { 264 mite->channel_allocated[i] = 1; 265 channel = &mite->channels[i]; 266 channel->ring = ring; 267 break; 268 } 269 } 270 comedi_spin_unlock_irqrestore(&mite->lock, flags); 271 return channel; 272} 273 274void mite_release_channel(struct mite_channel *mite_chan) 275{ 276 struct mite_struct *mite = mite_chan->mite; 277 unsigned long flags; 278 279 /* spin lock to prevent races with mite_request_channel */ 280 comedi_spin_lock_irqsave(&mite->lock, flags); 281 if (mite->channel_allocated[mite_chan->channel]) { 282 mite_dma_disarm(mite_chan); 283 mite_dma_reset(mite_chan); 284/* disable all channel's interrupts (do it after disarm/reset so 285MITE_CHCR reg isn't changed while dma is still active!) */ 286 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | 287 CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE | 288 CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | 289 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, 290 mite->mite_io_addr + MITE_CHCR(mite_chan->channel)); 291 mite->channel_allocated[mite_chan->channel] = 0; 292 mite_chan->ring = NULL; 293 mmiowb(); 294 } 295 comedi_spin_unlock_irqrestore(&mite->lock, flags); 296} 297 298void mite_dma_arm(struct mite_channel *mite_chan) 299{ 300 struct mite_struct *mite = mite_chan->mite; 301 int chor; 302 unsigned long flags; 303 304 MDPRINTK("mite_dma_arm ch%i\n", channel); 305 /* memory barrier is intended to insure any twiddling with the buffer 306 is done before writing to the mite to arm dma transfer */ 307 smp_mb(); 308 /* arm */ 309 chor = CHOR_START; 310 comedi_spin_lock_irqsave(&mite->lock, flags); 311 mite_chan->done = 0; 312 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 313 mmiowb(); 314 comedi_spin_unlock_irqrestore(&mite->lock, flags); 315/* mite_dma_tcr(mite, channel); */ 316} 317 318/**************************************/ 319 320int mite_buf_change(struct mite_dma_descriptor_ring *ring, comedi_async * async) 321{ 322 unsigned int n_links; 323 int i; 324 325 if (ring->descriptors) { 326 dma_free_coherent(ring->hw_dev, 327 ring->n_links * sizeof(struct mite_dma_descriptor), 328 ring->descriptors, ring->descriptors_dma_addr); 329 } 330 ring->descriptors = NULL; 331 ring->descriptors_dma_addr = 0; 332 ring->n_links = 0; 333 334 if (async->prealloc_bufsz == 0) { 335 return 0; 336 } 337 n_links = async->prealloc_bufsz >> PAGE_SHIFT; 338 339 MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links); 340 341 ring->descriptors = 342 dma_alloc_coherent(ring->hw_dev, 343 n_links * sizeof(struct mite_dma_descriptor), 344 &ring->descriptors_dma_addr, GFP_KERNEL); 345 if (!ring->descriptors) { 346 printk("mite: ring buffer allocation failed\n"); 347 return -ENOMEM; 348 } 349 ring->n_links = n_links; 350 351 for (i = 0; i < n_links; i++) { 352 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE); 353 ring->descriptors[i].addr = 354 cpu_to_le32(async->buf_page_list[i].dma_addr); 355 ring->descriptors[i].next = 356 cpu_to_le32(ring->descriptors_dma_addr + (i + 357 1) * sizeof(struct mite_dma_descriptor)); 358 } 359 ring->descriptors[n_links - 1].next = 360 cpu_to_le32(ring->descriptors_dma_addr); 361 /* barrier is meant to insure that all the writes to the dma descriptors 362 have completed before the dma controller is commanded to read them */ 363 smp_wmb(); 364 return 0; 365} 366 367void mite_prep_dma(struct mite_channel *mite_chan, 368 unsigned int num_device_bits, unsigned int num_memory_bits) 369{ 370 unsigned int chor, chcr, mcr, dcr, lkcr; 371 struct mite_struct *mite = mite_chan->mite; 372 373 MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel); 374 375 /* reset DMA and FIFO */ 376 chor = CHOR_DMARESET | CHOR_FRESET; 377 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 378 379 /* short link chaining mode */ 380 chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE | 381 CHCR_BURSTEN; 382 /* 383 * Link Complete Interrupt: interrupt every time a link 384 * in MITE_RING is completed. This can generate a lot of 385 * extra interrupts, but right now we update the values 386 * of buf_int_ptr and buf_int_count at each interrupt. A 387 * better method is to poll the MITE before each user 388 * "read()" to calculate the number of bytes available. 389 */ 390 chcr |= CHCR_SET_LC_IE; 391 if (num_memory_bits == 32 && num_device_bits == 16) { 392 /* Doing a combined 32 and 16 bit byteswap gets the 16 bit samples into the fifo in the right order. 393 Tested doing 32 bit memory to 16 bit device transfers to the analog out of a pxi-6281, 394 which has mite version = 1, type = 4. This also works for dma reads from the counters 395 on e-series boards. */ 396 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY; 397 } 398 if (mite_chan->dir == COMEDI_INPUT) { 399 chcr |= CHCR_DEV_TO_MEM; 400 } 401 writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel)); 402 403 /* to/from memory */ 404 mcr = CR_RL(64) | CR_ASEQUP; 405 switch (num_memory_bits) { 406 case 8: 407 mcr |= CR_PSIZE8; 408 break; 409 case 16: 410 mcr |= CR_PSIZE16; 411 break; 412 case 32: 413 mcr |= CR_PSIZE32; 414 break; 415 default: 416 rt_printk 417 ("mite: bug! invalid mem bit width for dma transfer\n"); 418 break; 419 } 420 writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel)); 421 422 /* from/to device */ 423 dcr = CR_RL(64) | CR_ASEQUP; 424 dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel); 425 switch (num_device_bits) { 426 case 8: 427 dcr |= CR_PSIZE8; 428 break; 429 case 16: 430 dcr |= CR_PSIZE16; 431 break; 432 case 32: 433 dcr |= CR_PSIZE32; 434 break; 435 default: 436 rt_printk 437 ("mite: bug! invalid dev bit width for dma transfer\n"); 438 break; 439 } 440 writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel)); 441 442 /* reset the DAR */ 443 writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel)); 444 445 /* the link is 32bits */ 446 lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32; 447 writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel)); 448 449 /* starting address for link chaining */ 450 writel(mite_chan->ring->descriptors_dma_addr, 451 mite->mite_io_addr + MITE_LKAR(mite_chan->channel)); 452 453 MDPRINTK("exit mite_prep_dma\n"); 454} 455 456u32 mite_device_bytes_transferred(struct mite_channel *mite_chan) 457{ 458 struct mite_struct *mite = mite_chan->mite; 459 return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel)); 460} 461 462u32 mite_bytes_in_transit(struct mite_channel *mite_chan) 463{ 464 struct mite_struct *mite = mite_chan->mite; 465 return readl(mite->mite_io_addr + 466 MITE_FCR(mite_chan->channel)) & 0x000000FF; 467} 468 469/* returns lower bound for number of bytes transferred from device to memory */ 470u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan) 471{ 472 u32 device_byte_count; 473 474 device_byte_count = mite_device_bytes_transferred(mite_chan); 475 return device_byte_count - mite_bytes_in_transit(mite_chan); 476} 477 478/* returns upper bound for number of bytes transferred from device to memory */ 479u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan) 480{ 481 u32 in_transit_count; 482 483 in_transit_count = mite_bytes_in_transit(mite_chan); 484 return mite_device_bytes_transferred(mite_chan) - in_transit_count; 485} 486 487/* returns lower bound for number of bytes read from memory for transfer to device */ 488u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan) 489{ 490 u32 device_byte_count; 491 492 device_byte_count = mite_device_bytes_transferred(mite_chan); 493 return device_byte_count + mite_bytes_in_transit(mite_chan); 494} 495 496/* returns upper bound for number of bytes read from memory for transfer to device */ 497u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan) 498{ 499 u32 in_transit_count; 500 501 in_transit_count = mite_bytes_in_transit(mite_chan); 502 return mite_device_bytes_transferred(mite_chan) + in_transit_count; 503} 504 505unsigned mite_dma_tcr(struct mite_channel *mite_chan) 506{ 507 struct mite_struct *mite = mite_chan->mite; 508 int tcr; 509 int lkar; 510 511 lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel)); 512 tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel)); 513 MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel, 514 lkar, tcr); 515 516 return tcr; 517} 518 519void mite_dma_disarm(struct mite_channel *mite_chan) 520{ 521 struct mite_struct *mite = mite_chan->mite; 522 unsigned chor; 523 524 /* disarm */ 525 chor = CHOR_ABORT; 526 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 527} 528 529int mite_sync_input_dma(struct mite_channel *mite_chan, comedi_async * async) 530{ 531 int count; 532 unsigned int nbytes, old_alloc_count; 533 const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice); 534 535 old_alloc_count = async->buf_write_alloc_count; 536 /* write alloc as much as we can */ 537 comedi_buf_write_alloc(async, async->prealloc_bufsz); 538 539 nbytes = mite_bytes_written_to_memory_lb(mite_chan); 540 if ((int)(mite_bytes_written_to_memory_ub(mite_chan) - 541 old_alloc_count) > 0) { 542 rt_printk("mite: DMA overwrite of free area\n"); 543 async->events |= COMEDI_CB_OVERFLOW; 544 return -1; 545 } 546 547 count = nbytes - async->buf_write_count; 548 /* it's possible count will be negative due to 549 * conservative value returned by mite_bytes_written_to_memory_lb */ 550 if (count <= 0) { 551 return 0; 552 } 553 comedi_buf_write_free(async, count); 554 555 async->scan_progress += count; 556 if (async->scan_progress >= bytes_per_scan) { 557 async->scan_progress %= bytes_per_scan; 558 async->events |= COMEDI_CB_EOS; 559 } 560 async->events |= COMEDI_CB_BLOCK; 561 return 0; 562} 563 564int mite_sync_output_dma(struct mite_channel *mite_chan, comedi_async * async) 565{ 566 int count; 567 u32 nbytes_ub, nbytes_lb; 568 unsigned int old_alloc_count; 569 u32 stop_count = 570 async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice); 571 572 old_alloc_count = async->buf_read_alloc_count; 573 /* read alloc as much as we can */ 574 comedi_buf_read_alloc(async, async->prealloc_bufsz); 575 nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan); 576 if (async->cmd.stop_src == TRIG_COUNT && 577 (int)(nbytes_lb - stop_count) > 0) 578 nbytes_lb = stop_count; 579 nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan); 580 if (async->cmd.stop_src == TRIG_COUNT && 581 (int)(nbytes_ub - stop_count) > 0) 582 nbytes_ub = stop_count; 583 if ((int)(nbytes_ub - old_alloc_count) > 0) { 584 rt_printk("mite: DMA underrun\n"); 585 async->events |= COMEDI_CB_OVERFLOW; 586 return -1; 587 } 588 count = nbytes_lb - async->buf_read_count; 589 if (count <= 0) { 590 return 0; 591 } 592 if (count) { 593 comedi_buf_read_free(async, count); 594 async->events |= COMEDI_CB_BLOCK; 595 } 596 return 0; 597} 598 599unsigned mite_get_status(struct mite_channel *mite_chan) 600{ 601 struct mite_struct *mite = mite_chan->mite; 602 unsigned status; 603 unsigned long flags; 604 605 comedi_spin_lock_irqsave(&mite->lock, flags); 606 status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel)); 607 if (status & CHSR_DONE) { 608 mite_chan->done = 1; 609 writel(CHOR_CLRDONE, 610 mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); 611 } 612 mmiowb(); 613 comedi_spin_unlock_irqrestore(&mite->lock, flags); 614 return status; 615} 616 617int mite_done(struct mite_channel *mite_chan) 618{ 619 struct mite_struct *mite = mite_chan->mite; 620 unsigned long flags; 621 int done; 622 623 mite_get_status(mite_chan); 624 comedi_spin_lock_irqsave(&mite->lock, flags); 625 done = mite_chan->done; 626 comedi_spin_unlock_irqrestore(&mite->lock, flags); 627 return done; 628} 629 630#ifdef DEBUG_MITE 631 632static void mite_decode(char **bit_str, unsigned int bits); 633 634/* names of bits in mite registers */ 635 636static const char *const mite_CHOR_strings[] = { 637 "start", "cont", "stop", "abort", 638 "freset", "clrlc", "clrrb", "clrdone", 639 "clr_lpause", "set_lpause", "clr_send_tc", 640 "set_send_tc", "12", "13", "14", 641 "15", "16", "17", "18", 642 "19", "20", "21", "22", 643 "23", "24", "25", "26", 644 "27", "28", "29", "30", 645 "dmareset", 646}; 647 648static const char *const mite_CHCR_strings[] = { 649 "continue", "ringbuff", "2", "3", 650 "4", "5", "6", "7", 651 "8", "9", "10", "11", 652 "12", "13", "bursten", "fifodis", 653 "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie", 654 "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie", 655 "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie", 656 "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie", 657}; 658 659static const char *const mite_MCR_strings[] = { 660 "amdevice", "1", "2", "3", 661 "4", "5", "portio", "portvxi", 662 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11", 663 "12", "13", "blocken", "berhand", 664 "reqsintlim/reqs0", "reqs1", "reqs2", "rd32", 665 "rd512", "rl1", "rl2", "rl8", 666 "24", "25", "26", "27", 667 "28", "29", "30", "stopen", 668}; 669 670static const char *const mite_DCR_strings[] = { 671 "amdevice", "1", "2", "3", 672 "4", "5", "portio", "portvxi", 673 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2", 674 "aseqxp8", "13", "blocken", "berhand", 675 "reqsintlim", "reqs1", "reqs2", "rd32", 676 "rd512", "rl1", "rl2", "rl8", 677 "23", "24", "25", "27", 678 "28", "wsdevc", "wsdevs", "rwdevpack", 679}; 680 681static const char *const mite_LKCR_strings[] = { 682 "amdevice", "1", "2", "3", 683 "4", "5", "portio", "portvxi", 684 "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown", 685 "12", "13", "14", "berhand", 686 "16", "17", "18", "rd32", 687 "rd512", "rl1", "rl2", "rl8", 688 "24", "25", "26", "27", 689 "28", "29", "30", "chngend", 690}; 691 692static const char *const mite_CHSR_strings[] = { 693 "d.err0", "d.err1", "m.err0", "m.err1", 694 "l.err0", "l.err1", "drq0", "drq1", 695 "end", "xferr", "operr0", "operr1", 696 "stops", "habort", "sabort", "error", 697 "16", "conts_rb", "18", "linkc", 698 "20", "drdy", "22", "mrdy", 699 "24", "done", "26", "sars", 700 "28", "lpauses", "30", "int", 701}; 702 703void mite_dump_regs(struct mite_channel *mite_chan) 704{ 705 unsigned long mite_io_addr = 706 (unsigned long)mite_chan->mite->mite_io_addr; 707 unsigned long addr = 0; 708 unsigned long temp = 0; 709 710 printk("mite_dump_regs ch%i\n", mite_chan->channel); 711 printk("mite address is =0x%08lx\n", mite_io_addr); 712 713 addr = mite_io_addr + MITE_CHOR(channel); 714 printk("mite status[CHOR]at 0x%08lx =0x%08lx\n", addr, temp = 715 readl(addr)); 716 mite_decode(mite_CHOR_strings, temp); 717 addr = mite_io_addr + MITE_CHCR(channel); 718 printk("mite status[CHCR]at 0x%08lx =0x%08lx\n", addr, temp = 719 readl(addr)); 720 mite_decode(mite_CHCR_strings, temp); 721 addr = mite_io_addr + MITE_TCR(channel); 722 printk("mite status[TCR] at 0x%08lx =0x%08x\n", addr, readl(addr)); 723 addr = mite_io_addr + MITE_MCR(channel); 724 printk("mite status[MCR] at 0x%08lx =0x%08lx\n", addr, temp = 725 readl(addr)); 726 mite_decode(mite_MCR_strings, temp); 727 728 addr = mite_io_addr + MITE_MAR(channel); 729 printk("mite status[MAR] at 0x%08lx =0x%08x\n", addr, readl(addr)); 730 addr = mite_io_addr + MITE_DCR(channel); 731 printk("mite status[DCR] at 0x%08lx =0x%08lx\n", addr, temp = 732 readl(addr)); 733 mite_decode(mite_DCR_strings, temp); 734 addr = mite_io_addr + MITE_DAR(channel); 735 printk("mite status[DAR] at 0x%08lx =0x%08x\n", addr, readl(addr)); 736 addr = mite_io_addr + MITE_LKCR(channel); 737 printk("mite status[LKCR]at 0x%08lx =0x%08lx\n", addr, temp = 738 readl(addr)); 739 mite_decode(mite_LKCR_strings, temp); 740 addr = mite_io_addr + MITE_LKAR(channel); 741 printk("mite status[LKAR]at 0x%08lx =0x%08x\n", addr, readl(addr)); 742 743 addr = mite_io_addr + MITE_CHSR(channel); 744 printk("mite status[CHSR]at 0x%08lx =0x%08lx\n", addr, temp = 745 readl(addr)); 746 mite_decode(mite_CHSR_strings, temp); 747 addr = mite_io_addr + MITE_FCR(channel); 748 printk("mite status[FCR] at 0x%08lx =0x%08x\n\n", addr, readl(addr)); 749} 750 751static void mite_decode(char **bit_str, unsigned int bits) 752{ 753 int i; 754 755 for (i = 31; i >= 0; i--) { 756 if (bits & (1 << i)) { 757 printk(" %s", bit_str[i]); 758 } 759 } 760 printk("\n"); 761} 762#endif 763 764#ifdef MODULE 765int __init init_module(void) 766{ 767 mite_init(); 768 mite_list_devices(); 769 770 return 0; 771} 772 773void __exit cleanup_module(void) 774{ 775 mite_cleanup(); 776} 777 778EXPORT_SYMBOL(mite_dma_tcr); 779EXPORT_SYMBOL(mite_dma_arm); 780EXPORT_SYMBOL(mite_dma_disarm); 781EXPORT_SYMBOL(mite_sync_input_dma); 782EXPORT_SYMBOL(mite_sync_output_dma); 783EXPORT_SYMBOL(mite_setup); 784EXPORT_SYMBOL(mite_setup2); 785EXPORT_SYMBOL(mite_unsetup); 786#if 0 787EXPORT_SYMBOL(mite_kvmem_segment_load); 788EXPORT_SYMBOL(mite_ll_from_kvmem); 789EXPORT_SYMBOL(mite_setregs); 790#endif 791EXPORT_SYMBOL(mite_devices); 792EXPORT_SYMBOL(mite_list_devices); 793EXPORT_SYMBOL(mite_request_channel_in_range); 794EXPORT_SYMBOL(mite_release_channel); 795EXPORT_SYMBOL(mite_prep_dma); 796EXPORT_SYMBOL(mite_buf_change); 797EXPORT_SYMBOL(mite_bytes_written_to_memory_lb); 798EXPORT_SYMBOL(mite_bytes_written_to_memory_ub); 799EXPORT_SYMBOL(mite_bytes_read_from_memory_lb); 800EXPORT_SYMBOL(mite_bytes_read_from_memory_ub); 801EXPORT_SYMBOL(mite_bytes_in_transit); 802EXPORT_SYMBOL(mite_get_status); 803EXPORT_SYMBOL(mite_done); 804#ifdef DEBUG_MITE 805EXPORT_SYMBOL(mite_decode); 806EXPORT_SYMBOL(mite_dump_regs); 807#endif 808 809#endif 810