mite.h revision 4e40cee9c8a46d4231d28ae7ae6d9938cf0526d5 
1/*
2    module/mite.h
3    Hardware driver for NI Mite PCI interface chip
4
5    COMEDI - Linux Control and Measurement Device Interface
6    Copyright (C) 1999 David A. Schleef <ds@schleef.org>
7
8    This program is free software; you can redistribute it and/or modify
9    it under the terms of the GNU General Public License as published by
10    the Free Software Foundation; either version 2 of the License, or
11    (at your option) any later version.
12
13    This program is distributed in the hope that it will be useful,
14    but WITHOUT ANY WARRANTY; without even the implied warranty of
15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16    GNU General Public License for more details.
17
18    You should have received a copy of the GNU General Public License
19    along with this program; if not, write to the Free Software
20    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21
22*/
23
24#ifndef _MITE_H_
25#define _MITE_H_
26
27#include <linux/pci.h>
28#include "../comedidev.h"
29
30/*  #define DEBUG_MITE */
31#define PCIMIO_COMPAT
32
33#ifdef DEBUG_MITE
34#define MDPRINTK(format, args...)	printk(format , ## args)
35#else
36#define MDPRINTK(format, args...)
37#endif
38
39#define MAX_MITE_DMA_CHANNELS 8
40
41struct mite_dma_descriptor {
42	u32 count;
43	u32 addr;
44	u32 next;
45	u32 dar;
46};
47
48struct mite_dma_descriptor_ring {
49	struct device *hw_dev;
50	unsigned int n_links;
51	struct mite_dma_descriptor *descriptors;
52	dma_addr_t descriptors_dma_addr;
53};
54
55struct mite_channel {
56	struct mite_struct *mite;
57	unsigned channel;
58	int dir;
59	int done;
60	struct mite_dma_descriptor_ring *ring;
61};
62
63struct mite_struct {
64	struct mite_struct *next;
65	int used;
66
67	struct pci_dev *pcidev;
68	resource_size_t mite_phys_addr;
69	void *mite_io_addr;
70	resource_size_t daq_phys_addr;
71	void *daq_io_addr;
72
73	struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
74	short channel_allocated[MAX_MITE_DMA_CHANNELS];
75	int num_channels;
76	unsigned fifo_size;
77	spinlock_t lock;
78};
79
80static inline struct mite_dma_descriptor_ring *mite_alloc_ring(struct
81							       mite_struct
82							       *mite)
83{
84	struct mite_dma_descriptor_ring *ring =
85	    kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
86	if (ring == NULL)
87		return ring;
88	ring->hw_dev = get_device(&mite->pcidev->dev);
89	if (ring->hw_dev == NULL) {
90		kfree(ring);
91		return NULL;
92	}
93	ring->n_links = 0;
94	ring->descriptors = NULL;
95	ring->descriptors_dma_addr = 0;
96	return ring;
97};
98
99static inline void mite_free_ring(struct mite_dma_descriptor_ring *ring)
100{
101	if (ring) {
102		if (ring->descriptors) {
103			dma_free_coherent(ring->hw_dev,
104					  ring->n_links *
105					  sizeof(struct mite_dma_descriptor),
106					  ring->descriptors,
107					  ring->descriptors_dma_addr);
108		}
109		put_device(ring->hw_dev);
110		kfree(ring);
111	}
112};
113
114extern struct mite_struct *mite_devices;
115
116static inline unsigned int mite_irq(struct mite_struct *mite)
117{
118	return mite->pcidev->irq;
119};
120
121static inline unsigned int mite_device_id(struct mite_struct *mite)
122{
123	return mite->pcidev->device;
124};
125
126void mite_init(void);
127void mite_cleanup(void);
128int mite_setup(struct mite_struct *mite);
129int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1);
130void mite_unsetup(struct mite_struct *mite);
131void mite_list_devices(void);
132struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
133						   struct
134						   mite_dma_descriptor_ring
135						   *ring, unsigned min_channel,
136						   unsigned max_channel);
137static inline struct mite_channel *mite_request_channel(struct mite_struct
138							*mite,
139							struct
140							mite_dma_descriptor_ring
141							*ring)
142{
143	return mite_request_channel_in_range(mite, ring, 0,
144					     mite->num_channels - 1);
145}
146
147void mite_release_channel(struct mite_channel *mite_chan);
148
149unsigned mite_dma_tcr(struct mite_channel *mite_chan);
150void mite_dma_arm(struct mite_channel *mite_chan);
151void mite_dma_disarm(struct mite_channel *mite_chan);
152int mite_sync_input_dma(struct mite_channel *mite_chan,
153			struct comedi_async *async);
154int mite_sync_output_dma(struct mite_channel *mite_chan,
155			 struct comedi_async *async);
156u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
157u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
158u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
159u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
160u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
161unsigned mite_get_status(struct mite_channel *mite_chan);
162int mite_done(struct mite_channel *mite_chan);
163
164void mite_prep_dma(struct mite_channel *mite_chan,
165		   unsigned int num_device_bits, unsigned int num_memory_bits);
166int mite_buf_change(struct mite_dma_descriptor_ring *ring,
167		    struct comedi_async *async);
168
169#ifdef DEBUG_MITE
170void mite_print_chsr(unsigned int chsr);
171void mite_dump_regs(struct mite_channel *mite_chan);
172#endif
173
174static inline int CHAN_OFFSET(int channel)
175{
176	return 0x500 + 0x100 * channel;
177};
178
179enum mite_registers {
180	/* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
181	   written and read back.  The bits 0x1f always read as 1.
182	   The rest always read as zero. */
183	MITE_UNKNOWN_DMA_BURST_REG = 0x28,
184	MITE_IODWBSR = 0xc0,	/* IO Device Window Base Size Register */
185	MITE_IODWBSR_1 = 0xc4,	/*  IO Device Window Base Size Register 1 */
186	MITE_IODWCR_1 = 0xf4,
187	MITE_PCI_CONFIG_OFFSET = 0x300,
188	MITE_CSIGR = 0x460	/* chip signature */
189};
190static inline int MITE_CHOR(int channel)
191{				/*  channel operation */
192	return CHAN_OFFSET(channel) + 0x0;
193};
194
195static inline int MITE_CHCR(int channel)
196{				/*  channel control */
197	return CHAN_OFFSET(channel) + 0x4;
198};
199
200static inline int MITE_TCR(int channel)
201{				/*  transfer count */
202	return CHAN_OFFSET(channel) + 0x8;
203};
204
205static inline int MITE_MCR(int channel)
206{				/*  memory configuration */
207	return CHAN_OFFSET(channel) + 0xc;
208};
209
210static inline int MITE_MAR(int channel)
211{				/*  memory address */
212	return CHAN_OFFSET(channel) + 0x10;
213};
214
215static inline int MITE_DCR(int channel)
216{				/*  device configuration */
217	return CHAN_OFFSET(channel) + 0x14;
218};
219
220static inline int MITE_DAR(int channel)
221{				/*  device address */
222	return CHAN_OFFSET(channel) + 0x18;
223};
224
225static inline int MITE_LKCR(int channel)
226{				/*  link configuration */
227	return CHAN_OFFSET(channel) + 0x1c;
228};
229
230static inline int MITE_LKAR(int channel)
231{				/*  link address */
232	return CHAN_OFFSET(channel) + 0x20;
233};
234
235static inline int MITE_LLKAR(int channel)
236{				/*  see mite section of tnt5002 manual */
237	return CHAN_OFFSET(channel) + 0x24;
238};
239
240static inline int MITE_BAR(int channel)
241{				/*  base address */
242	return CHAN_OFFSET(channel) + 0x28;
243};
244
245static inline int MITE_BCR(int channel)
246{				/*  base count */
247	return CHAN_OFFSET(channel) + 0x2c;
248};
249
250static inline int MITE_SAR(int channel)
251{				/*  ? address */
252	return CHAN_OFFSET(channel) + 0x30;
253};
254
255static inline int MITE_WSCR(int channel)
256{				/*  ? */
257	return CHAN_OFFSET(channel) + 0x34;
258};
259
260static inline int MITE_WSER(int channel)
261{				/*  ? */
262	return CHAN_OFFSET(channel) + 0x38;
263};
264
265static inline int MITE_CHSR(int channel)
266{				/*  channel status */
267	return CHAN_OFFSET(channel) + 0x3c;
268};
269
270static inline int MITE_FCR(int channel)
271{				/*  fifo count */
272	return CHAN_OFFSET(channel) + 0x40;
273};
274
275enum MITE_IODWBSR_bits {
276	WENAB = 0x80,		/*  window enable */
277};
278
279static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
280{
281	unsigned order = 0;
282	while (size >>= 1)
283		++order;
284	BUG_ON(order < 1);
285	return (order - 1) & 0x1f;
286}
287
288enum MITE_UNKNOWN_DMA_BURST_bits {
289	UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
290};
291
292static inline int mite_csigr_version(u32 csigr_bits)
293{
294	return csigr_bits & 0xf;
295};
296
297static inline int mite_csigr_type(u32 csigr_bits)
298{				/*  original mite = 0, minimite = 1 */
299	return (csigr_bits >> 4) & 0xf;
300};
301
302static inline int mite_csigr_mmode(u32 csigr_bits)
303{				/*  mite mode, minimite = 1 */
304	return (csigr_bits >> 8) & 0x3;
305};
306
307static inline int mite_csigr_imode(u32 csigr_bits)
308{				/*  cpu port interface mode, pci = 0x3 */
309	return (csigr_bits >> 12) & 0x3;
310};
311
312static inline int mite_csigr_dmac(u32 csigr_bits)
313{				/*  number of dma channels */
314	return (csigr_bits >> 16) & 0xf;
315};
316
317static inline int mite_csigr_wpdep(u32 csigr_bits)
318{				/*  write post fifo depth */
319	unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
320	if (wpdep_bits == 0)
321		return 0;
322	else
323		return 1 << (wpdep_bits - 1);
324};
325
326static inline int mite_csigr_wins(u32 csigr_bits)
327{
328	return (csigr_bits >> 24) & 0x1f;
329};
330
331static inline int mite_csigr_iowins(u32 csigr_bits)
332{				/*  number of io windows */
333	return (csigr_bits >> 29) & 0x7;
334};
335
336enum MITE_MCR_bits {
337	MCRPON = 0,
338};
339
340enum MITE_DCR_bits {
341	DCR_NORMAL = (1 << 29),
342	DCRPON = 0,
343};
344
345enum MITE_CHOR_bits {
346	CHOR_DMARESET = (1 << 31),
347	CHOR_SET_SEND_TC = (1 << 11),
348	CHOR_CLR_SEND_TC = (1 << 10),
349	CHOR_SET_LPAUSE = (1 << 9),
350	CHOR_CLR_LPAUSE = (1 << 8),
351	CHOR_CLRDONE = (1 << 7),
352	CHOR_CLRRB = (1 << 6),
353	CHOR_CLRLC = (1 << 5),
354	CHOR_FRESET = (1 << 4),
355	CHOR_ABORT = (1 << 3),	/* stop without emptying fifo */
356	CHOR_STOP = (1 << 2),	/* stop after emptying fifo */
357	CHOR_CONT = (1 << 1),
358	CHOR_START = (1 << 0),
359	CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
360};
361
362enum MITE_CHCR_bits {
363	CHCR_SET_DMA_IE = (1 << 31),
364	CHCR_CLR_DMA_IE = (1 << 30),
365	CHCR_SET_LINKP_IE = (1 << 29),
366	CHCR_CLR_LINKP_IE = (1 << 28),
367	CHCR_SET_SAR_IE = (1 << 27),
368	CHCR_CLR_SAR_IE = (1 << 26),
369	CHCR_SET_DONE_IE = (1 << 25),
370	CHCR_CLR_DONE_IE = (1 << 24),
371	CHCR_SET_MRDY_IE = (1 << 23),
372	CHCR_CLR_MRDY_IE = (1 << 22),
373	CHCR_SET_DRDY_IE = (1 << 21),
374	CHCR_CLR_DRDY_IE = (1 << 20),
375	CHCR_SET_LC_IE = (1 << 19),
376	CHCR_CLR_LC_IE = (1 << 18),
377	CHCR_SET_CONT_RB_IE = (1 << 17),
378	CHCR_CLR_CONT_RB_IE = (1 << 16),
379	CHCR_FIFODIS = (1 << 15),
380	CHCR_FIFO_ON = 0,
381	CHCR_BURSTEN = (1 << 14),
382	CHCR_NO_BURSTEN = 0,
383	CHCR_BYTE_SWAP_DEVICE = (1 << 6),
384	CHCR_BYTE_SWAP_MEMORY = (1 << 4),
385	CHCR_DIR = (1 << 3),
386	CHCR_DEV_TO_MEM = CHCR_DIR,
387	CHCR_MEM_TO_DEV = 0,
388	CHCR_NORMAL = (0 << 0),
389	CHCR_CONTINUE = (1 << 0),
390	CHCR_RINGBUFF = (2 << 0),
391	CHCR_LINKSHORT = (4 << 0),
392	CHCR_LINKLONG = (5 << 0),
393	CHCRPON =
394	    (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
395	     CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
396	     CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
397};
398
399enum ConfigRegister_bits {
400	CR_REQS_MASK = 0x7 << 16,
401	CR_ASEQDONT = 0x0 << 10,
402	CR_ASEQUP = 0x1 << 10,
403	CR_ASEQDOWN = 0x2 << 10,
404	CR_ASEQ_MASK = 0x3 << 10,
405	CR_PSIZE8 = (1 << 8),
406	CR_PSIZE16 = (2 << 8),
407	CR_PSIZE32 = (3 << 8),
408	CR_PORTCPU = (0 << 6),
409	CR_PORTIO = (1 << 6),
410	CR_PORTVXI = (2 << 6),
411	CR_PORTMXI = (3 << 6),
412	CR_AMDEVICE = (1 << 0),
413};
414static inline int CR_REQS(int source)
415{
416	return (source & 0x7) << 16;
417};
418
419static inline int CR_REQSDRQ(unsigned drq_line)
420{
421	/* This also works on m-series when
422	   using channels (drq_line) 4 or 5. */
423	return CR_REQS((drq_line & 0x3) | 0x4);
424}
425
426static inline int CR_RL(unsigned int retry_limit)
427{
428	int value = 0;
429
430	while (retry_limit) {
431		retry_limit >>= 1;
432		value++;
433	}
434	if (value > 0x7)
435		printk("comedi: bug! retry_limit too large\n");
436	return (value & 0x7) << 21;
437}
438
439enum CHSR_bits {
440	CHSR_INT = (1 << 31),
441	CHSR_LPAUSES = (1 << 29),
442	CHSR_SARS = (1 << 27),
443	CHSR_DONE = (1 << 25),
444	CHSR_MRDY = (1 << 23),
445	CHSR_DRDY = (1 << 21),
446	CHSR_LINKC = (1 << 19),
447	CHSR_CONTS_RB = (1 << 17),
448	CHSR_ERROR = (1 << 15),
449	CHSR_SABORT = (1 << 14),
450	CHSR_HABORT = (1 << 13),
451	CHSR_STOPS = (1 << 12),
452	CHSR_OPERR_mask = (3 << 10),
453	CHSR_OPERR_NOERROR = (0 << 10),
454	CHSR_OPERR_FIFOERROR = (1 << 10),
455	CHSR_OPERR_LINKERROR = (1 << 10),	/* ??? */
456	CHSR_XFERR = (1 << 9),
457	CHSR_END = (1 << 8),
458	CHSR_DRQ1 = (1 << 7),
459	CHSR_DRQ0 = (1 << 6),
460	CHSR_LxERR_mask = (3 << 4),
461	CHSR_LBERR = (1 << 4),
462	CHSR_LRERR = (2 << 4),
463	CHSR_LOERR = (3 << 4),
464	CHSR_MxERR_mask = (3 << 2),
465	CHSR_MBERR = (1 << 2),
466	CHSR_MRERR = (2 << 2),
467	CHSR_MOERR = (3 << 2),
468	CHSR_DxERR_mask = (3 << 0),
469	CHSR_DBERR = (1 << 0),
470	CHSR_DRERR = (2 << 0),
471	CHSR_DOERR = (3 << 0),
472};
473
474static inline void mite_dma_reset(struct mite_channel *mite_chan)
475{
476	writel(CHOR_DMARESET | CHOR_FRESET,
477	       mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
478};
479
480#endif
481