ni_660x.c revision 0a85b6f0ab0d2edb0d41b32697111ce0e4f43496
1/* 2 comedi/drivers/ni_660x.c 3 Hardware driver for NI 660x devices 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18*/ 19 20/* 21Driver: ni_660x 22Description: National Instruments 660x counter/timer boards 23Devices: 24[National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602, 25 PXI-6608 26Author: J.P. Mellor <jpmellor@rose-hulman.edu>, 27 Herman.Bruyninckx@mech.kuleuven.ac.be, 28 Wim.Meeussen@mech.kuleuven.ac.be, 29 Klaas.Gadeyne@mech.kuleuven.ac.be, 30 Frank Mori Hess <fmhess@users.sourceforge.net> 31Updated: Thu Oct 18 12:56:06 EDT 2007 32Status: experimental 33 34Encoders work. PulseGeneration (both single pulse and pulse train) 35works. Buffered commands work for input but not output. 36 37References: 38DAQ 660x Register-Level Programmer Manual (NI 370505A-01) 39DAQ 6601/6602 User Manual (NI 322137B-01) 40 41*/ 42 43#include <linux/interrupt.h> 44#include "../comedidev.h" 45#include "mite.h" 46#include "ni_tio.h" 47 48enum ni_660x_constants { 49 min_counter_pfi_chan = 8, 50 max_dio_pfi_chan = 31, 51 counters_per_chip = 4 52}; 53 54#define NUM_PFI_CHANNELS 40 55/* really there are only up to 3 dma channels, but the register layout allows for 4 */ 56#define MAX_DMA_CHANNEL 4 57 58/* See Register-Level Programmer Manual page 3.1 */ 59enum NI_660x_Register { 60 G0InterruptAcknowledge, 61 G0StatusRegister, 62 G1InterruptAcknowledge, 63 G1StatusRegister, 64 G01StatusRegister, 65 G0CommandRegister, 66 STCDIOParallelInput, 67 G1CommandRegister, 68 G0HWSaveRegister, 69 G1HWSaveRegister, 70 STCDIOOutput, 71 STCDIOControl, 72 G0SWSaveRegister, 73 G1SWSaveRegister, 74 G0ModeRegister, 75 G01JointStatus1Register, 76 G1ModeRegister, 77 STCDIOSerialInput, 78 G0LoadARegister, 79 G01JointStatus2Register, 80 G0LoadBRegister, 81 G1LoadARegister, 82 G1LoadBRegister, 83 G0InputSelectRegister, 84 G1InputSelectRegister, 85 G0AutoincrementRegister, 86 G1AutoincrementRegister, 87 G01JointResetRegister, 88 G0InterruptEnable, 89 G1InterruptEnable, 90 G0CountingModeRegister, 91 G1CountingModeRegister, 92 G0SecondGateRegister, 93 G1SecondGateRegister, 94 G0DMAConfigRegister, 95 G0DMAStatusRegister, 96 G1DMAConfigRegister, 97 G1DMAStatusRegister, 98 G2InterruptAcknowledge, 99 G2StatusRegister, 100 G3InterruptAcknowledge, 101 G3StatusRegister, 102 G23StatusRegister, 103 G2CommandRegister, 104 G3CommandRegister, 105 G2HWSaveRegister, 106 G3HWSaveRegister, 107 G2SWSaveRegister, 108 G3SWSaveRegister, 109 G2ModeRegister, 110 G23JointStatus1Register, 111 G3ModeRegister, 112 G2LoadARegister, 113 G23JointStatus2Register, 114 G2LoadBRegister, 115 G3LoadARegister, 116 G3LoadBRegister, 117 G2InputSelectRegister, 118 G3InputSelectRegister, 119 G2AutoincrementRegister, 120 G3AutoincrementRegister, 121 G23JointResetRegister, 122 G2InterruptEnable, 123 G3InterruptEnable, 124 G2CountingModeRegister, 125 G3CountingModeRegister, 126 G3SecondGateRegister, 127 G2SecondGateRegister, 128 G2DMAConfigRegister, 129 G2DMAStatusRegister, 130 G3DMAConfigRegister, 131 G3DMAStatusRegister, 132 DIO32Input, 133 DIO32Output, 134 ClockConfigRegister, 135 GlobalInterruptStatusRegister, 136 DMAConfigRegister, 137 GlobalInterruptConfigRegister, 138 IOConfigReg0_1, 139 IOConfigReg2_3, 140 IOConfigReg4_5, 141 IOConfigReg6_7, 142 IOConfigReg8_9, 143 IOConfigReg10_11, 144 IOConfigReg12_13, 145 IOConfigReg14_15, 146 IOConfigReg16_17, 147 IOConfigReg18_19, 148 IOConfigReg20_21, 149 IOConfigReg22_23, 150 IOConfigReg24_25, 151 IOConfigReg26_27, 152 IOConfigReg28_29, 153 IOConfigReg30_31, 154 IOConfigReg32_33, 155 IOConfigReg34_35, 156 IOConfigReg36_37, 157 IOConfigReg38_39, 158 NumRegisters, 159}; 160 161static inline unsigned IOConfigReg(unsigned pfi_channel) 162{ 163 unsigned reg = IOConfigReg0_1 + pfi_channel / 2; 164 BUG_ON(reg > IOConfigReg38_39); 165 return reg; 166} 167 168enum ni_660x_register_width { 169 DATA_1B, 170 DATA_2B, 171 DATA_4B 172}; 173 174enum ni_660x_register_direction { 175 NI_660x_READ, 176 NI_660x_WRITE, 177 NI_660x_READ_WRITE 178}; 179 180enum ni_660x_pfi_output_select { 181 pfi_output_select_high_Z = 0, 182 pfi_output_select_counter = 1, 183 pfi_output_select_do = 2, 184 num_pfi_output_selects 185}; 186 187enum ni_660x_subdevices { 188 NI_660X_DIO_SUBDEV = 1, 189 NI_660X_GPCT_SUBDEV_0 = 2 190}; 191static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index) 192{ 193 return NI_660X_GPCT_SUBDEV_0 + index; 194} 195 196struct NI_660xRegisterData { 197 198 const char *name; /* Register Name */ 199 int offset; /* Offset from base address from GPCT chip */ 200 enum ni_660x_register_direction direction; 201 enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */ 202}; 203 204static const struct NI_660xRegisterData registerData[NumRegisters] = { 205 {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B}, 206 {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B}, 207 {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B}, 208 {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B}, 209 {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B}, 210 {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B}, 211 {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B}, 212 {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B}, 213 {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B}, 214 {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B}, 215 {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B}, 216 {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B}, 217 {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B}, 218 {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B}, 219 {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B}, 220 {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B}, 221 {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B}, 222 {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B}, 223 {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B}, 224 {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B}, 225 {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B}, 226 {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B}, 227 {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B}, 228 {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B}, 229 {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B}, 230 {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B}, 231 {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B}, 232 {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B}, 233 {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B}, 234 {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B}, 235 {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B}, 236 {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B}, 237 {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B}, 238 {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B}, 239 {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B}, 240 {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B}, 241 {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B}, 242 {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B}, 243 {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B}, 244 {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B}, 245 {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B}, 246 {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B}, 247 {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B}, 248 {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B}, 249 {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B}, 250 {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B}, 251 {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B}, 252 {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B}, 253 {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B}, 254 {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B}, 255 {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B}, 256 {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B}, 257 {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B}, 258 {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B}, 259 {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B}, 260 {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B}, 261 {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B}, 262 {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B}, 263 {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B}, 264 {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B}, 265 {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B}, 266 {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B}, 267 {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B}, 268 {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B}, 269 {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B}, 270 {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B}, 271 {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B}, 272 {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B}, 273 {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B}, 274 {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B}, 275 {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B}, 276 {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B}, 277 {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B}, 278 {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B}, 279 {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B}, 280 {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B}, 281 {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B}, 282 {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B}, 283 {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B}, 284 {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B}, 285 {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B}, 286 {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B}, 287 {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B}, 288 {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B}, 289 {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B}, 290 {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B}, 291 {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B}, 292 {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B}, 293 {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B}, 294 {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B}, 295 {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B}, 296 {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B}, 297 {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B}, 298 {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B}, 299 {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B}, 300 {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B}, 301 {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B}, 302 {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B} 303}; 304 305/* kind of ENABLE for the second counter */ 306enum clock_config_register_bits { 307 CounterSwap = 0x1 << 21 308}; 309 310/* ioconfigreg */ 311static inline unsigned ioconfig_bitshift(unsigned pfi_channel) 312{ 313 if (pfi_channel % 2) 314 return 0; 315 else 316 return 8; 317} 318 319static inline unsigned pfi_output_select_mask(unsigned pfi_channel) 320{ 321 return 0x3 << ioconfig_bitshift(pfi_channel); 322} 323 324static inline unsigned pfi_output_select_bits(unsigned pfi_channel, 325 unsigned output_select) 326{ 327 return (output_select & 0x3) << ioconfig_bitshift(pfi_channel); 328} 329 330static inline unsigned pfi_input_select_mask(unsigned pfi_channel) 331{ 332 return 0x7 << (4 + ioconfig_bitshift(pfi_channel)); 333} 334 335static inline unsigned pfi_input_select_bits(unsigned pfi_channel, 336 unsigned input_select) 337{ 338 return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel)); 339} 340 341/* dma configuration register bits */ 342static inline unsigned dma_select_mask(unsigned dma_channel) 343{ 344 BUG_ON(dma_channel >= MAX_DMA_CHANNEL); 345 return 0x1f << (8 * dma_channel); 346} 347 348enum dma_selection { 349 dma_selection_none = 0x1f, 350}; 351static inline unsigned dma_selection_counter(unsigned counter_index) 352{ 353 BUG_ON(counter_index >= counters_per_chip); 354 return counter_index; 355} 356 357static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection) 358{ 359 BUG_ON(dma_channel >= MAX_DMA_CHANNEL); 360 return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel); 361} 362 363static inline unsigned dma_reset_bit(unsigned dma_channel) 364{ 365 BUG_ON(dma_channel >= MAX_DMA_CHANNEL); 366 return 0x80 << (8 * dma_channel); 367} 368 369enum global_interrupt_status_register_bits { 370 Counter_0_Int_Bit = 0x100, 371 Counter_1_Int_Bit = 0x200, 372 Counter_2_Int_Bit = 0x400, 373 Counter_3_Int_Bit = 0x800, 374 Cascade_Int_Bit = 0x20000000, 375 Global_Int_Bit = 0x80000000 376}; 377 378enum global_interrupt_config_register_bits { 379 Cascade_Int_Enable_Bit = 0x20000000, 380 Global_Int_Polarity_Bit = 0x40000000, 381 Global_Int_Enable_Bit = 0x80000000 382}; 383 384/* Offset of the GPCT chips from the base-adress of the card */ 385static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 }; /* First chip is at base-address + 386 0x00, etc. */ 387 388/* Board description*/ 389struct ni_660x_board { 390 unsigned short dev_id; /* `lspci` will show you this */ 391 const char *name; 392 unsigned n_chips; /* total number of TIO chips */ 393}; 394 395static const struct ni_660x_board ni_660x_boards[] = { 396 { 397 .dev_id = 0x2c60, 398 .name = "PCI-6601", 399 .n_chips = 1, 400 }, 401 { 402 .dev_id = 0x1310, 403 .name = "PCI-6602", 404 .n_chips = 2, 405 }, 406 { 407 .dev_id = 0x1360, 408 .name = "PXI-6602", 409 .n_chips = 2, 410 }, 411 { 412 .dev_id = 0x2cc0, 413 .name = "PXI-6608", 414 .n_chips = 2, 415 }, 416}; 417 418#define NI_660X_MAX_NUM_CHIPS 2 419#define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip) 420 421static DEFINE_PCI_DEVICE_TABLE(ni_660x_pci_table) = { 422 { 423 PCI_VENDOR_ID_NATINST, 0x2c60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 424 PCI_VENDOR_ID_NATINST, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 425 PCI_VENDOR_ID_NATINST, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 426 PCI_VENDOR_ID_NATINST, 0x2cc0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 427 0} 428}; 429 430MODULE_DEVICE_TABLE(pci, ni_660x_pci_table); 431 432struct ni_660x_private { 433 struct mite_struct *mite; 434 struct ni_gpct_device *counter_dev; 435 uint64_t pfi_direction_bits; 436 struct mite_dma_descriptor_ring 437 *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip]; 438 spinlock_t mite_channel_lock; 439 /* interrupt_lock prevents races between interrupt and comedi_poll */ 440 spinlock_t interrupt_lock; 441 unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS]; 442 spinlock_t soft_reg_copy_lock; 443 unsigned short pfi_output_selects[NUM_PFI_CHANNELS]; 444}; 445 446static inline struct ni_660x_private *private(struct comedi_device *dev) 447{ 448 return dev->private; 449} 450 451/* initialized in ni_660x_find_device() */ 452static inline const struct ni_660x_board *board(struct comedi_device *dev) 453{ 454 return dev->board_ptr; 455} 456 457#define n_ni_660x_boards (sizeof(ni_660x_boards)/sizeof(ni_660x_boards[0])) 458 459static int ni_660x_attach(struct comedi_device *dev, 460 struct comedi_devconfig *it); 461static int ni_660x_detach(struct comedi_device *dev); 462static void init_tio_chip(struct comedi_device *dev, int chipset); 463static void ni_660x_select_pfi_output(struct comedi_device *dev, 464 unsigned pfi_channel, 465 unsigned output_select); 466 467static struct comedi_driver driver_ni_660x = { 468 .driver_name = "ni_660x", 469 .module = THIS_MODULE, 470 .attach = ni_660x_attach, 471 .detach = ni_660x_detach, 472}; 473 474COMEDI_PCI_INITCLEANUP(driver_ni_660x, ni_660x_pci_table); 475 476static int ni_660x_find_device(struct comedi_device *dev, int bus, int slot); 477static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan, 478 unsigned source); 479 480/* Possible instructions for a GPCT */ 481static int ni_660x_GPCT_rinsn(struct comedi_device *dev, 482 struct comedi_subdevice *s, 483 struct comedi_insn *insn, unsigned int *data); 484static int ni_660x_GPCT_insn_config(struct comedi_device *dev, 485 struct comedi_subdevice *s, 486 struct comedi_insn *insn, 487 unsigned int *data); 488static int ni_660x_GPCT_winsn(struct comedi_device *dev, 489 struct comedi_subdevice *s, 490 struct comedi_insn *insn, unsigned int *data); 491 492/* Possible instructions for Digital IO */ 493static int ni_660x_dio_insn_config(struct comedi_device *dev, 494 struct comedi_subdevice *s, 495 struct comedi_insn *insn, 496 unsigned int *data); 497static int ni_660x_dio_insn_bits(struct comedi_device *dev, 498 struct comedi_subdevice *s, 499 struct comedi_insn *insn, unsigned int *data); 500 501static inline unsigned ni_660x_num_counters(struct comedi_device *dev) 502{ 503 return board(dev)->n_chips * counters_per_chip; 504} 505 506static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg) 507{ 508 enum NI_660x_Register ni_660x_register; 509 switch (reg) { 510 case NITIO_G0_Autoincrement_Reg: 511 ni_660x_register = G0AutoincrementRegister; 512 break; 513 case NITIO_G1_Autoincrement_Reg: 514 ni_660x_register = G1AutoincrementRegister; 515 break; 516 case NITIO_G2_Autoincrement_Reg: 517 ni_660x_register = G2AutoincrementRegister; 518 break; 519 case NITIO_G3_Autoincrement_Reg: 520 ni_660x_register = G3AutoincrementRegister; 521 break; 522 case NITIO_G0_Command_Reg: 523 ni_660x_register = G0CommandRegister; 524 break; 525 case NITIO_G1_Command_Reg: 526 ni_660x_register = G1CommandRegister; 527 break; 528 case NITIO_G2_Command_Reg: 529 ni_660x_register = G2CommandRegister; 530 break; 531 case NITIO_G3_Command_Reg: 532 ni_660x_register = G3CommandRegister; 533 break; 534 case NITIO_G0_HW_Save_Reg: 535 ni_660x_register = G0HWSaveRegister; 536 break; 537 case NITIO_G1_HW_Save_Reg: 538 ni_660x_register = G1HWSaveRegister; 539 break; 540 case NITIO_G2_HW_Save_Reg: 541 ni_660x_register = G2HWSaveRegister; 542 break; 543 case NITIO_G3_HW_Save_Reg: 544 ni_660x_register = G3HWSaveRegister; 545 break; 546 case NITIO_G0_SW_Save_Reg: 547 ni_660x_register = G0SWSaveRegister; 548 break; 549 case NITIO_G1_SW_Save_Reg: 550 ni_660x_register = G1SWSaveRegister; 551 break; 552 case NITIO_G2_SW_Save_Reg: 553 ni_660x_register = G2SWSaveRegister; 554 break; 555 case NITIO_G3_SW_Save_Reg: 556 ni_660x_register = G3SWSaveRegister; 557 break; 558 case NITIO_G0_Mode_Reg: 559 ni_660x_register = G0ModeRegister; 560 break; 561 case NITIO_G1_Mode_Reg: 562 ni_660x_register = G1ModeRegister; 563 break; 564 case NITIO_G2_Mode_Reg: 565 ni_660x_register = G2ModeRegister; 566 break; 567 case NITIO_G3_Mode_Reg: 568 ni_660x_register = G3ModeRegister; 569 break; 570 case NITIO_G0_LoadA_Reg: 571 ni_660x_register = G0LoadARegister; 572 break; 573 case NITIO_G1_LoadA_Reg: 574 ni_660x_register = G1LoadARegister; 575 break; 576 case NITIO_G2_LoadA_Reg: 577 ni_660x_register = G2LoadARegister; 578 break; 579 case NITIO_G3_LoadA_Reg: 580 ni_660x_register = G3LoadARegister; 581 break; 582 case NITIO_G0_LoadB_Reg: 583 ni_660x_register = G0LoadBRegister; 584 break; 585 case NITIO_G1_LoadB_Reg: 586 ni_660x_register = G1LoadBRegister; 587 break; 588 case NITIO_G2_LoadB_Reg: 589 ni_660x_register = G2LoadBRegister; 590 break; 591 case NITIO_G3_LoadB_Reg: 592 ni_660x_register = G3LoadBRegister; 593 break; 594 case NITIO_G0_Input_Select_Reg: 595 ni_660x_register = G0InputSelectRegister; 596 break; 597 case NITIO_G1_Input_Select_Reg: 598 ni_660x_register = G1InputSelectRegister; 599 break; 600 case NITIO_G2_Input_Select_Reg: 601 ni_660x_register = G2InputSelectRegister; 602 break; 603 case NITIO_G3_Input_Select_Reg: 604 ni_660x_register = G3InputSelectRegister; 605 break; 606 case NITIO_G01_Status_Reg: 607 ni_660x_register = G01StatusRegister; 608 break; 609 case NITIO_G23_Status_Reg: 610 ni_660x_register = G23StatusRegister; 611 break; 612 case NITIO_G01_Joint_Reset_Reg: 613 ni_660x_register = G01JointResetRegister; 614 break; 615 case NITIO_G23_Joint_Reset_Reg: 616 ni_660x_register = G23JointResetRegister; 617 break; 618 case NITIO_G01_Joint_Status1_Reg: 619 ni_660x_register = G01JointStatus1Register; 620 break; 621 case NITIO_G23_Joint_Status1_Reg: 622 ni_660x_register = G23JointStatus1Register; 623 break; 624 case NITIO_G01_Joint_Status2_Reg: 625 ni_660x_register = G01JointStatus2Register; 626 break; 627 case NITIO_G23_Joint_Status2_Reg: 628 ni_660x_register = G23JointStatus2Register; 629 break; 630 case NITIO_G0_Counting_Mode_Reg: 631 ni_660x_register = G0CountingModeRegister; 632 break; 633 case NITIO_G1_Counting_Mode_Reg: 634 ni_660x_register = G1CountingModeRegister; 635 break; 636 case NITIO_G2_Counting_Mode_Reg: 637 ni_660x_register = G2CountingModeRegister; 638 break; 639 case NITIO_G3_Counting_Mode_Reg: 640 ni_660x_register = G3CountingModeRegister; 641 break; 642 case NITIO_G0_Second_Gate_Reg: 643 ni_660x_register = G0SecondGateRegister; 644 break; 645 case NITIO_G1_Second_Gate_Reg: 646 ni_660x_register = G1SecondGateRegister; 647 break; 648 case NITIO_G2_Second_Gate_Reg: 649 ni_660x_register = G2SecondGateRegister; 650 break; 651 case NITIO_G3_Second_Gate_Reg: 652 ni_660x_register = G3SecondGateRegister; 653 break; 654 case NITIO_G0_DMA_Config_Reg: 655 ni_660x_register = G0DMAConfigRegister; 656 break; 657 case NITIO_G0_DMA_Status_Reg: 658 ni_660x_register = G0DMAStatusRegister; 659 break; 660 case NITIO_G1_DMA_Config_Reg: 661 ni_660x_register = G1DMAConfigRegister; 662 break; 663 case NITIO_G1_DMA_Status_Reg: 664 ni_660x_register = G1DMAStatusRegister; 665 break; 666 case NITIO_G2_DMA_Config_Reg: 667 ni_660x_register = G2DMAConfigRegister; 668 break; 669 case NITIO_G2_DMA_Status_Reg: 670 ni_660x_register = G2DMAStatusRegister; 671 break; 672 case NITIO_G3_DMA_Config_Reg: 673 ni_660x_register = G3DMAConfigRegister; 674 break; 675 case NITIO_G3_DMA_Status_Reg: 676 ni_660x_register = G3DMAStatusRegister; 677 break; 678 case NITIO_G0_Interrupt_Acknowledge_Reg: 679 ni_660x_register = G0InterruptAcknowledge; 680 break; 681 case NITIO_G1_Interrupt_Acknowledge_Reg: 682 ni_660x_register = G1InterruptAcknowledge; 683 break; 684 case NITIO_G2_Interrupt_Acknowledge_Reg: 685 ni_660x_register = G2InterruptAcknowledge; 686 break; 687 case NITIO_G3_Interrupt_Acknowledge_Reg: 688 ni_660x_register = G3InterruptAcknowledge; 689 break; 690 case NITIO_G0_Status_Reg: 691 ni_660x_register = G0StatusRegister; 692 break; 693 case NITIO_G1_Status_Reg: 694 ni_660x_register = G0StatusRegister; 695 break; 696 case NITIO_G2_Status_Reg: 697 ni_660x_register = G0StatusRegister; 698 break; 699 case NITIO_G3_Status_Reg: 700 ni_660x_register = G0StatusRegister; 701 break; 702 case NITIO_G0_Interrupt_Enable_Reg: 703 ni_660x_register = G0InterruptEnable; 704 break; 705 case NITIO_G1_Interrupt_Enable_Reg: 706 ni_660x_register = G1InterruptEnable; 707 break; 708 case NITIO_G2_Interrupt_Enable_Reg: 709 ni_660x_register = G2InterruptEnable; 710 break; 711 case NITIO_G3_Interrupt_Enable_Reg: 712 ni_660x_register = G3InterruptEnable; 713 break; 714 default: 715 printk("%s: unhandled register 0x%x in switch.\n", 716 __func__, reg); 717 BUG(); 718 return 0; 719 break; 720 } 721 return ni_660x_register; 722} 723 724static inline void ni_660x_write_register(struct comedi_device *dev, 725 unsigned chip_index, unsigned bits, 726 enum NI_660x_Register reg) 727{ 728 void *const write_address = 729 private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] + 730 registerData[reg].offset; 731 732 switch (registerData[reg].size) { 733 case DATA_2B: 734 writew(bits, write_address); 735 break; 736 case DATA_4B: 737 writel(bits, write_address); 738 break; 739 default: 740 printk("%s: %s: bug! unhandled case (reg=0x%x) in switch.\n", 741 __FILE__, __func__, reg); 742 BUG(); 743 break; 744 } 745} 746 747static inline unsigned ni_660x_read_register(struct comedi_device *dev, 748 unsigned chip_index, 749 enum NI_660x_Register reg) 750{ 751 void *const read_address = 752 private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] + 753 registerData[reg].offset; 754 755 switch (registerData[reg].size) { 756 case DATA_2B: 757 return readw(read_address); 758 break; 759 case DATA_4B: 760 return readl(read_address); 761 break; 762 default: 763 printk("%s: %s: bug! unhandled case (reg=0x%x) in switch.\n", 764 __FILE__, __func__, reg); 765 BUG(); 766 break; 767 } 768 return 0; 769} 770 771static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, 772 enum ni_gpct_register reg) 773{ 774 struct comedi_device *dev = counter->counter_dev->dev; 775 enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg); 776 ni_660x_write_register(dev, counter->chip_index, bits, 777 ni_660x_register); 778} 779 780static unsigned ni_gpct_read_register(struct ni_gpct *counter, 781 enum ni_gpct_register reg) 782{ 783 struct comedi_device *dev = counter->counter_dev->dev; 784 enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg); 785 return ni_660x_read_register(dev, counter->chip_index, 786 ni_660x_register); 787} 788 789static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private 790 *priv, 791 struct ni_gpct 792 *counter) 793{ 794 return priv->mite_rings[counter->chip_index][counter->counter_index]; 795} 796 797static inline void ni_660x_set_dma_channel(struct comedi_device *dev, 798 unsigned mite_channel, 799 struct ni_gpct *counter) 800{ 801 unsigned long flags; 802 spin_lock_irqsave(&private(dev)->soft_reg_copy_lock, flags); 803 private(dev)->dma_configuration_soft_copies[counter->chip_index] &= 804 ~dma_select_mask(mite_channel); 805 private(dev)->dma_configuration_soft_copies[counter->chip_index] |= 806 dma_select_bits(mite_channel, 807 dma_selection_counter(counter->counter_index)); 808 ni_660x_write_register(dev, counter->chip_index, 809 private(dev)-> 810 dma_configuration_soft_copies 811 [counter->chip_index] | 812 dma_reset_bit(mite_channel), DMAConfigRegister); 813 mmiowb(); 814 spin_unlock_irqrestore(&private(dev)->soft_reg_copy_lock, flags); 815} 816 817static inline void ni_660x_unset_dma_channel(struct comedi_device *dev, 818 unsigned mite_channel, 819 struct ni_gpct *counter) 820{ 821 unsigned long flags; 822 spin_lock_irqsave(&private(dev)->soft_reg_copy_lock, flags); 823 private(dev)->dma_configuration_soft_copies[counter->chip_index] &= 824 ~dma_select_mask(mite_channel); 825 private(dev)->dma_configuration_soft_copies[counter->chip_index] |= 826 dma_select_bits(mite_channel, dma_selection_none); 827 ni_660x_write_register(dev, counter->chip_index, 828 private(dev)-> 829 dma_configuration_soft_copies 830 [counter->chip_index], DMAConfigRegister); 831 mmiowb(); 832 spin_unlock_irqrestore(&private(dev)->soft_reg_copy_lock, flags); 833} 834 835static int ni_660x_request_mite_channel(struct comedi_device *dev, 836 struct ni_gpct *counter, 837 enum comedi_io_direction direction) 838{ 839 unsigned long flags; 840 struct mite_channel *mite_chan; 841 842 spin_lock_irqsave(&private(dev)->mite_channel_lock, flags); 843 BUG_ON(counter->mite_chan); 844 mite_chan = 845 mite_request_channel(private(dev)->mite, mite_ring(private(dev), 846 counter)); 847 if (mite_chan == NULL) { 848 spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags); 849 comedi_error(dev, 850 "failed to reserve mite dma channel for counter."); 851 return -EBUSY; 852 } 853 mite_chan->dir = direction; 854 ni_tio_set_mite_channel(counter, mite_chan); 855 ni_660x_set_dma_channel(dev, mite_chan->channel, counter); 856 spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags); 857 return 0; 858} 859 860void ni_660x_release_mite_channel(struct comedi_device *dev, 861 struct ni_gpct *counter) 862{ 863 unsigned long flags; 864 865 spin_lock_irqsave(&private(dev)->mite_channel_lock, flags); 866 if (counter->mite_chan) { 867 struct mite_channel *mite_chan = counter->mite_chan; 868 869 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter); 870 ni_tio_set_mite_channel(counter, NULL); 871 mite_release_channel(mite_chan); 872 } 873 spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags); 874} 875 876static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 877{ 878 int retval; 879 880 struct ni_gpct *counter = subdev_to_counter(s); 881/* const struct comedi_cmd *cmd = &s->async->cmd; */ 882 883 retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT); 884 if (retval) { 885 comedi_error(dev, 886 "no dma channel available for use by counter"); 887 return retval; 888 } 889 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL); 890 retval = ni_tio_cmd(counter, s->async); 891 892 return retval; 893} 894 895static int ni_660x_cmdtest(struct comedi_device *dev, 896 struct comedi_subdevice *s, struct comedi_cmd *cmd) 897{ 898 struct ni_gpct *counter = subdev_to_counter(s); 899 900 return ni_tio_cmdtest(counter, cmd); 901} 902 903static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 904{ 905 struct ni_gpct *counter = subdev_to_counter(s); 906 int retval; 907 908 retval = ni_tio_cancel(counter); 909 ni_660x_release_mite_channel(dev, counter); 910 return retval; 911} 912 913static void set_tio_counterswap(struct comedi_device *dev, int chipset) 914{ 915 /* See P. 3.5 of the Register-Level Programming manual. The 916 CounterSwap bit has to be set on the second chip, otherwise 917 it will try to use the same pins as the first chip. 918 */ 919 if (chipset) 920 ni_660x_write_register(dev, chipset, CounterSwap, 921 ClockConfigRegister); 922 else 923 ni_660x_write_register(dev, chipset, 0, ClockConfigRegister); 924} 925 926static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev, 927 struct comedi_subdevice *s) 928{ 929 ni_tio_handle_interrupt(subdev_to_counter(s), s); 930 if (s->async->events) { 931 if (s->async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR | 932 COMEDI_CB_OVERFLOW)) { 933 ni_660x_cancel(dev, s); 934 } 935 comedi_event(dev, s); 936 } 937} 938 939static irqreturn_t ni_660x_interrupt(int irq, void *d) 940{ 941 struct comedi_device *dev = d; 942 struct comedi_subdevice *s; 943 unsigned i; 944 unsigned long flags; 945 946 if (dev->attached == 0) 947 return IRQ_NONE; 948 /* lock to avoid race with comedi_poll */ 949 spin_lock_irqsave(&private(dev)->interrupt_lock, flags); 950 smp_mb(); 951 for (i = 0; i < ni_660x_num_counters(dev); ++i) { 952 s = dev->subdevices + NI_660X_GPCT_SUBDEV(i); 953 ni_660x_handle_gpct_interrupt(dev, s); 954 } 955 spin_unlock_irqrestore(&private(dev)->interrupt_lock, flags); 956 return IRQ_HANDLED; 957} 958 959static int ni_660x_input_poll(struct comedi_device *dev, 960 struct comedi_subdevice *s) 961{ 962 unsigned long flags; 963 /* lock to avoid race with comedi_poll */ 964 spin_lock_irqsave(&private(dev)->interrupt_lock, flags); 965 mite_sync_input_dma(subdev_to_counter(s)->mite_chan, s->async); 966 spin_unlock_irqrestore(&private(dev)->interrupt_lock, flags); 967 return comedi_buf_read_n_available(s->async); 968} 969 970static int ni_660x_buf_change(struct comedi_device *dev, 971 struct comedi_subdevice *s, 972 unsigned long new_size) 973{ 974 int ret; 975 976 ret = mite_buf_change(mite_ring(private(dev), subdev_to_counter(s)), 977 s->async); 978 if (ret < 0) 979 return ret; 980 981 return 0; 982} 983 984static int ni_660x_allocate_private(struct comedi_device *dev) 985{ 986 int retval; 987 unsigned i; 988 989 retval = alloc_private(dev, sizeof(struct ni_660x_private)); 990 if (retval < 0) 991 return retval; 992 993 spin_lock_init(&private(dev)->mite_channel_lock); 994 spin_lock_init(&private(dev)->interrupt_lock); 995 spin_lock_init(&private(dev)->soft_reg_copy_lock); 996 for (i = 0; i < NUM_PFI_CHANNELS; ++i) { 997 private(dev)->pfi_output_selects[i] = pfi_output_select_counter; 998 } 999 return 0; 1000} 1001 1002static int ni_660x_alloc_mite_rings(struct comedi_device *dev) 1003{ 1004 unsigned i; 1005 unsigned j; 1006 1007 for (i = 0; i < board(dev)->n_chips; ++i) { 1008 for (j = 0; j < counters_per_chip; ++j) { 1009 private(dev)->mite_rings[i][j] = 1010 mite_alloc_ring(private(dev)->mite); 1011 if (private(dev)->mite_rings[i][j] == NULL) { 1012 return -ENOMEM; 1013 } 1014 } 1015 } 1016 return 0; 1017} 1018 1019static void ni_660x_free_mite_rings(struct comedi_device *dev) 1020{ 1021 unsigned i; 1022 unsigned j; 1023 1024 for (i = 0; i < board(dev)->n_chips; ++i) { 1025 for (j = 0; j < counters_per_chip; ++j) { 1026 mite_free_ring(private(dev)->mite_rings[i][j]); 1027 } 1028 } 1029} 1030 1031static int ni_660x_attach(struct comedi_device *dev, 1032 struct comedi_devconfig *it) 1033{ 1034 struct comedi_subdevice *s; 1035 int ret; 1036 unsigned i; 1037 unsigned global_interrupt_config_bits; 1038 1039 printk("comedi%d: ni_660x: ", dev->minor); 1040 1041 ret = ni_660x_allocate_private(dev); 1042 if (ret < 0) 1043 return ret; 1044 ret = ni_660x_find_device(dev, it->options[0], it->options[1]); 1045 if (ret < 0) 1046 return ret; 1047 1048 dev->board_name = board(dev)->name; 1049 1050 ret = mite_setup2(private(dev)->mite, 1); 1051 if (ret < 0) { 1052 printk("error setting up mite\n"); 1053 return ret; 1054 } 1055 comedi_set_hw_dev(dev, &private(dev)->mite->pcidev->dev); 1056 ret = ni_660x_alloc_mite_rings(dev); 1057 if (ret < 0) 1058 return ret; 1059 1060 printk(" %s ", dev->board_name); 1061 1062 dev->n_subdevices = 2 + NI_660X_MAX_NUM_COUNTERS; 1063 1064 if (alloc_subdevices(dev, dev->n_subdevices) < 0) 1065 return -ENOMEM; 1066 1067 s = dev->subdevices + 0; 1068 /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */ 1069 s->type = COMEDI_SUBD_UNUSED; 1070 1071 s = dev->subdevices + NI_660X_DIO_SUBDEV; 1072 /* DIGITAL I/O SUBDEVICE */ 1073 s->type = COMEDI_SUBD_DIO; 1074 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; 1075 s->n_chan = NUM_PFI_CHANNELS; 1076 s->maxdata = 1; 1077 s->range_table = &range_digital; 1078 s->insn_bits = ni_660x_dio_insn_bits; 1079 s->insn_config = ni_660x_dio_insn_config; 1080 s->io_bits = 0; /* all bits default to input */ 1081 /* we use the ioconfig registers to control dio direction, so zero output enables in stc dio control reg */ 1082 ni_660x_write_register(dev, 0, 0, STCDIOControl); 1083 1084 private(dev)->counter_dev = ni_gpct_device_construct(dev, 1085 &ni_gpct_write_register, 1086 &ni_gpct_read_register, 1087 ni_gpct_variant_660x, 1088 ni_660x_num_counters 1089 (dev)); 1090 if (private(dev)->counter_dev == NULL) 1091 return -ENOMEM; 1092 for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) { 1093 s = dev->subdevices + NI_660X_GPCT_SUBDEV(i); 1094 if (i < ni_660x_num_counters(dev)) { 1095 s->type = COMEDI_SUBD_COUNTER; 1096 s->subdev_flags = 1097 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | 1098 SDF_CMD_READ /* | SDF_CMD_WRITE */ ; 1099 s->n_chan = 3; 1100 s->maxdata = 0xffffffff; 1101 s->insn_read = ni_660x_GPCT_rinsn; 1102 s->insn_write = ni_660x_GPCT_winsn; 1103 s->insn_config = ni_660x_GPCT_insn_config; 1104 s->do_cmd = &ni_660x_cmd; 1105 s->len_chanlist = 1; 1106 s->do_cmdtest = &ni_660x_cmdtest; 1107 s->cancel = &ni_660x_cancel; 1108 s->poll = &ni_660x_input_poll; 1109 s->async_dma_dir = DMA_BIDIRECTIONAL; 1110 s->buf_change = &ni_660x_buf_change; 1111 s->private = &private(dev)->counter_dev->counters[i]; 1112 1113 private(dev)->counter_dev->counters[i].chip_index = 1114 i / counters_per_chip; 1115 private(dev)->counter_dev->counters[i].counter_index = 1116 i % counters_per_chip; 1117 } else { 1118 s->type = COMEDI_SUBD_UNUSED; 1119 } 1120 } 1121 for (i = 0; i < board(dev)->n_chips; ++i) { 1122 init_tio_chip(dev, i); 1123 } 1124 for (i = 0; i < ni_660x_num_counters(dev); ++i) { 1125 ni_tio_init_counter(&private(dev)->counter_dev->counters[i]); 1126 } 1127 for (i = 0; i < NUM_PFI_CHANNELS; ++i) { 1128 if (i < min_counter_pfi_chan) 1129 ni_660x_set_pfi_routing(dev, i, pfi_output_select_do); 1130 else 1131 ni_660x_set_pfi_routing(dev, i, 1132 pfi_output_select_counter); 1133 ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z); 1134 } 1135 /* to be safe, set counterswap bits on tio chips after all the counter 1136 outputs have been set to high impedance mode */ 1137 for (i = 0; i < board(dev)->n_chips; ++i) { 1138 set_tio_counterswap(dev, i); 1139 } 1140 ret = request_irq(mite_irq(private(dev)->mite), ni_660x_interrupt, 1141 IRQF_SHARED, "ni_660x", dev); 1142 if (ret < 0) { 1143 printk(" irq not available\n"); 1144 return ret; 1145 } 1146 dev->irq = mite_irq(private(dev)->mite); 1147 global_interrupt_config_bits = Global_Int_Enable_Bit; 1148 if (board(dev)->n_chips > 1) 1149 global_interrupt_config_bits |= Cascade_Int_Enable_Bit; 1150 ni_660x_write_register(dev, 0, global_interrupt_config_bits, 1151 GlobalInterruptConfigRegister); 1152 printk("attached\n"); 1153 return 0; 1154} 1155 1156static int ni_660x_detach(struct comedi_device *dev) 1157{ 1158 printk("comedi%d: ni_660x: remove\n", dev->minor); 1159 1160 /* Free irq */ 1161 if (dev->irq) 1162 free_irq(dev->irq, dev); 1163 1164 if (dev->private) { 1165 if (private(dev)->counter_dev) 1166 ni_gpct_device_destroy(private(dev)->counter_dev); 1167 if (private(dev)->mite) { 1168 ni_660x_free_mite_rings(dev); 1169 mite_unsetup(private(dev)->mite); 1170 } 1171 } 1172 return 0; 1173} 1174 1175static int 1176ni_660x_GPCT_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1177 struct comedi_insn *insn, unsigned int *data) 1178{ 1179 return ni_tio_rinsn(subdev_to_counter(s), insn, data); 1180} 1181 1182static void init_tio_chip(struct comedi_device *dev, int chipset) 1183{ 1184 unsigned i; 1185 1186 /* init dma configuration register */ 1187 private(dev)->dma_configuration_soft_copies[chipset] = 0; 1188 for (i = 0; i < MAX_DMA_CHANNEL; ++i) { 1189 private(dev)->dma_configuration_soft_copies[chipset] |= 1190 dma_select_bits(i, dma_selection_none) & dma_select_mask(i); 1191 } 1192 ni_660x_write_register(dev, chipset, 1193 private(dev)-> 1194 dma_configuration_soft_copies[chipset], 1195 DMAConfigRegister); 1196 for (i = 0; i < NUM_PFI_CHANNELS; ++i) { 1197 ni_660x_write_register(dev, chipset, 0, IOConfigReg(i)); 1198 } 1199} 1200 1201static int 1202ni_660x_GPCT_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 1203 struct comedi_insn *insn, unsigned int *data) 1204{ 1205 return ni_tio_insn_config(subdev_to_counter(s), insn, data); 1206} 1207 1208static int ni_660x_GPCT_winsn(struct comedi_device *dev, 1209 struct comedi_subdevice *s, 1210 struct comedi_insn *insn, unsigned int *data) 1211{ 1212 return ni_tio_winsn(subdev_to_counter(s), insn, data); 1213} 1214 1215static int ni_660x_find_device(struct comedi_device *dev, int bus, int slot) 1216{ 1217 struct mite_struct *mite; 1218 int i; 1219 1220 for (mite = mite_devices; mite; mite = mite->next) { 1221 if (mite->used) 1222 continue; 1223 if (bus || slot) { 1224 if (bus != mite->pcidev->bus->number || 1225 slot != PCI_SLOT(mite->pcidev->devfn)) 1226 continue; 1227 } 1228 1229 for (i = 0; i < n_ni_660x_boards; i++) { 1230 if (mite_device_id(mite) == ni_660x_boards[i].dev_id) { 1231 dev->board_ptr = ni_660x_boards + i; 1232 private(dev)->mite = mite; 1233 return 0; 1234 } 1235 } 1236 } 1237 printk("no device found\n"); 1238 mite_list_devices(); 1239 return -EIO; 1240} 1241 1242static int ni_660x_dio_insn_bits(struct comedi_device *dev, 1243 struct comedi_subdevice *s, 1244 struct comedi_insn *insn, unsigned int *data) 1245{ 1246 unsigned base_bitfield_channel = CR_CHAN(insn->chanspec); 1247 1248 /* Check if we have to write some bits */ 1249 if (data[0]) { 1250 s->state &= ~(data[0] << base_bitfield_channel); 1251 s->state |= (data[0] & data[1]) << base_bitfield_channel; 1252 /* Write out the new digital output lines */ 1253 ni_660x_write_register(dev, 0, s->state, DIO32Output); 1254 } 1255 /* on return, data[1] contains the value of the digital 1256 * input and output lines. */ 1257 data[1] = 1258 (ni_660x_read_register(dev, 0, 1259 DIO32Input) >> base_bitfield_channel); 1260 return 2; 1261} 1262 1263static void ni_660x_select_pfi_output(struct comedi_device *dev, 1264 unsigned pfi_channel, 1265 unsigned output_select) 1266{ 1267 static const unsigned counter_4_7_first_pfi = 8; 1268 static const unsigned counter_4_7_last_pfi = 23; 1269 unsigned active_chipset = 0; 1270 unsigned idle_chipset = 0; 1271 unsigned active_bits; 1272 unsigned idle_bits; 1273 1274 if (board(dev)->n_chips > 1) { 1275 if (output_select == pfi_output_select_counter && 1276 pfi_channel >= counter_4_7_first_pfi && 1277 pfi_channel <= counter_4_7_last_pfi) { 1278 active_chipset = 1; 1279 idle_chipset = 0; 1280 } else { 1281 active_chipset = 0; 1282 idle_chipset = 1; 1283 } 1284 } 1285 1286 if (idle_chipset != active_chipset) { 1287 idle_bits = 1288 ni_660x_read_register(dev, idle_chipset, 1289 IOConfigReg(pfi_channel)); 1290 idle_bits &= ~pfi_output_select_mask(pfi_channel); 1291 idle_bits |= 1292 pfi_output_select_bits(pfi_channel, 1293 pfi_output_select_high_Z); 1294 ni_660x_write_register(dev, idle_chipset, idle_bits, 1295 IOConfigReg(pfi_channel)); 1296 } 1297 1298 active_bits = 1299 ni_660x_read_register(dev, active_chipset, 1300 IOConfigReg(pfi_channel)); 1301 active_bits &= ~pfi_output_select_mask(pfi_channel); 1302 active_bits |= pfi_output_select_bits(pfi_channel, output_select); 1303 ni_660x_write_register(dev, active_chipset, active_bits, 1304 IOConfigReg(pfi_channel)); 1305} 1306 1307static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan, 1308 unsigned source) 1309{ 1310 if (source > num_pfi_output_selects) 1311 return -EINVAL; 1312 if (source == pfi_output_select_high_Z) 1313 return -EINVAL; 1314 if (chan < min_counter_pfi_chan) { 1315 if (source == pfi_output_select_counter) 1316 return -EINVAL; 1317 } else if (chan > max_dio_pfi_chan) { 1318 if (source == pfi_output_select_do) 1319 return -EINVAL; 1320 } 1321 BUG_ON(chan >= NUM_PFI_CHANNELS); 1322 1323 private(dev)->pfi_output_selects[chan] = source; 1324 if (private(dev)->pfi_direction_bits & (((uint64_t) 1) << chan)) 1325 ni_660x_select_pfi_output(dev, chan, 1326 private(dev)-> 1327 pfi_output_selects[chan]); 1328 return 0; 1329} 1330 1331static unsigned ni_660x_get_pfi_routing(struct comedi_device *dev, 1332 unsigned chan) 1333{ 1334 BUG_ON(chan >= NUM_PFI_CHANNELS); 1335 return private(dev)->pfi_output_selects[chan]; 1336} 1337 1338static void ni660x_config_filter(struct comedi_device *dev, 1339 unsigned pfi_channel, 1340 enum ni_gpct_filter_select filter) 1341{ 1342 unsigned bits = ni_660x_read_register(dev, 0, IOConfigReg(pfi_channel)); 1343 bits &= ~pfi_input_select_mask(pfi_channel); 1344 bits |= pfi_input_select_bits(pfi_channel, filter); 1345 ni_660x_write_register(dev, 0, bits, IOConfigReg(pfi_channel)); 1346} 1347 1348static int ni_660x_dio_insn_config(struct comedi_device *dev, 1349 struct comedi_subdevice *s, 1350 struct comedi_insn *insn, unsigned int *data) 1351{ 1352 int chan = CR_CHAN(insn->chanspec); 1353 1354 /* The input or output configuration of each digital line is 1355 * configured by a special insn_config instruction. chanspec 1356 * contains the channel to be changed, and data[0] contains the 1357 * value COMEDI_INPUT or COMEDI_OUTPUT. */ 1358 1359 switch (data[0]) { 1360 case INSN_CONFIG_DIO_OUTPUT: 1361 private(dev)->pfi_direction_bits |= ((uint64_t) 1) << chan; 1362 ni_660x_select_pfi_output(dev, chan, 1363 private(dev)-> 1364 pfi_output_selects[chan]); 1365 break; 1366 case INSN_CONFIG_DIO_INPUT: 1367 private(dev)->pfi_direction_bits &= ~(((uint64_t) 1) << chan); 1368 ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z); 1369 break; 1370 case INSN_CONFIG_DIO_QUERY: 1371 data[1] = 1372 (private(dev)->pfi_direction_bits & 1373 (((uint64_t) 1) << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT; 1374 return 0; 1375 case INSN_CONFIG_SET_ROUTING: 1376 return ni_660x_set_pfi_routing(dev, chan, data[1]); 1377 break; 1378 case INSN_CONFIG_GET_ROUTING: 1379 data[1] = ni_660x_get_pfi_routing(dev, chan); 1380 break; 1381 case INSN_CONFIG_FILTER: 1382 ni660x_config_filter(dev, chan, data[1]); 1383 break; 1384 default: 1385 return -EINVAL; 1386 break; 1387 }; 1388 return 0; 1389} 1390