ni_660x.c revision 25436dc9d84f1be60ff549c9ab712bba2835f284
1/* 2 comedi/drivers/ni_660x.c 3 Hardware driver for NI 660x devices 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18*/ 19 20/* 21Driver: ni_660x 22Description: National Instruments 660x counter/timer boards 23Devices: 24[National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602, 25 PXI-6608 26Author: J.P. Mellor <jpmellor@rose-hulman.edu>, 27 Herman.Bruyninckx@mech.kuleuven.ac.be, 28 Wim.Meeussen@mech.kuleuven.ac.be, 29 Klaas.Gadeyne@mech.kuleuven.ac.be, 30 Frank Mori Hess <fmhess@users.sourceforge.net> 31Updated: Thu Oct 18 12:56:06 EDT 2007 32Status: experimental 33 34Encoders work. PulseGeneration (both single pulse and pulse train) 35works. Buffered commands work for input but not output. 36 37References: 38DAQ 660x Register-Level Programmer Manual (NI 370505A-01) 39DAQ 6601/6602 User Manual (NI 322137B-01) 40 41*/ 42 43#include <linux/interrupt.h> 44#include "../comedidev.h" 45#include "mite.h" 46#include "ni_tio.h" 47 48enum ni_660x_constants { 49 min_counter_pfi_chan = 8, 50 max_dio_pfi_chan = 31, 51 counters_per_chip = 4 52}; 53 54#define NUM_PFI_CHANNELS 40 55/* really there are only up to 3 dma channels, but the register layout allows for 4 */ 56#define MAX_DMA_CHANNEL 4 57 58/* See Register-Level Programmer Manual page 3.1 */ 59enum NI_660x_Register { 60 G0InterruptAcknowledge, 61 G0StatusRegister, 62 G1InterruptAcknowledge, 63 G1StatusRegister, 64 G01StatusRegister, 65 G0CommandRegister, 66 STCDIOParallelInput, 67 G1CommandRegister, 68 G0HWSaveRegister, 69 G1HWSaveRegister, 70 STCDIOOutput, 71 STCDIOControl, 72 G0SWSaveRegister, 73 G1SWSaveRegister, 74 G0ModeRegister, 75 G01JointStatus1Register, 76 G1ModeRegister, 77 STCDIOSerialInput, 78 G0LoadARegister, 79 G01JointStatus2Register, 80 G0LoadBRegister, 81 G1LoadARegister, 82 G1LoadBRegister, 83 G0InputSelectRegister, 84 G1InputSelectRegister, 85 G0AutoincrementRegister, 86 G1AutoincrementRegister, 87 G01JointResetRegister, 88 G0InterruptEnable, 89 G1InterruptEnable, 90 G0CountingModeRegister, 91 G1CountingModeRegister, 92 G0SecondGateRegister, 93 G1SecondGateRegister, 94 G0DMAConfigRegister, 95 G0DMAStatusRegister, 96 G1DMAConfigRegister, 97 G1DMAStatusRegister, 98 G2InterruptAcknowledge, 99 G2StatusRegister, 100 G3InterruptAcknowledge, 101 G3StatusRegister, 102 G23StatusRegister, 103 G2CommandRegister, 104 G3CommandRegister, 105 G2HWSaveRegister, 106 G3HWSaveRegister, 107 G2SWSaveRegister, 108 G3SWSaveRegister, 109 G2ModeRegister, 110 G23JointStatus1Register, 111 G3ModeRegister, 112 G2LoadARegister, 113 G23JointStatus2Register, 114 G2LoadBRegister, 115 G3LoadARegister, 116 G3LoadBRegister, 117 G2InputSelectRegister, 118 G3InputSelectRegister, 119 G2AutoincrementRegister, 120 G3AutoincrementRegister, 121 G23JointResetRegister, 122 G2InterruptEnable, 123 G3InterruptEnable, 124 G2CountingModeRegister, 125 G3CountingModeRegister, 126 G3SecondGateRegister, 127 G2SecondGateRegister, 128 G2DMAConfigRegister, 129 G2DMAStatusRegister, 130 G3DMAConfigRegister, 131 G3DMAStatusRegister, 132 DIO32Input, 133 DIO32Output, 134 ClockConfigRegister, 135 GlobalInterruptStatusRegister, 136 DMAConfigRegister, 137 GlobalInterruptConfigRegister, 138 IOConfigReg0_1, 139 IOConfigReg2_3, 140 IOConfigReg4_5, 141 IOConfigReg6_7, 142 IOConfigReg8_9, 143 IOConfigReg10_11, 144 IOConfigReg12_13, 145 IOConfigReg14_15, 146 IOConfigReg16_17, 147 IOConfigReg18_19, 148 IOConfigReg20_21, 149 IOConfigReg22_23, 150 IOConfigReg24_25, 151 IOConfigReg26_27, 152 IOConfigReg28_29, 153 IOConfigReg30_31, 154 IOConfigReg32_33, 155 IOConfigReg34_35, 156 IOConfigReg36_37, 157 IOConfigReg38_39, 158 NumRegisters, 159}; 160 161static inline unsigned IOConfigReg(unsigned pfi_channel) 162{ 163 unsigned reg = IOConfigReg0_1 + pfi_channel / 2; 164 BUG_ON(reg > IOConfigReg38_39); 165 return reg; 166} 167 168enum ni_660x_register_width { 169 DATA_1B, 170 DATA_2B, 171 DATA_4B 172}; 173 174enum ni_660x_register_direction { 175 NI_660x_READ, 176 NI_660x_WRITE, 177 NI_660x_READ_WRITE 178}; 179 180enum ni_660x_pfi_output_select { 181 pfi_output_select_high_Z = 0, 182 pfi_output_select_counter = 1, 183 pfi_output_select_do = 2, 184 num_pfi_output_selects 185}; 186 187enum ni_660x_subdevices { 188 NI_660X_DIO_SUBDEV = 1, 189 NI_660X_GPCT_SUBDEV_0 = 2 190}; 191static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index) 192{ 193 return NI_660X_GPCT_SUBDEV_0 + index; 194} 195 196struct NI_660xRegisterData { 197 198 const char *name; /* Register Name */ 199 int offset; /* Offset from base address from GPCT chip */ 200 enum ni_660x_register_direction direction; 201 enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */ 202}; 203 204 205static const struct NI_660xRegisterData registerData[NumRegisters] = { 206 {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B}, 207 {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B}, 208 {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B}, 209 {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B}, 210 {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B}, 211 {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B}, 212 {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B}, 213 {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B}, 214 {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B}, 215 {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B}, 216 {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B}, 217 {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B}, 218 {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B}, 219 {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B}, 220 {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B}, 221 {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B}, 222 {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B}, 223 {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B}, 224 {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B}, 225 {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B}, 226 {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B}, 227 {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B}, 228 {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B}, 229 {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B}, 230 {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B}, 231 {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B}, 232 {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B}, 233 {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B}, 234 {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B}, 235 {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B}, 236 {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B}, 237 {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B}, 238 {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B}, 239 {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B}, 240 {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B}, 241 {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B}, 242 {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B}, 243 {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B}, 244 {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B}, 245 {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B}, 246 {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B}, 247 {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B}, 248 {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B}, 249 {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B}, 250 {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B}, 251 {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B}, 252 {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B}, 253 {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B}, 254 {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B}, 255 {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B}, 256 {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B}, 257 {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B}, 258 {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B}, 259 {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B}, 260 {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B}, 261 {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B}, 262 {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B}, 263 {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B}, 264 {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B}, 265 {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B}, 266 {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B}, 267 {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B}, 268 {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B}, 269 {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B}, 270 {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B}, 271 {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B}, 272 {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B}, 273 {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B}, 274 {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B}, 275 {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B}, 276 {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B}, 277 {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B}, 278 {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B}, 279 {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B}, 280 {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B}, 281 {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B}, 282 {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B}, 283 {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B}, 284 {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B}, 285 {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B}, 286 {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B}, 287 {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B}, 288 {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B}, 289 {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B}, 290 {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B}, 291 {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B}, 292 {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B}, 293 {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B}, 294 {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B}, 295 {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B}, 296 {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B}, 297 {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B}, 298 {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B}, 299 {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B}, 300 {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B}, 301 {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B}, 302 {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B}, 303 {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B} 304}; 305 306/* kind of ENABLE for the second counter */ 307enum clock_config_register_bits { 308 CounterSwap = 0x1 << 21 309}; 310 311/* ioconfigreg */ 312static inline unsigned ioconfig_bitshift(unsigned pfi_channel) 313{ 314 if (pfi_channel % 2) 315 return 0; 316 else 317 return 8; 318} 319static inline unsigned pfi_output_select_mask(unsigned pfi_channel) 320{ 321 return 0x3 << ioconfig_bitshift(pfi_channel); 322} 323static inline unsigned pfi_output_select_bits(unsigned pfi_channel, 324 unsigned output_select) 325{ 326 return (output_select & 0x3) << ioconfig_bitshift(pfi_channel); 327} 328static inline unsigned pfi_input_select_mask(unsigned pfi_channel) 329{ 330 return 0x7 << (4 + ioconfig_bitshift(pfi_channel)); 331} 332static inline unsigned pfi_input_select_bits(unsigned pfi_channel, 333 unsigned input_select) 334{ 335 return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel)); 336} 337 338/* dma configuration register bits */ 339static inline unsigned dma_select_mask(unsigned dma_channel) 340{ 341 BUG_ON(dma_channel >= MAX_DMA_CHANNEL); 342 return 0x1f << (8 * dma_channel); 343} 344enum dma_selection { 345 dma_selection_none = 0x1f, 346}; 347static inline unsigned dma_selection_counter(unsigned counter_index) 348{ 349 BUG_ON(counter_index >= counters_per_chip); 350 return counter_index; 351} 352static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection) 353{ 354 BUG_ON(dma_channel >= MAX_DMA_CHANNEL); 355 return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel); 356} 357static inline unsigned dma_reset_bit(unsigned dma_channel) 358{ 359 BUG_ON(dma_channel >= MAX_DMA_CHANNEL); 360 return 0x80 << (8 * dma_channel); 361} 362 363enum global_interrupt_status_register_bits { 364 Counter_0_Int_Bit = 0x100, 365 Counter_1_Int_Bit = 0x200, 366 Counter_2_Int_Bit = 0x400, 367 Counter_3_Int_Bit = 0x800, 368 Cascade_Int_Bit = 0x20000000, 369 Global_Int_Bit = 0x80000000 370}; 371 372enum global_interrupt_config_register_bits { 373 Cascade_Int_Enable_Bit = 0x20000000, 374 Global_Int_Polarity_Bit = 0x40000000, 375 Global_Int_Enable_Bit = 0x80000000 376}; 377 378/* Offset of the GPCT chips from the base-adress of the card */ 379static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 }; /* First chip is at base-address + 380 0x00, etc. */ 381 382/* Board description*/ 383struct ni_660x_board { 384 unsigned short dev_id; /* `lspci` will show you this */ 385 const char *name; 386 unsigned n_chips; /* total number of TIO chips */ 387}; 388 389static const struct ni_660x_board ni_660x_boards[] = { 390 { 391 .dev_id = 0x2c60, 392 .name = "PCI-6601", 393 .n_chips = 1, 394 }, 395 { 396 .dev_id = 0x1310, 397 .name = "PCI-6602", 398 .n_chips = 2, 399 }, 400 { 401 .dev_id = 0x1360, 402 .name = "PXI-6602", 403 .n_chips = 2, 404 }, 405 { 406 .dev_id = 0x2cc0, 407 .name = "PXI-6608", 408 .n_chips = 2, 409 }, 410}; 411 412#define NI_660X_MAX_NUM_CHIPS 2 413#define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip) 414 415static DEFINE_PCI_DEVICE_TABLE(ni_660x_pci_table) = { 416 {PCI_VENDOR_ID_NATINST, 0x2c60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 417 {PCI_VENDOR_ID_NATINST, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 418 {PCI_VENDOR_ID_NATINST, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 419 {PCI_VENDOR_ID_NATINST, 0x2cc0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 420 {0} 421}; 422 423MODULE_DEVICE_TABLE(pci, ni_660x_pci_table); 424 425struct ni_660x_private { 426 struct mite_struct *mite; 427 struct ni_gpct_device *counter_dev; 428 uint64_t pfi_direction_bits; 429 struct mite_dma_descriptor_ring 430 *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip]; 431 spinlock_t mite_channel_lock; 432 /* interrupt_lock prevents races between interrupt and comedi_poll */ 433 spinlock_t interrupt_lock; 434 unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS]; 435 spinlock_t soft_reg_copy_lock; 436 unsigned short pfi_output_selects[NUM_PFI_CHANNELS]; 437}; 438 439static inline struct ni_660x_private *private(struct comedi_device * dev) 440{ 441 return dev->private; 442} 443 444/* initialized in ni_660x_find_device() */ 445static inline const struct ni_660x_board *board(struct comedi_device * dev) 446{ 447 return dev->board_ptr; 448} 449 450#define n_ni_660x_boards (sizeof(ni_660x_boards)/sizeof(ni_660x_boards[0])) 451 452static int ni_660x_attach(struct comedi_device *dev, struct comedi_devconfig *it); 453static int ni_660x_detach(struct comedi_device *dev); 454static void init_tio_chip(struct comedi_device *dev, int chipset); 455static void ni_660x_select_pfi_output(struct comedi_device *dev, unsigned pfi_channel, 456 unsigned output_select); 457 458static struct comedi_driver driver_ni_660x = { 459 .driver_name = "ni_660x", 460 .module = THIS_MODULE, 461 .attach = ni_660x_attach, 462 .detach = ni_660x_detach, 463}; 464 465COMEDI_PCI_INITCLEANUP(driver_ni_660x, ni_660x_pci_table); 466 467static int ni_660x_find_device(struct comedi_device *dev, int bus, int slot); 468static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan, 469 unsigned source); 470 471/* Possible instructions for a GPCT */ 472static int ni_660x_GPCT_rinsn(struct comedi_device *dev, 473 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data); 474static int ni_660x_GPCT_insn_config(struct comedi_device *dev, 475 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data); 476static int ni_660x_GPCT_winsn(struct comedi_device *dev, 477 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data); 478 479/* Possible instructions for Digital IO */ 480static int ni_660x_dio_insn_config(struct comedi_device *dev, 481 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data); 482static int ni_660x_dio_insn_bits(struct comedi_device *dev, 483 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data); 484 485static inline unsigned ni_660x_num_counters(struct comedi_device *dev) 486{ 487 return board(dev)->n_chips * counters_per_chip; 488} 489 490static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg) 491{ 492 enum NI_660x_Register ni_660x_register; 493 switch (reg) { 494 case NITIO_G0_Autoincrement_Reg: 495 ni_660x_register = G0AutoincrementRegister; 496 break; 497 case NITIO_G1_Autoincrement_Reg: 498 ni_660x_register = G1AutoincrementRegister; 499 break; 500 case NITIO_G2_Autoincrement_Reg: 501 ni_660x_register = G2AutoincrementRegister; 502 break; 503 case NITIO_G3_Autoincrement_Reg: 504 ni_660x_register = G3AutoincrementRegister; 505 break; 506 case NITIO_G0_Command_Reg: 507 ni_660x_register = G0CommandRegister; 508 break; 509 case NITIO_G1_Command_Reg: 510 ni_660x_register = G1CommandRegister; 511 break; 512 case NITIO_G2_Command_Reg: 513 ni_660x_register = G2CommandRegister; 514 break; 515 case NITIO_G3_Command_Reg: 516 ni_660x_register = G3CommandRegister; 517 break; 518 case NITIO_G0_HW_Save_Reg: 519 ni_660x_register = G0HWSaveRegister; 520 break; 521 case NITIO_G1_HW_Save_Reg: 522 ni_660x_register = G1HWSaveRegister; 523 break; 524 case NITIO_G2_HW_Save_Reg: 525 ni_660x_register = G2HWSaveRegister; 526 break; 527 case NITIO_G3_HW_Save_Reg: 528 ni_660x_register = G3HWSaveRegister; 529 break; 530 case NITIO_G0_SW_Save_Reg: 531 ni_660x_register = G0SWSaveRegister; 532 break; 533 case NITIO_G1_SW_Save_Reg: 534 ni_660x_register = G1SWSaveRegister; 535 break; 536 case NITIO_G2_SW_Save_Reg: 537 ni_660x_register = G2SWSaveRegister; 538 break; 539 case NITIO_G3_SW_Save_Reg: 540 ni_660x_register = G3SWSaveRegister; 541 break; 542 case NITIO_G0_Mode_Reg: 543 ni_660x_register = G0ModeRegister; 544 break; 545 case NITIO_G1_Mode_Reg: 546 ni_660x_register = G1ModeRegister; 547 break; 548 case NITIO_G2_Mode_Reg: 549 ni_660x_register = G2ModeRegister; 550 break; 551 case NITIO_G3_Mode_Reg: 552 ni_660x_register = G3ModeRegister; 553 break; 554 case NITIO_G0_LoadA_Reg: 555 ni_660x_register = G0LoadARegister; 556 break; 557 case NITIO_G1_LoadA_Reg: 558 ni_660x_register = G1LoadARegister; 559 break; 560 case NITIO_G2_LoadA_Reg: 561 ni_660x_register = G2LoadARegister; 562 break; 563 case NITIO_G3_LoadA_Reg: 564 ni_660x_register = G3LoadARegister; 565 break; 566 case NITIO_G0_LoadB_Reg: 567 ni_660x_register = G0LoadBRegister; 568 break; 569 case NITIO_G1_LoadB_Reg: 570 ni_660x_register = G1LoadBRegister; 571 break; 572 case NITIO_G2_LoadB_Reg: 573 ni_660x_register = G2LoadBRegister; 574 break; 575 case NITIO_G3_LoadB_Reg: 576 ni_660x_register = G3LoadBRegister; 577 break; 578 case NITIO_G0_Input_Select_Reg: 579 ni_660x_register = G0InputSelectRegister; 580 break; 581 case NITIO_G1_Input_Select_Reg: 582 ni_660x_register = G1InputSelectRegister; 583 break; 584 case NITIO_G2_Input_Select_Reg: 585 ni_660x_register = G2InputSelectRegister; 586 break; 587 case NITIO_G3_Input_Select_Reg: 588 ni_660x_register = G3InputSelectRegister; 589 break; 590 case NITIO_G01_Status_Reg: 591 ni_660x_register = G01StatusRegister; 592 break; 593 case NITIO_G23_Status_Reg: 594 ni_660x_register = G23StatusRegister; 595 break; 596 case NITIO_G01_Joint_Reset_Reg: 597 ni_660x_register = G01JointResetRegister; 598 break; 599 case NITIO_G23_Joint_Reset_Reg: 600 ni_660x_register = G23JointResetRegister; 601 break; 602 case NITIO_G01_Joint_Status1_Reg: 603 ni_660x_register = G01JointStatus1Register; 604 break; 605 case NITIO_G23_Joint_Status1_Reg: 606 ni_660x_register = G23JointStatus1Register; 607 break; 608 case NITIO_G01_Joint_Status2_Reg: 609 ni_660x_register = G01JointStatus2Register; 610 break; 611 case NITIO_G23_Joint_Status2_Reg: 612 ni_660x_register = G23JointStatus2Register; 613 break; 614 case NITIO_G0_Counting_Mode_Reg: 615 ni_660x_register = G0CountingModeRegister; 616 break; 617 case NITIO_G1_Counting_Mode_Reg: 618 ni_660x_register = G1CountingModeRegister; 619 break; 620 case NITIO_G2_Counting_Mode_Reg: 621 ni_660x_register = G2CountingModeRegister; 622 break; 623 case NITIO_G3_Counting_Mode_Reg: 624 ni_660x_register = G3CountingModeRegister; 625 break; 626 case NITIO_G0_Second_Gate_Reg: 627 ni_660x_register = G0SecondGateRegister; 628 break; 629 case NITIO_G1_Second_Gate_Reg: 630 ni_660x_register = G1SecondGateRegister; 631 break; 632 case NITIO_G2_Second_Gate_Reg: 633 ni_660x_register = G2SecondGateRegister; 634 break; 635 case NITIO_G3_Second_Gate_Reg: 636 ni_660x_register = G3SecondGateRegister; 637 break; 638 case NITIO_G0_DMA_Config_Reg: 639 ni_660x_register = G0DMAConfigRegister; 640 break; 641 case NITIO_G0_DMA_Status_Reg: 642 ni_660x_register = G0DMAStatusRegister; 643 break; 644 case NITIO_G1_DMA_Config_Reg: 645 ni_660x_register = G1DMAConfigRegister; 646 break; 647 case NITIO_G1_DMA_Status_Reg: 648 ni_660x_register = G1DMAStatusRegister; 649 break; 650 case NITIO_G2_DMA_Config_Reg: 651 ni_660x_register = G2DMAConfigRegister; 652 break; 653 case NITIO_G2_DMA_Status_Reg: 654 ni_660x_register = G2DMAStatusRegister; 655 break; 656 case NITIO_G3_DMA_Config_Reg: 657 ni_660x_register = G3DMAConfigRegister; 658 break; 659 case NITIO_G3_DMA_Status_Reg: 660 ni_660x_register = G3DMAStatusRegister; 661 break; 662 case NITIO_G0_Interrupt_Acknowledge_Reg: 663 ni_660x_register = G0InterruptAcknowledge; 664 break; 665 case NITIO_G1_Interrupt_Acknowledge_Reg: 666 ni_660x_register = G1InterruptAcknowledge; 667 break; 668 case NITIO_G2_Interrupt_Acknowledge_Reg: 669 ni_660x_register = G2InterruptAcknowledge; 670 break; 671 case NITIO_G3_Interrupt_Acknowledge_Reg: 672 ni_660x_register = G3InterruptAcknowledge; 673 break; 674 case NITIO_G0_Status_Reg: 675 ni_660x_register = G0StatusRegister; 676 break; 677 case NITIO_G1_Status_Reg: 678 ni_660x_register = G0StatusRegister; 679 break; 680 case NITIO_G2_Status_Reg: 681 ni_660x_register = G0StatusRegister; 682 break; 683 case NITIO_G3_Status_Reg: 684 ni_660x_register = G0StatusRegister; 685 break; 686 case NITIO_G0_Interrupt_Enable_Reg: 687 ni_660x_register = G0InterruptEnable; 688 break; 689 case NITIO_G1_Interrupt_Enable_Reg: 690 ni_660x_register = G1InterruptEnable; 691 break; 692 case NITIO_G2_Interrupt_Enable_Reg: 693 ni_660x_register = G2InterruptEnable; 694 break; 695 case NITIO_G3_Interrupt_Enable_Reg: 696 ni_660x_register = G3InterruptEnable; 697 break; 698 default: 699 printk("%s: unhandled register 0x%x in switch.\n", 700 __func__, reg); 701 BUG(); 702 return 0; 703 break; 704 } 705 return ni_660x_register; 706} 707 708static inline void ni_660x_write_register(struct comedi_device *dev, 709 unsigned chip_index, unsigned bits, enum NI_660x_Register reg) 710{ 711 void *const write_address = 712 private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] + 713 registerData[reg].offset; 714 715 switch (registerData[reg].size) { 716 case DATA_2B: 717 writew(bits, write_address); 718 break; 719 case DATA_4B: 720 writel(bits, write_address); 721 break; 722 default: 723 printk("%s: %s: bug! unhandled case (reg=0x%x) in switch.\n", 724 __FILE__, __func__, reg); 725 BUG(); 726 break; 727 } 728} 729 730static inline unsigned ni_660x_read_register(struct comedi_device *dev, 731 unsigned chip_index, enum NI_660x_Register reg) 732{ 733 void *const read_address = 734 private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] + 735 registerData[reg].offset; 736 737 switch (registerData[reg].size) { 738 case DATA_2B: 739 return readw(read_address); 740 break; 741 case DATA_4B: 742 return readl(read_address); 743 break; 744 default: 745 printk("%s: %s: bug! unhandled case (reg=0x%x) in switch.\n", 746 __FILE__, __func__, reg); 747 BUG(); 748 break; 749 } 750 return 0; 751} 752 753static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, 754 enum ni_gpct_register reg) 755{ 756 struct comedi_device *dev = counter->counter_dev->dev; 757 enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg); 758 ni_660x_write_register(dev, counter->chip_index, bits, 759 ni_660x_register); 760} 761 762static unsigned ni_gpct_read_register(struct ni_gpct *counter, 763 enum ni_gpct_register reg) 764{ 765 struct comedi_device *dev = counter->counter_dev->dev; 766 enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg); 767 return ni_660x_read_register(dev, counter->chip_index, 768 ni_660x_register); 769} 770 771static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private * priv, 772 struct ni_gpct *counter) 773{ 774 return priv->mite_rings[counter->chip_index][counter->counter_index]; 775} 776 777static inline void ni_660x_set_dma_channel(struct comedi_device *dev, 778 unsigned mite_channel, struct ni_gpct *counter) 779{ 780 unsigned long flags; 781 spin_lock_irqsave(&private(dev)->soft_reg_copy_lock, flags); 782 private(dev)->dma_configuration_soft_copies[counter->chip_index] &= 783 ~dma_select_mask(mite_channel); 784 private(dev)->dma_configuration_soft_copies[counter->chip_index] |= 785 dma_select_bits(mite_channel, 786 dma_selection_counter(counter->counter_index)); 787 ni_660x_write_register(dev, counter->chip_index, 788 private(dev)->dma_configuration_soft_copies[counter-> 789 chip_index] | dma_reset_bit(mite_channel), 790 DMAConfigRegister); 791 mmiowb(); 792 spin_unlock_irqrestore(&private(dev)->soft_reg_copy_lock, flags); 793} 794 795static inline void ni_660x_unset_dma_channel(struct comedi_device *dev, 796 unsigned mite_channel, struct ni_gpct *counter) 797{ 798 unsigned long flags; 799 spin_lock_irqsave(&private(dev)->soft_reg_copy_lock, flags); 800 private(dev)->dma_configuration_soft_copies[counter->chip_index] &= 801 ~dma_select_mask(mite_channel); 802 private(dev)->dma_configuration_soft_copies[counter->chip_index] |= 803 dma_select_bits(mite_channel, dma_selection_none); 804 ni_660x_write_register(dev, counter->chip_index, 805 private(dev)->dma_configuration_soft_copies[counter-> 806 chip_index], DMAConfigRegister); 807 mmiowb(); 808 spin_unlock_irqrestore(&private(dev)->soft_reg_copy_lock, flags); 809} 810 811static int ni_660x_request_mite_channel(struct comedi_device *dev, 812 struct ni_gpct *counter, enum comedi_io_direction direction) 813{ 814 unsigned long flags; 815 struct mite_channel *mite_chan; 816 817 spin_lock_irqsave(&private(dev)->mite_channel_lock, flags); 818 BUG_ON(counter->mite_chan); 819 mite_chan = 820 mite_request_channel(private(dev)->mite, mite_ring(private(dev), 821 counter)); 822 if (mite_chan == NULL) { 823 spin_unlock_irqrestore(&private(dev)->mite_channel_lock, 824 flags); 825 comedi_error(dev, 826 "failed to reserve mite dma channel for counter."); 827 return -EBUSY; 828 } 829 mite_chan->dir = direction; 830 ni_tio_set_mite_channel(counter, mite_chan); 831 ni_660x_set_dma_channel(dev, mite_chan->channel, counter); 832 spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags); 833 return 0; 834} 835 836void ni_660x_release_mite_channel(struct comedi_device *dev, struct ni_gpct *counter) 837{ 838 unsigned long flags; 839 840 spin_lock_irqsave(&private(dev)->mite_channel_lock, flags); 841 if (counter->mite_chan) { 842 struct mite_channel *mite_chan = counter->mite_chan; 843 844 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter); 845 ni_tio_set_mite_channel(counter, NULL); 846 mite_release_channel(mite_chan); 847 } 848 spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags); 849} 850 851static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 852{ 853 int retval; 854 855 struct ni_gpct *counter = subdev_to_counter(s); 856/* const struct comedi_cmd *cmd = &s->async->cmd; */ 857 858 retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT); 859 if (retval) { 860 comedi_error(dev, 861 "no dma channel available for use by counter"); 862 return retval; 863 } 864 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL); 865 retval = ni_tio_cmd(counter, s->async); 866 867 return retval; 868} 869 870static int ni_660x_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 871 struct comedi_cmd *cmd) 872{ 873 struct ni_gpct *counter = subdev_to_counter(s); 874 875 return ni_tio_cmdtest(counter, cmd); 876} 877 878static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 879{ 880 struct ni_gpct *counter = subdev_to_counter(s); 881 int retval; 882 883 retval = ni_tio_cancel(counter); 884 ni_660x_release_mite_channel(dev, counter); 885 return retval; 886} 887 888static void set_tio_counterswap(struct comedi_device *dev, int chipset) 889{ 890 /* See P. 3.5 of the Register-Level Programming manual. The 891 CounterSwap bit has to be set on the second chip, otherwise 892 it will try to use the same pins as the first chip. 893 */ 894 if (chipset) 895 ni_660x_write_register(dev, chipset, CounterSwap, 896 ClockConfigRegister); 897 else 898 ni_660x_write_register(dev, chipset, 0, ClockConfigRegister); 899} 900 901static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev, 902 struct comedi_subdevice *s) 903{ 904 ni_tio_handle_interrupt(subdev_to_counter(s), s); 905 if (s->async->events) { 906 if (s->async-> 907 events & (COMEDI_CB_EOA | COMEDI_CB_ERROR | 908 COMEDI_CB_OVERFLOW)) { 909 ni_660x_cancel(dev, s); 910 } 911 comedi_event(dev, s); 912 } 913} 914 915static irqreturn_t ni_660x_interrupt(int irq, void *d) 916{ 917 struct comedi_device *dev = d; 918 struct comedi_subdevice *s; 919 unsigned i; 920 unsigned long flags; 921 922 if (dev->attached == 0) 923 return IRQ_NONE; 924 /* lock to avoid race with comedi_poll */ 925 spin_lock_irqsave(&private(dev)->interrupt_lock, flags); 926 smp_mb(); 927 for (i = 0; i < ni_660x_num_counters(dev); ++i) { 928 s = dev->subdevices + NI_660X_GPCT_SUBDEV(i); 929 ni_660x_handle_gpct_interrupt(dev, s); 930 } 931 spin_unlock_irqrestore(&private(dev)->interrupt_lock, flags); 932 return IRQ_HANDLED; 933} 934 935static int ni_660x_input_poll(struct comedi_device *dev, 936 struct comedi_subdevice *s) 937{ 938 unsigned long flags; 939 /* lock to avoid race with comedi_poll */ 940 spin_lock_irqsave(&private(dev)->interrupt_lock, flags); 941 mite_sync_input_dma(subdev_to_counter(s)->mite_chan, s->async); 942 spin_unlock_irqrestore(&private(dev)->interrupt_lock, flags); 943 return comedi_buf_read_n_available(s->async); 944} 945 946static int ni_660x_buf_change(struct comedi_device *dev, struct comedi_subdevice *s, 947 unsigned long new_size) 948{ 949 int ret; 950 951 ret = mite_buf_change(mite_ring(private(dev), subdev_to_counter(s)), 952 s->async); 953 if (ret < 0) 954 return ret; 955 956 return 0; 957} 958 959static int ni_660x_allocate_private(struct comedi_device *dev) 960{ 961 int retval; 962 unsigned i; 963 964 retval = alloc_private(dev, sizeof(struct ni_660x_private)); 965 if (retval < 0) 966 return retval; 967 968 spin_lock_init(&private(dev)->mite_channel_lock); 969 spin_lock_init(&private(dev)->interrupt_lock); 970 spin_lock_init(&private(dev)->soft_reg_copy_lock); 971 for (i = 0; i < NUM_PFI_CHANNELS; ++i) { 972 private(dev)->pfi_output_selects[i] = pfi_output_select_counter; 973 } 974 return 0; 975} 976 977static int ni_660x_alloc_mite_rings(struct comedi_device *dev) 978{ 979 unsigned i; 980 unsigned j; 981 982 for (i = 0; i < board(dev)->n_chips; ++i) { 983 for (j = 0; j < counters_per_chip; ++j) { 984 private(dev)->mite_rings[i][j] = 985 mite_alloc_ring(private(dev)->mite); 986 if (private(dev)->mite_rings[i][j] == NULL) { 987 return -ENOMEM; 988 } 989 } 990 } 991 return 0; 992} 993 994static void ni_660x_free_mite_rings(struct comedi_device *dev) 995{ 996 unsigned i; 997 unsigned j; 998 999 for (i = 0; i < board(dev)->n_chips; ++i) { 1000 for (j = 0; j < counters_per_chip; ++j) { 1001 mite_free_ring(private(dev)->mite_rings[i][j]); 1002 } 1003 } 1004} 1005 1006static int ni_660x_attach(struct comedi_device *dev, struct comedi_devconfig *it) 1007{ 1008 struct comedi_subdevice *s; 1009 int ret; 1010 unsigned i; 1011 unsigned global_interrupt_config_bits; 1012 1013 printk("comedi%d: ni_660x: ", dev->minor); 1014 1015 ret = ni_660x_allocate_private(dev); 1016 if (ret < 0) 1017 return ret; 1018 ret = ni_660x_find_device(dev, it->options[0], it->options[1]); 1019 if (ret < 0) 1020 return ret; 1021 1022 dev->board_name = board(dev)->name; 1023 1024 ret = mite_setup2(private(dev)->mite, 1); 1025 if (ret < 0) { 1026 printk("error setting up mite\n"); 1027 return ret; 1028 } 1029 comedi_set_hw_dev(dev, &private(dev)->mite->pcidev->dev); 1030 ret = ni_660x_alloc_mite_rings(dev); 1031 if (ret < 0) 1032 return ret; 1033 1034 printk(" %s ", dev->board_name); 1035 1036 dev->n_subdevices = 2 + NI_660X_MAX_NUM_COUNTERS; 1037 1038 if (alloc_subdevices(dev, dev->n_subdevices) < 0) 1039 return -ENOMEM; 1040 1041 s = dev->subdevices + 0; 1042 /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */ 1043 s->type = COMEDI_SUBD_UNUSED; 1044 1045 s = dev->subdevices + NI_660X_DIO_SUBDEV; 1046 /* DIGITAL I/O SUBDEVICE */ 1047 s->type = COMEDI_SUBD_DIO; 1048 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; 1049 s->n_chan = NUM_PFI_CHANNELS; 1050 s->maxdata = 1; 1051 s->range_table = &range_digital; 1052 s->insn_bits = ni_660x_dio_insn_bits; 1053 s->insn_config = ni_660x_dio_insn_config; 1054 s->io_bits = 0; /* all bits default to input */ 1055 /* we use the ioconfig registers to control dio direction, so zero output enables in stc dio control reg */ 1056 ni_660x_write_register(dev, 0, 0, STCDIOControl); 1057 1058 private(dev)->counter_dev = ni_gpct_device_construct(dev, 1059 &ni_gpct_write_register, &ni_gpct_read_register, 1060 ni_gpct_variant_660x, ni_660x_num_counters(dev)); 1061 if (private(dev)->counter_dev == NULL) 1062 return -ENOMEM; 1063 for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) { 1064 s = dev->subdevices + NI_660X_GPCT_SUBDEV(i); 1065 if (i < ni_660x_num_counters(dev)) { 1066 s->type = COMEDI_SUBD_COUNTER; 1067 s->subdev_flags = 1068 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | 1069 SDF_CMD_READ /* | SDF_CMD_WRITE */ ; 1070 s->n_chan = 3; 1071 s->maxdata = 0xffffffff; 1072 s->insn_read = ni_660x_GPCT_rinsn; 1073 s->insn_write = ni_660x_GPCT_winsn; 1074 s->insn_config = ni_660x_GPCT_insn_config; 1075 s->do_cmd = &ni_660x_cmd; 1076 s->len_chanlist = 1; 1077 s->do_cmdtest = &ni_660x_cmdtest; 1078 s->cancel = &ni_660x_cancel; 1079 s->poll = &ni_660x_input_poll; 1080 s->async_dma_dir = DMA_BIDIRECTIONAL; 1081 s->buf_change = &ni_660x_buf_change; 1082 s->private = &private(dev)->counter_dev->counters[i]; 1083 1084 private(dev)->counter_dev->counters[i].chip_index = 1085 i / counters_per_chip; 1086 private(dev)->counter_dev->counters[i].counter_index = 1087 i % counters_per_chip; 1088 } else { 1089 s->type = COMEDI_SUBD_UNUSED; 1090 } 1091 } 1092 for (i = 0; i < board(dev)->n_chips; ++i) { 1093 init_tio_chip(dev, i); 1094 } 1095 for (i = 0; i < ni_660x_num_counters(dev); ++i) { 1096 ni_tio_init_counter(&private(dev)->counter_dev->counters[i]); 1097 } 1098 for (i = 0; i < NUM_PFI_CHANNELS; ++i) { 1099 if (i < min_counter_pfi_chan) 1100 ni_660x_set_pfi_routing(dev, i, pfi_output_select_do); 1101 else 1102 ni_660x_set_pfi_routing(dev, i, 1103 pfi_output_select_counter); 1104 ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z); 1105 } 1106 /* to be safe, set counterswap bits on tio chips after all the counter 1107 outputs have been set to high impedance mode */ 1108 for (i = 0; i < board(dev)->n_chips; ++i) { 1109 set_tio_counterswap(dev, i); 1110 } 1111 ret = request_irq(mite_irq(private(dev)->mite), ni_660x_interrupt, 1112 IRQF_SHARED, "ni_660x", dev); 1113 if (ret < 0) { 1114 printk(" irq not available\n"); 1115 return ret; 1116 } 1117 dev->irq = mite_irq(private(dev)->mite); 1118 global_interrupt_config_bits = Global_Int_Enable_Bit; 1119 if (board(dev)->n_chips > 1) 1120 global_interrupt_config_bits |= Cascade_Int_Enable_Bit; 1121 ni_660x_write_register(dev, 0, global_interrupt_config_bits, 1122 GlobalInterruptConfigRegister); 1123 printk("attached\n"); 1124 return 0; 1125} 1126 1127static int ni_660x_detach(struct comedi_device *dev) 1128{ 1129 printk("comedi%d: ni_660x: remove\n", dev->minor); 1130 1131 /* Free irq */ 1132 if (dev->irq) 1133 free_irq(dev->irq, dev); 1134 1135 if (dev->private) { 1136 if (private(dev)->counter_dev) 1137 ni_gpct_device_destroy(private(dev)->counter_dev); 1138 if (private(dev)->mite) { 1139 ni_660x_free_mite_rings(dev); 1140 mite_unsetup(private(dev)->mite); 1141 } 1142 } 1143 return 0; 1144} 1145 1146static int 1147ni_660x_GPCT_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1148 struct comedi_insn *insn, unsigned int *data) 1149{ 1150 return ni_tio_rinsn(subdev_to_counter(s), insn, data); 1151} 1152 1153static void init_tio_chip(struct comedi_device *dev, int chipset) 1154{ 1155 unsigned i; 1156 1157 /* init dma configuration register */ 1158 private(dev)->dma_configuration_soft_copies[chipset] = 0; 1159 for (i = 0; i < MAX_DMA_CHANNEL; ++i) { 1160 private(dev)->dma_configuration_soft_copies[chipset] |= 1161 dma_select_bits(i, 1162 dma_selection_none) & dma_select_mask(i); 1163 } 1164 ni_660x_write_register(dev, chipset, 1165 private(dev)->dma_configuration_soft_copies[chipset], 1166 DMAConfigRegister); 1167 for (i = 0; i < NUM_PFI_CHANNELS; ++i) 1168 { 1169 ni_660x_write_register(dev, chipset, 0, IOConfigReg(i)); 1170 } 1171} 1172 1173static int 1174ni_660x_GPCT_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 1175 struct comedi_insn *insn, unsigned int *data) 1176{ 1177 return ni_tio_insn_config(subdev_to_counter(s), insn, data); 1178} 1179 1180static int ni_660x_GPCT_winsn(struct comedi_device *dev, 1181 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) 1182{ 1183 return ni_tio_winsn(subdev_to_counter(s), insn, data); 1184} 1185 1186static int ni_660x_find_device(struct comedi_device *dev, int bus, int slot) 1187{ 1188 struct mite_struct *mite; 1189 int i; 1190 1191 for (mite = mite_devices; mite; mite = mite->next) { 1192 if (mite->used) 1193 continue; 1194 if (bus || slot) { 1195 if (bus != mite->pcidev->bus->number || 1196 slot != PCI_SLOT(mite->pcidev->devfn)) 1197 continue; 1198 } 1199 1200 for (i = 0; i < n_ni_660x_boards; i++) { 1201 if (mite_device_id(mite) == ni_660x_boards[i].dev_id) { 1202 dev->board_ptr = ni_660x_boards + i; 1203 private(dev)->mite = mite; 1204 return 0; 1205 } 1206 } 1207 } 1208 printk("no device found\n"); 1209 mite_list_devices(); 1210 return -EIO; 1211} 1212 1213static int ni_660x_dio_insn_bits(struct comedi_device *dev, 1214 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) 1215{ 1216 unsigned base_bitfield_channel = CR_CHAN(insn->chanspec); 1217 1218 /* Check if we have to write some bits */ 1219 if (data[0]) { 1220 s->state &= ~(data[0] << base_bitfield_channel); 1221 s->state |= (data[0] & data[1]) << base_bitfield_channel; 1222 /* Write out the new digital output lines */ 1223 ni_660x_write_register(dev, 0, s->state, DIO32Output); 1224 } 1225 /* on return, data[1] contains the value of the digital 1226 * input and output lines. */ 1227 data[1] = 1228 (ni_660x_read_register(dev, 0, 1229 DIO32Input) >> base_bitfield_channel); 1230 return 2; 1231} 1232 1233static void ni_660x_select_pfi_output(struct comedi_device *dev, unsigned pfi_channel, 1234 unsigned output_select) 1235{ 1236 static const unsigned counter_4_7_first_pfi = 8; 1237 static const unsigned counter_4_7_last_pfi = 23; 1238 unsigned active_chipset = 0; 1239 unsigned idle_chipset = 0; 1240 unsigned active_bits; 1241 unsigned idle_bits; 1242 1243 if (board (dev)->n_chips > 1) { 1244 if (output_select == pfi_output_select_counter && 1245 pfi_channel >= counter_4_7_first_pfi && 1246 pfi_channel <= counter_4_7_last_pfi) { 1247 active_chipset = 1; 1248 idle_chipset = 0; 1249 }else { 1250 active_chipset = 0; 1251 idle_chipset = 1; 1252 } 1253 } 1254 1255 if (idle_chipset != active_chipset) { 1256 idle_bits = ni_660x_read_register(dev, idle_chipset, IOConfigReg(pfi_channel)); 1257 idle_bits &= ~pfi_output_select_mask(pfi_channel); 1258 idle_bits |= pfi_output_select_bits(pfi_channel, pfi_output_select_high_Z); 1259 ni_660x_write_register(dev, idle_chipset, idle_bits, IOConfigReg(pfi_channel)); 1260 } 1261 1262 active_bits = ni_660x_read_register(dev, active_chipset, IOConfigReg(pfi_channel)); 1263 active_bits &= ~pfi_output_select_mask(pfi_channel); 1264 active_bits |= pfi_output_select_bits(pfi_channel, output_select); 1265 ni_660x_write_register(dev, active_chipset, active_bits, IOConfigReg(pfi_channel)); 1266} 1267 1268static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan, 1269 unsigned source) 1270{ 1271 if (source > num_pfi_output_selects) 1272 return -EINVAL; 1273 if (source == pfi_output_select_high_Z) 1274 return -EINVAL; 1275 if (chan < min_counter_pfi_chan) { 1276 if (source == pfi_output_select_counter) 1277 return -EINVAL; 1278 } else if (chan > max_dio_pfi_chan) { 1279 if (source == pfi_output_select_do) 1280 return -EINVAL; 1281 } 1282 BUG_ON(chan >= NUM_PFI_CHANNELS); 1283 1284 private(dev)->pfi_output_selects[chan] = source; 1285 if (private(dev)->pfi_direction_bits & (((uint64_t) 1) << chan)) 1286 ni_660x_select_pfi_output(dev, chan, 1287 private(dev)->pfi_output_selects[chan]); 1288 return 0; 1289} 1290 1291static unsigned ni_660x_get_pfi_routing(struct comedi_device *dev, unsigned chan) 1292{ 1293 BUG_ON(chan >= NUM_PFI_CHANNELS); 1294 return private(dev)->pfi_output_selects[chan]; 1295} 1296 1297static void ni660x_config_filter(struct comedi_device *dev, unsigned pfi_channel, 1298 enum ni_gpct_filter_select filter) 1299{ 1300 unsigned bits = ni_660x_read_register(dev, 0, IOConfigReg(pfi_channel)); 1301 bits &= ~pfi_input_select_mask(pfi_channel); 1302 bits |= pfi_input_select_bits(pfi_channel, filter); 1303 ni_660x_write_register(dev, 0, bits, IOConfigReg(pfi_channel)); 1304} 1305 1306static int ni_660x_dio_insn_config(struct comedi_device *dev, 1307 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) 1308{ 1309 int chan = CR_CHAN(insn->chanspec); 1310 1311 /* The input or output configuration of each digital line is 1312 * configured by a special insn_config instruction. chanspec 1313 * contains the channel to be changed, and data[0] contains the 1314 * value COMEDI_INPUT or COMEDI_OUTPUT. */ 1315 1316 switch (data[0]) { 1317 case INSN_CONFIG_DIO_OUTPUT: 1318 private(dev)->pfi_direction_bits |= ((uint64_t) 1) << chan; 1319 ni_660x_select_pfi_output(dev, chan, 1320 private(dev)->pfi_output_selects[chan]); 1321 break; 1322 case INSN_CONFIG_DIO_INPUT: 1323 private(dev)->pfi_direction_bits &= ~(((uint64_t) 1) << chan); 1324 ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z); 1325 break; 1326 case INSN_CONFIG_DIO_QUERY: 1327 data[1] = 1328 (private(dev)-> 1329 pfi_direction_bits & (((uint64_t) 1) << chan)) ? 1330 COMEDI_OUTPUT : COMEDI_INPUT; 1331 return 0; 1332 case INSN_CONFIG_SET_ROUTING: 1333 return ni_660x_set_pfi_routing(dev, chan, data[1]); 1334 break; 1335 case INSN_CONFIG_GET_ROUTING: 1336 data[1] = ni_660x_get_pfi_routing(dev, chan); 1337 break; 1338 case INSN_CONFIG_FILTER: 1339 ni660x_config_filter(dev, chan, data[1]); 1340 break; 1341 default: 1342 return -EINVAL; 1343 break; 1344 }; 1345 return 0; 1346} 1347