ni_660x.c revision 900b78088567d2033c58d4e2433c3d2558f56b76
1/*
2  comedi/drivers/ni_660x.c
3  Hardware driver for NI 660x devices
4
5  This program is free software; you can redistribute it and/or modify
6  it under the terms of the GNU General Public License as published by
7  the Free Software Foundation; either version 2 of the License, or
8  (at your option) any later version.
9
10  This program is distributed in the hope that it will be useful,
11  but WITHOUT ANY WARRANTY; without even the implied warranty of
12  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  GNU General Public License for more details.
14
15  You should have received a copy of the GNU General Public License
16  along with this program; if not, write to the Free Software
17  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18*/
19
20/*
21Driver: ni_660x
22Description: National Instruments 660x counter/timer boards
23Devices:
24[National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
25	PXI-6608
26Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
27	Herman.Bruyninckx@mech.kuleuven.ac.be,
28	Wim.Meeussen@mech.kuleuven.ac.be,
29	Klaas.Gadeyne@mech.kuleuven.ac.be,
30	Frank Mori Hess <fmhess@users.sourceforge.net>
31Updated: Thu Oct 18 12:56:06 EDT 2007
32Status: experimental
33
34Encoders work.  PulseGeneration (both single pulse and pulse train)
35works. Buffered commands work for input but not output.
36
37References:
38DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
39DAQ 6601/6602 User Manual (NI 322137B-01)
40
41*/
42
43#include <linux/interrupt.h>
44#include "../comedidev.h"
45#include "mite.h"
46#include "ni_tio.h"
47
48enum ni_660x_constants {
49	min_counter_pfi_chan = 8,
50	max_dio_pfi_chan = 31,
51	counters_per_chip = 4
52};
53
54#define NUM_PFI_CHANNELS 40
55/* really there are only up to 3 dma channels, but the register layout allows
56for 4 */
57
58#define MAX_DMA_CHANNEL 4
59
60/* See Register-Level Programmer Manual page 3.1 */
61enum NI_660x_Register {
62	G0InterruptAcknowledge,
63	G0StatusRegister,
64	G1InterruptAcknowledge,
65	G1StatusRegister,
66	G01StatusRegister,
67	G0CommandRegister,
68	STCDIOParallelInput,
69	G1CommandRegister,
70	G0HWSaveRegister,
71	G1HWSaveRegister,
72	STCDIOOutput,
73	STCDIOControl,
74	G0SWSaveRegister,
75	G1SWSaveRegister,
76	G0ModeRegister,
77	G01JointStatus1Register,
78	G1ModeRegister,
79	STCDIOSerialInput,
80	G0LoadARegister,
81	G01JointStatus2Register,
82	G0LoadBRegister,
83	G1LoadARegister,
84	G1LoadBRegister,
85	G0InputSelectRegister,
86	G1InputSelectRegister,
87	G0AutoincrementRegister,
88	G1AutoincrementRegister,
89	G01JointResetRegister,
90	G0InterruptEnable,
91	G1InterruptEnable,
92	G0CountingModeRegister,
93	G1CountingModeRegister,
94	G0SecondGateRegister,
95	G1SecondGateRegister,
96	G0DMAConfigRegister,
97	G0DMAStatusRegister,
98	G1DMAConfigRegister,
99	G1DMAStatusRegister,
100	G2InterruptAcknowledge,
101	G2StatusRegister,
102	G3InterruptAcknowledge,
103	G3StatusRegister,
104	G23StatusRegister,
105	G2CommandRegister,
106	G3CommandRegister,
107	G2HWSaveRegister,
108	G3HWSaveRegister,
109	G2SWSaveRegister,
110	G3SWSaveRegister,
111	G2ModeRegister,
112	G23JointStatus1Register,
113	G3ModeRegister,
114	G2LoadARegister,
115	G23JointStatus2Register,
116	G2LoadBRegister,
117	G3LoadARegister,
118	G3LoadBRegister,
119	G2InputSelectRegister,
120	G3InputSelectRegister,
121	G2AutoincrementRegister,
122	G3AutoincrementRegister,
123	G23JointResetRegister,
124	G2InterruptEnable,
125	G3InterruptEnable,
126	G2CountingModeRegister,
127	G3CountingModeRegister,
128	G3SecondGateRegister,
129	G2SecondGateRegister,
130	G2DMAConfigRegister,
131	G2DMAStatusRegister,
132	G3DMAConfigRegister,
133	G3DMAStatusRegister,
134	DIO32Input,
135	DIO32Output,
136	ClockConfigRegister,
137	GlobalInterruptStatusRegister,
138	DMAConfigRegister,
139	GlobalInterruptConfigRegister,
140	IOConfigReg0_1,
141	IOConfigReg2_3,
142	IOConfigReg4_5,
143	IOConfigReg6_7,
144	IOConfigReg8_9,
145	IOConfigReg10_11,
146	IOConfigReg12_13,
147	IOConfigReg14_15,
148	IOConfigReg16_17,
149	IOConfigReg18_19,
150	IOConfigReg20_21,
151	IOConfigReg22_23,
152	IOConfigReg24_25,
153	IOConfigReg26_27,
154	IOConfigReg28_29,
155	IOConfigReg30_31,
156	IOConfigReg32_33,
157	IOConfigReg34_35,
158	IOConfigReg36_37,
159	IOConfigReg38_39,
160	NumRegisters,
161};
162
163static inline unsigned IOConfigReg(unsigned pfi_channel)
164{
165	unsigned reg = IOConfigReg0_1 + pfi_channel / 2;
166	BUG_ON(reg > IOConfigReg38_39);
167	return reg;
168}
169
170enum ni_660x_register_width {
171	DATA_1B,
172	DATA_2B,
173	DATA_4B
174};
175
176enum ni_660x_register_direction {
177	NI_660x_READ,
178	NI_660x_WRITE,
179	NI_660x_READ_WRITE
180};
181
182enum ni_660x_pfi_output_select {
183	pfi_output_select_high_Z = 0,
184	pfi_output_select_counter = 1,
185	pfi_output_select_do = 2,
186	num_pfi_output_selects
187};
188
189enum ni_660x_subdevices {
190	NI_660X_DIO_SUBDEV = 1,
191	NI_660X_GPCT_SUBDEV_0 = 2
192};
193static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index)
194{
195	return NI_660X_GPCT_SUBDEV_0 + index;
196}
197
198struct NI_660xRegisterData {
199
200	const char *name;	/*  Register Name */
201	int offset;		/*  Offset from base address from GPCT chip */
202	enum ni_660x_register_direction direction;
203	enum ni_660x_register_width size; /*  1 byte, 2 bytes, or 4 bytes */
204};
205
206static const struct NI_660xRegisterData registerData[NumRegisters] = {
207	{"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B},
208	{"G0 Status Register", 0x004, NI_660x_READ, DATA_2B},
209	{"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B},
210	{"G1 Status Register", 0x006, NI_660x_READ, DATA_2B},
211	{"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B},
212	{"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B},
213	{"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B},
214	{"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B},
215	{"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B},
216	{"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B},
217	{"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B},
218	{"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B},
219	{"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B},
220	{"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B},
221	{"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B},
222	{"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B},
223	{"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B},
224	{"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B},
225	{"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B},
226	{"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B},
227	{"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B},
228	{"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B},
229	{"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B},
230	{"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B},
231	{"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B},
232	{"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B},
233	{"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B},
234	{"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B},
235	{"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B},
236	{"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B},
237	{"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B},
238	{"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B},
239	{"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B},
240	{"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B},
241	{"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B},
242	{"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B},
243	{"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B},
244	{"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B},
245	{"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B},
246	{"G2 Status Register", 0x104, NI_660x_READ, DATA_2B},
247	{"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B},
248	{"G3 Status Register", 0x106, NI_660x_READ, DATA_2B},
249	{"G23 Status Register", 0x108, NI_660x_READ, DATA_2B},
250	{"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B},
251	{"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B},
252	{"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B},
253	{"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B},
254	{"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B},
255	{"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B},
256	{"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B},
257	{"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B},
258	{"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B},
259	{"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B},
260	{"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B},
261	{"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B},
262	{"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B},
263	{"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B},
264	{"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B},
265	{"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B},
266	{"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B},
267	{"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B},
268	{"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B},
269	{"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B},
270	{"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B},
271	{"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B},
272	{"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B},
273	{"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B},
274	{"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B},
275	{"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B},
276	{"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B},
277	{"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B},
278	{"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B},
279	{"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B},
280	{"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B},
281	{"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B},
282	{"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B},
283	{"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B},
284	{"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B},
285	{"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B},
286	{"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B},
287	{"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B},
288	{"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B},
289	{"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B},
290	{"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B},
291	{"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B},
292	{"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B},
293	{"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B},
294	{"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B},
295	{"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B},
296	{"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B},
297	{"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B},
298	{"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B},
299	{"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B},
300	{"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B},
301	{"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B},
302	{"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B},
303	{"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B},
304	{"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B}
305};
306
307/* kind of ENABLE for the second counter */
308enum clock_config_register_bits {
309	CounterSwap = 0x1 << 21
310};
311
312/* ioconfigreg */
313static inline unsigned ioconfig_bitshift(unsigned pfi_channel)
314{
315	if (pfi_channel % 2)
316		return 0;
317	else
318		return 8;
319}
320
321static inline unsigned pfi_output_select_mask(unsigned pfi_channel)
322{
323	return 0x3 << ioconfig_bitshift(pfi_channel);
324}
325
326static inline unsigned pfi_output_select_bits(unsigned pfi_channel,
327					      unsigned output_select)
328{
329	return (output_select & 0x3) << ioconfig_bitshift(pfi_channel);
330}
331
332static inline unsigned pfi_input_select_mask(unsigned pfi_channel)
333{
334	return 0x7 << (4 + ioconfig_bitshift(pfi_channel));
335}
336
337static inline unsigned pfi_input_select_bits(unsigned pfi_channel,
338					     unsigned input_select)
339{
340	return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel));
341}
342
343/* dma configuration register bits */
344static inline unsigned dma_select_mask(unsigned dma_channel)
345{
346	BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
347	return 0x1f << (8 * dma_channel);
348}
349
350enum dma_selection {
351	dma_selection_none = 0x1f,
352};
353static inline unsigned dma_selection_counter(unsigned counter_index)
354{
355	BUG_ON(counter_index >= counters_per_chip);
356	return counter_index;
357}
358
359static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection)
360{
361	BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
362	return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel);
363}
364
365static inline unsigned dma_reset_bit(unsigned dma_channel)
366{
367	BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
368	return 0x80 << (8 * dma_channel);
369}
370
371enum global_interrupt_status_register_bits {
372	Counter_0_Int_Bit = 0x100,
373	Counter_1_Int_Bit = 0x200,
374	Counter_2_Int_Bit = 0x400,
375	Counter_3_Int_Bit = 0x800,
376	Cascade_Int_Bit = 0x20000000,
377	Global_Int_Bit = 0x80000000
378};
379
380enum global_interrupt_config_register_bits {
381	Cascade_Int_Enable_Bit = 0x20000000,
382	Global_Int_Polarity_Bit = 0x40000000,
383	Global_Int_Enable_Bit = 0x80000000
384};
385
386/* Offset of the GPCT chips from the base-adress of the card */
387/* First chip is at base-address + 0x00, etc. */
388static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 };
389
390/* Board description*/
391struct ni_660x_board {
392	unsigned short dev_id;	/* `lspci` will show you this */
393	const char *name;
394	unsigned n_chips;	/* total number of TIO chips */
395};
396
397static const struct ni_660x_board ni_660x_boards[] = {
398	{
399	 .dev_id = 0x2c60,
400	 .name = "PCI-6601",
401	 .n_chips = 1,
402	 },
403	{
404	 .dev_id = 0x1310,
405	 .name = "PCI-6602",
406	 .n_chips = 2,
407	 },
408	{
409	 .dev_id = 0x1360,
410	 .name = "PXI-6602",
411	 .n_chips = 2,
412	 },
413	{
414	 .dev_id = 0x2cc0,
415	 .name = "PXI-6608",
416	 .n_chips = 2,
417	 },
418};
419
420#define NI_660X_MAX_NUM_CHIPS 2
421#define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip)
422
423static DEFINE_PCI_DEVICE_TABLE(ni_660x_pci_table) = {
424	{
425	PCI_VENDOR_ID_NATINST, 0x2c60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
426	PCI_VENDOR_ID_NATINST, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
427	PCI_VENDOR_ID_NATINST, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
428	PCI_VENDOR_ID_NATINST, 0x2cc0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
429	0}
430};
431
432MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
433
434struct ni_660x_private {
435	struct mite_struct *mite;
436	struct ni_gpct_device *counter_dev;
437	uint64_t pfi_direction_bits;
438	struct mite_dma_descriptor_ring
439	*mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip];
440	spinlock_t mite_channel_lock;
441	/* interrupt_lock prevents races between interrupt and comedi_poll */
442	spinlock_t interrupt_lock;
443	unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS];
444	spinlock_t soft_reg_copy_lock;
445	unsigned short pfi_output_selects[NUM_PFI_CHANNELS];
446};
447
448static inline struct ni_660x_private *private(struct comedi_device *dev)
449{
450	return dev->private;
451}
452
453/* initialized in ni_660x_find_device() */
454static inline const struct ni_660x_board *board(struct comedi_device *dev)
455{
456	return dev->board_ptr;
457}
458
459#define n_ni_660x_boards ARRAY_SIZE(ni_660x_boards)
460
461static int ni_660x_attach(struct comedi_device *dev,
462			  struct comedi_devconfig *it);
463static int ni_660x_detach(struct comedi_device *dev);
464static void init_tio_chip(struct comedi_device *dev, int chipset);
465static void ni_660x_select_pfi_output(struct comedi_device *dev,
466				      unsigned pfi_channel,
467				      unsigned output_select);
468
469static struct comedi_driver driver_ni_660x = {
470	.driver_name = "ni_660x",
471	.module = THIS_MODULE,
472	.attach = ni_660x_attach,
473	.detach = ni_660x_detach,
474};
475
476COMEDI_PCI_INITCLEANUP(driver_ni_660x, ni_660x_pci_table);
477
478static int ni_660x_find_device(struct comedi_device *dev, int bus, int slot);
479static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
480				   unsigned source);
481
482/* Possible instructions for a GPCT */
483static int ni_660x_GPCT_rinsn(struct comedi_device *dev,
484			      struct comedi_subdevice *s,
485			      struct comedi_insn *insn, unsigned int *data);
486static int ni_660x_GPCT_insn_config(struct comedi_device *dev,
487				    struct comedi_subdevice *s,
488				    struct comedi_insn *insn,
489				    unsigned int *data);
490static int ni_660x_GPCT_winsn(struct comedi_device *dev,
491			      struct comedi_subdevice *s,
492			      struct comedi_insn *insn, unsigned int *data);
493
494/* Possible instructions for Digital IO */
495static int ni_660x_dio_insn_config(struct comedi_device *dev,
496				   struct comedi_subdevice *s,
497				   struct comedi_insn *insn,
498				   unsigned int *data);
499static int ni_660x_dio_insn_bits(struct comedi_device *dev,
500				 struct comedi_subdevice *s,
501				 struct comedi_insn *insn, unsigned int *data);
502
503static inline unsigned ni_660x_num_counters(struct comedi_device *dev)
504{
505	return board(dev)->n_chips * counters_per_chip;
506}
507
508static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg)
509{
510	enum NI_660x_Register ni_660x_register;
511	switch (reg) {
512	case NITIO_G0_Autoincrement_Reg:
513		ni_660x_register = G0AutoincrementRegister;
514		break;
515	case NITIO_G1_Autoincrement_Reg:
516		ni_660x_register = G1AutoincrementRegister;
517		break;
518	case NITIO_G2_Autoincrement_Reg:
519		ni_660x_register = G2AutoincrementRegister;
520		break;
521	case NITIO_G3_Autoincrement_Reg:
522		ni_660x_register = G3AutoincrementRegister;
523		break;
524	case NITIO_G0_Command_Reg:
525		ni_660x_register = G0CommandRegister;
526		break;
527	case NITIO_G1_Command_Reg:
528		ni_660x_register = G1CommandRegister;
529		break;
530	case NITIO_G2_Command_Reg:
531		ni_660x_register = G2CommandRegister;
532		break;
533	case NITIO_G3_Command_Reg:
534		ni_660x_register = G3CommandRegister;
535		break;
536	case NITIO_G0_HW_Save_Reg:
537		ni_660x_register = G0HWSaveRegister;
538		break;
539	case NITIO_G1_HW_Save_Reg:
540		ni_660x_register = G1HWSaveRegister;
541		break;
542	case NITIO_G2_HW_Save_Reg:
543		ni_660x_register = G2HWSaveRegister;
544		break;
545	case NITIO_G3_HW_Save_Reg:
546		ni_660x_register = G3HWSaveRegister;
547		break;
548	case NITIO_G0_SW_Save_Reg:
549		ni_660x_register = G0SWSaveRegister;
550		break;
551	case NITIO_G1_SW_Save_Reg:
552		ni_660x_register = G1SWSaveRegister;
553		break;
554	case NITIO_G2_SW_Save_Reg:
555		ni_660x_register = G2SWSaveRegister;
556		break;
557	case NITIO_G3_SW_Save_Reg:
558		ni_660x_register = G3SWSaveRegister;
559		break;
560	case NITIO_G0_Mode_Reg:
561		ni_660x_register = G0ModeRegister;
562		break;
563	case NITIO_G1_Mode_Reg:
564		ni_660x_register = G1ModeRegister;
565		break;
566	case NITIO_G2_Mode_Reg:
567		ni_660x_register = G2ModeRegister;
568		break;
569	case NITIO_G3_Mode_Reg:
570		ni_660x_register = G3ModeRegister;
571		break;
572	case NITIO_G0_LoadA_Reg:
573		ni_660x_register = G0LoadARegister;
574		break;
575	case NITIO_G1_LoadA_Reg:
576		ni_660x_register = G1LoadARegister;
577		break;
578	case NITIO_G2_LoadA_Reg:
579		ni_660x_register = G2LoadARegister;
580		break;
581	case NITIO_G3_LoadA_Reg:
582		ni_660x_register = G3LoadARegister;
583		break;
584	case NITIO_G0_LoadB_Reg:
585		ni_660x_register = G0LoadBRegister;
586		break;
587	case NITIO_G1_LoadB_Reg:
588		ni_660x_register = G1LoadBRegister;
589		break;
590	case NITIO_G2_LoadB_Reg:
591		ni_660x_register = G2LoadBRegister;
592		break;
593	case NITIO_G3_LoadB_Reg:
594		ni_660x_register = G3LoadBRegister;
595		break;
596	case NITIO_G0_Input_Select_Reg:
597		ni_660x_register = G0InputSelectRegister;
598		break;
599	case NITIO_G1_Input_Select_Reg:
600		ni_660x_register = G1InputSelectRegister;
601		break;
602	case NITIO_G2_Input_Select_Reg:
603		ni_660x_register = G2InputSelectRegister;
604		break;
605	case NITIO_G3_Input_Select_Reg:
606		ni_660x_register = G3InputSelectRegister;
607		break;
608	case NITIO_G01_Status_Reg:
609		ni_660x_register = G01StatusRegister;
610		break;
611	case NITIO_G23_Status_Reg:
612		ni_660x_register = G23StatusRegister;
613		break;
614	case NITIO_G01_Joint_Reset_Reg:
615		ni_660x_register = G01JointResetRegister;
616		break;
617	case NITIO_G23_Joint_Reset_Reg:
618		ni_660x_register = G23JointResetRegister;
619		break;
620	case NITIO_G01_Joint_Status1_Reg:
621		ni_660x_register = G01JointStatus1Register;
622		break;
623	case NITIO_G23_Joint_Status1_Reg:
624		ni_660x_register = G23JointStatus1Register;
625		break;
626	case NITIO_G01_Joint_Status2_Reg:
627		ni_660x_register = G01JointStatus2Register;
628		break;
629	case NITIO_G23_Joint_Status2_Reg:
630		ni_660x_register = G23JointStatus2Register;
631		break;
632	case NITIO_G0_Counting_Mode_Reg:
633		ni_660x_register = G0CountingModeRegister;
634		break;
635	case NITIO_G1_Counting_Mode_Reg:
636		ni_660x_register = G1CountingModeRegister;
637		break;
638	case NITIO_G2_Counting_Mode_Reg:
639		ni_660x_register = G2CountingModeRegister;
640		break;
641	case NITIO_G3_Counting_Mode_Reg:
642		ni_660x_register = G3CountingModeRegister;
643		break;
644	case NITIO_G0_Second_Gate_Reg:
645		ni_660x_register = G0SecondGateRegister;
646		break;
647	case NITIO_G1_Second_Gate_Reg:
648		ni_660x_register = G1SecondGateRegister;
649		break;
650	case NITIO_G2_Second_Gate_Reg:
651		ni_660x_register = G2SecondGateRegister;
652		break;
653	case NITIO_G3_Second_Gate_Reg:
654		ni_660x_register = G3SecondGateRegister;
655		break;
656	case NITIO_G0_DMA_Config_Reg:
657		ni_660x_register = G0DMAConfigRegister;
658		break;
659	case NITIO_G0_DMA_Status_Reg:
660		ni_660x_register = G0DMAStatusRegister;
661		break;
662	case NITIO_G1_DMA_Config_Reg:
663		ni_660x_register = G1DMAConfigRegister;
664		break;
665	case NITIO_G1_DMA_Status_Reg:
666		ni_660x_register = G1DMAStatusRegister;
667		break;
668	case NITIO_G2_DMA_Config_Reg:
669		ni_660x_register = G2DMAConfigRegister;
670		break;
671	case NITIO_G2_DMA_Status_Reg:
672		ni_660x_register = G2DMAStatusRegister;
673		break;
674	case NITIO_G3_DMA_Config_Reg:
675		ni_660x_register = G3DMAConfigRegister;
676		break;
677	case NITIO_G3_DMA_Status_Reg:
678		ni_660x_register = G3DMAStatusRegister;
679		break;
680	case NITIO_G0_Interrupt_Acknowledge_Reg:
681		ni_660x_register = G0InterruptAcknowledge;
682		break;
683	case NITIO_G1_Interrupt_Acknowledge_Reg:
684		ni_660x_register = G1InterruptAcknowledge;
685		break;
686	case NITIO_G2_Interrupt_Acknowledge_Reg:
687		ni_660x_register = G2InterruptAcknowledge;
688		break;
689	case NITIO_G3_Interrupt_Acknowledge_Reg:
690		ni_660x_register = G3InterruptAcknowledge;
691		break;
692	case NITIO_G0_Status_Reg:
693		ni_660x_register = G0StatusRegister;
694		break;
695	case NITIO_G1_Status_Reg:
696		ni_660x_register = G1StatusRegister;
697		break;
698	case NITIO_G2_Status_Reg:
699		ni_660x_register = G2StatusRegister;
700		break;
701	case NITIO_G3_Status_Reg:
702		ni_660x_register = G3StatusRegister;
703		break;
704	case NITIO_G0_Interrupt_Enable_Reg:
705		ni_660x_register = G0InterruptEnable;
706		break;
707	case NITIO_G1_Interrupt_Enable_Reg:
708		ni_660x_register = G1InterruptEnable;
709		break;
710	case NITIO_G2_Interrupt_Enable_Reg:
711		ni_660x_register = G2InterruptEnable;
712		break;
713	case NITIO_G3_Interrupt_Enable_Reg:
714		ni_660x_register = G3InterruptEnable;
715		break;
716	default:
717		printk(KERN_WARNING "%s: unhandled register 0x%x in switch.\n",
718		       __func__, reg);
719		BUG();
720		return 0;
721		break;
722	}
723	return ni_660x_register;
724}
725
726static inline void ni_660x_write_register(struct comedi_device *dev,
727					  unsigned chip_index, unsigned bits,
728					  enum NI_660x_Register reg)
729{
730	void *const write_address =
731	    private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
732	    registerData[reg].offset;
733
734	switch (registerData[reg].size) {
735	case DATA_2B:
736		writew(bits, write_address);
737		break;
738	case DATA_4B:
739		writel(bits, write_address);
740		break;
741	default:
742		printk(KERN_WARNING "%s: %s: bug! unhandled case (reg=0x%x) in switch.\n",
743		       __FILE__, __func__, reg);
744		BUG();
745		break;
746	}
747}
748
749static inline unsigned ni_660x_read_register(struct comedi_device *dev,
750					     unsigned chip_index,
751					     enum NI_660x_Register reg)
752{
753	void *const read_address =
754	    private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
755	    registerData[reg].offset;
756
757	switch (registerData[reg].size) {
758	case DATA_2B:
759		return readw(read_address);
760		break;
761	case DATA_4B:
762		return readl(read_address);
763		break;
764	default:
765		printk(KERN_WARNING "%s: %s: bug! unhandled case (reg=0x%x) in switch.\n",
766		       __FILE__, __func__, reg);
767		BUG();
768		break;
769	}
770	return 0;
771}
772
773static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
774				   enum ni_gpct_register reg)
775{
776	struct comedi_device *dev = counter->counter_dev->dev;
777	enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
778	ni_660x_write_register(dev, counter->chip_index, bits,
779			       ni_660x_register);
780}
781
782static unsigned ni_gpct_read_register(struct ni_gpct *counter,
783				      enum ni_gpct_register reg)
784{
785	struct comedi_device *dev = counter->counter_dev->dev;
786	enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
787	return ni_660x_read_register(dev, counter->chip_index,
788				     ni_660x_register);
789}
790
791static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private
792							 *priv,
793							 struct ni_gpct
794							 *counter)
795{
796	return priv->mite_rings[counter->chip_index][counter->counter_index];
797}
798
799static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
800					   unsigned mite_channel,
801					   struct ni_gpct *counter)
802{
803	unsigned long flags;
804	spin_lock_irqsave(&private(dev)->soft_reg_copy_lock, flags);
805	private(dev)->dma_configuration_soft_copies[counter->chip_index] &=
806	    ~dma_select_mask(mite_channel);
807	private(dev)->dma_configuration_soft_copies[counter->chip_index] |=
808	    dma_select_bits(mite_channel,
809			    dma_selection_counter(counter->counter_index));
810	ni_660x_write_register(dev, counter->chip_index,
811			       private(dev)->
812			       dma_configuration_soft_copies
813			       [counter->chip_index] |
814			       dma_reset_bit(mite_channel), DMAConfigRegister);
815	mmiowb();
816	spin_unlock_irqrestore(&private(dev)->soft_reg_copy_lock, flags);
817}
818
819static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
820					     unsigned mite_channel,
821					     struct ni_gpct *counter)
822{
823	unsigned long flags;
824	spin_lock_irqsave(&private(dev)->soft_reg_copy_lock, flags);
825	private(dev)->dma_configuration_soft_copies[counter->chip_index] &=
826	    ~dma_select_mask(mite_channel);
827	private(dev)->dma_configuration_soft_copies[counter->chip_index] |=
828	    dma_select_bits(mite_channel, dma_selection_none);
829	ni_660x_write_register(dev, counter->chip_index,
830			       private(dev)->
831			       dma_configuration_soft_copies
832			       [counter->chip_index], DMAConfigRegister);
833	mmiowb();
834	spin_unlock_irqrestore(&private(dev)->soft_reg_copy_lock, flags);
835}
836
837static int ni_660x_request_mite_channel(struct comedi_device *dev,
838					struct ni_gpct *counter,
839					enum comedi_io_direction direction)
840{
841	unsigned long flags;
842	struct mite_channel *mite_chan;
843
844	spin_lock_irqsave(&private(dev)->mite_channel_lock, flags);
845	BUG_ON(counter->mite_chan);
846	mite_chan =
847	    mite_request_channel(private(dev)->mite, mite_ring(private(dev),
848							       counter));
849	if (mite_chan == NULL) {
850		spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags);
851		comedi_error(dev,
852			     "failed to reserve mite dma channel for counter.");
853		return -EBUSY;
854	}
855	mite_chan->dir = direction;
856	ni_tio_set_mite_channel(counter, mite_chan);
857	ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
858	spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags);
859	return 0;
860}
861
862void ni_660x_release_mite_channel(struct comedi_device *dev,
863				  struct ni_gpct *counter)
864{
865	unsigned long flags;
866
867	spin_lock_irqsave(&private(dev)->mite_channel_lock, flags);
868	if (counter->mite_chan) {
869		struct mite_channel *mite_chan = counter->mite_chan;
870
871		ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
872		ni_tio_set_mite_channel(counter, NULL);
873		mite_release_channel(mite_chan);
874	}
875	spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags);
876}
877
878static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
879{
880	int retval;
881
882	struct ni_gpct *counter = subdev_to_counter(s);
883/* const struct comedi_cmd *cmd = &s->async->cmd; */
884
885	retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
886	if (retval) {
887		comedi_error(dev,
888			     "no dma channel available for use by counter");
889		return retval;
890	}
891	ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
892	retval = ni_tio_cmd(counter, s->async);
893
894	return retval;
895}
896
897static int ni_660x_cmdtest(struct comedi_device *dev,
898			   struct comedi_subdevice *s, struct comedi_cmd *cmd)
899{
900	struct ni_gpct *counter = subdev_to_counter(s);
901
902	return ni_tio_cmdtest(counter, cmd);
903}
904
905static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
906{
907	struct ni_gpct *counter = subdev_to_counter(s);
908	int retval;
909
910	retval = ni_tio_cancel(counter);
911	ni_660x_release_mite_channel(dev, counter);
912	return retval;
913}
914
915static void set_tio_counterswap(struct comedi_device *dev, int chipset)
916{
917	/* See P. 3.5 of the Register-Level Programming manual.  The
918	   CounterSwap bit has to be set on the second chip, otherwise
919	   it will try to use the same pins as the first chip.
920	 */
921	if (chipset)
922		ni_660x_write_register(dev, chipset, CounterSwap,
923				       ClockConfigRegister);
924	else
925		ni_660x_write_register(dev, chipset, 0, ClockConfigRegister);
926}
927
928static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
929					  struct comedi_subdevice *s)
930{
931	ni_tio_handle_interrupt(subdev_to_counter(s), s);
932	if (s->async->events) {
933		if (s->async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
934					COMEDI_CB_OVERFLOW)) {
935			ni_660x_cancel(dev, s);
936		}
937		comedi_event(dev, s);
938	}
939}
940
941static irqreturn_t ni_660x_interrupt(int irq, void *d)
942{
943	struct comedi_device *dev = d;
944	struct comedi_subdevice *s;
945	unsigned i;
946	unsigned long flags;
947
948	if (dev->attached == 0)
949		return IRQ_NONE;
950	/* lock to avoid race with comedi_poll */
951	spin_lock_irqsave(&private(dev)->interrupt_lock, flags);
952	smp_mb();
953	for (i = 0; i < ni_660x_num_counters(dev); ++i) {
954		s = dev->subdevices + NI_660X_GPCT_SUBDEV(i);
955		ni_660x_handle_gpct_interrupt(dev, s);
956	}
957	spin_unlock_irqrestore(&private(dev)->interrupt_lock, flags);
958	return IRQ_HANDLED;
959}
960
961static int ni_660x_input_poll(struct comedi_device *dev,
962			      struct comedi_subdevice *s)
963{
964	unsigned long flags;
965	/* lock to avoid race with comedi_poll */
966	spin_lock_irqsave(&private(dev)->interrupt_lock, flags);
967	mite_sync_input_dma(subdev_to_counter(s)->mite_chan, s->async);
968	spin_unlock_irqrestore(&private(dev)->interrupt_lock, flags);
969	return comedi_buf_read_n_available(s->async);
970}
971
972static int ni_660x_buf_change(struct comedi_device *dev,
973			      struct comedi_subdevice *s,
974			      unsigned long new_size)
975{
976	int ret;
977
978	ret = mite_buf_change(mite_ring(private(dev), subdev_to_counter(s)),
979			      s->async);
980	if (ret < 0)
981		return ret;
982
983	return 0;
984}
985
986static int ni_660x_allocate_private(struct comedi_device *dev)
987{
988	int retval;
989	unsigned i;
990
991	retval = alloc_private(dev, sizeof(struct ni_660x_private));
992	if (retval < 0)
993		return retval;
994
995	spin_lock_init(&private(dev)->mite_channel_lock);
996	spin_lock_init(&private(dev)->interrupt_lock);
997	spin_lock_init(&private(dev)->soft_reg_copy_lock);
998	for (i = 0; i < NUM_PFI_CHANNELS; ++i)
999		private(dev)->pfi_output_selects[i] = pfi_output_select_counter;
1000
1001	return 0;
1002}
1003
1004static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
1005{
1006	unsigned i;
1007	unsigned j;
1008
1009	for (i = 0; i < board(dev)->n_chips; ++i) {
1010		for (j = 0; j < counters_per_chip; ++j) {
1011			private(dev)->mite_rings[i][j] =
1012			    mite_alloc_ring(private(dev)->mite);
1013			if (private(dev)->mite_rings[i][j] == NULL)
1014				return -ENOMEM;
1015		}
1016	}
1017	return 0;
1018}
1019
1020static void ni_660x_free_mite_rings(struct comedi_device *dev)
1021{
1022	unsigned i;
1023	unsigned j;
1024
1025	for (i = 0; i < board(dev)->n_chips; ++i) {
1026		for (j = 0; j < counters_per_chip; ++j)
1027			mite_free_ring(private(dev)->mite_rings[i][j]);
1028	}
1029}
1030
1031static int ni_660x_attach(struct comedi_device *dev,
1032			  struct comedi_devconfig *it)
1033{
1034	struct comedi_subdevice *s;
1035	int ret;
1036	unsigned i;
1037	unsigned global_interrupt_config_bits;
1038
1039	printk(KERN_INFO "comedi%d: ni_660x: ", dev->minor);
1040
1041	ret = ni_660x_allocate_private(dev);
1042	if (ret < 0)
1043		return ret;
1044	ret = ni_660x_find_device(dev, it->options[0], it->options[1]);
1045	if (ret < 0)
1046		return ret;
1047
1048	dev->board_name = board(dev)->name;
1049
1050	ret = mite_setup2(private(dev)->mite, 1);
1051	if (ret < 0) {
1052		printk(KERN_WARNING "error setting up mite\n");
1053		return ret;
1054	}
1055	comedi_set_hw_dev(dev, &private(dev)->mite->pcidev->dev);
1056	ret = ni_660x_alloc_mite_rings(dev);
1057	if (ret < 0)
1058		return ret;
1059
1060	printk(KERN_INFO " %s ", dev->board_name);
1061
1062	dev->n_subdevices = 2 + NI_660X_MAX_NUM_COUNTERS;
1063
1064	if (alloc_subdevices(dev, dev->n_subdevices) < 0)
1065		return -ENOMEM;
1066
1067	s = dev->subdevices + 0;
1068	/* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
1069	s->type = COMEDI_SUBD_UNUSED;
1070
1071	s = dev->subdevices + NI_660X_DIO_SUBDEV;
1072	/* DIGITAL I/O SUBDEVICE */
1073	s->type = COMEDI_SUBD_DIO;
1074	s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1075	s->n_chan = NUM_PFI_CHANNELS;
1076	s->maxdata = 1;
1077	s->range_table = &range_digital;
1078	s->insn_bits = ni_660x_dio_insn_bits;
1079	s->insn_config = ni_660x_dio_insn_config;
1080	s->io_bits = 0;		/* all bits default to input */
1081	/*  we use the ioconfig registers to control dio direction, so zero
1082	output enables in stc dio control reg */
1083	ni_660x_write_register(dev, 0, 0, STCDIOControl);
1084
1085	private(dev)->counter_dev
1086		= ni_gpct_device_construct(dev,
1087					   &ni_gpct_write_register,
1088					   &ni_gpct_read_register,
1089					   ni_gpct_variant_660x,
1090					   ni_660x_num_counters
1091					   (dev));
1092	if (private(dev)->counter_dev == NULL)
1093		return -ENOMEM;
1094	for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) {
1095		s = dev->subdevices + NI_660X_GPCT_SUBDEV(i);
1096		if (i < ni_660x_num_counters(dev)) {
1097			s->type = COMEDI_SUBD_COUNTER;
1098			s->subdev_flags =
1099			    SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
1100			    SDF_CMD_READ /* | SDF_CMD_WRITE */ ;
1101			s->n_chan = 3;
1102			s->maxdata = 0xffffffff;
1103			s->insn_read = ni_660x_GPCT_rinsn;
1104			s->insn_write = ni_660x_GPCT_winsn;
1105			s->insn_config = ni_660x_GPCT_insn_config;
1106			s->do_cmd = &ni_660x_cmd;
1107			s->len_chanlist = 1;
1108			s->do_cmdtest = &ni_660x_cmdtest;
1109			s->cancel = &ni_660x_cancel;
1110			s->poll = &ni_660x_input_poll;
1111			s->async_dma_dir = DMA_BIDIRECTIONAL;
1112			s->buf_change = &ni_660x_buf_change;
1113			s->private = &private(dev)->counter_dev->counters[i];
1114
1115			private(dev)->counter_dev->counters[i].chip_index =
1116			    i / counters_per_chip;
1117			private(dev)->counter_dev->counters[i].counter_index =
1118			    i % counters_per_chip;
1119		} else {
1120			s->type = COMEDI_SUBD_UNUSED;
1121		}
1122	}
1123	for (i = 0; i < board(dev)->n_chips; ++i)
1124		init_tio_chip(dev, i);
1125
1126	for (i = 0; i < ni_660x_num_counters(dev); ++i)
1127		ni_tio_init_counter(&private(dev)->counter_dev->counters[i]);
1128
1129	for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
1130		if (i < min_counter_pfi_chan)
1131			ni_660x_set_pfi_routing(dev, i, pfi_output_select_do);
1132		else
1133			ni_660x_set_pfi_routing(dev, i,
1134						pfi_output_select_counter);
1135		ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z);
1136	}
1137	/* to be safe, set counterswap bits on tio chips after all the counter
1138	   outputs have been set to high impedance mode */
1139	for (i = 0; i < board(dev)->n_chips; ++i)
1140		set_tio_counterswap(dev, i);
1141
1142	ret = request_irq(mite_irq(private(dev)->mite), ni_660x_interrupt,
1143			  IRQF_SHARED, "ni_660x", dev);
1144	if (ret < 0) {
1145		printk(KERN_WARNING " irq not available\n");
1146		return ret;
1147	}
1148	dev->irq = mite_irq(private(dev)->mite);
1149	global_interrupt_config_bits = Global_Int_Enable_Bit;
1150	if (board(dev)->n_chips > 1)
1151		global_interrupt_config_bits |= Cascade_Int_Enable_Bit;
1152	ni_660x_write_register(dev, 0, global_interrupt_config_bits,
1153			       GlobalInterruptConfigRegister);
1154	printk(KERN_INFO "attached\n");
1155	return 0;
1156}
1157
1158static int ni_660x_detach(struct comedi_device *dev)
1159{
1160	printk(KERN_INFO "comedi%d: ni_660x: remove\n", dev->minor);
1161
1162	/* Free irq */
1163	if (dev->irq)
1164		free_irq(dev->irq, dev);
1165
1166	if (dev->private) {
1167		if (private(dev)->counter_dev)
1168			ni_gpct_device_destroy(private(dev)->counter_dev);
1169		if (private(dev)->mite) {
1170			ni_660x_free_mite_rings(dev);
1171			mite_unsetup(private(dev)->mite);
1172		}
1173	}
1174	return 0;
1175}
1176
1177static int
1178ni_660x_GPCT_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1179		   struct comedi_insn *insn, unsigned int *data)
1180{
1181	return ni_tio_rinsn(subdev_to_counter(s), insn, data);
1182}
1183
1184static void init_tio_chip(struct comedi_device *dev, int chipset)
1185{
1186	unsigned i;
1187
1188	/*  init dma configuration register */
1189	private(dev)->dma_configuration_soft_copies[chipset] = 0;
1190	for (i = 0; i < MAX_DMA_CHANNEL; ++i) {
1191		private(dev)->dma_configuration_soft_copies[chipset] |=
1192		    dma_select_bits(i, dma_selection_none) & dma_select_mask(i);
1193	}
1194	ni_660x_write_register(dev, chipset,
1195			       private(dev)->
1196			       dma_configuration_soft_copies[chipset],
1197			       DMAConfigRegister);
1198	for (i = 0; i < NUM_PFI_CHANNELS; ++i)
1199		ni_660x_write_register(dev, chipset, 0, IOConfigReg(i));
1200}
1201
1202static int
1203ni_660x_GPCT_insn_config(struct comedi_device *dev, struct comedi_subdevice *s,
1204			 struct comedi_insn *insn, unsigned int *data)
1205{
1206	return ni_tio_insn_config(subdev_to_counter(s), insn, data);
1207}
1208
1209static int ni_660x_GPCT_winsn(struct comedi_device *dev,
1210			      struct comedi_subdevice *s,
1211			      struct comedi_insn *insn, unsigned int *data)
1212{
1213	return ni_tio_winsn(subdev_to_counter(s), insn, data);
1214}
1215
1216static int ni_660x_find_device(struct comedi_device *dev, int bus, int slot)
1217{
1218	struct mite_struct *mite;
1219	int i;
1220
1221	for (mite = mite_devices; mite; mite = mite->next) {
1222		if (mite->used)
1223			continue;
1224		if (bus || slot) {
1225			if (bus != mite->pcidev->bus->number ||
1226			    slot != PCI_SLOT(mite->pcidev->devfn))
1227				continue;
1228		}
1229
1230		for (i = 0; i < n_ni_660x_boards; i++) {
1231			if (mite_device_id(mite) == ni_660x_boards[i].dev_id) {
1232				dev->board_ptr = ni_660x_boards + i;
1233				private(dev)->mite = mite;
1234				return 0;
1235			}
1236		}
1237	}
1238	printk(KERN_WARNING "no device found\n");
1239	mite_list_devices();
1240	return -EIO;
1241}
1242
1243static int ni_660x_dio_insn_bits(struct comedi_device *dev,
1244				 struct comedi_subdevice *s,
1245				 struct comedi_insn *insn, unsigned int *data)
1246{
1247	unsigned base_bitfield_channel = CR_CHAN(insn->chanspec);
1248
1249	/*  Check if we have to write some bits */
1250	if (data[0]) {
1251		s->state &= ~(data[0] << base_bitfield_channel);
1252		s->state |= (data[0] & data[1]) << base_bitfield_channel;
1253		/* Write out the new digital output lines */
1254		ni_660x_write_register(dev, 0, s->state, DIO32Output);
1255	}
1256	/* on return, data[1] contains the value of the digital
1257	 * input and output lines. */
1258	data[1] =
1259	    (ni_660x_read_register(dev, 0,
1260				   DIO32Input) >> base_bitfield_channel);
1261	return 2;
1262}
1263
1264static void ni_660x_select_pfi_output(struct comedi_device *dev,
1265				      unsigned pfi_channel,
1266				      unsigned output_select)
1267{
1268	static const unsigned counter_4_7_first_pfi = 8;
1269	static const unsigned counter_4_7_last_pfi = 23;
1270	unsigned active_chipset = 0;
1271	unsigned idle_chipset = 0;
1272	unsigned active_bits;
1273	unsigned idle_bits;
1274
1275	if (board(dev)->n_chips > 1) {
1276		if (output_select == pfi_output_select_counter &&
1277		    pfi_channel >= counter_4_7_first_pfi &&
1278		    pfi_channel <= counter_4_7_last_pfi) {
1279			active_chipset = 1;
1280			idle_chipset = 0;
1281		} else {
1282			active_chipset = 0;
1283			idle_chipset = 1;
1284		}
1285	}
1286
1287	if (idle_chipset != active_chipset) {
1288		idle_bits =
1289		    ni_660x_read_register(dev, idle_chipset,
1290					  IOConfigReg(pfi_channel));
1291		idle_bits &= ~pfi_output_select_mask(pfi_channel);
1292		idle_bits |=
1293		    pfi_output_select_bits(pfi_channel,
1294					   pfi_output_select_high_Z);
1295		ni_660x_write_register(dev, idle_chipset, idle_bits,
1296				       IOConfigReg(pfi_channel));
1297	}
1298
1299	active_bits =
1300	    ni_660x_read_register(dev, active_chipset,
1301				  IOConfigReg(pfi_channel));
1302	active_bits &= ~pfi_output_select_mask(pfi_channel);
1303	active_bits |= pfi_output_select_bits(pfi_channel, output_select);
1304	ni_660x_write_register(dev, active_chipset, active_bits,
1305			       IOConfigReg(pfi_channel));
1306}
1307
1308static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
1309				   unsigned source)
1310{
1311	if (source > num_pfi_output_selects)
1312		return -EINVAL;
1313	if (source == pfi_output_select_high_Z)
1314		return -EINVAL;
1315	if (chan < min_counter_pfi_chan) {
1316		if (source == pfi_output_select_counter)
1317			return -EINVAL;
1318	} else if (chan > max_dio_pfi_chan) {
1319		if (source == pfi_output_select_do)
1320			return -EINVAL;
1321	}
1322	BUG_ON(chan >= NUM_PFI_CHANNELS);
1323
1324	private(dev)->pfi_output_selects[chan] = source;
1325	if (private(dev)->pfi_direction_bits & (((uint64_t) 1) << chan))
1326		ni_660x_select_pfi_output(dev, chan,
1327					  private(dev)->
1328					  pfi_output_selects[chan]);
1329	return 0;
1330}
1331
1332static unsigned ni_660x_get_pfi_routing(struct comedi_device *dev,
1333					unsigned chan)
1334{
1335	BUG_ON(chan >= NUM_PFI_CHANNELS);
1336	return private(dev)->pfi_output_selects[chan];
1337}
1338
1339static void ni660x_config_filter(struct comedi_device *dev,
1340				 unsigned pfi_channel,
1341				 enum ni_gpct_filter_select filter)
1342{
1343	unsigned bits = ni_660x_read_register(dev, 0, IOConfigReg(pfi_channel));
1344	bits &= ~pfi_input_select_mask(pfi_channel);
1345	bits |= pfi_input_select_bits(pfi_channel, filter);
1346	ni_660x_write_register(dev, 0, bits, IOConfigReg(pfi_channel));
1347}
1348
1349static int ni_660x_dio_insn_config(struct comedi_device *dev,
1350				   struct comedi_subdevice *s,
1351				   struct comedi_insn *insn, unsigned int *data)
1352{
1353	int chan = CR_CHAN(insn->chanspec);
1354
1355	/* The input or output configuration of each digital line is
1356	 * configured by a special insn_config instruction.  chanspec
1357	 * contains the channel to be changed, and data[0] contains the
1358	 * value COMEDI_INPUT or COMEDI_OUTPUT. */
1359
1360	switch (data[0]) {
1361	case INSN_CONFIG_DIO_OUTPUT:
1362		private(dev)->pfi_direction_bits |= ((uint64_t) 1) << chan;
1363		ni_660x_select_pfi_output(dev, chan,
1364					  private(dev)->
1365					  pfi_output_selects[chan]);
1366		break;
1367	case INSN_CONFIG_DIO_INPUT:
1368		private(dev)->pfi_direction_bits &= ~(((uint64_t) 1) << chan);
1369		ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z);
1370		break;
1371	case INSN_CONFIG_DIO_QUERY:
1372		data[1] =
1373		    (private(dev)->pfi_direction_bits &
1374		     (((uint64_t) 1) << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1375		return 0;
1376	case INSN_CONFIG_SET_ROUTING:
1377		return ni_660x_set_pfi_routing(dev, chan, data[1]);
1378		break;
1379	case INSN_CONFIG_GET_ROUTING:
1380		data[1] = ni_660x_get_pfi_routing(dev, chan);
1381		break;
1382	case INSN_CONFIG_FILTER:
1383		ni660x_config_filter(dev, chan, data[1]);
1384		break;
1385	default:
1386		return -EINVAL;
1387		break;
1388	};
1389	return 0;
1390}
1391