ni_atmio16d.c revision 68c3dbff9fc9f25872408d0e95980d41733d48d0
1/* 2 comedi/drivers/ni_atmio16d.c 3 Hardware driver for National Instruments AT-MIO16D board 4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20 */ 21/* 22Driver: ni_atmio16d 23Description: National Instruments AT-MIO-16D 24Author: Chris R. Baugher <baugher@enteract.com> 25Status: unknown 26Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d) 27*/ 28/* 29 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who 30 * wrote the driver for Advantec's pcl812 boards. I used the interrupt 31 * handling code from his driver as an example for this one. 32 * 33 * Chris Baugher 34 * 5/1/2000 35 * 36 */ 37 38#include "../comedidev.h" 39 40#include <linux/ioport.h> 41 42#include "8255.h" 43 44/* Configuration and Status Registers */ 45#define COM_REG_1 0x00 /* wo 16 */ 46#define STAT_REG 0x00 /* ro 16 */ 47#define COM_REG_2 0x02 /* wo 16 */ 48/* Event Strobe Registers */ 49#define START_CONVERT_REG 0x08 /* wo 16 */ 50#define START_DAQ_REG 0x0A /* wo 16 */ 51#define AD_CLEAR_REG 0x0C /* wo 16 */ 52#define EXT_STROBE_REG 0x0E /* wo 16 */ 53/* Analog Output Registers */ 54#define DAC0_REG 0x10 /* wo 16 */ 55#define DAC1_REG 0x12 /* wo 16 */ 56#define INT2CLR_REG 0x14 /* wo 16 */ 57/* Analog Input Registers */ 58#define MUX_CNTR_REG 0x04 /* wo 16 */ 59#define MUX_GAIN_REG 0x06 /* wo 16 */ 60#define AD_FIFO_REG 0x16 /* ro 16 */ 61#define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */ 62/* AM9513A Counter/Timer Registers */ 63#define AM9513A_DATA_REG 0x18 /* rw 16 */ 64#define AM9513A_COM_REG 0x1A /* wo 16 */ 65#define AM9513A_STAT_REG 0x1A /* ro 16 */ 66/* MIO-16 Digital I/O Registers */ 67#define MIO_16_DIG_IN_REG 0x1C /* ro 16 */ 68#define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */ 69/* RTSI Switch Registers */ 70#define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */ 71#define RTSI_SW_STROBE_REG 0x1F /* wo 8 */ 72/* DIO-24 Registers */ 73#define DIO_24_PORTA_REG 0x00 /* rw 8 */ 74#define DIO_24_PORTB_REG 0x01 /* rw 8 */ 75#define DIO_24_PORTC_REG 0x02 /* rw 8 */ 76#define DIO_24_CNFG_REG 0x03 /* wo 8 */ 77 78/* Command Register bits */ 79#define COMREG1_2SCADC 0x0001 80#define COMREG1_1632CNT 0x0002 81#define COMREG1_SCANEN 0x0008 82#define COMREG1_DAQEN 0x0010 83#define COMREG1_DMAEN 0x0020 84#define COMREG1_CONVINTEN 0x0080 85#define COMREG2_SCN2 0x0010 86#define COMREG2_INTEN 0x0080 87#define COMREG2_DOUTEN0 0x0100 88#define COMREG2_DOUTEN1 0x0200 89/* Status Register bits */ 90#define STAT_AD_OVERRUN 0x0100 91#define STAT_AD_OVERFLOW 0x0200 92#define STAT_AD_DAQPROG 0x0800 93#define STAT_AD_CONVAVAIL 0x2000 94#define STAT_AD_DAQSTOPINT 0x4000 95/* AM9513A Counter/Timer defines */ 96#define CLOCK_1_MHZ 0x8B25 97#define CLOCK_100_KHZ 0x8C25 98#define CLOCK_10_KHZ 0x8D25 99#define CLOCK_1_KHZ 0x8E25 100#define CLOCK_100_HZ 0x8F25 101/* Other miscellaneous defines */ 102#define ATMIO16D_SIZE 32 /* bus address range */ 103#define devpriv ((struct atmio16d_private *)dev->private) 104#define ATMIO16D_TIMEOUT 10 105 106struct atmio16_board_t { 107 108 const char *name; 109 int has_8255; 110}; 111 112static const struct atmio16_board_t atmio16_boards[] = { 113 { 114 .name = "atmio16", 115 .has_8255 = 0, 116 }, 117 { 118 .name = "atmio16d", 119 .has_8255 = 1, 120 }, 121}; 122 123#define n_atmio16_boards sizeof(atmio16_boards)/sizeof(atmio16_boards[0]) 124 125#define boardtype ((const struct atmio16_board_t *)dev->board_ptr) 126 127/* function prototypes */ 128static int atmio16d_attach(struct comedi_device * dev, struct comedi_devconfig * it); 129static int atmio16d_detach(struct comedi_device * dev); 130static irqreturn_t atmio16d_interrupt(int irq, void *d); 131static int atmio16d_ai_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s, 132 struct comedi_cmd * cmd); 133static int atmio16d_ai_cmd(struct comedi_device * dev, struct comedi_subdevice * s); 134static int atmio16d_ai_cancel(struct comedi_device * dev, struct comedi_subdevice * s); 135static void reset_counters(struct comedi_device * dev); 136static void reset_atmio16d(struct comedi_device * dev); 137 138/* main driver struct */ 139static struct comedi_driver driver_atmio16d = { 140 .driver_name = "atmio16", 141 .module = THIS_MODULE, 142 .attach = atmio16d_attach, 143 .detach = atmio16d_detach, 144 .board_name = &atmio16_boards[0].name, 145 .num_names = n_atmio16_boards, 146 .offset = sizeof(struct atmio16_board_t), 147}; 148 149COMEDI_INITCLEANUP(driver_atmio16d); 150 151/* range structs */ 152static const struct comedi_lrange range_atmio16d_ai_10_bipolar = { 4, { 153 BIP_RANGE(10), 154 BIP_RANGE(1), 155 BIP_RANGE(0.1), 156 BIP_RANGE(0.02) 157 } 158}; 159 160static const struct comedi_lrange range_atmio16d_ai_5_bipolar = { 4, { 161 BIP_RANGE(5), 162 BIP_RANGE(0.5), 163 BIP_RANGE(0.05), 164 BIP_RANGE(0.01) 165 } 166}; 167 168static const struct comedi_lrange range_atmio16d_ai_unipolar = { 4, { 169 UNI_RANGE(10), 170 UNI_RANGE(1), 171 UNI_RANGE(0.1), 172 UNI_RANGE(0.02) 173 } 174}; 175 176/* private data struct */ 177struct atmio16d_private { 178 enum { adc_diff, adc_singleended } adc_mux; 179 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range; 180 enum { adc_2comp, adc_straight } adc_coding; 181 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range; 182 enum { dac_internal, dac_external } dac0_reference, dac1_reference; 183 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding; 184 const struct comedi_lrange *ao_range_type_list[2]; 185 unsigned int ao_readback[2]; 186 unsigned int com_reg_1_state; /* current state of command register 1 */ 187 unsigned int com_reg_2_state; /* current state of command register 2 */ 188}; 189 190static void reset_counters(struct comedi_device *dev) 191{ 192 /* Counter 2 */ 193 outw(0xFFC2, dev->iobase + AM9513A_COM_REG); 194 outw(0xFF02, dev->iobase + AM9513A_COM_REG); 195 outw(0x4, dev->iobase + AM9513A_DATA_REG); 196 outw(0xFF0A, dev->iobase + AM9513A_COM_REG); 197 outw(0x3, dev->iobase + AM9513A_DATA_REG); 198 outw(0xFF42, dev->iobase + AM9513A_COM_REG); 199 outw(0xFF42, dev->iobase + AM9513A_COM_REG); 200 /* Counter 3 */ 201 outw(0xFFC4, dev->iobase + AM9513A_COM_REG); 202 outw(0xFF03, dev->iobase + AM9513A_COM_REG); 203 outw(0x4, dev->iobase + AM9513A_DATA_REG); 204 outw(0xFF0B, dev->iobase + AM9513A_COM_REG); 205 outw(0x3, dev->iobase + AM9513A_DATA_REG); 206 outw(0xFF44, dev->iobase + AM9513A_COM_REG); 207 outw(0xFF44, dev->iobase + AM9513A_COM_REG); 208 /* Counter 4 */ 209 outw(0xFFC8, dev->iobase + AM9513A_COM_REG); 210 outw(0xFF04, dev->iobase + AM9513A_COM_REG); 211 outw(0x4, dev->iobase + AM9513A_DATA_REG); 212 outw(0xFF0C, dev->iobase + AM9513A_COM_REG); 213 outw(0x3, dev->iobase + AM9513A_DATA_REG); 214 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 215 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 216 /* Counter 5 */ 217 outw(0xFFD0, dev->iobase + AM9513A_COM_REG); 218 outw(0xFF05, dev->iobase + AM9513A_COM_REG); 219 outw(0x4, dev->iobase + AM9513A_DATA_REG); 220 outw(0xFF0D, dev->iobase + AM9513A_COM_REG); 221 outw(0x3, dev->iobase + AM9513A_DATA_REG); 222 outw(0xFF50, dev->iobase + AM9513A_COM_REG); 223 outw(0xFF50, dev->iobase + AM9513A_COM_REG); 224 225 outw(0, dev->iobase + AD_CLEAR_REG); 226} 227 228static void reset_atmio16d(struct comedi_device *dev) 229{ 230 int i; 231 232 /* now we need to initialize the board */ 233 outw(0, dev->iobase + COM_REG_1); 234 outw(0, dev->iobase + COM_REG_2); 235 outw(0, dev->iobase + MUX_GAIN_REG); 236 /* init AM9513A timer */ 237 outw(0xFFFF, dev->iobase + AM9513A_COM_REG); 238 outw(0xFFEF, dev->iobase + AM9513A_COM_REG); 239 outw(0xFF17, dev->iobase + AM9513A_COM_REG); 240 outw(0xF000, dev->iobase + AM9513A_DATA_REG); 241 for (i = 1; i <= 5; ++i) { 242 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG); 243 outw(0x0004, dev->iobase + AM9513A_DATA_REG); 244 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG); 245 outw(0x3, dev->iobase + AM9513A_DATA_REG); 246 } 247 outw(0xFF5F, dev->iobase + AM9513A_COM_REG); 248 /* timer init done */ 249 outw(0, dev->iobase + AD_CLEAR_REG); 250 outw(0, dev->iobase + INT2CLR_REG); 251 /* select straight binary mode for Analog Input */ 252 devpriv->com_reg_1_state |= 1; 253 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 254 devpriv->adc_coding = adc_straight; 255 /* zero the analog outputs */ 256 outw(2048, dev->iobase + DAC0_REG); 257 outw(2048, dev->iobase + DAC1_REG); 258} 259 260static irqreturn_t atmio16d_interrupt(int irq, void *d) 261{ 262 struct comedi_device *dev = d; 263 struct comedi_subdevice *s = dev->subdevices + 0; 264 265/* printk("atmio16d_interrupt!\n"); */ 266 267 comedi_buf_put(s->async, inw(dev->iobase + AD_FIFO_REG)); 268 269 comedi_event(dev, s); 270 return IRQ_HANDLED; 271} 272 273static int atmio16d_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 274 struct comedi_cmd *cmd) 275{ 276 int err = 0, tmp; 277#ifdef DEBUG1 278 printk("atmio16d_ai_cmdtest\n"); 279#endif 280 /* make sure triggers are valid */ 281 tmp = cmd->start_src; 282 cmd->start_src &= TRIG_NOW; 283 if (!cmd->start_src || tmp != cmd->start_src) 284 err++; 285 286 tmp = cmd->scan_begin_src; 287 cmd->scan_begin_src &= TRIG_FOLLOW | TRIG_TIMER; 288 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 289 err++; 290 291 tmp = cmd->convert_src; 292 cmd->convert_src &= TRIG_TIMER; 293 if (!cmd->convert_src || tmp != cmd->convert_src) 294 err++; 295 296 tmp = cmd->scan_end_src; 297 cmd->scan_end_src &= TRIG_COUNT; 298 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 299 err++; 300 301 tmp = cmd->stop_src; 302 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 303 if (!cmd->stop_src || tmp != cmd->stop_src) 304 err++; 305 306 if (err) 307 return 1; 308 309 /* step 2: make sure trigger sources are unique and mutually compatible */ 310 /* note that mutual compatiblity is not an issue here */ 311 if (cmd->scan_begin_src != TRIG_FOLLOW && 312 cmd->scan_begin_src != TRIG_EXT && 313 cmd->scan_begin_src != TRIG_TIMER) 314 err++; 315 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 316 err++; 317 318 if (err) 319 return 2; 320 321 /* step 3: make sure arguments are trivially compatible */ 322 323 if (cmd->start_arg != 0) { 324 cmd->start_arg = 0; 325 err++; 326 } 327 if (cmd->scan_begin_src == TRIG_FOLLOW) { 328 /* internal trigger */ 329 if (cmd->scan_begin_arg != 0) { 330 cmd->scan_begin_arg = 0; 331 err++; 332 } 333 } else { 334#if 0 335 /* external trigger */ 336 /* should be level/edge, hi/lo specification here */ 337 if (cmd->scan_begin_arg != 0) { 338 cmd->scan_begin_arg = 0; 339 err++; 340 } 341#endif 342 } 343 344 if (cmd->convert_arg < 10000) { 345 cmd->convert_arg = 10000; 346 err++; 347 } 348#if 0 349 if (cmd->convert_arg > SLOWEST_TIMER) { 350 cmd->convert_arg = SLOWEST_TIMER; 351 err++; 352 } 353#endif 354 if (cmd->scan_end_arg != cmd->chanlist_len) { 355 cmd->scan_end_arg = cmd->chanlist_len; 356 err++; 357 } 358 if (cmd->stop_src == TRIG_COUNT) { 359 /* any count is allowed */ 360 } else { 361 /* TRIG_NONE */ 362 if (cmd->stop_arg != 0) { 363 cmd->stop_arg = 0; 364 err++; 365 } 366 } 367 368 if (err) 369 return 3; 370 371 return 0; 372} 373 374static int atmio16d_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 375{ 376 struct comedi_cmd *cmd = &s->async->cmd; 377 unsigned int timer, base_clock; 378 unsigned int sample_count, tmp, chan, gain; 379 int i; 380#ifdef DEBUG1 381 printk("atmio16d_ai_cmd\n"); 382#endif 383 /* This is slowly becoming a working command interface. * 384 * It is still uber-experimental */ 385 386 reset_counters(dev); 387 s->async->cur_chan = 0; 388 389 /* check if scanning multiple channels */ 390 if (cmd->chanlist_len < 2) { 391 devpriv->com_reg_1_state &= ~COMREG1_SCANEN; 392 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 393 } else { 394 devpriv->com_reg_1_state |= COMREG1_SCANEN; 395 devpriv->com_reg_2_state |= COMREG2_SCN2; 396 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 397 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2); 398 } 399 400 /* Setup the Mux-Gain Counter */ 401 for (i = 0; i < cmd->chanlist_len; ++i) { 402 chan = CR_CHAN(cmd->chanlist[i]); 403 gain = CR_RANGE(cmd->chanlist[i]); 404 outw(i, dev->iobase + MUX_CNTR_REG); 405 tmp = chan | (gain << 6); 406 if (i == cmd->scan_end_arg - 1) 407 tmp |= 0x0010; /* set LASTONE bit */ 408 outw(tmp, dev->iobase + MUX_GAIN_REG); 409 } 410 411 /* Now program the sample interval timer */ 412 /* Figure out which clock to use then get an 413 * appropriate timer value */ 414 if (cmd->convert_arg < 65536000) { 415 base_clock = CLOCK_1_MHZ; 416 timer = cmd->convert_arg / 1000; 417 } else if (cmd->convert_arg < 655360000) { 418 base_clock = CLOCK_100_KHZ; 419 timer = cmd->convert_arg / 10000; 420 } else if (cmd->convert_arg <= 0xffffffff /* 6553600000 */) { 421 base_clock = CLOCK_10_KHZ; 422 timer = cmd->convert_arg / 100000; 423 } else if (cmd->convert_arg <= 0xffffffff /* 65536000000 */) { 424 base_clock = CLOCK_1_KHZ; 425 timer = cmd->convert_arg / 1000000; 426 } 427 outw(0xFF03, dev->iobase + AM9513A_COM_REG); 428 outw(base_clock, dev->iobase + AM9513A_DATA_REG); 429 outw(0xFF0B, dev->iobase + AM9513A_COM_REG); 430 outw(0x2, dev->iobase + AM9513A_DATA_REG); 431 outw(0xFF44, dev->iobase + AM9513A_COM_REG); 432 outw(0xFFF3, dev->iobase + AM9513A_COM_REG); 433 outw(timer, dev->iobase + AM9513A_DATA_REG); 434 outw(0xFF24, dev->iobase + AM9513A_COM_REG); 435 436 /* Now figure out how many samples to get */ 437 /* and program the sample counter */ 438 sample_count = cmd->stop_arg * cmd->scan_end_arg; 439 outw(0xFF04, dev->iobase + AM9513A_COM_REG); 440 outw(0x1025, dev->iobase + AM9513A_DATA_REG); 441 outw(0xFF0C, dev->iobase + AM9513A_COM_REG); 442 if (sample_count < 65536) { 443 /* use only Counter 4 */ 444 outw(sample_count, dev->iobase + AM9513A_DATA_REG); 445 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 446 outw(0xFFF4, dev->iobase + AM9513A_COM_REG); 447 outw(0xFF28, dev->iobase + AM9513A_COM_REG); 448 devpriv->com_reg_1_state &= ~COMREG1_1632CNT; 449 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 450 } else { 451 /* Counter 4 and 5 are needed */ 452 453 tmp = sample_count & 0xFFFF; 454 if (tmp) 455 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG); 456 else 457 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG); 458 459 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 460 outw(0, dev->iobase + AM9513A_DATA_REG); 461 outw(0xFF28, dev->iobase + AM9513A_COM_REG); 462 outw(0xFF05, dev->iobase + AM9513A_COM_REG); 463 outw(0x25, dev->iobase + AM9513A_DATA_REG); 464 outw(0xFF0D, dev->iobase + AM9513A_COM_REG); 465 tmp = sample_count & 0xFFFF; 466 if ((tmp == 0) || (tmp == 1)) { 467 outw((sample_count >> 16) & 0xFFFF, 468 dev->iobase + AM9513A_DATA_REG); 469 } else { 470 outw(((sample_count >> 16) & 0xFFFF) + 1, 471 dev->iobase + AM9513A_DATA_REG); 472 } 473 outw(0xFF70, dev->iobase + AM9513A_COM_REG); 474 devpriv->com_reg_1_state |= COMREG1_1632CNT; 475 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 476 } 477 478 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */ 479 /* Figure out which clock to use then get an 480 * appropriate timer value */ 481 if (cmd->chanlist_len > 1) { 482 if (cmd->scan_begin_arg < 65536000) { 483 base_clock = CLOCK_1_MHZ; 484 timer = cmd->scan_begin_arg / 1000; 485 } else if (cmd->scan_begin_arg < 655360000) { 486 base_clock = CLOCK_100_KHZ; 487 timer = cmd->scan_begin_arg / 10000; 488 } else if (cmd->scan_begin_arg < 0xffffffff /* 6553600000 */) { 489 base_clock = CLOCK_10_KHZ; 490 timer = cmd->scan_begin_arg / 100000; 491 } else if (cmd->scan_begin_arg < 0xffffffff /* 65536000000 */) { 492 base_clock = CLOCK_1_KHZ; 493 timer = cmd->scan_begin_arg / 1000000; 494 } 495 outw(0xFF02, dev->iobase + AM9513A_COM_REG); 496 outw(base_clock, dev->iobase + AM9513A_DATA_REG); 497 outw(0xFF0A, dev->iobase + AM9513A_COM_REG); 498 outw(0x2, dev->iobase + AM9513A_DATA_REG); 499 outw(0xFF42, dev->iobase + AM9513A_COM_REG); 500 outw(0xFFF2, dev->iobase + AM9513A_COM_REG); 501 outw(timer, dev->iobase + AM9513A_DATA_REG); 502 outw(0xFF22, dev->iobase + AM9513A_COM_REG); 503 } 504 505 /* Clear the A/D FIFO and reset the MUX counter */ 506 outw(0, dev->iobase + AD_CLEAR_REG); 507 outw(0, dev->iobase + MUX_CNTR_REG); 508 outw(0, dev->iobase + INT2CLR_REG); 509 /* enable this acquisition operation */ 510 devpriv->com_reg_1_state |= COMREG1_DAQEN; 511 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 512 /* enable interrupts for conversion completion */ 513 devpriv->com_reg_1_state |= COMREG1_CONVINTEN; 514 devpriv->com_reg_2_state |= COMREG2_INTEN; 515 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 516 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2); 517 /* apply a trigger. this starts the counters! */ 518 outw(0, dev->iobase + START_DAQ_REG); 519 520 return 0; 521} 522 523/* This will cancel a running acquisition operation */ 524static int atmio16d_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 525{ 526 reset_atmio16d(dev); 527 528 return 0; 529} 530 531/* Mode 0 is used to get a single conversion on demand */ 532static int atmio16d_ai_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 533 struct comedi_insn *insn, unsigned int *data) 534{ 535 int i, t; 536 int chan; 537 int gain; 538 int status; 539 540#ifdef DEBUG1 541 printk("atmio16d_ai_insn_read\n"); 542#endif 543 chan = CR_CHAN(insn->chanspec); 544 gain = CR_RANGE(insn->chanspec); 545 546 /* reset the Analog input circuitry */ 547 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */ 548 /* reset the Analog Input MUX Counter to 0 */ 549 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */ 550 551 /* set the Input MUX gain */ 552 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG); 553 554 for (i = 0; i < insn->n; i++) { 555 /* start the conversion */ 556 outw(0, dev->iobase + START_CONVERT_REG); 557 /* wait for it to finish */ 558 for (t = 0; t < ATMIO16D_TIMEOUT; t++) { 559 /* check conversion status */ 560 status = inw(dev->iobase + STAT_REG); 561#ifdef DEBUG1 562 printk("status=%x\n", status); 563#endif 564 if (status & STAT_AD_CONVAVAIL) { 565 /* read the data now */ 566 data[i] = inw(dev->iobase + AD_FIFO_REG); 567 /* change to two's complement if need be */ 568 if (devpriv->adc_coding == adc_2comp) { 569 data[i] ^= 0x800; 570 } 571 break; 572 } 573 if (status & STAT_AD_OVERFLOW) { 574 printk("atmio16d: a/d FIFO overflow\n"); 575 outw(0, dev->iobase + AD_CLEAR_REG); 576 577 return -ETIME; 578 } 579 } 580 /* end waiting, now check if it timed out */ 581 if (t == ATMIO16D_TIMEOUT) { 582 rt_printk("atmio16d: timeout\n"); 583 584 return -ETIME; 585 } 586 } 587 588 return i; 589} 590 591static int atmio16d_ao_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 592 struct comedi_insn *insn, unsigned int *data) 593{ 594 int i; 595#ifdef DEBUG1 596 printk("atmio16d_ao_insn_read\n"); 597#endif 598 599 for (i = 0; i < insn->n; i++) { 600 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)]; 601 } 602 603 return i; 604} 605 606static int atmio16d_ao_insn_write(struct comedi_device *dev, struct comedi_subdevice *s, 607 struct comedi_insn *insn, unsigned int *data) 608{ 609 int i; 610 int chan; 611 int d; 612#ifdef DEBUG1 613 printk("atmio16d_ao_insn_write\n"); 614#endif 615 616 chan = CR_CHAN(insn->chanspec); 617 618 for (i = 0; i < insn->n; i++) { 619 d = data[i]; 620 switch (chan) { 621 case 0: 622 if (devpriv->dac0_coding == dac_2comp) { 623 d ^= 0x800; 624 } 625 outw(d, dev->iobase + DAC0_REG); 626 break; 627 case 1: 628 if (devpriv->dac1_coding == dac_2comp) { 629 d ^= 0x800; 630 } 631 outw(d, dev->iobase + DAC1_REG); 632 break; 633 default: 634 return -EINVAL; 635 } 636 devpriv->ao_readback[chan] = data[i]; 637 } 638 return i; 639} 640 641static int atmio16d_dio_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, 642 struct comedi_insn *insn, unsigned int *data) 643{ 644 if (insn->n != 2) 645 return -EINVAL; 646 647 if (data[0]) { 648 s->state &= ~data[0]; 649 s->state |= (data[0] | data[1]); 650 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG); 651 } 652 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG); 653 654 return 2; 655} 656 657static int atmio16d_dio_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 658 struct comedi_insn *insn, unsigned int *data) 659{ 660 int i; 661 int mask; 662 663 for (i = 0; i < insn->n; i++) { 664 mask = (CR_CHAN(insn->chanspec) < 4) ? 0x0f : 0xf0; 665 s->io_bits &= ~mask; 666 if (data[i]) 667 s->io_bits |= mask; 668 } 669 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1); 670 if (s->io_bits & 0x0f) 671 devpriv->com_reg_2_state |= COMREG2_DOUTEN0; 672 if (s->io_bits & 0xf0) 673 devpriv->com_reg_2_state |= COMREG2_DOUTEN1; 674 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2); 675 676 return i; 677} 678 679/* 680 options[0] - I/O port 681 options[1] - MIO irq 682 0 == no irq 683 N == irq N {3,4,5,6,7,9,10,11,12,14,15} 684 options[2] - DIO irq 685 0 == no irq 686 N == irq N {3,4,5,6,7,9} 687 options[3] - DMA1 channel 688 0 == no DMA 689 N == DMA N {5,6,7} 690 options[4] - DMA2 channel 691 0 == no DMA 692 N == DMA N {5,6,7} 693 694 options[5] - a/d mux 695 0=differential, 1=single 696 options[6] - a/d range 697 0=bipolar10, 1=bipolar5, 2=unipolar10 698 699 options[7] - dac0 range 700 0=bipolar, 1=unipolar 701 options[8] - dac0 reference 702 0=internal, 1=external 703 options[9] - dac0 coding 704 0=2's comp, 1=straight binary 705 706 options[10] - dac1 range 707 options[11] - dac1 reference 708 options[12] - dac1 coding 709 */ 710 711static int atmio16d_attach(struct comedi_device *dev, struct comedi_devconfig *it) 712{ 713 unsigned int irq; 714 unsigned long iobase; 715 int ret; 716 717 struct comedi_subdevice *s; 718 719 /* make sure the address range is free and allocate it */ 720 iobase = it->options[0]; 721 printk("comedi%d: atmio16d: 0x%04lx ", dev->minor, iobase); 722 if (!request_region(iobase, ATMIO16D_SIZE, "ni_atmio16d")) { 723 printk("I/O port conflict\n"); 724 return -EIO; 725 } 726 dev->iobase = iobase; 727 728 /* board name */ 729 dev->board_name = boardtype->name; 730 731 ret = alloc_subdevices(dev, 4); 732 if (ret < 0) 733 return ret; 734 735 ret = alloc_private(dev, sizeof(struct atmio16d_private)); 736 if (ret < 0) 737 return ret; 738 739 /* reset the atmio16d hardware */ 740 reset_atmio16d(dev); 741 742 /* check if our interrupt is available and get it */ 743 irq = it->options[1]; 744 if (irq) { 745 746 ret = comedi_request_irq(irq, atmio16d_interrupt, 747 0, "atmio16d", dev); 748 if (ret < 0) { 749 printk("failed to allocate irq %u\n", irq); 750 return ret; 751 } 752 dev->irq = irq; 753 printk("( irq = %u )\n", irq); 754 } else { 755 printk("( no irq )"); 756 } 757 758 /* set device options */ 759 devpriv->adc_mux = it->options[5]; 760 devpriv->adc_range = it->options[6]; 761 762 devpriv->dac0_range = it->options[7]; 763 devpriv->dac0_reference = it->options[8]; 764 devpriv->dac0_coding = it->options[9]; 765 devpriv->dac1_range = it->options[10]; 766 devpriv->dac1_reference = it->options[11]; 767 devpriv->dac1_coding = it->options[12]; 768 769 /* setup sub-devices */ 770 s = dev->subdevices + 0; 771 dev->read_subdev = s; 772 /* ai subdevice */ 773 s->type = COMEDI_SUBD_AI; 774 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_CMD_READ; 775 s->n_chan = (devpriv->adc_mux ? 16 : 8); 776 s->len_chanlist = 16; 777 s->insn_read = atmio16d_ai_insn_read; 778 s->do_cmdtest = atmio16d_ai_cmdtest; 779 s->do_cmd = atmio16d_ai_cmd; 780 s->cancel = atmio16d_ai_cancel; 781 s->maxdata = 0xfff; /* 4095 decimal */ 782 switch (devpriv->adc_range) { 783 case adc_bipolar10: 784 s->range_table = &range_atmio16d_ai_10_bipolar; 785 break; 786 case adc_bipolar5: 787 s->range_table = &range_atmio16d_ai_5_bipolar; 788 break; 789 case adc_unipolar10: 790 s->range_table = &range_atmio16d_ai_unipolar; 791 break; 792 } 793 794 /* ao subdevice */ 795 s++; 796 s->type = COMEDI_SUBD_AO; 797 s->subdev_flags = SDF_WRITABLE; 798 s->n_chan = 2; 799 s->insn_read = atmio16d_ao_insn_read; 800 s->insn_write = atmio16d_ao_insn_write; 801 s->maxdata = 0xfff; /* 4095 decimal */ 802 s->range_table_list = devpriv->ao_range_type_list; 803 switch (devpriv->dac0_range) { 804 case dac_bipolar: 805 devpriv->ao_range_type_list[0] = &range_bipolar10; 806 break; 807 case dac_unipolar: 808 devpriv->ao_range_type_list[0] = &range_unipolar10; 809 break; 810 } 811 switch (devpriv->dac1_range) { 812 case dac_bipolar: 813 devpriv->ao_range_type_list[1] = &range_bipolar10; 814 break; 815 case dac_unipolar: 816 devpriv->ao_range_type_list[1] = &range_unipolar10; 817 break; 818 } 819 820 /* Digital I/O */ 821 s++; 822 s->type = COMEDI_SUBD_DIO; 823 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 824 s->n_chan = 8; 825 s->insn_bits = atmio16d_dio_insn_bits; 826 s->insn_config = atmio16d_dio_insn_config; 827 s->maxdata = 1; 828 s->range_table = &range_digital; 829 830 /* 8255 subdevice */ 831 s++; 832 if (boardtype->has_8255) { 833 subdev_8255_init(dev, s, NULL, dev->iobase); 834 } else { 835 s->type = COMEDI_SUBD_UNUSED; 836 } 837 838/* don't yet know how to deal with counter/timers */ 839#if 0 840 s++; 841 /* do */ 842 s->type = COMEDI_SUBD_TIMER; 843 s->n_chan = 0; 844 s->maxdata = 0 845#endif 846 printk("\n"); 847 848 return 0; 849} 850 851static int atmio16d_detach(struct comedi_device *dev) 852{ 853 printk("comedi%d: atmio16d: remove\n", dev->minor); 854 855 if (dev->subdevices && boardtype->has_8255) 856 subdev_8255_cleanup(dev, dev->subdevices + 3); 857 858 if (dev->irq) 859 comedi_free_irq(dev->irq, dev); 860 861 reset_atmio16d(dev); 862 863 if (dev->iobase) 864 release_region(dev->iobase, ATMIO16D_SIZE); 865 866 return 0; 867} 868