ni_atmio16d.c revision 9ced1de69125b60f40127eddaa3be2a92bb0a1df
1/* 2 comedi/drivers/ni_atmio16d.c 3 Hardware driver for National Instruments AT-MIO16D board 4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20 */ 21/* 22Driver: ni_atmio16d 23Description: National Instruments AT-MIO-16D 24Author: Chris R. Baugher <baugher@enteract.com> 25Status: unknown 26Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d) 27*/ 28/* 29 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who 30 * wrote the driver for Advantec's pcl812 boards. I used the interrupt 31 * handling code from his driver as an example for this one. 32 * 33 * Chris Baugher 34 * 5/1/2000 35 * 36 */ 37 38#include "../comedidev.h" 39 40#include <linux/ioport.h> 41 42#include "8255.h" 43 44/* Configuration and Status Registers */ 45#define COM_REG_1 0x00 /* wo 16 */ 46#define STAT_REG 0x00 /* ro 16 */ 47#define COM_REG_2 0x02 /* wo 16 */ 48/* Event Strobe Registers */ 49#define START_CONVERT_REG 0x08 /* wo 16 */ 50#define START_DAQ_REG 0x0A /* wo 16 */ 51#define AD_CLEAR_REG 0x0C /* wo 16 */ 52#define EXT_STROBE_REG 0x0E /* wo 16 */ 53/* Analog Output Registers */ 54#define DAC0_REG 0x10 /* wo 16 */ 55#define DAC1_REG 0x12 /* wo 16 */ 56#define INT2CLR_REG 0x14 /* wo 16 */ 57/* Analog Input Registers */ 58#define MUX_CNTR_REG 0x04 /* wo 16 */ 59#define MUX_GAIN_REG 0x06 /* wo 16 */ 60#define AD_FIFO_REG 0x16 /* ro 16 */ 61#define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */ 62/* AM9513A Counter/Timer Registers */ 63#define AM9513A_DATA_REG 0x18 /* rw 16 */ 64#define AM9513A_COM_REG 0x1A /* wo 16 */ 65#define AM9513A_STAT_REG 0x1A /* ro 16 */ 66/* MIO-16 Digital I/O Registers */ 67#define MIO_16_DIG_IN_REG 0x1C /* ro 16 */ 68#define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */ 69/* RTSI Switch Registers */ 70#define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */ 71#define RTSI_SW_STROBE_REG 0x1F /* wo 8 */ 72/* DIO-24 Registers */ 73#define DIO_24_PORTA_REG 0x00 /* rw 8 */ 74#define DIO_24_PORTB_REG 0x01 /* rw 8 */ 75#define DIO_24_PORTC_REG 0x02 /* rw 8 */ 76#define DIO_24_CNFG_REG 0x03 /* wo 8 */ 77 78/* Command Register bits */ 79#define COMREG1_2SCADC 0x0001 80#define COMREG1_1632CNT 0x0002 81#define COMREG1_SCANEN 0x0008 82#define COMREG1_DAQEN 0x0010 83#define COMREG1_DMAEN 0x0020 84#define COMREG1_CONVINTEN 0x0080 85#define COMREG2_SCN2 0x0010 86#define COMREG2_INTEN 0x0080 87#define COMREG2_DOUTEN0 0x0100 88#define COMREG2_DOUTEN1 0x0200 89/* Status Register bits */ 90#define STAT_AD_OVERRUN 0x0100 91#define STAT_AD_OVERFLOW 0x0200 92#define STAT_AD_DAQPROG 0x0800 93#define STAT_AD_CONVAVAIL 0x2000 94#define STAT_AD_DAQSTOPINT 0x4000 95/* AM9513A Counter/Timer defines */ 96#define CLOCK_1_MHZ 0x8B25 97#define CLOCK_100_KHZ 0x8C25 98#define CLOCK_10_KHZ 0x8D25 99#define CLOCK_1_KHZ 0x8E25 100#define CLOCK_100_HZ 0x8F25 101/* Other miscellaneous defines */ 102#define ATMIO16D_SIZE 32 /* bus address range */ 103#define devpriv ((atmio16d_private *)dev->private) 104#define ATMIO16D_TIMEOUT 10 105 106typedef struct { 107 const char *name; 108 int has_8255; 109} atmio16_board_t; 110static const atmio16_board_t atmio16_boards[] = { 111 { 112 name: "atmio16", 113 has_8255:0, 114 }, 115 { 116 name: "atmio16d", 117 has_8255:1, 118 }, 119}; 120 121#define n_atmio16_boards sizeof(atmio16_boards)/sizeof(atmio16_boards[0]) 122 123#define boardtype ((const atmio16_board_t *)dev->board_ptr) 124 125/* function prototypes */ 126static int atmio16d_attach(struct comedi_device * dev, comedi_devconfig * it); 127static int atmio16d_detach(struct comedi_device * dev); 128static irqreturn_t atmio16d_interrupt(int irq, void *d PT_REGS_ARG); 129static int atmio16d_ai_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s, 130 comedi_cmd * cmd); 131static int atmio16d_ai_cmd(struct comedi_device * dev, struct comedi_subdevice * s); 132static int atmio16d_ai_cancel(struct comedi_device * dev, struct comedi_subdevice * s); 133static void reset_counters(struct comedi_device * dev); 134static void reset_atmio16d(struct comedi_device * dev); 135 136/* main driver struct */ 137static struct comedi_driver driver_atmio16d = { 138 driver_name:"atmio16", 139 module:THIS_MODULE, 140 attach:atmio16d_attach, 141 detach:atmio16d_detach, 142 board_name:&atmio16_boards[0].name, 143 num_names:n_atmio16_boards, 144 offset:sizeof(atmio16_board_t), 145}; 146 147COMEDI_INITCLEANUP(driver_atmio16d); 148 149/* range structs */ 150static const struct comedi_lrange range_atmio16d_ai_10_bipolar = { 4, { 151 BIP_RANGE(10), 152 BIP_RANGE(1), 153 BIP_RANGE(0.1), 154 BIP_RANGE(0.02) 155 } 156}; 157 158static const struct comedi_lrange range_atmio16d_ai_5_bipolar = { 4, { 159 BIP_RANGE(5), 160 BIP_RANGE(0.5), 161 BIP_RANGE(0.05), 162 BIP_RANGE(0.01) 163 } 164}; 165 166static const struct comedi_lrange range_atmio16d_ai_unipolar = { 4, { 167 UNI_RANGE(10), 168 UNI_RANGE(1), 169 UNI_RANGE(0.1), 170 UNI_RANGE(0.02) 171 } 172}; 173 174/* private data struct */ 175typedef struct { 176 enum { adc_diff, adc_singleended } adc_mux; 177 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range; 178 enum { adc_2comp, adc_straight } adc_coding; 179 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range; 180 enum { dac_internal, dac_external } dac0_reference, dac1_reference; 181 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding; 182 const struct comedi_lrange *ao_range_type_list[2]; 183 unsigned int ao_readback[2]; 184 unsigned int com_reg_1_state; /* current state of command register 1 */ 185 unsigned int com_reg_2_state; /* current state of command register 2 */ 186} atmio16d_private; 187 188static void reset_counters(struct comedi_device * dev) 189{ 190 /* Counter 2 */ 191 outw(0xFFC2, dev->iobase + AM9513A_COM_REG); 192 outw(0xFF02, dev->iobase + AM9513A_COM_REG); 193 outw(0x4, dev->iobase + AM9513A_DATA_REG); 194 outw(0xFF0A, dev->iobase + AM9513A_COM_REG); 195 outw(0x3, dev->iobase + AM9513A_DATA_REG); 196 outw(0xFF42, dev->iobase + AM9513A_COM_REG); 197 outw(0xFF42, dev->iobase + AM9513A_COM_REG); 198 /* Counter 3 */ 199 outw(0xFFC4, dev->iobase + AM9513A_COM_REG); 200 outw(0xFF03, dev->iobase + AM9513A_COM_REG); 201 outw(0x4, dev->iobase + AM9513A_DATA_REG); 202 outw(0xFF0B, dev->iobase + AM9513A_COM_REG); 203 outw(0x3, dev->iobase + AM9513A_DATA_REG); 204 outw(0xFF44, dev->iobase + AM9513A_COM_REG); 205 outw(0xFF44, dev->iobase + AM9513A_COM_REG); 206 /* Counter 4 */ 207 outw(0xFFC8, dev->iobase + AM9513A_COM_REG); 208 outw(0xFF04, dev->iobase + AM9513A_COM_REG); 209 outw(0x4, dev->iobase + AM9513A_DATA_REG); 210 outw(0xFF0C, dev->iobase + AM9513A_COM_REG); 211 outw(0x3, dev->iobase + AM9513A_DATA_REG); 212 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 213 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 214 /* Counter 5 */ 215 outw(0xFFD0, dev->iobase + AM9513A_COM_REG); 216 outw(0xFF05, dev->iobase + AM9513A_COM_REG); 217 outw(0x4, dev->iobase + AM9513A_DATA_REG); 218 outw(0xFF0D, dev->iobase + AM9513A_COM_REG); 219 outw(0x3, dev->iobase + AM9513A_DATA_REG); 220 outw(0xFF50, dev->iobase + AM9513A_COM_REG); 221 outw(0xFF50, dev->iobase + AM9513A_COM_REG); 222 223 outw(0, dev->iobase + AD_CLEAR_REG); 224} 225 226static void reset_atmio16d(struct comedi_device * dev) 227{ 228 int i; 229 230 /* now we need to initialize the board */ 231 outw(0, dev->iobase + COM_REG_1); 232 outw(0, dev->iobase + COM_REG_2); 233 outw(0, dev->iobase + MUX_GAIN_REG); 234 /* init AM9513A timer */ 235 outw(0xFFFF, dev->iobase + AM9513A_COM_REG); 236 outw(0xFFEF, dev->iobase + AM9513A_COM_REG); 237 outw(0xFF17, dev->iobase + AM9513A_COM_REG); 238 outw(0xF000, dev->iobase + AM9513A_DATA_REG); 239 for (i = 1; i <= 5; ++i) { 240 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG); 241 outw(0x0004, dev->iobase + AM9513A_DATA_REG); 242 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG); 243 outw(0x3, dev->iobase + AM9513A_DATA_REG); 244 } 245 outw(0xFF5F, dev->iobase + AM9513A_COM_REG); 246 /* timer init done */ 247 outw(0, dev->iobase + AD_CLEAR_REG); 248 outw(0, dev->iobase + INT2CLR_REG); 249 /* select straight binary mode for Analog Input */ 250 devpriv->com_reg_1_state |= 1; 251 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 252 devpriv->adc_coding = adc_straight; 253 /* zero the analog outputs */ 254 outw(2048, dev->iobase + DAC0_REG); 255 outw(2048, dev->iobase + DAC1_REG); 256} 257 258static irqreturn_t atmio16d_interrupt(int irq, void *d PT_REGS_ARG) 259{ 260 struct comedi_device *dev = d; 261 struct comedi_subdevice *s = dev->subdevices + 0; 262 263// printk("atmio16d_interrupt!\n"); 264 265 comedi_buf_put(s->async, inw(dev->iobase + AD_FIFO_REG)); 266 267 comedi_event(dev, s); 268 return IRQ_HANDLED; 269} 270 271static int atmio16d_ai_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s, 272 comedi_cmd * cmd) 273{ 274 int err = 0, tmp; 275#ifdef DEBUG1 276 printk("atmio16d_ai_cmdtest\n"); 277#endif 278 /* make sure triggers are valid */ 279 tmp = cmd->start_src; 280 cmd->start_src &= TRIG_NOW; 281 if (!cmd->start_src || tmp != cmd->start_src) 282 err++; 283 284 tmp = cmd->scan_begin_src; 285 cmd->scan_begin_src &= TRIG_FOLLOW | TRIG_TIMER; 286 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 287 err++; 288 289 tmp = cmd->convert_src; 290 cmd->convert_src &= TRIG_TIMER; 291 if (!cmd->convert_src || tmp != cmd->convert_src) 292 err++; 293 294 tmp = cmd->scan_end_src; 295 cmd->scan_end_src &= TRIG_COUNT; 296 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 297 err++; 298 299 tmp = cmd->stop_src; 300 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 301 if (!cmd->stop_src || tmp != cmd->stop_src) 302 err++; 303 304 if (err) 305 return 1; 306 307 /* step 2: make sure trigger sources are unique and mutually compatible */ 308 /* note that mutual compatiblity is not an issue here */ 309 if (cmd->scan_begin_src != TRIG_FOLLOW && 310 cmd->scan_begin_src != TRIG_EXT && 311 cmd->scan_begin_src != TRIG_TIMER) 312 err++; 313 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 314 err++; 315 316 if (err) 317 return 2; 318 319 /* step 3: make sure arguments are trivially compatible */ 320 321 if (cmd->start_arg != 0) { 322 cmd->start_arg = 0; 323 err++; 324 } 325 if (cmd->scan_begin_src == TRIG_FOLLOW) { 326 /* internal trigger */ 327 if (cmd->scan_begin_arg != 0) { 328 cmd->scan_begin_arg = 0; 329 err++; 330 } 331 } else { 332#if 0 333 /* external trigger */ 334 /* should be level/edge, hi/lo specification here */ 335 if (cmd->scan_begin_arg != 0) { 336 cmd->scan_begin_arg = 0; 337 err++; 338 } 339#endif 340 } 341 342 if (cmd->convert_arg < 10000) { 343 cmd->convert_arg = 10000; 344 err++; 345 } 346#if 0 347 if (cmd->convert_arg > SLOWEST_TIMER) { 348 cmd->convert_arg = SLOWEST_TIMER; 349 err++; 350 } 351#endif 352 if (cmd->scan_end_arg != cmd->chanlist_len) { 353 cmd->scan_end_arg = cmd->chanlist_len; 354 err++; 355 } 356 if (cmd->stop_src == TRIG_COUNT) { 357 /* any count is allowed */ 358 } else { 359 /* TRIG_NONE */ 360 if (cmd->stop_arg != 0) { 361 cmd->stop_arg = 0; 362 err++; 363 } 364 } 365 366 if (err) 367 return 3; 368 369 return 0; 370} 371 372static int atmio16d_ai_cmd(struct comedi_device * dev, struct comedi_subdevice * s) 373{ 374 comedi_cmd *cmd = &s->async->cmd; 375 unsigned int timer, base_clock; 376 unsigned int sample_count, tmp, chan, gain; 377 int i; 378#ifdef DEBUG1 379 printk("atmio16d_ai_cmd\n"); 380#endif 381 /* This is slowly becoming a working command interface. * 382 * It is still uber-experimental */ 383 384 reset_counters(dev); 385 s->async->cur_chan = 0; 386 387 /* check if scanning multiple channels */ 388 if (cmd->chanlist_len < 2) { 389 devpriv->com_reg_1_state &= ~COMREG1_SCANEN; 390 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 391 } else { 392 devpriv->com_reg_1_state |= COMREG1_SCANEN; 393 devpriv->com_reg_2_state |= COMREG2_SCN2; 394 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 395 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2); 396 } 397 398 /* Setup the Mux-Gain Counter */ 399 for (i = 0; i < cmd->chanlist_len; ++i) { 400 chan = CR_CHAN(cmd->chanlist[i]); 401 gain = CR_RANGE(cmd->chanlist[i]); 402 outw(i, dev->iobase + MUX_CNTR_REG); 403 tmp = chan | (gain << 6); 404 if (i == cmd->scan_end_arg - 1) 405 tmp |= 0x0010; /* set LASTONE bit */ 406 outw(tmp, dev->iobase + MUX_GAIN_REG); 407 } 408 409 /* Now program the sample interval timer */ 410 /* Figure out which clock to use then get an 411 * appropriate timer value */ 412 if (cmd->convert_arg < 65536000) { 413 base_clock = CLOCK_1_MHZ; 414 timer = cmd->convert_arg / 1000; 415 } else if (cmd->convert_arg < 655360000) { 416 base_clock = CLOCK_100_KHZ; 417 timer = cmd->convert_arg / 10000; 418 } else if (cmd->convert_arg <= 0xffffffff /* 6553600000 */ ) { 419 base_clock = CLOCK_10_KHZ; 420 timer = cmd->convert_arg / 100000; 421 } else if (cmd->convert_arg <= 0xffffffff /* 65536000000 */ ) { 422 base_clock = CLOCK_1_KHZ; 423 timer = cmd->convert_arg / 1000000; 424 } 425 outw(0xFF03, dev->iobase + AM9513A_COM_REG); 426 outw(base_clock, dev->iobase + AM9513A_DATA_REG); 427 outw(0xFF0B, dev->iobase + AM9513A_COM_REG); 428 outw(0x2, dev->iobase + AM9513A_DATA_REG); 429 outw(0xFF44, dev->iobase + AM9513A_COM_REG); 430 outw(0xFFF3, dev->iobase + AM9513A_COM_REG); 431 outw(timer, dev->iobase + AM9513A_DATA_REG); 432 outw(0xFF24, dev->iobase + AM9513A_COM_REG); 433 434 /* Now figure out how many samples to get */ 435 /* and program the sample counter */ 436 sample_count = cmd->stop_arg * cmd->scan_end_arg; 437 outw(0xFF04, dev->iobase + AM9513A_COM_REG); 438 outw(0x1025, dev->iobase + AM9513A_DATA_REG); 439 outw(0xFF0C, dev->iobase + AM9513A_COM_REG); 440 if (sample_count < 65536) { 441 /* use only Counter 4 */ 442 outw(sample_count, dev->iobase + AM9513A_DATA_REG); 443 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 444 outw(0xFFF4, dev->iobase + AM9513A_COM_REG); 445 outw(0xFF28, dev->iobase + AM9513A_COM_REG); 446 devpriv->com_reg_1_state &= ~COMREG1_1632CNT; 447 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 448 } else { 449 /* Counter 4 and 5 are needed */ 450 if ((tmp = sample_count & 0xFFFF)) { 451 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG); 452 } else { 453 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG); 454 } 455 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 456 outw(0, dev->iobase + AM9513A_DATA_REG); 457 outw(0xFF28, dev->iobase + AM9513A_COM_REG); 458 outw(0xFF05, dev->iobase + AM9513A_COM_REG); 459 outw(0x25, dev->iobase + AM9513A_DATA_REG); 460 outw(0xFF0D, dev->iobase + AM9513A_COM_REG); 461 tmp = sample_count & 0xFFFF; 462 if ((tmp == 0) || (tmp == 1)) { 463 outw((sample_count >> 16) & 0xFFFF, 464 dev->iobase + AM9513A_DATA_REG); 465 } else { 466 outw(((sample_count >> 16) & 0xFFFF) + 1, 467 dev->iobase + AM9513A_DATA_REG); 468 } 469 outw(0xFF70, dev->iobase + AM9513A_COM_REG); 470 devpriv->com_reg_1_state |= COMREG1_1632CNT; 471 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 472 } 473 474 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */ 475 /* Figure out which clock to use then get an 476 * appropriate timer value */ 477 if (cmd->chanlist_len > 1) { 478 if (cmd->scan_begin_arg < 65536000) { 479 base_clock = CLOCK_1_MHZ; 480 timer = cmd->scan_begin_arg / 1000; 481 } else if (cmd->scan_begin_arg < 655360000) { 482 base_clock = CLOCK_100_KHZ; 483 timer = cmd->scan_begin_arg / 10000; 484 } else if (cmd->scan_begin_arg < 0xffffffff /* 6553600000 */ ) { 485 base_clock = CLOCK_10_KHZ; 486 timer = cmd->scan_begin_arg / 100000; 487 } else if (cmd->scan_begin_arg < 0xffffffff /* 65536000000 */ ) { 488 base_clock = CLOCK_1_KHZ; 489 timer = cmd->scan_begin_arg / 1000000; 490 } 491 outw(0xFF02, dev->iobase + AM9513A_COM_REG); 492 outw(base_clock, dev->iobase + AM9513A_DATA_REG); 493 outw(0xFF0A, dev->iobase + AM9513A_COM_REG); 494 outw(0x2, dev->iobase + AM9513A_DATA_REG); 495 outw(0xFF42, dev->iobase + AM9513A_COM_REG); 496 outw(0xFFF2, dev->iobase + AM9513A_COM_REG); 497 outw(timer, dev->iobase + AM9513A_DATA_REG); 498 outw(0xFF22, dev->iobase + AM9513A_COM_REG); 499 } 500 501 /* Clear the A/D FIFO and reset the MUX counter */ 502 outw(0, dev->iobase + AD_CLEAR_REG); 503 outw(0, dev->iobase + MUX_CNTR_REG); 504 outw(0, dev->iobase + INT2CLR_REG); 505 /* enable this acquisition operation */ 506 devpriv->com_reg_1_state |= COMREG1_DAQEN; 507 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 508 /* enable interrupts for conversion completion */ 509 devpriv->com_reg_1_state |= COMREG1_CONVINTEN; 510 devpriv->com_reg_2_state |= COMREG2_INTEN; 511 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 512 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2); 513 /* apply a trigger. this starts the counters! */ 514 outw(0, dev->iobase + START_DAQ_REG); 515 516 return 0; 517} 518 519/* This will cancel a running acquisition operation */ 520static int atmio16d_ai_cancel(struct comedi_device * dev, struct comedi_subdevice * s) 521{ 522 reset_atmio16d(dev); 523 524 return 0; 525} 526 527/* Mode 0 is used to get a single conversion on demand */ 528static int atmio16d_ai_insn_read(struct comedi_device * dev, struct comedi_subdevice * s, 529 comedi_insn * insn, unsigned int * data) 530{ 531 int i, t; 532 int chan; 533 int gain; 534 int status; 535 536#ifdef DEBUG1 537 printk("atmio16d_ai_insn_read\n"); 538#endif 539 chan = CR_CHAN(insn->chanspec); 540 gain = CR_RANGE(insn->chanspec); 541 542 /* reset the Analog input circuitry */ 543 //outw( 0, dev->iobase+AD_CLEAR_REG ); 544 /* reset the Analog Input MUX Counter to 0 */ 545 //outw( 0, dev->iobase+MUX_CNTR_REG ); 546 547 /* set the Input MUX gain */ 548 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG); 549 550 for (i = 0; i < insn->n; i++) { 551 /* start the conversion */ 552 outw(0, dev->iobase + START_CONVERT_REG); 553 /* wait for it to finish */ 554 for (t = 0; t < ATMIO16D_TIMEOUT; t++) { 555 /* check conversion status */ 556 status = inw(dev->iobase + STAT_REG); 557#ifdef DEBUG1 558 printk("status=%x\n", status); 559#endif 560 if (status & STAT_AD_CONVAVAIL) { 561 /* read the data now */ 562 data[i] = inw(dev->iobase + AD_FIFO_REG); 563 /* change to two's complement if need be */ 564 if (devpriv->adc_coding == adc_2comp) { 565 data[i] ^= 0x800; 566 } 567 break; 568 } 569 if (status & STAT_AD_OVERFLOW) { 570 printk("atmio16d: a/d FIFO overflow\n"); 571 outw(0, dev->iobase + AD_CLEAR_REG); 572 573 return -ETIME; 574 } 575 } 576 /* end waiting, now check if it timed out */ 577 if (t == ATMIO16D_TIMEOUT) { 578 rt_printk("atmio16d: timeout\n"); 579 580 return -ETIME; 581 } 582 } 583 584 return i; 585} 586 587static int atmio16d_ao_insn_read(struct comedi_device * dev, struct comedi_subdevice * s, 588 comedi_insn * insn, unsigned int * data) 589{ 590 int i; 591#ifdef DEBUG1 592 printk("atmio16d_ao_insn_read\n"); 593#endif 594 595 for (i = 0; i < insn->n; i++) { 596 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)]; 597 } 598 599 return i; 600} 601 602static int atmio16d_ao_insn_write(struct comedi_device * dev, struct comedi_subdevice * s, 603 comedi_insn * insn, unsigned int * data) 604{ 605 int i; 606 int chan; 607 int d; 608#ifdef DEBUG1 609 printk("atmio16d_ao_insn_write\n"); 610#endif 611 612 chan = CR_CHAN(insn->chanspec); 613 614 for (i = 0; i < insn->n; i++) { 615 d = data[i]; 616 switch (chan) { 617 case 0: 618 if (devpriv->dac0_coding == dac_2comp) { 619 d ^= 0x800; 620 } 621 outw(d, dev->iobase + DAC0_REG); 622 break; 623 case 1: 624 if (devpriv->dac1_coding == dac_2comp) { 625 d ^= 0x800; 626 } 627 outw(d, dev->iobase + DAC1_REG); 628 break; 629 default: 630 return -EINVAL; 631 } 632 devpriv->ao_readback[chan] = data[i]; 633 } 634 return i; 635} 636 637static int atmio16d_dio_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s, 638 comedi_insn * insn, unsigned int * data) 639{ 640 if (insn->n != 2) 641 return -EINVAL; 642 643 if (data[0]) { 644 s->state &= ~data[0]; 645 s->state |= (data[0] | data[1]); 646 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG); 647 } 648 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG); 649 650 return 2; 651} 652 653static int atmio16d_dio_insn_config(struct comedi_device * dev, struct comedi_subdevice * s, 654 comedi_insn * insn, unsigned int * data) 655{ 656 int i; 657 int mask; 658 659 for (i = 0; i < insn->n; i++) { 660 mask = (CR_CHAN(insn->chanspec) < 4) ? 0x0f : 0xf0; 661 s->io_bits &= ~mask; 662 if (data[i]) 663 s->io_bits |= mask; 664 } 665 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1); 666 if (s->io_bits & 0x0f) 667 devpriv->com_reg_2_state |= COMREG2_DOUTEN0; 668 if (s->io_bits & 0xf0) 669 devpriv->com_reg_2_state |= COMREG2_DOUTEN1; 670 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2); 671 672 return i; 673} 674 675/* 676 options[0] - I/O port 677 options[1] - MIO irq 678 0 == no irq 679 N == irq N {3,4,5,6,7,9,10,11,12,14,15} 680 options[2] - DIO irq 681 0 == no irq 682 N == irq N {3,4,5,6,7,9} 683 options[3] - DMA1 channel 684 0 == no DMA 685 N == DMA N {5,6,7} 686 options[4] - DMA2 channel 687 0 == no DMA 688 N == DMA N {5,6,7} 689 690 options[5] - a/d mux 691 0=differential, 1=single 692 options[6] - a/d range 693 0=bipolar10, 1=bipolar5, 2=unipolar10 694 695 options[7] - dac0 range 696 0=bipolar, 1=unipolar 697 options[8] - dac0 reference 698 0=internal, 1=external 699 options[9] - dac0 coding 700 0=2's comp, 1=straight binary 701 702 options[10] - dac1 range 703 options[11] - dac1 reference 704 options[12] - dac1 coding 705 */ 706 707static int atmio16d_attach(struct comedi_device * dev, comedi_devconfig * it) 708{ 709 unsigned int irq; 710 unsigned long iobase; 711 int ret; 712 713 struct comedi_subdevice *s; 714 715 /* make sure the address range is free and allocate it */ 716 iobase = it->options[0]; 717 printk("comedi%d: atmio16d: 0x%04lx ", dev->minor, iobase); 718 if (!request_region(iobase, ATMIO16D_SIZE, "ni_atmio16d")) { 719 printk("I/O port conflict\n"); 720 return -EIO; 721 } 722 dev->iobase = iobase; 723 724 /* board name */ 725 dev->board_name = boardtype->name; 726 727 if ((ret = alloc_subdevices(dev, 4)) < 0) 728 return ret; 729 if ((ret = alloc_private(dev, sizeof(atmio16d_private))) < 0) 730 return ret; 731 732 /* reset the atmio16d hardware */ 733 reset_atmio16d(dev); 734 735 /* check if our interrupt is available and get it */ 736 irq = it->options[1]; 737 if (irq) { 738 if ((ret = comedi_request_irq(irq, atmio16d_interrupt, 739 0, "atmio16d", dev)) < 0) { 740 printk("failed to allocate irq %u\n", irq); 741 return ret; 742 } 743 dev->irq = irq; 744 printk("( irq = %u )\n", irq); 745 } else { 746 printk("( no irq )"); 747 } 748 749 /* set device options */ 750 devpriv->adc_mux = it->options[5]; 751 devpriv->adc_range = it->options[6]; 752 753 devpriv->dac0_range = it->options[7]; 754 devpriv->dac0_reference = it->options[8]; 755 devpriv->dac0_coding = it->options[9]; 756 devpriv->dac1_range = it->options[10]; 757 devpriv->dac1_reference = it->options[11]; 758 devpriv->dac1_coding = it->options[12]; 759 760 /* setup sub-devices */ 761 s = dev->subdevices + 0; 762 dev->read_subdev = s; 763 /* ai subdevice */ 764 s->type = COMEDI_SUBD_AI; 765 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_CMD_READ; 766 s->n_chan = (devpriv->adc_mux ? 16 : 8); 767 s->len_chanlist = 16; 768 s->insn_read = atmio16d_ai_insn_read; 769 s->do_cmdtest = atmio16d_ai_cmdtest; 770 s->do_cmd = atmio16d_ai_cmd; 771 s->cancel = atmio16d_ai_cancel; 772 s->maxdata = 0xfff; /* 4095 decimal */ 773 switch (devpriv->adc_range) { 774 case adc_bipolar10: 775 s->range_table = &range_atmio16d_ai_10_bipolar; 776 break; 777 case adc_bipolar5: 778 s->range_table = &range_atmio16d_ai_5_bipolar; 779 break; 780 case adc_unipolar10: 781 s->range_table = &range_atmio16d_ai_unipolar; 782 break; 783 } 784 785 /* ao subdevice */ 786 s++; 787 s->type = COMEDI_SUBD_AO; 788 s->subdev_flags = SDF_WRITABLE; 789 s->n_chan = 2; 790 s->insn_read = atmio16d_ao_insn_read; 791 s->insn_write = atmio16d_ao_insn_write; 792 s->maxdata = 0xfff; /* 4095 decimal */ 793 s->range_table_list = devpriv->ao_range_type_list; 794 switch (devpriv->dac0_range) { 795 case dac_bipolar: 796 devpriv->ao_range_type_list[0] = &range_bipolar10; 797 break; 798 case dac_unipolar: 799 devpriv->ao_range_type_list[0] = &range_unipolar10; 800 break; 801 } 802 switch (devpriv->dac1_range) { 803 case dac_bipolar: 804 devpriv->ao_range_type_list[1] = &range_bipolar10; 805 break; 806 case dac_unipolar: 807 devpriv->ao_range_type_list[1] = &range_unipolar10; 808 break; 809 } 810 811 /* Digital I/O */ 812 s++; 813 s->type = COMEDI_SUBD_DIO; 814 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 815 s->n_chan = 8; 816 s->insn_bits = atmio16d_dio_insn_bits; 817 s->insn_config = atmio16d_dio_insn_config; 818 s->maxdata = 1; 819 s->range_table = &range_digital; 820 821 /* 8255 subdevice */ 822 s++; 823 if (boardtype->has_8255) { 824 subdev_8255_init(dev, s, NULL, dev->iobase); 825 } else { 826 s->type = COMEDI_SUBD_UNUSED; 827 } 828 829/* don't yet know how to deal with counter/timers */ 830#if 0 831 s++; 832 /* do */ 833 s->type = COMEDI_SUBD_TIMER; 834 s->n_chan = 0; 835 s->maxdata = 0 836#endif 837 printk("\n"); 838 839 return 0; 840} 841 842static int atmio16d_detach(struct comedi_device * dev) 843{ 844 printk("comedi%d: atmio16d: remove\n", dev->minor); 845 846 if (dev->subdevices && boardtype->has_8255) 847 subdev_8255_cleanup(dev, dev->subdevices + 3); 848 849 if (dev->irq) 850 comedi_free_irq(dev->irq, dev); 851 852 reset_atmio16d(dev); 853 854 if (dev->iobase) 855 release_region(dev->iobase, ATMIO16D_SIZE); 856 857 return 0; 858} 859