ni_labpc.c revision 2bb9c335902a5d59fc084170aaae0ccc9d9d4012
1/* 2 comedi/drivers/ni_labpc.c 3 Driver for National Instruments Lab-PC series boards and compatibles 4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20************************************************************************ 21*/ 22/* 23Driver: ni_labpc 24Description: National Instruments Lab-PC (& compatibles) 25Author: Frank Mori Hess <fmhess@users.sourceforge.net> 26Devices: [National Instruments] Lab-PC-1200 (labpc-1200), 27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc) 28Status: works 29 30Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges 31and analog references will work, the available ranges/arefs will 32depend on how you have configured the jumpers on your board 33(see your owner's manual). 34 35Kernel-level ISA plug-and-play support for the lab-pc-1200 36boards has not 37yet been added to the driver, mainly due to the fact that 38I don't know the device id numbers. If you have one 39of these boards, 40please file a bug report at https://bugs.comedi.org/ 41so I can get the necessary information from you. 42 43The 1200 series boards have onboard calibration dacs for correcting 44analog input/output offsets and gains. The proper settings for these 45caldacs are stored on the board's eeprom. To read the caldac values 46from the eeprom and store them into a file that can be then be used by 47comedilib, use the comedi_calibrate program. 48 49Configuration options - ISA boards: 50 [0] - I/O port base address 51 [1] - IRQ (optional, required for timed or externally triggered conversions) 52 [2] - DMA channel (optional) 53 54Configuration options - PCI boards: 55 [0] - bus (optional) 56 [1] - slot (optional) 57 58The Lab-pc+ has quirky chanlist requirements 59when scanning multiple channels. Multiple channel scan 60sequence must start at highest channel, then decrement down to 61channel 0. The rest of the cards can scan down like lab-pc+ or scan 62up from channel zero. Chanlists consisting of all one channel 63are also legal, and allow you to pace conversions in bursts. 64 65*/ 66 67/* 68 69NI manuals: 70341309a (labpc-1200 register manual) 71340914a (pci-1200) 72320502b (lab-pc+) 73 74*/ 75 76#undef LABPC_DEBUG 77/* #define LABPC_DEBUG enable debugging messages */ 78 79#include <linux/interrupt.h> 80#include "../comedidev.h" 81 82#include <linux/delay.h> 83#include <asm/dma.h> 84 85#include "8253.h" 86#include "8255.h" 87#include "mite.h" 88#include "comedi_fc.h" 89#include "ni_labpc.h" 90 91#define DRV_NAME "ni_labpc" 92 93#define LABPC_SIZE 32 /* size of io region used by board */ 94#define LABPC_TIMER_BASE 500 /* 2 MHz master clock */ 95 96/* Registers for the lab-pc+ */ 97 98/* write-only registers */ 99#define COMMAND1_REG 0x0 100#define ADC_GAIN_MASK (0x7 << 4) 101#define ADC_CHAN_BITS(x) ((x) & 0x7) 102#define ADC_SCAN_EN_BIT 0x80 /* enables multi channel scans */ 103#define COMMAND2_REG 0x1 104#define PRETRIG_BIT 0x1 /* enable pretriggering (used in conjunction with SWTRIG) */ 105#define HWTRIG_BIT 0x2 /* enable paced conversions on external trigger */ 106#define SWTRIG_BIT 0x4 /* enable paced conversions */ 107#define CASCADE_BIT 0x8 /* use two cascaded counters for pacing */ 108#define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1)) 109#define COMMAND3_REG 0x2 110#define DMA_EN_BIT 0x1 /* enable dma transfers */ 111#define DIO_INTR_EN_BIT 0x2 /* enable interrupts for 8255 */ 112#define DMATC_INTR_EN_BIT 0x4 /* enable dma terminal count interrupt */ 113#define TIMER_INTR_EN_BIT 0x8 /* enable timer interrupt */ 114#define ERR_INTR_EN_BIT 0x10 /* enable error interrupt */ 115#define ADC_FNE_INTR_EN_BIT 0x20 /* enable fifo not empty interrupt */ 116#define ADC_CONVERT_REG 0x3 117#define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1)) 118#define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1)) 119#define ADC_CLEAR_REG 0x8 120#define DMATC_CLEAR_REG 0xa 121#define TIMER_CLEAR_REG 0xc 122#define COMMAND6_REG 0xe /* 1200 boards only */ 123#define ADC_COMMON_BIT 0x1 /* select ground or common-mode reference */ 124#define ADC_UNIP_BIT 0x2 /* adc unipolar */ 125#define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) /* dac unipolar */ 126#define ADC_FHF_INTR_EN_BIT 0x20 /* enable fifo half full interrupt */ 127#define A1_INTR_EN_BIT 0x40 /* enable interrupt on end of hardware count */ 128#define ADC_SCAN_UP_BIT 0x80 /* scan up from channel zero instead of down to zero */ 129#define COMMAND4_REG 0xf 130#define INTERVAL_SCAN_EN_BIT 0x1 /* enables 'interval' scanning */ 131#define EXT_SCAN_EN_BIT 0x2 /* enables external signal on counter b1 output to trigger scan */ 132#define EXT_CONVERT_OUT_BIT 0x4 /* chooses direction (output or input) for EXTCONV* line */ 133#define ADC_DIFF_BIT 0x8 /* chooses differential inputs for adc (in conjunction with board jumper) */ 134#define EXT_CONVERT_DISABLE_BIT 0x10 135#define COMMAND5_REG 0x1c /* 1200 boards only, calibration stuff */ 136#define EEPROM_WRITE_UNPROTECT_BIT 0x4 /* enable eeprom for write */ 137#define DITHER_EN_BIT 0x8 /* enable dithering */ 138#define CALDAC_LOAD_BIT 0x10 /* load calibration dac */ 139#define SCLOCK_BIT 0x20 /* serial clock - rising edge writes, falling edge reads */ 140#define SDATA_BIT 0x40 /* serial data bit for writing to eeprom or calibration dacs */ 141#define EEPROM_EN_BIT 0x80 /* enable eeprom for read/write */ 142#define INTERVAL_COUNT_REG 0x1e 143#define INTERVAL_LOAD_REG 0x1f 144#define INTERVAL_LOAD_BITS 0x1 145 146/* read-only registers */ 147#define STATUS1_REG 0x0 148#define DATA_AVAIL_BIT 0x1 /* data is available in fifo */ 149#define OVERRUN_BIT 0x2 /* overrun has occurred */ 150#define OVERFLOW_BIT 0x4 /* fifo overflow */ 151#define TIMER_BIT 0x8 /* timer interrupt has occured */ 152#define DMATC_BIT 0x10 /* dma terminal count has occured */ 153#define EXT_TRIG_BIT 0x40 /* external trigger has occured */ 154#define STATUS2_REG 0x1d /* 1200 boards only */ 155#define EEPROM_OUT_BIT 0x1 /* programmable eeprom serial output */ 156#define A1_TC_BIT 0x2 /* counter A1 terminal count */ 157#define FNHF_BIT 0x4 /* fifo not half full */ 158#define ADC_FIFO_REG 0xa 159 160#define DIO_BASE_REG 0x10 161#define COUNTER_A_BASE_REG 0x14 162#define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3) 163#define INIT_A0_BITS 0x14 /* check modes put conversion pacer output in harmless state (a0 mode 2) */ 164#define INIT_A1_BITS 0x70 /* put hardware conversion counter output in harmless state (a1 mode 0) */ 165#define COUNTER_B_BASE_REG 0x18 166 167static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it); 168static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 169static irqreturn_t labpc_interrupt(int irq, void *d); 170static int labpc_drain_fifo(struct comedi_device *dev); 171static void labpc_drain_dma(struct comedi_device *dev); 172static void handle_isa_dma(struct comedi_device *dev); 173static void labpc_drain_dregs(struct comedi_device *dev); 174static int labpc_ai_cmdtest(struct comedi_device *dev, 175 struct comedi_subdevice *s, struct comedi_cmd *cmd); 176static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 177static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 178 struct comedi_insn *insn, unsigned int *data); 179static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 180 struct comedi_insn *insn, unsigned int *data); 181static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 182 struct comedi_insn *insn, unsigned int *data); 183static int labpc_calib_read_insn(struct comedi_device *dev, 184 struct comedi_subdevice *s, 185 struct comedi_insn *insn, unsigned int *data); 186static int labpc_calib_write_insn(struct comedi_device *dev, 187 struct comedi_subdevice *s, 188 struct comedi_insn *insn, unsigned int *data); 189static int labpc_eeprom_read_insn(struct comedi_device *dev, 190 struct comedi_subdevice *s, 191 struct comedi_insn *insn, unsigned int *data); 192static int labpc_eeprom_write_insn(struct comedi_device *dev, 193 struct comedi_subdevice *s, 194 struct comedi_insn *insn, 195 unsigned int *data); 196static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd); 197static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd); 198#ifdef CONFIG_COMEDI_PCI 199static int labpc_find_device(struct comedi_device *dev, int bus, int slot); 200#endif 201static int labpc_dio_mem_callback(int dir, int port, int data, 202 unsigned long arg); 203static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 204 unsigned int num_bits); 205static unsigned int labpc_serial_in(struct comedi_device *dev); 206static unsigned int labpc_eeprom_read(struct comedi_device *dev, 207 unsigned int address); 208static unsigned int labpc_eeprom_read_status(struct comedi_device *dev); 209static unsigned int labpc_eeprom_write(struct comedi_device *dev, 210 unsigned int address, 211 unsigned int value); 212static void write_caldac(struct comedi_device *dev, unsigned int channel, 213 unsigned int value); 214 215enum scan_mode { 216 MODE_SINGLE_CHAN, 217 MODE_SINGLE_CHAN_INTERVAL, 218 MODE_MULT_CHAN_UP, 219 MODE_MULT_CHAN_DOWN, 220}; 221 222/* analog input ranges */ 223#define NUM_LABPC_PLUS_AI_RANGES 16 224/* indicates unipolar ranges */ 225static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = { 226 0, 227 0, 228 0, 229 0, 230 0, 231 0, 232 0, 233 0, 234 1, 235 1, 236 1, 237 1, 238 1, 239 1, 240 1, 241 1, 242}; 243 244/* map range index to gain bits */ 245static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = { 246 0x00, 247 0x10, 248 0x20, 249 0x30, 250 0x40, 251 0x50, 252 0x60, 253 0x70, 254 0x00, 255 0x10, 256 0x20, 257 0x30, 258 0x40, 259 0x50, 260 0x60, 261 0x70, 262}; 263 264static const struct comedi_lrange range_labpc_plus_ai = { 265 NUM_LABPC_PLUS_AI_RANGES, 266 { 267 BIP_RANGE(5), 268 BIP_RANGE(4), 269 BIP_RANGE(2.5), 270 BIP_RANGE(1), 271 BIP_RANGE(0.5), 272 BIP_RANGE(0.25), 273 BIP_RANGE(0.1), 274 BIP_RANGE(0.05), 275 UNI_RANGE(10), 276 UNI_RANGE(8), 277 UNI_RANGE(5), 278 UNI_RANGE(2), 279 UNI_RANGE(1), 280 UNI_RANGE(0.5), 281 UNI_RANGE(0.2), 282 UNI_RANGE(0.1), 283 } 284}; 285 286#define NUM_LABPC_1200_AI_RANGES 14 287/* indicates unipolar ranges */ 288const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = { 289 0, 290 0, 291 0, 292 0, 293 0, 294 0, 295 0, 296 1, 297 1, 298 1, 299 1, 300 1, 301 1, 302 1, 303}; 304 305/* map range index to gain bits */ 306const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = { 307 0x00, 308 0x20, 309 0x30, 310 0x40, 311 0x50, 312 0x60, 313 0x70, 314 0x00, 315 0x20, 316 0x30, 317 0x40, 318 0x50, 319 0x60, 320 0x70, 321}; 322 323const struct comedi_lrange range_labpc_1200_ai = { 324 NUM_LABPC_1200_AI_RANGES, 325 { 326 BIP_RANGE(5), 327 BIP_RANGE(2.5), 328 BIP_RANGE(1), 329 BIP_RANGE(0.5), 330 BIP_RANGE(0.25), 331 BIP_RANGE(0.1), 332 BIP_RANGE(0.05), 333 UNI_RANGE(10), 334 UNI_RANGE(5), 335 UNI_RANGE(2), 336 UNI_RANGE(1), 337 UNI_RANGE(0.5), 338 UNI_RANGE(0.2), 339 UNI_RANGE(0.1), 340 } 341}; 342 343/* analog output ranges */ 344#define AO_RANGE_IS_UNIPOLAR 0x1 345static const struct comedi_lrange range_labpc_ao = { 346 2, 347 { 348 BIP_RANGE(5), 349 UNI_RANGE(10), 350 } 351}; 352 353/* functions that do inb/outb and readb/writeb so we can use 354 * function pointers to decide which to use */ 355static inline unsigned int labpc_inb(unsigned long address) 356{ 357 return inb(address); 358} 359 360static inline void labpc_outb(unsigned int byte, unsigned long address) 361{ 362 outb(byte, address); 363} 364 365static inline unsigned int labpc_readb(unsigned long address) 366{ 367 return readb((void *)address); 368} 369 370static inline void labpc_writeb(unsigned int byte, unsigned long address) 371{ 372 writeb(byte, (void *)address); 373} 374 375static const struct labpc_board_struct labpc_boards[] = { 376 { 377 .name = "lab-pc-1200", 378 .ai_speed = 10000, 379 .bustype = isa_bustype, 380 .register_layout = labpc_1200_layout, 381 .has_ao = 1, 382 .ai_range_table = &range_labpc_1200_ai, 383 .ai_range_code = labpc_1200_ai_gain_bits, 384 .ai_range_is_unipolar = labpc_1200_is_unipolar, 385 .ai_scan_up = 1, 386 .memory_mapped_io = 0, 387 }, 388 { 389 .name = "lab-pc-1200ai", 390 .ai_speed = 10000, 391 .bustype = isa_bustype, 392 .register_layout = labpc_1200_layout, 393 .has_ao = 0, 394 .ai_range_table = &range_labpc_1200_ai, 395 .ai_range_code = labpc_1200_ai_gain_bits, 396 .ai_range_is_unipolar = labpc_1200_is_unipolar, 397 .ai_scan_up = 1, 398 .memory_mapped_io = 0, 399 }, 400 { 401 .name = "lab-pc+", 402 .ai_speed = 12000, 403 .bustype = isa_bustype, 404 .register_layout = labpc_plus_layout, 405 .has_ao = 1, 406 .ai_range_table = &range_labpc_plus_ai, 407 .ai_range_code = labpc_plus_ai_gain_bits, 408 .ai_range_is_unipolar = labpc_plus_is_unipolar, 409 .ai_scan_up = 0, 410 .memory_mapped_io = 0, 411 }, 412#ifdef CONFIG_COMEDI_PCI 413 { 414 .name = "pci-1200", 415 .device_id = 0x161, 416 .ai_speed = 10000, 417 .bustype = pci_bustype, 418 .register_layout = labpc_1200_layout, 419 .has_ao = 1, 420 .ai_range_table = &range_labpc_1200_ai, 421 .ai_range_code = labpc_1200_ai_gain_bits, 422 .ai_range_is_unipolar = labpc_1200_is_unipolar, 423 .ai_scan_up = 1, 424 .memory_mapped_io = 1, 425 }, 426 /* dummy entry so pci board works when comedi_config is passed driver name */ 427 { 428 .name = DRV_NAME, 429 .bustype = pci_bustype, 430 }, 431#endif 432}; 433 434/* 435 * Useful for shorthand access to the particular board structure 436 */ 437#define thisboard ((struct labpc_board_struct *)dev->board_ptr) 438 439static const int dma_buffer_size = 0xff00; /* size in bytes of dma buffer */ 440static const int sample_size = 2; /* 2 bytes per sample */ 441 442#define devpriv ((struct labpc_private *)dev->private) 443 444static struct comedi_driver driver_labpc = { 445 .driver_name = DRV_NAME, 446 .module = THIS_MODULE, 447 .attach = labpc_attach, 448 .detach = labpc_common_detach, 449 .num_names = ARRAY_SIZE(labpc_boards), 450 .board_name = &labpc_boards[0].name, 451 .offset = sizeof(struct labpc_board_struct), 452}; 453 454#ifdef CONFIG_COMEDI_PCI 455static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = { 456 { 457 PCI_VENDOR_ID_NATINST, 0x161, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 458 0} 459}; 460 461MODULE_DEVICE_TABLE(pci, labpc_pci_table); 462#endif /* CONFIG_COMEDI_PCI */ 463 464static inline int labpc_counter_load(struct comedi_device *dev, 465 unsigned long base_address, 466 unsigned int counter_number, 467 unsigned int count, unsigned int mode) 468{ 469 if (thisboard->memory_mapped_io) 470 return i8254_mm_load((void *)base_address, 0, counter_number, 471 count, mode); 472 else 473 return i8254_load(base_address, 0, counter_number, count, mode); 474} 475 476int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, 477 unsigned int irq, unsigned int dma_chan) 478{ 479 struct comedi_subdevice *s; 480 int i; 481 unsigned long dma_flags, isr_flags; 482 short lsb, msb; 483 484 printk("comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, thisboard->name, 485 iobase); 486 if (irq) 487 printk(", irq %u", irq); 488 if (dma_chan) 489 printk(", dma %u", dma_chan); 490 printk("\n"); 491 492 if (iobase == 0) { 493 printk("io base address is zero!\n"); 494 return -EINVAL; 495 } 496 /* request io regions for isa boards */ 497 if (thisboard->bustype == isa_bustype) { 498 /* check if io addresses are available */ 499 if (!request_region(iobase, LABPC_SIZE, 500 driver_labpc.driver_name)) { 501 printk("I/O port conflict\n"); 502 return -EIO; 503 } 504 } 505 dev->iobase = iobase; 506 507 if (thisboard->memory_mapped_io) { 508 devpriv->read_byte = labpc_readb; 509 devpriv->write_byte = labpc_writeb; 510 } else { 511 devpriv->read_byte = labpc_inb; 512 devpriv->write_byte = labpc_outb; 513 } 514 /* initialize board's command registers */ 515 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 516 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 517 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 518 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 519 if (thisboard->register_layout == labpc_1200_layout) { 520 devpriv->write_byte(devpriv->command5_bits, 521 dev->iobase + COMMAND5_REG); 522 devpriv->write_byte(devpriv->command6_bits, 523 dev->iobase + COMMAND6_REG); 524 } 525 526 /* grab our IRQ */ 527 if (irq) { 528 isr_flags = 0; 529 if (thisboard->bustype == pci_bustype) 530 isr_flags |= IRQF_SHARED; 531 if (request_irq(irq, labpc_interrupt, isr_flags, 532 driver_labpc.driver_name, dev)) { 533 printk("unable to allocate irq %u\n", irq); 534 return -EINVAL; 535 } 536 } 537 dev->irq = irq; 538 539 /* grab dma channel */ 540 if (dma_chan > 3) { 541 printk(" invalid dma channel %u\n", dma_chan); 542 return -EINVAL; 543 } else if (dma_chan) { 544 /* allocate dma buffer */ 545 devpriv->dma_buffer = 546 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA); 547 if (devpriv->dma_buffer == NULL) { 548 printk(" failed to allocate dma buffer\n"); 549 return -ENOMEM; 550 } 551 if (request_dma(dma_chan, driver_labpc.driver_name)) { 552 printk(" failed to allocate dma channel %u\n", 553 dma_chan); 554 return -EINVAL; 555 } 556 devpriv->dma_chan = dma_chan; 557 dma_flags = claim_dma_lock(); 558 disable_dma(devpriv->dma_chan); 559 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); 560 release_dma_lock(dma_flags); 561 } 562 563 dev->board_name = thisboard->name; 564 565 if (alloc_subdevices(dev, 5) < 0) 566 return -ENOMEM; 567 568 /* analog input subdevice */ 569 s = dev->subdevices + 0; 570 dev->read_subdev = s; 571 s->type = COMEDI_SUBD_AI; 572 s->subdev_flags = 573 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ; 574 s->n_chan = 8; 575 s->len_chanlist = 8; 576 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 577 s->range_table = thisboard->ai_range_table; 578 s->do_cmd = labpc_ai_cmd; 579 s->do_cmdtest = labpc_ai_cmdtest; 580 s->insn_read = labpc_ai_rinsn; 581 s->cancel = labpc_cancel; 582 583 /* analog output */ 584 s = dev->subdevices + 1; 585 if (thisboard->has_ao) { 586/* Could provide command support, except it only has a one sample 587 * hardware buffer for analog output and no underrun flag. */ 588 s->type = COMEDI_SUBD_AO; 589 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; 590 s->n_chan = NUM_AO_CHAN; 591 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 592 s->range_table = &range_labpc_ao; 593 s->insn_read = labpc_ao_rinsn; 594 s->insn_write = labpc_ao_winsn; 595 /* initialize analog outputs to a known value */ 596 for (i = 0; i < s->n_chan; i++) { 597 devpriv->ao_value[i] = s->maxdata / 2; 598 lsb = devpriv->ao_value[i] & 0xff; 599 msb = (devpriv->ao_value[i] >> 8) & 0xff; 600 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); 601 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); 602 } 603 } else { 604 s->type = COMEDI_SUBD_UNUSED; 605 } 606 607 /* 8255 dio */ 608 s = dev->subdevices + 2; 609 /* if board uses io memory we have to give a custom callback function to the 8255 driver */ 610 if (thisboard->memory_mapped_io) 611 subdev_8255_init(dev, s, labpc_dio_mem_callback, 612 (unsigned long)(dev->iobase + DIO_BASE_REG)); 613 else 614 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG); 615 616 /* calibration subdevices for boards that have one */ 617 s = dev->subdevices + 3; 618 if (thisboard->register_layout == labpc_1200_layout) { 619 s->type = COMEDI_SUBD_CALIB; 620 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 621 s->n_chan = 16; 622 s->maxdata = 0xff; 623 s->insn_read = labpc_calib_read_insn; 624 s->insn_write = labpc_calib_write_insn; 625 626 for (i = 0; i < s->n_chan; i++) 627 write_caldac(dev, i, s->maxdata / 2); 628 } else 629 s->type = COMEDI_SUBD_UNUSED; 630 631 /* EEPROM */ 632 s = dev->subdevices + 4; 633 if (thisboard->register_layout == labpc_1200_layout) { 634 s->type = COMEDI_SUBD_MEMORY; 635 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 636 s->n_chan = EEPROM_SIZE; 637 s->maxdata = 0xff; 638 s->insn_read = labpc_eeprom_read_insn; 639 s->insn_write = labpc_eeprom_write_insn; 640 641 for (i = 0; i < EEPROM_SIZE; i++) 642 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); 643#ifdef LABPC_DEBUG 644 printk(" eeprom:"); 645 for (i = 0; i < EEPROM_SIZE; i++) { 646 printk(" %i:0x%x ", i, devpriv->eeprom_data[i]); 647 } 648 printk("\n"); 649#endif 650 } else 651 s->type = COMEDI_SUBD_UNUSED; 652 653 return 0; 654} 655 656static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) 657{ 658 unsigned long iobase = 0; 659 unsigned int irq = 0; 660 unsigned int dma_chan = 0; 661#ifdef CONFIG_COMEDI_PCI 662 int retval; 663#endif 664 665 /* allocate and initialize dev->private */ 666 if (alloc_private(dev, sizeof(struct labpc_private)) < 0) 667 return -ENOMEM; 668 669 /* get base address, irq etc. based on bustype */ 670 switch (thisboard->bustype) { 671 case isa_bustype: 672 iobase = it->options[0]; 673 irq = it->options[1]; 674 dma_chan = it->options[2]; 675 break; 676 case pci_bustype: 677#ifdef CONFIG_COMEDI_PCI 678 retval = labpc_find_device(dev, it->options[0], it->options[1]); 679 if (retval < 0) { 680 return retval; 681 } 682 retval = mite_setup(devpriv->mite); 683 if (retval < 0) 684 return retval; 685 iobase = (unsigned long)devpriv->mite->daq_io_addr; 686 irq = mite_irq(devpriv->mite); 687#else 688 printk(" this driver has not been built with PCI support.\n"); 689 return -EINVAL; 690#endif 691 break; 692 case pcmcia_bustype: 693 printk 694 (" this driver does not support pcmcia cards, use ni_labpc_cs.o\n"); 695 return -EINVAL; 696 break; 697 default: 698 printk("bug! couldn't determine board type\n"); 699 return -EINVAL; 700 break; 701 } 702 703 return labpc_common_attach(dev, iobase, irq, dma_chan); 704} 705 706/* adapted from ni_pcimio for finding mite based boards (pc-1200) */ 707#ifdef CONFIG_COMEDI_PCI 708static int labpc_find_device(struct comedi_device *dev, int bus, int slot) 709{ 710 struct mite_struct *mite; 711 int i; 712 for (mite = mite_devices; mite; mite = mite->next) { 713 if (mite->used) 714 continue; 715 /* if bus/slot are specified then make sure we have the right bus/slot */ 716 if (bus || slot) { 717 if (bus != mite->pcidev->bus->number 718 || slot != PCI_SLOT(mite->pcidev->devfn)) 719 continue; 720 } 721 for (i = 0; i < driver_labpc.num_names; i++) { 722 if (labpc_boards[i].bustype != pci_bustype) 723 continue; 724 if (mite_device_id(mite) == labpc_boards[i].device_id) { 725 devpriv->mite = mite; 726 /* fixup board pointer, in case we were using the dummy "ni_labpc" entry */ 727 dev->board_ptr = &labpc_boards[i]; 728 return 0; 729 } 730 } 731 } 732 printk("no device found\n"); 733 mite_list_devices(); 734 return -EIO; 735} 736#endif 737 738int labpc_common_detach(struct comedi_device *dev) 739{ 740 printk("comedi%d: ni_labpc: detach\n", dev->minor); 741 742 if (dev->subdevices) 743 subdev_8255_cleanup(dev, dev->subdevices + 2); 744 745 /* only free stuff if it has been allocated by _attach */ 746 if (devpriv->dma_buffer) 747 kfree(devpriv->dma_buffer); 748 if (devpriv->dma_chan) 749 free_dma(devpriv->dma_chan); 750 if (dev->irq) 751 free_irq(dev->irq, dev); 752 if (thisboard->bustype == isa_bustype && dev->iobase) 753 release_region(dev->iobase, LABPC_SIZE); 754#ifdef CONFIG_COMEDI_PCI 755 if (devpriv->mite) 756 mite_unsetup(devpriv->mite); 757#endif 758 759 return 0; 760}; 761 762static void labpc_clear_adc_fifo(const struct comedi_device *dev) 763{ 764 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 765 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 766 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 767} 768 769static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 770{ 771 unsigned long flags; 772 773 spin_lock_irqsave(&dev->spinlock, flags); 774 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 775 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 776 spin_unlock_irqrestore(&dev->spinlock, flags); 777 778 devpriv->command3_bits = 0; 779 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 780 781 return 0; 782} 783 784static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) 785{ 786 if (cmd->chanlist_len == 1) 787 return MODE_SINGLE_CHAN; 788 789 /* chanlist may be NULL during cmdtest. */ 790 if (cmd->chanlist == NULL) 791 return MODE_MULT_CHAN_UP; 792 793 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) 794 return MODE_SINGLE_CHAN_INTERVAL; 795 796 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) 797 return MODE_MULT_CHAN_UP; 798 799 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) 800 return MODE_MULT_CHAN_DOWN; 801 802 printk("ni_labpc: bug! this should never happen\n"); 803 804 return 0; 805} 806 807static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, 808 const struct comedi_cmd *cmd) 809{ 810 int mode, channel, range, aref, i; 811 812 if (cmd->chanlist == NULL) 813 return 0; 814 815 mode = labpc_ai_scan_mode(cmd); 816 817 if (mode == MODE_SINGLE_CHAN) 818 return 0; 819 820 if (mode == MODE_SINGLE_CHAN_INTERVAL) { 821 if (cmd->chanlist_len > 0xff) { 822 comedi_error(dev, 823 "ni_labpc: chanlist too long for single channel interval mode\n"); 824 return 1; 825 } 826 } 827 828 channel = CR_CHAN(cmd->chanlist[0]); 829 range = CR_RANGE(cmd->chanlist[0]); 830 aref = CR_AREF(cmd->chanlist[0]); 831 832 for (i = 0; i < cmd->chanlist_len; i++) { 833 834 switch (mode) { 835 case MODE_SINGLE_CHAN_INTERVAL: 836 if (CR_CHAN(cmd->chanlist[i]) != channel) { 837 comedi_error(dev, 838 "channel scanning order specified in chanlist is not supported by hardware.\n"); 839 return 1; 840 } 841 break; 842 case MODE_MULT_CHAN_UP: 843 if (CR_CHAN(cmd->chanlist[i]) != i) { 844 comedi_error(dev, 845 "channel scanning order specified in chanlist is not supported by hardware.\n"); 846 return 1; 847 } 848 break; 849 case MODE_MULT_CHAN_DOWN: 850 if (CR_CHAN(cmd->chanlist[i]) != 851 cmd->chanlist_len - i - 1) { 852 comedi_error(dev, 853 "channel scanning order specified in chanlist is not supported by hardware.\n"); 854 return 1; 855 } 856 break; 857 default: 858 printk("ni_labpc: bug! in chanlist check\n"); 859 return 1; 860 break; 861 } 862 863 if (CR_RANGE(cmd->chanlist[i]) != range) { 864 comedi_error(dev, 865 "entries in chanlist must all have the same range\n"); 866 return 1; 867 } 868 869 if (CR_AREF(cmd->chanlist[i]) != aref) { 870 comedi_error(dev, 871 "entries in chanlist must all have the same reference\n"); 872 return 1; 873 } 874 } 875 876 return 0; 877} 878 879static int labpc_use_continuous_mode(const struct comedi_cmd *cmd) 880{ 881 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN) 882 return 1; 883 884 if (cmd->scan_begin_src == TRIG_FOLLOW) 885 return 1; 886 887 return 0; 888} 889 890static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd) 891{ 892 if (cmd->convert_src != TRIG_TIMER) 893 return 0; 894 895 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 896 cmd->scan_begin_src == TRIG_TIMER) 897 return cmd->scan_begin_arg; 898 899 return cmd->convert_arg; 900} 901 902static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns) 903{ 904 if (cmd->convert_src != TRIG_TIMER) 905 return; 906 907 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 908 cmd->scan_begin_src == TRIG_TIMER) { 909 cmd->scan_begin_arg = ns; 910 if (cmd->convert_arg > cmd->scan_begin_arg) 911 cmd->convert_arg = cmd->scan_begin_arg; 912 } else 913 cmd->convert_arg = ns; 914} 915 916static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd) 917{ 918 if (cmd->scan_begin_src != TRIG_TIMER) 919 return 0; 920 921 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 922 cmd->convert_src == TRIG_TIMER) 923 return 0; 924 925 return cmd->scan_begin_arg; 926} 927 928static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns) 929{ 930 if (cmd->scan_begin_src != TRIG_TIMER) 931 return; 932 933 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 934 cmd->convert_src == TRIG_TIMER) 935 return; 936 937 cmd->scan_begin_arg = ns; 938} 939 940static int labpc_ai_cmdtest(struct comedi_device *dev, 941 struct comedi_subdevice *s, struct comedi_cmd *cmd) 942{ 943 int err = 0; 944 int tmp, tmp2; 945 int stop_mask; 946 947 /* step 1: make sure trigger sources are trivially valid */ 948 949 tmp = cmd->start_src; 950 cmd->start_src &= TRIG_NOW | TRIG_EXT; 951 if (!cmd->start_src || tmp != cmd->start_src) 952 err++; 953 954 tmp = cmd->scan_begin_src; 955 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT; 956 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 957 err++; 958 959 tmp = cmd->convert_src; 960 cmd->convert_src &= TRIG_TIMER | TRIG_EXT; 961 if (!cmd->convert_src || tmp != cmd->convert_src) 962 err++; 963 964 tmp = cmd->scan_end_src; 965 cmd->scan_end_src &= TRIG_COUNT; 966 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 967 err++; 968 969 tmp = cmd->stop_src; 970 stop_mask = TRIG_COUNT | TRIG_NONE; 971 if (thisboard->register_layout == labpc_1200_layout) 972 stop_mask |= TRIG_EXT; 973 cmd->stop_src &= stop_mask; 974 if (!cmd->stop_src || tmp != cmd->stop_src) 975 err++; 976 977 if (err) 978 return 1; 979 980 /* step 2: make sure trigger sources are unique and mutually compatible */ 981 982 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) 983 err++; 984 if (cmd->scan_begin_src != TRIG_TIMER && 985 cmd->scan_begin_src != TRIG_FOLLOW && 986 cmd->scan_begin_src != TRIG_EXT) 987 err++; 988 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT) 989 err++; 990 if (cmd->stop_src != TRIG_COUNT && 991 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE) 992 err++; 993 994 /* can't have external stop and start triggers at once */ 995 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) 996 err++; 997 998 if (err) 999 return 2; 1000 1001 /* step 3: make sure arguments are trivially compatible */ 1002 1003 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) { 1004 cmd->start_arg = 0; 1005 err++; 1006 } 1007 1008 if (!cmd->chanlist_len) { 1009 err++; 1010 } 1011 if (cmd->scan_end_arg != cmd->chanlist_len) { 1012 cmd->scan_end_arg = cmd->chanlist_len; 1013 err++; 1014 } 1015 1016 if (cmd->convert_src == TRIG_TIMER) { 1017 if (cmd->convert_arg < thisboard->ai_speed) { 1018 cmd->convert_arg = thisboard->ai_speed; 1019 err++; 1020 } 1021 } 1022 /* make sure scan timing is not too fast */ 1023 if (cmd->scan_begin_src == TRIG_TIMER) { 1024 if (cmd->convert_src == TRIG_TIMER && 1025 cmd->scan_begin_arg < 1026 cmd->convert_arg * cmd->chanlist_len) { 1027 cmd->scan_begin_arg = 1028 cmd->convert_arg * cmd->chanlist_len; 1029 err++; 1030 } 1031 if (cmd->scan_begin_arg < 1032 thisboard->ai_speed * cmd->chanlist_len) { 1033 cmd->scan_begin_arg = 1034 thisboard->ai_speed * cmd->chanlist_len; 1035 err++; 1036 } 1037 } 1038 /* stop source */ 1039 switch (cmd->stop_src) { 1040 case TRIG_COUNT: 1041 if (!cmd->stop_arg) { 1042 cmd->stop_arg = 1; 1043 err++; 1044 } 1045 break; 1046 case TRIG_NONE: 1047 if (cmd->stop_arg != 0) { 1048 cmd->stop_arg = 0; 1049 err++; 1050 } 1051 break; 1052 /* TRIG_EXT doesn't care since it doesn't trigger off a numbered channel */ 1053 default: 1054 break; 1055 } 1056 1057 if (err) 1058 return 3; 1059 1060 /* step 4: fix up any arguments */ 1061 1062 tmp = cmd->convert_arg; 1063 tmp2 = cmd->scan_begin_arg; 1064 labpc_adc_timing(dev, cmd); 1065 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) 1066 err++; 1067 1068 if (err) 1069 return 4; 1070 1071 if (labpc_ai_chanlist_invalid(dev, cmd)) 1072 return 5; 1073 1074 return 0; 1075} 1076 1077static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 1078{ 1079 int channel, range, aref; 1080 unsigned long irq_flags; 1081 int ret; 1082 struct comedi_async *async = s->async; 1083 struct comedi_cmd *cmd = &async->cmd; 1084 enum transfer_type xfer; 1085 unsigned long flags; 1086 1087 if (!dev->irq) { 1088 comedi_error(dev, "no irq assigned, cannot perform command"); 1089 return -1; 1090 } 1091 1092 range = CR_RANGE(cmd->chanlist[0]); 1093 aref = CR_AREF(cmd->chanlist[0]); 1094 1095 /* make sure board is disabled before setting up aquisition */ 1096 spin_lock_irqsave(&dev->spinlock, flags); 1097 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1098 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1099 spin_unlock_irqrestore(&dev->spinlock, flags); 1100 1101 devpriv->command3_bits = 0; 1102 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1103 1104 /* initialize software conversion count */ 1105 if (cmd->stop_src == TRIG_COUNT) { 1106 devpriv->count = cmd->stop_arg * cmd->chanlist_len; 1107 } 1108 /* setup hardware conversion counter */ 1109 if (cmd->stop_src == TRIG_EXT) { 1110 /* load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0 */ 1111 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1112 1, 3, 0); 1113 if (ret < 0) { 1114 comedi_error(dev, "error loading counter a1"); 1115 return -1; 1116 } 1117 } else /* otherwise, just put a1 in mode 0 with no count to set its output low */ 1118 devpriv->write_byte(INIT_A1_BITS, 1119 dev->iobase + COUNTER_A_CONTROL_REG); 1120 1121 /* figure out what method we will use to transfer data */ 1122 if (devpriv->dma_chan && /* need a dma channel allocated */ 1123 /* dma unsafe at RT priority, and too much setup time for TRIG_WAKE_EOS for */ 1124 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 && 1125 /* only available on the isa boards */ 1126 thisboard->bustype == isa_bustype) { 1127 xfer = isa_dma_transfer; 1128 } else if (thisboard->register_layout == labpc_1200_layout && /* pc-plus has no fifo-half full interrupt */ 1129 /* wake-end-of-scan should interrupt on fifo not empty */ 1130 (cmd->flags & TRIG_WAKE_EOS) == 0 && 1131 /* make sure we are taking more than just a few points */ 1132 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { 1133 xfer = fifo_half_full_transfer; 1134 } else 1135 xfer = fifo_not_empty_transfer; 1136 devpriv->current_transfer = xfer; 1137 1138 /* setup command6 register for 1200 boards */ 1139 if (thisboard->register_layout == labpc_1200_layout) { 1140 /* reference inputs to ground or common? */ 1141 if (aref != AREF_GROUND) 1142 devpriv->command6_bits |= ADC_COMMON_BIT; 1143 else 1144 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1145 /* bipolar or unipolar range? */ 1146 if (thisboard->ai_range_is_unipolar[range]) 1147 devpriv->command6_bits |= ADC_UNIP_BIT; 1148 else 1149 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1150 /* interrupt on fifo half full? */ 1151 if (xfer == fifo_half_full_transfer) 1152 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT; 1153 else 1154 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1155 /* enable interrupt on counter a1 terminal count? */ 1156 if (cmd->stop_src == TRIG_EXT) 1157 devpriv->command6_bits |= A1_INTR_EN_BIT; 1158 else 1159 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1160 /* are we scanning up or down through channels? */ 1161 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1162 devpriv->command6_bits |= ADC_SCAN_UP_BIT; 1163 else 1164 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT; 1165 /* write to register */ 1166 devpriv->write_byte(devpriv->command6_bits, 1167 dev->iobase + COMMAND6_REG); 1168 } 1169 1170 /* setup channel list, etc (command1 register) */ 1171 devpriv->command1_bits = 0; 1172 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1173 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); 1174 else 1175 channel = CR_CHAN(cmd->chanlist[0]); 1176 /* munge channel bits for differential / scan disabled mode */ 1177 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF) 1178 channel *= 2; 1179 devpriv->command1_bits |= ADC_CHAN_BITS(channel); 1180 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1181 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1182 /* manual says to set scan enable bit on second pass */ 1183 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP || 1184 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) { 1185 devpriv->command1_bits |= ADC_SCAN_EN_BIT; 1186 /* need a brief delay before enabling scan, or scan list will get screwed when you switch 1187 * between scan up to scan down mode - dunno why */ 1188 udelay(1); 1189 devpriv->write_byte(devpriv->command1_bits, 1190 dev->iobase + COMMAND1_REG); 1191 } 1192 /* setup any external triggering/pacing (command4 register) */ 1193 devpriv->command4_bits = 0; 1194 if (cmd->convert_src != TRIG_EXT) 1195 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1196 /* XXX should discard first scan when using interval scanning 1197 * since manual says it is not synced with scan clock */ 1198 if (labpc_use_continuous_mode(cmd) == 0) { 1199 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT; 1200 if (cmd->scan_begin_src == TRIG_EXT) 1201 devpriv->command4_bits |= EXT_SCAN_EN_BIT; 1202 } 1203 /* single-ended/differential */ 1204 if (aref == AREF_DIFF) 1205 devpriv->command4_bits |= ADC_DIFF_BIT; 1206 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1207 1208 devpriv->write_byte(cmd->chanlist_len, 1209 dev->iobase + INTERVAL_COUNT_REG); 1210 /* load count */ 1211 devpriv->write_byte(INTERVAL_LOAD_BITS, 1212 dev->iobase + INTERVAL_LOAD_REG); 1213 1214 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) { 1215 /* set up pacing */ 1216 labpc_adc_timing(dev, cmd); 1217 /* load counter b0 in mode 3 */ 1218 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1219 0, devpriv->divisor_b0, 3); 1220 if (ret < 0) { 1221 comedi_error(dev, "error loading counter b0"); 1222 return -1; 1223 } 1224 } 1225 /* set up conversion pacing */ 1226 if (labpc_ai_convert_period(cmd)) { 1227 /* load counter a0 in mode 2 */ 1228 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1229 0, devpriv->divisor_a0, 2); 1230 if (ret < 0) { 1231 comedi_error(dev, "error loading counter a0"); 1232 return -1; 1233 } 1234 } else 1235 devpriv->write_byte(INIT_A0_BITS, 1236 dev->iobase + COUNTER_A_CONTROL_REG); 1237 1238 /* set up scan pacing */ 1239 if (labpc_ai_scan_period(cmd)) { 1240 /* load counter b1 in mode 2 */ 1241 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1242 1, devpriv->divisor_b1, 2); 1243 if (ret < 0) { 1244 comedi_error(dev, "error loading counter b1"); 1245 return -1; 1246 } 1247 } 1248 1249 labpc_clear_adc_fifo(dev); 1250 1251 /* set up dma transfer */ 1252 if (xfer == isa_dma_transfer) { 1253 irq_flags = claim_dma_lock(); 1254 disable_dma(devpriv->dma_chan); 1255 /* clear flip-flop to make sure 2-byte registers for 1256 * count and address get set correctly */ 1257 clear_dma_ff(devpriv->dma_chan); 1258 set_dma_addr(devpriv->dma_chan, 1259 virt_to_bus(devpriv->dma_buffer)); 1260 /* set appropriate size of transfer */ 1261 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd); 1262 if (cmd->stop_src == TRIG_COUNT && 1263 devpriv->count * sample_size < devpriv->dma_transfer_size) { 1264 devpriv->dma_transfer_size = 1265 devpriv->count * sample_size; 1266 } 1267 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); 1268 enable_dma(devpriv->dma_chan); 1269 release_dma_lock(irq_flags); 1270 /* enable board's dma */ 1271 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT; 1272 } else 1273 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT; 1274 1275 /* enable error interrupts */ 1276 devpriv->command3_bits |= ERR_INTR_EN_BIT; 1277 /* enable fifo not empty interrupt? */ 1278 if (xfer == fifo_not_empty_transfer) 1279 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT; 1280 else 1281 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT; 1282 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1283 1284 /* startup aquisition */ 1285 1286 /* command2 reg */ 1287 /* use 2 cascaded counters for pacing */ 1288 spin_lock_irqsave(&dev->spinlock, flags); 1289 devpriv->command2_bits |= CASCADE_BIT; 1290 switch (cmd->start_src) { 1291 case TRIG_EXT: 1292 devpriv->command2_bits |= HWTRIG_BIT; 1293 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT; 1294 break; 1295 case TRIG_NOW: 1296 devpriv->command2_bits |= SWTRIG_BIT; 1297 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT; 1298 break; 1299 default: 1300 comedi_error(dev, "bug with start_src"); 1301 return -1; 1302 break; 1303 } 1304 switch (cmd->stop_src) { 1305 case TRIG_EXT: 1306 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT; 1307 break; 1308 case TRIG_COUNT: 1309 case TRIG_NONE: 1310 break; 1311 default: 1312 comedi_error(dev, "bug with stop_src"); 1313 return -1; 1314 } 1315 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1316 spin_unlock_irqrestore(&dev->spinlock, flags); 1317 1318 return 0; 1319} 1320 1321/* interrupt service routine */ 1322static irqreturn_t labpc_interrupt(int irq, void *d) 1323{ 1324 struct comedi_device *dev = d; 1325 struct comedi_subdevice *s = dev->read_subdev; 1326 struct comedi_async *async; 1327 struct comedi_cmd *cmd; 1328 1329 if (dev->attached == 0) { 1330 comedi_error(dev, "premature interrupt"); 1331 return IRQ_HANDLED; 1332 } 1333 1334 async = s->async; 1335 cmd = &async->cmd; 1336 async->events = 0; 1337 1338 /* read board status */ 1339 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1340 if (thisboard->register_layout == labpc_1200_layout) 1341 devpriv->status2_bits = 1342 devpriv->read_byte(dev->iobase + STATUS2_REG); 1343 1344 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT | 1345 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0 1346 && (devpriv->status2_bits & A1_TC_BIT) == 0 1347 && (devpriv->status2_bits & FNHF_BIT)) { 1348 return IRQ_NONE; 1349 } 1350 1351 if (devpriv->status1_bits & OVERRUN_BIT) { 1352 /* clear error interrupt */ 1353 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1354 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1355 comedi_event(dev, s); 1356 comedi_error(dev, "overrun"); 1357 return IRQ_HANDLED; 1358 } 1359 1360 if (devpriv->current_transfer == isa_dma_transfer) { 1361 /* if a dma terminal count of external stop trigger has occurred */ 1362 if (devpriv->status1_bits & DMATC_BIT || 1363 (thisboard->register_layout == labpc_1200_layout 1364 && devpriv->status2_bits & A1_TC_BIT)) { 1365 handle_isa_dma(dev); 1366 } 1367 } else 1368 labpc_drain_fifo(dev); 1369 1370 if (devpriv->status1_bits & TIMER_BIT) { 1371 comedi_error(dev, "handled timer interrupt?"); 1372 /* clear it */ 1373 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); 1374 } 1375 1376 if (devpriv->status1_bits & OVERFLOW_BIT) { 1377 /* clear error interrupt */ 1378 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1379 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1380 comedi_event(dev, s); 1381 comedi_error(dev, "overflow"); 1382 return IRQ_HANDLED; 1383 } 1384 /* handle external stop trigger */ 1385 if (cmd->stop_src == TRIG_EXT) { 1386 if (devpriv->status2_bits & A1_TC_BIT) { 1387 labpc_drain_dregs(dev); 1388 labpc_cancel(dev, s); 1389 async->events |= COMEDI_CB_EOA; 1390 } 1391 } 1392 1393 /* TRIG_COUNT end of acquisition */ 1394 if (cmd->stop_src == TRIG_COUNT) { 1395 if (devpriv->count == 0) { 1396 labpc_cancel(dev, s); 1397 async->events |= COMEDI_CB_EOA; 1398 } 1399 } 1400 1401 comedi_event(dev, s); 1402 return IRQ_HANDLED; 1403} 1404 1405/* read all available samples from ai fifo */ 1406static int labpc_drain_fifo(struct comedi_device *dev) 1407{ 1408 unsigned int lsb, msb; 1409 short data; 1410 struct comedi_async *async = dev->read_subdev->async; 1411 const int timeout = 10000; 1412 unsigned int i; 1413 1414 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1415 1416 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout; 1417 i++) { 1418 /* quit if we have all the data we want */ 1419 if (async->cmd.stop_src == TRIG_COUNT) { 1420 if (devpriv->count == 0) 1421 break; 1422 devpriv->count--; 1423 } 1424 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1425 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1426 data = (msb << 8) | lsb; 1427 cfc_write_to_buffer(dev->read_subdev, data); 1428 devpriv->status1_bits = 1429 devpriv->read_byte(dev->iobase + STATUS1_REG); 1430 } 1431 if (i == timeout) { 1432 comedi_error(dev, "ai timeout, fifo never empties"); 1433 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1434 return -1; 1435 } 1436 1437 return 0; 1438} 1439 1440static void labpc_drain_dma(struct comedi_device *dev) 1441{ 1442 struct comedi_subdevice *s = dev->read_subdev; 1443 struct comedi_async *async = s->async; 1444 int status; 1445 unsigned long flags; 1446 unsigned int max_points, num_points, residue, leftover; 1447 int i; 1448 1449 status = devpriv->status1_bits; 1450 1451 flags = claim_dma_lock(); 1452 disable_dma(devpriv->dma_chan); 1453 /* clear flip-flop to make sure 2-byte registers for 1454 * count and address get set correctly */ 1455 clear_dma_ff(devpriv->dma_chan); 1456 1457 /* figure out how many points to read */ 1458 max_points = devpriv->dma_transfer_size / sample_size; 1459 /* residue is the number of points left to be done on the dma 1460 * transfer. It should always be zero at this point unless 1461 * the stop_src is set to external triggering. 1462 */ 1463 residue = get_dma_residue(devpriv->dma_chan) / sample_size; 1464 num_points = max_points - residue; 1465 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) 1466 num_points = devpriv->count; 1467 1468 /* figure out how many points will be stored next time */ 1469 leftover = 0; 1470 if (async->cmd.stop_src != TRIG_COUNT) { 1471 leftover = devpriv->dma_transfer_size / sample_size; 1472 } else if (devpriv->count > num_points) { 1473 leftover = devpriv->count - num_points; 1474 if (leftover > max_points) 1475 leftover = max_points; 1476 } 1477 1478 /* write data to comedi buffer */ 1479 for (i = 0; i < num_points; i++) { 1480 cfc_write_to_buffer(s, devpriv->dma_buffer[i]); 1481 } 1482 if (async->cmd.stop_src == TRIG_COUNT) 1483 devpriv->count -= num_points; 1484 1485 /* set address and count for next transfer */ 1486 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); 1487 set_dma_count(devpriv->dma_chan, leftover * sample_size); 1488 release_dma_lock(flags); 1489 1490 async->events |= COMEDI_CB_BLOCK; 1491} 1492 1493static void handle_isa_dma(struct comedi_device *dev) 1494{ 1495 labpc_drain_dma(dev); 1496 1497 enable_dma(devpriv->dma_chan); 1498 1499 /* clear dma tc interrupt */ 1500 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); 1501} 1502 1503/* makes sure all data aquired by board is transfered to comedi (used 1504 * when aquisition is terminated by stop_src == TRIG_EXT). */ 1505static void labpc_drain_dregs(struct comedi_device *dev) 1506{ 1507 if (devpriv->current_transfer == isa_dma_transfer) 1508 labpc_drain_dma(dev); 1509 1510 labpc_drain_fifo(dev); 1511} 1512 1513static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1514 struct comedi_insn *insn, unsigned int *data) 1515{ 1516 int i, n; 1517 int chan, range; 1518 int lsb, msb; 1519 int timeout = 1000; 1520 unsigned long flags; 1521 1522 /* disable timed conversions */ 1523 spin_lock_irqsave(&dev->spinlock, flags); 1524 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1525 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1526 spin_unlock_irqrestore(&dev->spinlock, flags); 1527 1528 /* disable interrupt generation and dma */ 1529 devpriv->command3_bits = 0; 1530 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1531 1532 /* set gain and channel */ 1533 devpriv->command1_bits = 0; 1534 chan = CR_CHAN(insn->chanspec); 1535 range = CR_RANGE(insn->chanspec); 1536 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1537 /* munge channel bits for differential/scan disabled mode */ 1538 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1539 chan *= 2; 1540 devpriv->command1_bits |= ADC_CHAN_BITS(chan); 1541 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1542 1543 /* setup command6 register for 1200 boards */ 1544 if (thisboard->register_layout == labpc_1200_layout) { 1545 /* reference inputs to ground or common? */ 1546 if (CR_AREF(insn->chanspec) != AREF_GROUND) 1547 devpriv->command6_bits |= ADC_COMMON_BIT; 1548 else 1549 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1550 /* bipolar or unipolar range? */ 1551 if (thisboard->ai_range_is_unipolar[range]) 1552 devpriv->command6_bits |= ADC_UNIP_BIT; 1553 else 1554 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1555 /* don't interrupt on fifo half full */ 1556 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1557 /* don't enable interrupt on counter a1 terminal count? */ 1558 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1559 /* write to register */ 1560 devpriv->write_byte(devpriv->command6_bits, 1561 dev->iobase + COMMAND6_REG); 1562 } 1563 /* setup command4 register */ 1564 devpriv->command4_bits = 0; 1565 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1566 /* single-ended/differential */ 1567 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1568 devpriv->command4_bits |= ADC_DIFF_BIT; 1569 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1570 1571 /* initialize pacer counter output to make sure it doesn't cause any problems */ 1572 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG); 1573 1574 labpc_clear_adc_fifo(dev); 1575 1576 for (n = 0; n < insn->n; n++) { 1577 /* trigger conversion */ 1578 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG); 1579 1580 for (i = 0; i < timeout; i++) { 1581 if (devpriv->read_byte(dev->iobase + 1582 STATUS1_REG) & DATA_AVAIL_BIT) 1583 break; 1584 udelay(1); 1585 } 1586 if (i == timeout) { 1587 comedi_error(dev, "timeout"); 1588 return -ETIME; 1589 } 1590 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1591 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1592 data[n] = (msb << 8) | lsb; 1593 } 1594 1595 return n; 1596} 1597 1598/* analog output insn */ 1599static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 1600 struct comedi_insn *insn, unsigned int *data) 1601{ 1602 int channel, range; 1603 unsigned long flags; 1604 int lsb, msb; 1605 1606 channel = CR_CHAN(insn->chanspec); 1607 1608 /* turn off pacing of analog output channel */ 1609 /* note: hardware bug in daqcard-1200 means pacing cannot 1610 * be independently enabled/disabled for its the two channels */ 1611 spin_lock_irqsave(&dev->spinlock, flags); 1612 devpriv->command2_bits &= ~DAC_PACED_BIT(channel); 1613 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1614 spin_unlock_irqrestore(&dev->spinlock, flags); 1615 1616 /* set range */ 1617 if (thisboard->register_layout == labpc_1200_layout) { 1618 range = CR_RANGE(insn->chanspec); 1619 if (range & AO_RANGE_IS_UNIPOLAR) 1620 devpriv->command6_bits |= DAC_UNIP_BIT(channel); 1621 else 1622 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel); 1623 /* write to register */ 1624 devpriv->write_byte(devpriv->command6_bits, 1625 dev->iobase + COMMAND6_REG); 1626 } 1627 /* send data */ 1628 lsb = data[0] & 0xff; 1629 msb = (data[0] >> 8) & 0xff; 1630 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); 1631 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); 1632 1633 /* remember value for readback */ 1634 devpriv->ao_value[channel] = data[0]; 1635 1636 return 1; 1637} 1638 1639/* analog output readback insn */ 1640static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1641 struct comedi_insn *insn, unsigned int *data) 1642{ 1643 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; 1644 1645 return 1; 1646} 1647 1648static int labpc_calib_read_insn(struct comedi_device *dev, 1649 struct comedi_subdevice *s, 1650 struct comedi_insn *insn, unsigned int *data) 1651{ 1652 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)]; 1653 1654 return 1; 1655} 1656 1657static int labpc_calib_write_insn(struct comedi_device *dev, 1658 struct comedi_subdevice *s, 1659 struct comedi_insn *insn, unsigned int *data) 1660{ 1661 int channel = CR_CHAN(insn->chanspec); 1662 1663 write_caldac(dev, channel, data[0]); 1664 return 1; 1665} 1666 1667static int labpc_eeprom_read_insn(struct comedi_device *dev, 1668 struct comedi_subdevice *s, 1669 struct comedi_insn *insn, unsigned int *data) 1670{ 1671 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)]; 1672 1673 return 1; 1674} 1675 1676static int labpc_eeprom_write_insn(struct comedi_device *dev, 1677 struct comedi_subdevice *s, 1678 struct comedi_insn *insn, unsigned int *data) 1679{ 1680 int channel = CR_CHAN(insn->chanspec); 1681 int ret; 1682 1683 /* only allow writes to user area of eeprom */ 1684 if (channel < 16 || channel > 127) { 1685 printk 1686 ("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)"); 1687 return -EINVAL; 1688 } 1689 1690 ret = labpc_eeprom_write(dev, channel, data[0]); 1691 if (ret < 0) 1692 return ret; 1693 1694 return 1; 1695} 1696 1697/* utility function that suggests a dma transfer size in bytes */ 1698static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd) 1699{ 1700 unsigned int size; 1701 unsigned int freq; 1702 1703 if (cmd.convert_src == TRIG_TIMER) 1704 freq = 1000000000 / cmd.convert_arg; 1705 /* return some default value */ 1706 else 1707 freq = 0xffffffff; 1708 1709 /* make buffer fill in no more than 1/3 second */ 1710 size = (freq / 3) * sample_size; 1711 1712 /* set a minimum and maximum size allowed */ 1713 if (size > dma_buffer_size) 1714 size = dma_buffer_size - dma_buffer_size % sample_size; 1715 else if (size < sample_size) 1716 size = sample_size; 1717 1718 return size; 1719} 1720 1721/* figures out what counter values to use based on command */ 1722static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) 1723{ 1724 const int max_counter_value = 0x10000; /* max value for 16 bit counter in mode 2 */ 1725 const int min_counter_value = 2; /* min value for 16 bit counter in mode 2 */ 1726 unsigned int base_period; 1727 1728 /* if both convert and scan triggers are TRIG_TIMER, then they both rely on counter b0 */ 1729 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) { 1730 /* pick the lowest b0 divisor value we can (for maximum input clock speed on convert and scan counters) */ 1731 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) / 1732 (LABPC_TIMER_BASE * max_counter_value) + 1; 1733 if (devpriv->divisor_b0 < min_counter_value) 1734 devpriv->divisor_b0 = min_counter_value; 1735 if (devpriv->divisor_b0 > max_counter_value) 1736 devpriv->divisor_b0 = max_counter_value; 1737 1738 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; 1739 1740 /* set a0 for conversion frequency and b1 for scan frequency */ 1741 switch (cmd->flags & TRIG_ROUND_MASK) { 1742 default: 1743 case TRIG_ROUND_NEAREST: 1744 devpriv->divisor_a0 = 1745 (labpc_ai_convert_period(cmd) + 1746 (base_period / 2)) / base_period; 1747 devpriv->divisor_b1 = 1748 (labpc_ai_scan_period(cmd) + 1749 (base_period / 2)) / base_period; 1750 break; 1751 case TRIG_ROUND_UP: 1752 devpriv->divisor_a0 = 1753 (labpc_ai_convert_period(cmd) + (base_period - 1754 1)) / base_period; 1755 devpriv->divisor_b1 = 1756 (labpc_ai_scan_period(cmd) + (base_period - 1757 1)) / base_period; 1758 break; 1759 case TRIG_ROUND_DOWN: 1760 devpriv->divisor_a0 = 1761 labpc_ai_convert_period(cmd) / base_period; 1762 devpriv->divisor_b1 = 1763 labpc_ai_scan_period(cmd) / base_period; 1764 break; 1765 } 1766 /* make sure a0 and b1 values are acceptable */ 1767 if (devpriv->divisor_a0 < min_counter_value) 1768 devpriv->divisor_a0 = min_counter_value; 1769 if (devpriv->divisor_a0 > max_counter_value) 1770 devpriv->divisor_a0 = max_counter_value; 1771 if (devpriv->divisor_b1 < min_counter_value) 1772 devpriv->divisor_b1 = min_counter_value; 1773 if (devpriv->divisor_b1 > max_counter_value) 1774 devpriv->divisor_b1 = max_counter_value; 1775 /* write corrected timings to command */ 1776 labpc_set_ai_convert_period(cmd, 1777 base_period * devpriv->divisor_a0); 1778 labpc_set_ai_scan_period(cmd, 1779 base_period * devpriv->divisor_b1); 1780 /* if only one TRIG_TIMER is used, we can employ the generic cascaded timing functions */ 1781 } else if (labpc_ai_scan_period(cmd)) { 1782 unsigned int scan_period; 1783 1784 scan_period = labpc_ai_scan_period(cmd); 1785 /* calculate cascaded counter values that give desired scan timing */ 1786 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1787 &(devpriv->divisor_b1), 1788 &(devpriv->divisor_b0), 1789 &scan_period, 1790 cmd->flags & TRIG_ROUND_MASK); 1791 labpc_set_ai_scan_period(cmd, scan_period); 1792 } else if (labpc_ai_convert_period(cmd)) { 1793 unsigned int convert_period; 1794 1795 convert_period = labpc_ai_convert_period(cmd); 1796 /* calculate cascaded counter values that give desired conversion timing */ 1797 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1798 &(devpriv->divisor_a0), 1799 &(devpriv->divisor_b0), 1800 &convert_period, 1801 cmd->flags & TRIG_ROUND_MASK); 1802 labpc_set_ai_convert_period(cmd, convert_period); 1803 } 1804} 1805 1806static int labpc_dio_mem_callback(int dir, int port, int data, 1807 unsigned long iobase) 1808{ 1809 if (dir) { 1810 writeb(data, (void *)(iobase + port)); 1811 return 0; 1812 } else { 1813 return readb((void *)(iobase + port)); 1814 } 1815} 1816 1817/* lowlevel write to eeprom/dac */ 1818static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 1819 unsigned int value_width) 1820{ 1821 int i; 1822 1823 for (i = 1; i <= value_width; i++) { 1824 /* clear serial clock */ 1825 devpriv->command5_bits &= ~SCLOCK_BIT; 1826 /* send bits most significant bit first */ 1827 if (value & (1 << (value_width - i))) 1828 devpriv->command5_bits |= SDATA_BIT; 1829 else 1830 devpriv->command5_bits &= ~SDATA_BIT; 1831 udelay(1); 1832 devpriv->write_byte(devpriv->command5_bits, 1833 dev->iobase + COMMAND5_REG); 1834 /* set clock to load bit */ 1835 devpriv->command5_bits |= SCLOCK_BIT; 1836 udelay(1); 1837 devpriv->write_byte(devpriv->command5_bits, 1838 dev->iobase + COMMAND5_REG); 1839 } 1840} 1841 1842/* lowlevel read from eeprom */ 1843static unsigned int labpc_serial_in(struct comedi_device *dev) 1844{ 1845 unsigned int value = 0; 1846 int i; 1847 const int value_width = 8; /* number of bits wide values are */ 1848 1849 for (i = 1; i <= value_width; i++) { 1850 /* set serial clock */ 1851 devpriv->command5_bits |= SCLOCK_BIT; 1852 udelay(1); 1853 devpriv->write_byte(devpriv->command5_bits, 1854 dev->iobase + COMMAND5_REG); 1855 /* clear clock bit */ 1856 devpriv->command5_bits &= ~SCLOCK_BIT; 1857 udelay(1); 1858 devpriv->write_byte(devpriv->command5_bits, 1859 dev->iobase + COMMAND5_REG); 1860 /* read bits most significant bit first */ 1861 udelay(1); 1862 devpriv->status2_bits = 1863 devpriv->read_byte(dev->iobase + STATUS2_REG); 1864 if (devpriv->status2_bits & EEPROM_OUT_BIT) { 1865 value |= 1 << (value_width - i); 1866 } 1867 } 1868 1869 return value; 1870} 1871 1872static unsigned int labpc_eeprom_read(struct comedi_device *dev, 1873 unsigned int address) 1874{ 1875 unsigned int value; 1876 const int read_instruction = 0x3; /* bits to tell eeprom to expect a read */ 1877 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1878 1879 /* enable read/write to eeprom */ 1880 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1881 udelay(1); 1882 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1883 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1884 udelay(1); 1885 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1886 1887 /* send read instruction */ 1888 labpc_serial_out(dev, read_instruction, write_length); 1889 /* send 8 bit address to read from */ 1890 labpc_serial_out(dev, address, write_length); 1891 /* read result */ 1892 value = labpc_serial_in(dev); 1893 1894 /* disable read/write to eeprom */ 1895 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1896 udelay(1); 1897 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1898 1899 return value; 1900} 1901 1902static unsigned int labpc_eeprom_write(struct comedi_device *dev, 1903 unsigned int address, unsigned int value) 1904{ 1905 const int write_enable_instruction = 0x6; 1906 const int write_instruction = 0x2; 1907 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1908 const int write_in_progress_bit = 0x1; 1909 const int timeout = 10000; 1910 int i; 1911 1912 /* make sure there isn't already a write in progress */ 1913 for (i = 0; i < timeout; i++) { 1914 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == 1915 0) 1916 break; 1917 } 1918 if (i == timeout) { 1919 comedi_error(dev, "eeprom write timed out"); 1920 return -ETIME; 1921 } 1922 /* update software copy of eeprom */ 1923 devpriv->eeprom_data[address] = value; 1924 1925 /* enable read/write to eeprom */ 1926 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1927 udelay(1); 1928 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1929 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1930 udelay(1); 1931 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1932 1933 /* send write_enable instruction */ 1934 labpc_serial_out(dev, write_enable_instruction, write_length); 1935 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1936 udelay(1); 1937 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1938 1939 /* send write instruction */ 1940 devpriv->command5_bits |= EEPROM_EN_BIT; 1941 udelay(1); 1942 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1943 labpc_serial_out(dev, write_instruction, write_length); 1944 /* send 8 bit address to write to */ 1945 labpc_serial_out(dev, address, write_length); 1946 /* write value */ 1947 labpc_serial_out(dev, value, write_length); 1948 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1949 udelay(1); 1950 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1951 1952 /* disable read/write to eeprom */ 1953 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1954 udelay(1); 1955 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1956 1957 return 0; 1958} 1959 1960static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) 1961{ 1962 unsigned int value; 1963 const int read_status_instruction = 0x5; 1964 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1965 1966 /* enable read/write to eeprom */ 1967 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1968 udelay(1); 1969 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1970 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1971 udelay(1); 1972 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1973 1974 /* send read status instruction */ 1975 labpc_serial_out(dev, read_status_instruction, write_length); 1976 /* read result */ 1977 value = labpc_serial_in(dev); 1978 1979 /* disable read/write to eeprom */ 1980 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1981 udelay(1); 1982 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1983 1984 return value; 1985} 1986 1987/* writes to 8 bit calibration dacs */ 1988static void write_caldac(struct comedi_device *dev, unsigned int channel, 1989 unsigned int value) 1990{ 1991 if (value == devpriv->caldac[channel]) 1992 return; 1993 devpriv->caldac[channel] = value; 1994 1995 /* clear caldac load bit and make sure we don't write to eeprom */ 1996 devpriv->command5_bits &= 1997 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1998 udelay(1); 1999 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2000 2001 /* write 4 bit channel */ 2002 labpc_serial_out(dev, channel, 4); 2003 /* write 8 bit caldac value */ 2004 labpc_serial_out(dev, value, 8); 2005 2006 /* set and clear caldac bit to load caldac value */ 2007 devpriv->command5_bits |= CALDAC_LOAD_BIT; 2008 udelay(1); 2009 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2010 devpriv->command5_bits &= ~CALDAC_LOAD_BIT; 2011 udelay(1); 2012 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2013} 2014 2015#ifdef CONFIG_COMEDI_PCI 2016COMEDI_PCI_INITCLEANUP(driver_labpc, labpc_pci_table); 2017#else 2018COMEDI_INITCLEANUP(driver_labpc); 2019#endif 2020 2021EXPORT_SYMBOL_GPL(labpc_common_attach); 2022EXPORT_SYMBOL_GPL(labpc_common_detach); 2023EXPORT_SYMBOL_GPL(range_labpc_1200_ai); 2024EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); 2025EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar); 2026