ni_labpc.c revision 412bd046b0a1726f8b168d5056d21213932f9d84
1/* 2 comedi/drivers/ni_labpc.c 3 Driver for National Instruments Lab-PC series boards and compatibles 4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20************************************************************************ 21*/ 22/* 23Driver: ni_labpc 24Description: National Instruments Lab-PC (& compatibles) 25Author: Frank Mori Hess <fmhess@users.sourceforge.net> 26Devices: [National Instruments] Lab-PC-1200 (labpc-1200), 27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc) 28Status: works 29 30Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges 31and analog references will work, the available ranges/arefs will 32depend on how you have configured the jumpers on your board 33(see your owner's manual). 34 35Kernel-level ISA plug-and-play support for the lab-pc-1200 36boards has not 37yet been added to the driver, mainly due to the fact that 38I don't know the device id numbers. If you have one 39of these boards, 40please file a bug report at https://bugs.comedi.org/ 41so I can get the necessary information from you. 42 43The 1200 series boards have onboard calibration dacs for correcting 44analog input/output offsets and gains. The proper settings for these 45caldacs are stored on the board's eeprom. To read the caldac values 46from the eeprom and store them into a file that can be then be used by 47comedilib, use the comedi_calibrate program. 48 49Configuration options - ISA boards: 50 [0] - I/O port base address 51 [1] - IRQ (optional, required for timed or externally triggered conversions) 52 [2] - DMA channel (optional) 53 54Configuration options - PCI boards: 55 [0] - bus (optional) 56 [1] - slot (optional) 57 58The Lab-pc+ has quirky chanlist requirements 59when scanning multiple channels. Multiple channel scan 60sequence must start at highest channel, then decrement down to 61channel 0. The rest of the cards can scan down like lab-pc+ or scan 62up from channel zero. Chanlists consisting of all one channel 63are also legal, and allow you to pace conversions in bursts. 64 65*/ 66 67/* 68 69NI manuals: 70341309a (labpc-1200 register manual) 71340914a (pci-1200) 72320502b (lab-pc+) 73 74*/ 75 76#undef LABPC_DEBUG 77/* #define LABPC_DEBUG enable debugging messages */ 78 79#include <linux/interrupt.h> 80#include "../comedidev.h" 81 82#include <linux/delay.h> 83#include <asm/dma.h> 84 85#include "8253.h" 86#include "8255.h" 87#include "mite.h" 88#include "comedi_fc.h" 89#include "ni_labpc.h" 90 91#define DRV_NAME "ni_labpc" 92 93#define LABPC_SIZE 32 /* size of io region used by board */ 94#define LABPC_TIMER_BASE 500 /* 2 MHz master clock */ 95 96/* Registers for the lab-pc+ */ 97 98/* write-only registers */ 99#define COMMAND1_REG 0x0 100#define ADC_GAIN_MASK (0x7 << 4) 101#define ADC_CHAN_BITS(x) ((x) & 0x7) 102#define ADC_SCAN_EN_BIT 0x80 /* enables multi channel scans */ 103#define COMMAND2_REG 0x1 104#define PRETRIG_BIT 0x1 /* enable pretriggering (used in conjunction with SWTRIG) */ 105#define HWTRIG_BIT 0x2 /* enable paced conversions on external trigger */ 106#define SWTRIG_BIT 0x4 /* enable paced conversions */ 107#define CASCADE_BIT 0x8 /* use two cascaded counters for pacing */ 108#define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1)) 109#define COMMAND3_REG 0x2 110#define DMA_EN_BIT 0x1 /* enable dma transfers */ 111#define DIO_INTR_EN_BIT 0x2 /* enable interrupts for 8255 */ 112#define DMATC_INTR_EN_BIT 0x4 /* enable dma terminal count interrupt */ 113#define TIMER_INTR_EN_BIT 0x8 /* enable timer interrupt */ 114#define ERR_INTR_EN_BIT 0x10 /* enable error interrupt */ 115#define ADC_FNE_INTR_EN_BIT 0x20 /* enable fifo not empty interrupt */ 116#define ADC_CONVERT_REG 0x3 117#define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1)) 118#define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1)) 119#define ADC_CLEAR_REG 0x8 120#define DMATC_CLEAR_REG 0xa 121#define TIMER_CLEAR_REG 0xc 122#define COMMAND6_REG 0xe /* 1200 boards only */ 123#define ADC_COMMON_BIT 0x1 /* select ground or common-mode reference */ 124#define ADC_UNIP_BIT 0x2 /* adc unipolar */ 125#define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) /* dac unipolar */ 126#define ADC_FHF_INTR_EN_BIT 0x20 /* enable fifo half full interrupt */ 127#define A1_INTR_EN_BIT 0x40 /* enable interrupt on end of hardware count */ 128#define ADC_SCAN_UP_BIT 0x80 /* scan up from channel zero instead of down to zero */ 129#define COMMAND4_REG 0xf 130#define INTERVAL_SCAN_EN_BIT 0x1 /* enables 'interval' scanning */ 131#define EXT_SCAN_EN_BIT 0x2 /* enables external signal on counter b1 output to trigger scan */ 132#define EXT_CONVERT_OUT_BIT 0x4 /* chooses direction (output or input) for EXTCONV* line */ 133#define ADC_DIFF_BIT 0x8 /* chooses differential inputs for adc (in conjunction with board jumper) */ 134#define EXT_CONVERT_DISABLE_BIT 0x10 135#define COMMAND5_REG 0x1c /* 1200 boards only, calibration stuff */ 136#define EEPROM_WRITE_UNPROTECT_BIT 0x4 /* enable eeprom for write */ 137#define DITHER_EN_BIT 0x8 /* enable dithering */ 138#define CALDAC_LOAD_BIT 0x10 /* load calibration dac */ 139#define SCLOCK_BIT 0x20 /* serial clock - rising edge writes, falling edge reads */ 140#define SDATA_BIT 0x40 /* serial data bit for writing to eeprom or calibration dacs */ 141#define EEPROM_EN_BIT 0x80 /* enable eeprom for read/write */ 142#define INTERVAL_COUNT_REG 0x1e 143#define INTERVAL_LOAD_REG 0x1f 144#define INTERVAL_LOAD_BITS 0x1 145 146/* read-only registers */ 147#define STATUS1_REG 0x0 148#define DATA_AVAIL_BIT 0x1 /* data is available in fifo */ 149#define OVERRUN_BIT 0x2 /* overrun has occurred */ 150#define OVERFLOW_BIT 0x4 /* fifo overflow */ 151#define TIMER_BIT 0x8 /* timer interrupt has occured */ 152#define DMATC_BIT 0x10 /* dma terminal count has occured */ 153#define EXT_TRIG_BIT 0x40 /* external trigger has occured */ 154#define STATUS2_REG 0x1d /* 1200 boards only */ 155#define EEPROM_OUT_BIT 0x1 /* programmable eeprom serial output */ 156#define A1_TC_BIT 0x2 /* counter A1 terminal count */ 157#define FNHF_BIT 0x4 /* fifo not half full */ 158#define ADC_FIFO_REG 0xa 159 160#define DIO_BASE_REG 0x10 161#define COUNTER_A_BASE_REG 0x14 162#define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3) 163#define INIT_A0_BITS 0x14 /* check modes put conversion pacer output in harmless state (a0 mode 2) */ 164#define INIT_A1_BITS 0x70 /* put hardware conversion counter output in harmless state (a1 mode 0) */ 165#define COUNTER_B_BASE_REG 0x18 166 167static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it); 168static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 169static irqreturn_t labpc_interrupt(int irq, void *d); 170static int labpc_drain_fifo(struct comedi_device *dev); 171static void labpc_drain_dma(struct comedi_device *dev); 172static void handle_isa_dma(struct comedi_device *dev); 173static void labpc_drain_dregs(struct comedi_device *dev); 174static int labpc_ai_cmdtest(struct comedi_device *dev, 175 struct comedi_subdevice *s, struct comedi_cmd *cmd); 176static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 177static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 178 struct comedi_insn *insn, unsigned int *data); 179static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 180 struct comedi_insn *insn, unsigned int *data); 181static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 182 struct comedi_insn *insn, unsigned int *data); 183static int labpc_calib_read_insn(struct comedi_device *dev, 184 struct comedi_subdevice *s, 185 struct comedi_insn *insn, unsigned int *data); 186static int labpc_calib_write_insn(struct comedi_device *dev, 187 struct comedi_subdevice *s, 188 struct comedi_insn *insn, unsigned int *data); 189static int labpc_eeprom_read_insn(struct comedi_device *dev, 190 struct comedi_subdevice *s, 191 struct comedi_insn *insn, unsigned int *data); 192static int labpc_eeprom_write_insn(struct comedi_device *dev, 193 struct comedi_subdevice *s, 194 struct comedi_insn *insn, 195 unsigned int *data); 196static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd); 197static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd); 198#ifdef CONFIG_COMEDI_PCI 199static int labpc_find_device(struct comedi_device *dev, int bus, int slot); 200#endif 201static int labpc_dio_mem_callback(int dir, int port, int data, 202 unsigned long arg); 203static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 204 unsigned int num_bits); 205static unsigned int labpc_serial_in(struct comedi_device *dev); 206static unsigned int labpc_eeprom_read(struct comedi_device *dev, 207 unsigned int address); 208static unsigned int labpc_eeprom_read_status(struct comedi_device *dev); 209static unsigned int labpc_eeprom_write(struct comedi_device *dev, 210 unsigned int address, 211 unsigned int value); 212static void write_caldac(struct comedi_device *dev, unsigned int channel, 213 unsigned int value); 214 215enum scan_mode { 216 MODE_SINGLE_CHAN, 217 MODE_SINGLE_CHAN_INTERVAL, 218 MODE_MULT_CHAN_UP, 219 MODE_MULT_CHAN_DOWN, 220}; 221 222/* analog input ranges */ 223#define NUM_LABPC_PLUS_AI_RANGES 16 224/* indicates unipolar ranges */ 225static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = { 226 0, 227 0, 228 0, 229 0, 230 0, 231 0, 232 0, 233 0, 234 1, 235 1, 236 1, 237 1, 238 1, 239 1, 240 1, 241 1, 242}; 243 244/* map range index to gain bits */ 245static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = { 246 0x00, 247 0x10, 248 0x20, 249 0x30, 250 0x40, 251 0x50, 252 0x60, 253 0x70, 254 0x00, 255 0x10, 256 0x20, 257 0x30, 258 0x40, 259 0x50, 260 0x60, 261 0x70, 262}; 263 264static const struct comedi_lrange range_labpc_plus_ai = { 265 NUM_LABPC_PLUS_AI_RANGES, 266 { 267 BIP_RANGE(5), 268 BIP_RANGE(4), 269 BIP_RANGE(2.5), 270 BIP_RANGE(1), 271 BIP_RANGE(0.5), 272 BIP_RANGE(0.25), 273 BIP_RANGE(0.1), 274 BIP_RANGE(0.05), 275 UNI_RANGE(10), 276 UNI_RANGE(8), 277 UNI_RANGE(5), 278 UNI_RANGE(2), 279 UNI_RANGE(1), 280 UNI_RANGE(0.5), 281 UNI_RANGE(0.2), 282 UNI_RANGE(0.1), 283 } 284}; 285 286#define NUM_LABPC_1200_AI_RANGES 14 287/* indicates unipolar ranges */ 288const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = { 289 0, 290 0, 291 0, 292 0, 293 0, 294 0, 295 0, 296 1, 297 1, 298 1, 299 1, 300 1, 301 1, 302 1, 303}; 304 305/* map range index to gain bits */ 306const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = { 307 0x00, 308 0x20, 309 0x30, 310 0x40, 311 0x50, 312 0x60, 313 0x70, 314 0x00, 315 0x20, 316 0x30, 317 0x40, 318 0x50, 319 0x60, 320 0x70, 321}; 322 323const struct comedi_lrange range_labpc_1200_ai = { 324 NUM_LABPC_1200_AI_RANGES, 325 { 326 BIP_RANGE(5), 327 BIP_RANGE(2.5), 328 BIP_RANGE(1), 329 BIP_RANGE(0.5), 330 BIP_RANGE(0.25), 331 BIP_RANGE(0.1), 332 BIP_RANGE(0.05), 333 UNI_RANGE(10), 334 UNI_RANGE(5), 335 UNI_RANGE(2), 336 UNI_RANGE(1), 337 UNI_RANGE(0.5), 338 UNI_RANGE(0.2), 339 UNI_RANGE(0.1), 340 } 341}; 342 343/* analog output ranges */ 344#define AO_RANGE_IS_UNIPOLAR 0x1 345static const struct comedi_lrange range_labpc_ao = { 346 2, 347 { 348 BIP_RANGE(5), 349 UNI_RANGE(10), 350 } 351}; 352 353/* functions that do inb/outb and readb/writeb so we can use 354 * function pointers to decide which to use */ 355static inline unsigned int labpc_inb(unsigned long address) 356{ 357 return inb(address); 358} 359 360static inline void labpc_outb(unsigned int byte, unsigned long address) 361{ 362 outb(byte, address); 363} 364 365static inline unsigned int labpc_readb(unsigned long address) 366{ 367 return readb((void *)address); 368} 369 370static inline void labpc_writeb(unsigned int byte, unsigned long address) 371{ 372 writeb(byte, (void *)address); 373} 374 375static const struct labpc_board_struct labpc_boards[] = { 376 { 377 .name = "lab-pc-1200", 378 .ai_speed = 10000, 379 .bustype = isa_bustype, 380 .register_layout = labpc_1200_layout, 381 .has_ao = 1, 382 .ai_range_table = &range_labpc_1200_ai, 383 .ai_range_code = labpc_1200_ai_gain_bits, 384 .ai_range_is_unipolar = labpc_1200_is_unipolar, 385 .ai_scan_up = 1, 386 .memory_mapped_io = 0, 387 }, 388 { 389 .name = "lab-pc-1200ai", 390 .ai_speed = 10000, 391 .bustype = isa_bustype, 392 .register_layout = labpc_1200_layout, 393 .has_ao = 0, 394 .ai_range_table = &range_labpc_1200_ai, 395 .ai_range_code = labpc_1200_ai_gain_bits, 396 .ai_range_is_unipolar = labpc_1200_is_unipolar, 397 .ai_scan_up = 1, 398 .memory_mapped_io = 0, 399 }, 400 { 401 .name = "lab-pc+", 402 .ai_speed = 12000, 403 .bustype = isa_bustype, 404 .register_layout = labpc_plus_layout, 405 .has_ao = 1, 406 .ai_range_table = &range_labpc_plus_ai, 407 .ai_range_code = labpc_plus_ai_gain_bits, 408 .ai_range_is_unipolar = labpc_plus_is_unipolar, 409 .ai_scan_up = 0, 410 .memory_mapped_io = 0, 411 }, 412#ifdef CONFIG_COMEDI_PCI 413 { 414 .name = "pci-1200", 415 .device_id = 0x161, 416 .ai_speed = 10000, 417 .bustype = pci_bustype, 418 .register_layout = labpc_1200_layout, 419 .has_ao = 1, 420 .ai_range_table = &range_labpc_1200_ai, 421 .ai_range_code = labpc_1200_ai_gain_bits, 422 .ai_range_is_unipolar = labpc_1200_is_unipolar, 423 .ai_scan_up = 1, 424 .memory_mapped_io = 1, 425 }, 426 /* dummy entry so pci board works when comedi_config is passed driver name */ 427 { 428 .name = DRV_NAME, 429 .bustype = pci_bustype, 430 }, 431#endif 432}; 433 434/* 435 * Useful for shorthand access to the particular board structure 436 */ 437#define thisboard ((struct labpc_board_struct *)dev->board_ptr) 438 439static const int dma_buffer_size = 0xff00; /* size in bytes of dma buffer */ 440static const int sample_size = 2; /* 2 bytes per sample */ 441 442#define devpriv ((struct labpc_private *)dev->private) 443 444static struct comedi_driver driver_labpc = { 445 .driver_name = DRV_NAME, 446 .module = THIS_MODULE, 447 .attach = labpc_attach, 448 .detach = labpc_common_detach, 449 .num_names = ARRAY_SIZE(labpc_boards), 450 .board_name = &labpc_boards[0].name, 451 .offset = sizeof(struct labpc_board_struct), 452}; 453 454#ifdef CONFIG_COMEDI_PCI 455static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = { 456 { 457 PCI_VENDOR_ID_NATINST, 0x161, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 458 0} 459}; 460 461MODULE_DEVICE_TABLE(pci, labpc_pci_table); 462#endif /* CONFIG_COMEDI_PCI */ 463 464static inline int labpc_counter_load(struct comedi_device *dev, 465 unsigned long base_address, 466 unsigned int counter_number, 467 unsigned int count, unsigned int mode) 468{ 469 if (thisboard->memory_mapped_io) 470 return i8254_mm_load((void *)base_address, 0, counter_number, 471 count, mode); 472 else 473 return i8254_load(base_address, 0, counter_number, count, mode); 474} 475 476int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, 477 unsigned int irq, unsigned int dma_chan) 478{ 479 struct comedi_subdevice *s; 480 int i; 481 unsigned long dma_flags, isr_flags; 482 short lsb, msb; 483 484 printk("comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, thisboard->name, 485 iobase); 486 if (irq) 487 printk(", irq %u", irq); 488 if (dma_chan) 489 printk(", dma %u", dma_chan); 490 printk("\n"); 491 492 if (iobase == 0) { 493 printk("io base address is zero!\n"); 494 return -EINVAL; 495 } 496 /* request io regions for isa boards */ 497 if (thisboard->bustype == isa_bustype) { 498 /* check if io addresses are available */ 499 if (!request_region(iobase, LABPC_SIZE, 500 driver_labpc.driver_name)) { 501 printk("I/O port conflict\n"); 502 return -EIO; 503 } 504 } 505 dev->iobase = iobase; 506 507 if (thisboard->memory_mapped_io) { 508 devpriv->read_byte = labpc_readb; 509 devpriv->write_byte = labpc_writeb; 510 } else { 511 devpriv->read_byte = labpc_inb; 512 devpriv->write_byte = labpc_outb; 513 } 514 /* initialize board's command registers */ 515 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 516 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 517 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 518 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 519 if (thisboard->register_layout == labpc_1200_layout) { 520 devpriv->write_byte(devpriv->command5_bits, 521 dev->iobase + COMMAND5_REG); 522 devpriv->write_byte(devpriv->command6_bits, 523 dev->iobase + COMMAND6_REG); 524 } 525 526 /* grab our IRQ */ 527 if (irq) { 528 isr_flags = 0; 529 if (thisboard->bustype == pci_bustype) 530 isr_flags |= IRQF_SHARED; 531 if (request_irq(irq, labpc_interrupt, isr_flags, 532 driver_labpc.driver_name, dev)) { 533 printk("unable to allocate irq %u\n", irq); 534 return -EINVAL; 535 } 536 } 537 dev->irq = irq; 538 539 /* grab dma channel */ 540 if (dma_chan > 3) { 541 printk(" invalid dma channel %u\n", dma_chan); 542 return -EINVAL; 543 } else if (dma_chan) { 544 /* allocate dma buffer */ 545 devpriv->dma_buffer = 546 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA); 547 if (devpriv->dma_buffer == NULL) { 548 printk(" failed to allocate dma buffer\n"); 549 return -ENOMEM; 550 } 551 if (request_dma(dma_chan, driver_labpc.driver_name)) { 552 printk(" failed to allocate dma channel %u\n", 553 dma_chan); 554 return -EINVAL; 555 } 556 devpriv->dma_chan = dma_chan; 557 dma_flags = claim_dma_lock(); 558 disable_dma(devpriv->dma_chan); 559 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); 560 release_dma_lock(dma_flags); 561 } 562 563 dev->board_name = thisboard->name; 564 565 if (alloc_subdevices(dev, 5) < 0) 566 return -ENOMEM; 567 568 /* analog input subdevice */ 569 s = dev->subdevices + 0; 570 dev->read_subdev = s; 571 s->type = COMEDI_SUBD_AI; 572 s->subdev_flags = 573 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ; 574 s->n_chan = 8; 575 s->len_chanlist = 8; 576 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 577 s->range_table = thisboard->ai_range_table; 578 s->do_cmd = labpc_ai_cmd; 579 s->do_cmdtest = labpc_ai_cmdtest; 580 s->insn_read = labpc_ai_rinsn; 581 s->cancel = labpc_cancel; 582 583 /* analog output */ 584 s = dev->subdevices + 1; 585 if (thisboard->has_ao) { 586 /* Could provide command support, except it only has a 587 * one sample hardware buffer for analog output and no 588 * underrun flag. */ 589 s->type = COMEDI_SUBD_AO; 590 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; 591 s->n_chan = NUM_AO_CHAN; 592 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 593 s->range_table = &range_labpc_ao; 594 s->insn_read = labpc_ao_rinsn; 595 s->insn_write = labpc_ao_winsn; 596 /* initialize analog outputs to a known value */ 597 for (i = 0; i < s->n_chan; i++) { 598 devpriv->ao_value[i] = s->maxdata / 2; 599 lsb = devpriv->ao_value[i] & 0xff; 600 msb = (devpriv->ao_value[i] >> 8) & 0xff; 601 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); 602 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); 603 } 604 } else { 605 s->type = COMEDI_SUBD_UNUSED; 606 } 607 608 /* 8255 dio */ 609 s = dev->subdevices + 2; 610 /* if board uses io memory we have to give a custom callback 611 * function to the 8255 driver */ 612 if (thisboard->memory_mapped_io) 613 subdev_8255_init(dev, s, labpc_dio_mem_callback, 614 (unsigned long)(dev->iobase + DIO_BASE_REG)); 615 else 616 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG); 617 618 /* calibration subdevices for boards that have one */ 619 s = dev->subdevices + 3; 620 if (thisboard->register_layout == labpc_1200_layout) { 621 s->type = COMEDI_SUBD_CALIB; 622 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 623 s->n_chan = 16; 624 s->maxdata = 0xff; 625 s->insn_read = labpc_calib_read_insn; 626 s->insn_write = labpc_calib_write_insn; 627 628 for (i = 0; i < s->n_chan; i++) 629 write_caldac(dev, i, s->maxdata / 2); 630 } else 631 s->type = COMEDI_SUBD_UNUSED; 632 633 /* EEPROM */ 634 s = dev->subdevices + 4; 635 if (thisboard->register_layout == labpc_1200_layout) { 636 s->type = COMEDI_SUBD_MEMORY; 637 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 638 s->n_chan = EEPROM_SIZE; 639 s->maxdata = 0xff; 640 s->insn_read = labpc_eeprom_read_insn; 641 s->insn_write = labpc_eeprom_write_insn; 642 643 for (i = 0; i < EEPROM_SIZE; i++) 644 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); 645#ifdef LABPC_DEBUG 646 printk(" eeprom:"); 647 for (i = 0; i < EEPROM_SIZE; i++) 648 printk(" %i:0x%x ", i, devpriv->eeprom_data[i]); 649 printk("\n"); 650#endif 651 } else 652 s->type = COMEDI_SUBD_UNUSED; 653 654 return 0; 655} 656 657static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) 658{ 659 unsigned long iobase = 0; 660 unsigned int irq = 0; 661 unsigned int dma_chan = 0; 662#ifdef CONFIG_COMEDI_PCI 663 int retval; 664#endif 665 666 /* allocate and initialize dev->private */ 667 if (alloc_private(dev, sizeof(struct labpc_private)) < 0) 668 return -ENOMEM; 669 670 /* get base address, irq etc. based on bustype */ 671 switch (thisboard->bustype) { 672 case isa_bustype: 673 iobase = it->options[0]; 674 irq = it->options[1]; 675 dma_chan = it->options[2]; 676 break; 677 case pci_bustype: 678#ifdef CONFIG_COMEDI_PCI 679 retval = labpc_find_device(dev, it->options[0], it->options[1]); 680 if (retval < 0) 681 return retval; 682 retval = mite_setup(devpriv->mite); 683 if (retval < 0) 684 return retval; 685 iobase = (unsigned long)devpriv->mite->daq_io_addr; 686 irq = mite_irq(devpriv->mite); 687#else 688 printk(" this driver has not been built with PCI support.\n"); 689 return -EINVAL; 690#endif 691 break; 692 case pcmcia_bustype: 693 printk 694 (" this driver does not support pcmcia cards, use ni_labpc_cs.o\n"); 695 return -EINVAL; 696 break; 697 default: 698 printk("bug! couldn't determine board type\n"); 699 return -EINVAL; 700 break; 701 } 702 703 return labpc_common_attach(dev, iobase, irq, dma_chan); 704} 705 706/* adapted from ni_pcimio for finding mite based boards (pc-1200) */ 707#ifdef CONFIG_COMEDI_PCI 708static int labpc_find_device(struct comedi_device *dev, int bus, int slot) 709{ 710 struct mite_struct *mite; 711 int i; 712 for (mite = mite_devices; mite; mite = mite->next) { 713 if (mite->used) 714 continue; 715 /* if bus/slot are specified then make sure we have the right bus/slot */ 716 if (bus || slot) { 717 if (bus != mite->pcidev->bus->number 718 || slot != PCI_SLOT(mite->pcidev->devfn)) 719 continue; 720 } 721 for (i = 0; i < driver_labpc.num_names; i++) { 722 if (labpc_boards[i].bustype != pci_bustype) 723 continue; 724 if (mite_device_id(mite) == labpc_boards[i].device_id) { 725 devpriv->mite = mite; 726 /* fixup board pointer, in case we were using the dummy "ni_labpc" entry */ 727 dev->board_ptr = &labpc_boards[i]; 728 return 0; 729 } 730 } 731 } 732 printk("no device found\n"); 733 mite_list_devices(); 734 return -EIO; 735} 736#endif 737 738int labpc_common_detach(struct comedi_device *dev) 739{ 740 printk("comedi%d: ni_labpc: detach\n", dev->minor); 741 742 if (dev->subdevices) 743 subdev_8255_cleanup(dev, dev->subdevices + 2); 744 745 /* only free stuff if it has been allocated by _attach */ 746 if (devpriv->dma_buffer) 747 kfree(devpriv->dma_buffer); 748 if (devpriv->dma_chan) 749 free_dma(devpriv->dma_chan); 750 if (dev->irq) 751 free_irq(dev->irq, dev); 752 if (thisboard->bustype == isa_bustype && dev->iobase) 753 release_region(dev->iobase, LABPC_SIZE); 754#ifdef CONFIG_COMEDI_PCI 755 if (devpriv->mite) 756 mite_unsetup(devpriv->mite); 757#endif 758 759 return 0; 760}; 761 762static void labpc_clear_adc_fifo(const struct comedi_device *dev) 763{ 764 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 765 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 766 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 767} 768 769static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 770{ 771 unsigned long flags; 772 773 spin_lock_irqsave(&dev->spinlock, flags); 774 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 775 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 776 spin_unlock_irqrestore(&dev->spinlock, flags); 777 778 devpriv->command3_bits = 0; 779 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 780 781 return 0; 782} 783 784static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) 785{ 786 if (cmd->chanlist_len == 1) 787 return MODE_SINGLE_CHAN; 788 789 /* chanlist may be NULL during cmdtest. */ 790 if (cmd->chanlist == NULL) 791 return MODE_MULT_CHAN_UP; 792 793 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) 794 return MODE_SINGLE_CHAN_INTERVAL; 795 796 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) 797 return MODE_MULT_CHAN_UP; 798 799 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) 800 return MODE_MULT_CHAN_DOWN; 801 802 printk("ni_labpc: bug! this should never happen\n"); 803 804 return 0; 805} 806 807static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, 808 const struct comedi_cmd *cmd) 809{ 810 int mode, channel, range, aref, i; 811 812 if (cmd->chanlist == NULL) 813 return 0; 814 815 mode = labpc_ai_scan_mode(cmd); 816 817 if (mode == MODE_SINGLE_CHAN) 818 return 0; 819 820 if (mode == MODE_SINGLE_CHAN_INTERVAL) { 821 if (cmd->chanlist_len > 0xff) { 822 comedi_error(dev, 823 "ni_labpc: chanlist too long for single channel interval mode\n"); 824 return 1; 825 } 826 } 827 828 channel = CR_CHAN(cmd->chanlist[0]); 829 range = CR_RANGE(cmd->chanlist[0]); 830 aref = CR_AREF(cmd->chanlist[0]); 831 832 for (i = 0; i < cmd->chanlist_len; i++) { 833 834 switch (mode) { 835 case MODE_SINGLE_CHAN_INTERVAL: 836 if (CR_CHAN(cmd->chanlist[i]) != channel) { 837 comedi_error(dev, 838 "channel scanning order specified in chanlist is not supported by hardware.\n"); 839 return 1; 840 } 841 break; 842 case MODE_MULT_CHAN_UP: 843 if (CR_CHAN(cmd->chanlist[i]) != i) { 844 comedi_error(dev, 845 "channel scanning order specified in chanlist is not supported by hardware.\n"); 846 return 1; 847 } 848 break; 849 case MODE_MULT_CHAN_DOWN: 850 if (CR_CHAN(cmd->chanlist[i]) != 851 cmd->chanlist_len - i - 1) { 852 comedi_error(dev, 853 "channel scanning order specified in chanlist is not supported by hardware.\n"); 854 return 1; 855 } 856 break; 857 default: 858 printk("ni_labpc: bug! in chanlist check\n"); 859 return 1; 860 break; 861 } 862 863 if (CR_RANGE(cmd->chanlist[i]) != range) { 864 comedi_error(dev, 865 "entries in chanlist must all have the same range\n"); 866 return 1; 867 } 868 869 if (CR_AREF(cmd->chanlist[i]) != aref) { 870 comedi_error(dev, 871 "entries in chanlist must all have the same reference\n"); 872 return 1; 873 } 874 } 875 876 return 0; 877} 878 879static int labpc_use_continuous_mode(const struct comedi_cmd *cmd) 880{ 881 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN) 882 return 1; 883 884 if (cmd->scan_begin_src == TRIG_FOLLOW) 885 return 1; 886 887 return 0; 888} 889 890static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd) 891{ 892 if (cmd->convert_src != TRIG_TIMER) 893 return 0; 894 895 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 896 cmd->scan_begin_src == TRIG_TIMER) 897 return cmd->scan_begin_arg; 898 899 return cmd->convert_arg; 900} 901 902static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns) 903{ 904 if (cmd->convert_src != TRIG_TIMER) 905 return; 906 907 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 908 cmd->scan_begin_src == TRIG_TIMER) { 909 cmd->scan_begin_arg = ns; 910 if (cmd->convert_arg > cmd->scan_begin_arg) 911 cmd->convert_arg = cmd->scan_begin_arg; 912 } else 913 cmd->convert_arg = ns; 914} 915 916static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd) 917{ 918 if (cmd->scan_begin_src != TRIG_TIMER) 919 return 0; 920 921 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 922 cmd->convert_src == TRIG_TIMER) 923 return 0; 924 925 return cmd->scan_begin_arg; 926} 927 928static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns) 929{ 930 if (cmd->scan_begin_src != TRIG_TIMER) 931 return; 932 933 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 934 cmd->convert_src == TRIG_TIMER) 935 return; 936 937 cmd->scan_begin_arg = ns; 938} 939 940static int labpc_ai_cmdtest(struct comedi_device *dev, 941 struct comedi_subdevice *s, struct comedi_cmd *cmd) 942{ 943 int err = 0; 944 int tmp, tmp2; 945 int stop_mask; 946 947 /* step 1: make sure trigger sources are trivially valid */ 948 949 tmp = cmd->start_src; 950 cmd->start_src &= TRIG_NOW | TRIG_EXT; 951 if (!cmd->start_src || tmp != cmd->start_src) 952 err++; 953 954 tmp = cmd->scan_begin_src; 955 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT; 956 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 957 err++; 958 959 tmp = cmd->convert_src; 960 cmd->convert_src &= TRIG_TIMER | TRIG_EXT; 961 if (!cmd->convert_src || tmp != cmd->convert_src) 962 err++; 963 964 tmp = cmd->scan_end_src; 965 cmd->scan_end_src &= TRIG_COUNT; 966 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 967 err++; 968 969 tmp = cmd->stop_src; 970 stop_mask = TRIG_COUNT | TRIG_NONE; 971 if (thisboard->register_layout == labpc_1200_layout) 972 stop_mask |= TRIG_EXT; 973 cmd->stop_src &= stop_mask; 974 if (!cmd->stop_src || tmp != cmd->stop_src) 975 err++; 976 977 if (err) 978 return 1; 979 980 /* step 2: make sure trigger sources are unique and mutually compatible */ 981 982 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) 983 err++; 984 if (cmd->scan_begin_src != TRIG_TIMER && 985 cmd->scan_begin_src != TRIG_FOLLOW && 986 cmd->scan_begin_src != TRIG_EXT) 987 err++; 988 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT) 989 err++; 990 if (cmd->stop_src != TRIG_COUNT && 991 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE) 992 err++; 993 994 /* can't have external stop and start triggers at once */ 995 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) 996 err++; 997 998 if (err) 999 return 2; 1000 1001 /* step 3: make sure arguments are trivially compatible */ 1002 1003 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) { 1004 cmd->start_arg = 0; 1005 err++; 1006 } 1007 1008 if (!cmd->chanlist_len) 1009 err++; 1010 1011 if (cmd->scan_end_arg != cmd->chanlist_len) { 1012 cmd->scan_end_arg = cmd->chanlist_len; 1013 err++; 1014 } 1015 1016 if (cmd->convert_src == TRIG_TIMER) { 1017 if (cmd->convert_arg < thisboard->ai_speed) { 1018 cmd->convert_arg = thisboard->ai_speed; 1019 err++; 1020 } 1021 } 1022 /* make sure scan timing is not too fast */ 1023 if (cmd->scan_begin_src == TRIG_TIMER) { 1024 if (cmd->convert_src == TRIG_TIMER && 1025 cmd->scan_begin_arg < 1026 cmd->convert_arg * cmd->chanlist_len) { 1027 cmd->scan_begin_arg = 1028 cmd->convert_arg * cmd->chanlist_len; 1029 err++; 1030 } 1031 if (cmd->scan_begin_arg < 1032 thisboard->ai_speed * cmd->chanlist_len) { 1033 cmd->scan_begin_arg = 1034 thisboard->ai_speed * cmd->chanlist_len; 1035 err++; 1036 } 1037 } 1038 /* stop source */ 1039 switch (cmd->stop_src) { 1040 case TRIG_COUNT: 1041 if (!cmd->stop_arg) { 1042 cmd->stop_arg = 1; 1043 err++; 1044 } 1045 break; 1046 case TRIG_NONE: 1047 if (cmd->stop_arg != 0) { 1048 cmd->stop_arg = 0; 1049 err++; 1050 } 1051 break; 1052 /* TRIG_EXT doesn't care since it doesn't trigger off a numbered channel */ 1053 default: 1054 break; 1055 } 1056 1057 if (err) 1058 return 3; 1059 1060 /* step 4: fix up any arguments */ 1061 1062 tmp = cmd->convert_arg; 1063 tmp2 = cmd->scan_begin_arg; 1064 labpc_adc_timing(dev, cmd); 1065 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) 1066 err++; 1067 1068 if (err) 1069 return 4; 1070 1071 if (labpc_ai_chanlist_invalid(dev, cmd)) 1072 return 5; 1073 1074 return 0; 1075} 1076 1077static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 1078{ 1079 int channel, range, aref; 1080 unsigned long irq_flags; 1081 int ret; 1082 struct comedi_async *async = s->async; 1083 struct comedi_cmd *cmd = &async->cmd; 1084 enum transfer_type xfer; 1085 unsigned long flags; 1086 1087 if (!dev->irq) { 1088 comedi_error(dev, "no irq assigned, cannot perform command"); 1089 return -1; 1090 } 1091 1092 range = CR_RANGE(cmd->chanlist[0]); 1093 aref = CR_AREF(cmd->chanlist[0]); 1094 1095 /* make sure board is disabled before setting up aquisition */ 1096 spin_lock_irqsave(&dev->spinlock, flags); 1097 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1098 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1099 spin_unlock_irqrestore(&dev->spinlock, flags); 1100 1101 devpriv->command3_bits = 0; 1102 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1103 1104 /* initialize software conversion count */ 1105 if (cmd->stop_src == TRIG_COUNT) 1106 devpriv->count = cmd->stop_arg * cmd->chanlist_len; 1107 /* setup hardware conversion counter */ 1108 if (cmd->stop_src == TRIG_EXT) { 1109 /* load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0 */ 1110 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1111 1, 3, 0); 1112 if (ret < 0) { 1113 comedi_error(dev, "error loading counter a1"); 1114 return -1; 1115 } 1116 } else /* otherwise, just put a1 in mode 0 with no count to set its output low */ 1117 devpriv->write_byte(INIT_A1_BITS, 1118 dev->iobase + COUNTER_A_CONTROL_REG); 1119 1120 /* figure out what method we will use to transfer data */ 1121 if (devpriv->dma_chan && /* need a dma channel allocated */ 1122 /* dma unsafe at RT priority, and too much setup time for TRIG_WAKE_EOS for */ 1123 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 && 1124 /* only available on the isa boards */ 1125 thisboard->bustype == isa_bustype) { 1126 xfer = isa_dma_transfer; 1127 } else if (thisboard->register_layout == labpc_1200_layout && /* pc-plus has no fifo-half full interrupt */ 1128 /* wake-end-of-scan should interrupt on fifo not empty */ 1129 (cmd->flags & TRIG_WAKE_EOS) == 0 && 1130 /* make sure we are taking more than just a few points */ 1131 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { 1132 xfer = fifo_half_full_transfer; 1133 } else 1134 xfer = fifo_not_empty_transfer; 1135 devpriv->current_transfer = xfer; 1136 1137 /* setup command6 register for 1200 boards */ 1138 if (thisboard->register_layout == labpc_1200_layout) { 1139 /* reference inputs to ground or common? */ 1140 if (aref != AREF_GROUND) 1141 devpriv->command6_bits |= ADC_COMMON_BIT; 1142 else 1143 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1144 /* bipolar or unipolar range? */ 1145 if (thisboard->ai_range_is_unipolar[range]) 1146 devpriv->command6_bits |= ADC_UNIP_BIT; 1147 else 1148 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1149 /* interrupt on fifo half full? */ 1150 if (xfer == fifo_half_full_transfer) 1151 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT; 1152 else 1153 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1154 /* enable interrupt on counter a1 terminal count? */ 1155 if (cmd->stop_src == TRIG_EXT) 1156 devpriv->command6_bits |= A1_INTR_EN_BIT; 1157 else 1158 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1159 /* are we scanning up or down through channels? */ 1160 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1161 devpriv->command6_bits |= ADC_SCAN_UP_BIT; 1162 else 1163 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT; 1164 /* write to register */ 1165 devpriv->write_byte(devpriv->command6_bits, 1166 dev->iobase + COMMAND6_REG); 1167 } 1168 1169 /* setup channel list, etc (command1 register) */ 1170 devpriv->command1_bits = 0; 1171 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1172 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); 1173 else 1174 channel = CR_CHAN(cmd->chanlist[0]); 1175 /* munge channel bits for differential / scan disabled mode */ 1176 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF) 1177 channel *= 2; 1178 devpriv->command1_bits |= ADC_CHAN_BITS(channel); 1179 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1180 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1181 /* manual says to set scan enable bit on second pass */ 1182 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP || 1183 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) { 1184 devpriv->command1_bits |= ADC_SCAN_EN_BIT; 1185 /* need a brief delay before enabling scan, or scan list will get screwed when you switch 1186 * between scan up to scan down mode - dunno why */ 1187 udelay(1); 1188 devpriv->write_byte(devpriv->command1_bits, 1189 dev->iobase + COMMAND1_REG); 1190 } 1191 /* setup any external triggering/pacing (command4 register) */ 1192 devpriv->command4_bits = 0; 1193 if (cmd->convert_src != TRIG_EXT) 1194 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1195 /* XXX should discard first scan when using interval scanning 1196 * since manual says it is not synced with scan clock */ 1197 if (labpc_use_continuous_mode(cmd) == 0) { 1198 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT; 1199 if (cmd->scan_begin_src == TRIG_EXT) 1200 devpriv->command4_bits |= EXT_SCAN_EN_BIT; 1201 } 1202 /* single-ended/differential */ 1203 if (aref == AREF_DIFF) 1204 devpriv->command4_bits |= ADC_DIFF_BIT; 1205 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1206 1207 devpriv->write_byte(cmd->chanlist_len, 1208 dev->iobase + INTERVAL_COUNT_REG); 1209 /* load count */ 1210 devpriv->write_byte(INTERVAL_LOAD_BITS, 1211 dev->iobase + INTERVAL_LOAD_REG); 1212 1213 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) { 1214 /* set up pacing */ 1215 labpc_adc_timing(dev, cmd); 1216 /* load counter b0 in mode 3 */ 1217 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1218 0, devpriv->divisor_b0, 3); 1219 if (ret < 0) { 1220 comedi_error(dev, "error loading counter b0"); 1221 return -1; 1222 } 1223 } 1224 /* set up conversion pacing */ 1225 if (labpc_ai_convert_period(cmd)) { 1226 /* load counter a0 in mode 2 */ 1227 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1228 0, devpriv->divisor_a0, 2); 1229 if (ret < 0) { 1230 comedi_error(dev, "error loading counter a0"); 1231 return -1; 1232 } 1233 } else 1234 devpriv->write_byte(INIT_A0_BITS, 1235 dev->iobase + COUNTER_A_CONTROL_REG); 1236 1237 /* set up scan pacing */ 1238 if (labpc_ai_scan_period(cmd)) { 1239 /* load counter b1 in mode 2 */ 1240 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1241 1, devpriv->divisor_b1, 2); 1242 if (ret < 0) { 1243 comedi_error(dev, "error loading counter b1"); 1244 return -1; 1245 } 1246 } 1247 1248 labpc_clear_adc_fifo(dev); 1249 1250 /* set up dma transfer */ 1251 if (xfer == isa_dma_transfer) { 1252 irq_flags = claim_dma_lock(); 1253 disable_dma(devpriv->dma_chan); 1254 /* clear flip-flop to make sure 2-byte registers for 1255 * count and address get set correctly */ 1256 clear_dma_ff(devpriv->dma_chan); 1257 set_dma_addr(devpriv->dma_chan, 1258 virt_to_bus(devpriv->dma_buffer)); 1259 /* set appropriate size of transfer */ 1260 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd); 1261 if (cmd->stop_src == TRIG_COUNT && 1262 devpriv->count * sample_size < devpriv->dma_transfer_size) { 1263 devpriv->dma_transfer_size = 1264 devpriv->count * sample_size; 1265 } 1266 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); 1267 enable_dma(devpriv->dma_chan); 1268 release_dma_lock(irq_flags); 1269 /* enable board's dma */ 1270 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT; 1271 } else 1272 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT; 1273 1274 /* enable error interrupts */ 1275 devpriv->command3_bits |= ERR_INTR_EN_BIT; 1276 /* enable fifo not empty interrupt? */ 1277 if (xfer == fifo_not_empty_transfer) 1278 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT; 1279 else 1280 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT; 1281 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1282 1283 /* startup aquisition */ 1284 1285 /* command2 reg */ 1286 /* use 2 cascaded counters for pacing */ 1287 spin_lock_irqsave(&dev->spinlock, flags); 1288 devpriv->command2_bits |= CASCADE_BIT; 1289 switch (cmd->start_src) { 1290 case TRIG_EXT: 1291 devpriv->command2_bits |= HWTRIG_BIT; 1292 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT; 1293 break; 1294 case TRIG_NOW: 1295 devpriv->command2_bits |= SWTRIG_BIT; 1296 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT; 1297 break; 1298 default: 1299 comedi_error(dev, "bug with start_src"); 1300 return -1; 1301 break; 1302 } 1303 switch (cmd->stop_src) { 1304 case TRIG_EXT: 1305 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT; 1306 break; 1307 case TRIG_COUNT: 1308 case TRIG_NONE: 1309 break; 1310 default: 1311 comedi_error(dev, "bug with stop_src"); 1312 return -1; 1313 } 1314 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1315 spin_unlock_irqrestore(&dev->spinlock, flags); 1316 1317 return 0; 1318} 1319 1320/* interrupt service routine */ 1321static irqreturn_t labpc_interrupt(int irq, void *d) 1322{ 1323 struct comedi_device *dev = d; 1324 struct comedi_subdevice *s = dev->read_subdev; 1325 struct comedi_async *async; 1326 struct comedi_cmd *cmd; 1327 1328 if (dev->attached == 0) { 1329 comedi_error(dev, "premature interrupt"); 1330 return IRQ_HANDLED; 1331 } 1332 1333 async = s->async; 1334 cmd = &async->cmd; 1335 async->events = 0; 1336 1337 /* read board status */ 1338 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1339 if (thisboard->register_layout == labpc_1200_layout) 1340 devpriv->status2_bits = 1341 devpriv->read_byte(dev->iobase + STATUS2_REG); 1342 1343 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT | 1344 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0 1345 && (devpriv->status2_bits & A1_TC_BIT) == 0 1346 && (devpriv->status2_bits & FNHF_BIT)) { 1347 return IRQ_NONE; 1348 } 1349 1350 if (devpriv->status1_bits & OVERRUN_BIT) { 1351 /* clear error interrupt */ 1352 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1353 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1354 comedi_event(dev, s); 1355 comedi_error(dev, "overrun"); 1356 return IRQ_HANDLED; 1357 } 1358 1359 if (devpriv->current_transfer == isa_dma_transfer) { 1360 /* if a dma terminal count of external stop trigger has occurred */ 1361 if (devpriv->status1_bits & DMATC_BIT || 1362 (thisboard->register_layout == labpc_1200_layout 1363 && devpriv->status2_bits & A1_TC_BIT)) { 1364 handle_isa_dma(dev); 1365 } 1366 } else 1367 labpc_drain_fifo(dev); 1368 1369 if (devpriv->status1_bits & TIMER_BIT) { 1370 comedi_error(dev, "handled timer interrupt?"); 1371 /* clear it */ 1372 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); 1373 } 1374 1375 if (devpriv->status1_bits & OVERFLOW_BIT) { 1376 /* clear error interrupt */ 1377 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1378 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1379 comedi_event(dev, s); 1380 comedi_error(dev, "overflow"); 1381 return IRQ_HANDLED; 1382 } 1383 /* handle external stop trigger */ 1384 if (cmd->stop_src == TRIG_EXT) { 1385 if (devpriv->status2_bits & A1_TC_BIT) { 1386 labpc_drain_dregs(dev); 1387 labpc_cancel(dev, s); 1388 async->events |= COMEDI_CB_EOA; 1389 } 1390 } 1391 1392 /* TRIG_COUNT end of acquisition */ 1393 if (cmd->stop_src == TRIG_COUNT) { 1394 if (devpriv->count == 0) { 1395 labpc_cancel(dev, s); 1396 async->events |= COMEDI_CB_EOA; 1397 } 1398 } 1399 1400 comedi_event(dev, s); 1401 return IRQ_HANDLED; 1402} 1403 1404/* read all available samples from ai fifo */ 1405static int labpc_drain_fifo(struct comedi_device *dev) 1406{ 1407 unsigned int lsb, msb; 1408 short data; 1409 struct comedi_async *async = dev->read_subdev->async; 1410 const int timeout = 10000; 1411 unsigned int i; 1412 1413 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1414 1415 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout; 1416 i++) { 1417 /* quit if we have all the data we want */ 1418 if (async->cmd.stop_src == TRIG_COUNT) { 1419 if (devpriv->count == 0) 1420 break; 1421 devpriv->count--; 1422 } 1423 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1424 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1425 data = (msb << 8) | lsb; 1426 cfc_write_to_buffer(dev->read_subdev, data); 1427 devpriv->status1_bits = 1428 devpriv->read_byte(dev->iobase + STATUS1_REG); 1429 } 1430 if (i == timeout) { 1431 comedi_error(dev, "ai timeout, fifo never empties"); 1432 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1433 return -1; 1434 } 1435 1436 return 0; 1437} 1438 1439static void labpc_drain_dma(struct comedi_device *dev) 1440{ 1441 struct comedi_subdevice *s = dev->read_subdev; 1442 struct comedi_async *async = s->async; 1443 int status; 1444 unsigned long flags; 1445 unsigned int max_points, num_points, residue, leftover; 1446 int i; 1447 1448 status = devpriv->status1_bits; 1449 1450 flags = claim_dma_lock(); 1451 disable_dma(devpriv->dma_chan); 1452 /* clear flip-flop to make sure 2-byte registers for 1453 * count and address get set correctly */ 1454 clear_dma_ff(devpriv->dma_chan); 1455 1456 /* figure out how many points to read */ 1457 max_points = devpriv->dma_transfer_size / sample_size; 1458 /* residue is the number of points left to be done on the dma 1459 * transfer. It should always be zero at this point unless 1460 * the stop_src is set to external triggering. 1461 */ 1462 residue = get_dma_residue(devpriv->dma_chan) / sample_size; 1463 num_points = max_points - residue; 1464 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) 1465 num_points = devpriv->count; 1466 1467 /* figure out how many points will be stored next time */ 1468 leftover = 0; 1469 if (async->cmd.stop_src != TRIG_COUNT) { 1470 leftover = devpriv->dma_transfer_size / sample_size; 1471 } else if (devpriv->count > num_points) { 1472 leftover = devpriv->count - num_points; 1473 if (leftover > max_points) 1474 leftover = max_points; 1475 } 1476 1477 /* write data to comedi buffer */ 1478 for (i = 0; i < num_points; i++) 1479 cfc_write_to_buffer(s, devpriv->dma_buffer[i]); 1480 if (async->cmd.stop_src == TRIG_COUNT) 1481 devpriv->count -= num_points; 1482 1483 /* set address and count for next transfer */ 1484 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); 1485 set_dma_count(devpriv->dma_chan, leftover * sample_size); 1486 release_dma_lock(flags); 1487 1488 async->events |= COMEDI_CB_BLOCK; 1489} 1490 1491static void handle_isa_dma(struct comedi_device *dev) 1492{ 1493 labpc_drain_dma(dev); 1494 1495 enable_dma(devpriv->dma_chan); 1496 1497 /* clear dma tc interrupt */ 1498 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); 1499} 1500 1501/* makes sure all data acquired by board is transfered to comedi (used 1502 * when aquisition is terminated by stop_src == TRIG_EXT). */ 1503static void labpc_drain_dregs(struct comedi_device *dev) 1504{ 1505 if (devpriv->current_transfer == isa_dma_transfer) 1506 labpc_drain_dma(dev); 1507 1508 labpc_drain_fifo(dev); 1509} 1510 1511static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1512 struct comedi_insn *insn, unsigned int *data) 1513{ 1514 int i, n; 1515 int chan, range; 1516 int lsb, msb; 1517 int timeout = 1000; 1518 unsigned long flags; 1519 1520 /* disable timed conversions */ 1521 spin_lock_irqsave(&dev->spinlock, flags); 1522 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1523 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1524 spin_unlock_irqrestore(&dev->spinlock, flags); 1525 1526 /* disable interrupt generation and dma */ 1527 devpriv->command3_bits = 0; 1528 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1529 1530 /* set gain and channel */ 1531 devpriv->command1_bits = 0; 1532 chan = CR_CHAN(insn->chanspec); 1533 range = CR_RANGE(insn->chanspec); 1534 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1535 /* munge channel bits for differential/scan disabled mode */ 1536 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1537 chan *= 2; 1538 devpriv->command1_bits |= ADC_CHAN_BITS(chan); 1539 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1540 1541 /* setup command6 register for 1200 boards */ 1542 if (thisboard->register_layout == labpc_1200_layout) { 1543 /* reference inputs to ground or common? */ 1544 if (CR_AREF(insn->chanspec) != AREF_GROUND) 1545 devpriv->command6_bits |= ADC_COMMON_BIT; 1546 else 1547 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1548 /* bipolar or unipolar range? */ 1549 if (thisboard->ai_range_is_unipolar[range]) 1550 devpriv->command6_bits |= ADC_UNIP_BIT; 1551 else 1552 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1553 /* don't interrupt on fifo half full */ 1554 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1555 /* don't enable interrupt on counter a1 terminal count? */ 1556 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1557 /* write to register */ 1558 devpriv->write_byte(devpriv->command6_bits, 1559 dev->iobase + COMMAND6_REG); 1560 } 1561 /* setup command4 register */ 1562 devpriv->command4_bits = 0; 1563 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1564 /* single-ended/differential */ 1565 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1566 devpriv->command4_bits |= ADC_DIFF_BIT; 1567 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1568 1569 /* initialize pacer counter output to make sure it doesn't cause any problems */ 1570 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG); 1571 1572 labpc_clear_adc_fifo(dev); 1573 1574 for (n = 0; n < insn->n; n++) { 1575 /* trigger conversion */ 1576 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG); 1577 1578 for (i = 0; i < timeout; i++) { 1579 if (devpriv->read_byte(dev->iobase + 1580 STATUS1_REG) & DATA_AVAIL_BIT) 1581 break; 1582 udelay(1); 1583 } 1584 if (i == timeout) { 1585 comedi_error(dev, "timeout"); 1586 return -ETIME; 1587 } 1588 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1589 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1590 data[n] = (msb << 8) | lsb; 1591 } 1592 1593 return n; 1594} 1595 1596/* analog output insn */ 1597static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 1598 struct comedi_insn *insn, unsigned int *data) 1599{ 1600 int channel, range; 1601 unsigned long flags; 1602 int lsb, msb; 1603 1604 channel = CR_CHAN(insn->chanspec); 1605 1606 /* turn off pacing of analog output channel */ 1607 /* note: hardware bug in daqcard-1200 means pacing cannot 1608 * be independently enabled/disabled for its the two channels */ 1609 spin_lock_irqsave(&dev->spinlock, flags); 1610 devpriv->command2_bits &= ~DAC_PACED_BIT(channel); 1611 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1612 spin_unlock_irqrestore(&dev->spinlock, flags); 1613 1614 /* set range */ 1615 if (thisboard->register_layout == labpc_1200_layout) { 1616 range = CR_RANGE(insn->chanspec); 1617 if (range & AO_RANGE_IS_UNIPOLAR) 1618 devpriv->command6_bits |= DAC_UNIP_BIT(channel); 1619 else 1620 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel); 1621 /* write to register */ 1622 devpriv->write_byte(devpriv->command6_bits, 1623 dev->iobase + COMMAND6_REG); 1624 } 1625 /* send data */ 1626 lsb = data[0] & 0xff; 1627 msb = (data[0] >> 8) & 0xff; 1628 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); 1629 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); 1630 1631 /* remember value for readback */ 1632 devpriv->ao_value[channel] = data[0]; 1633 1634 return 1; 1635} 1636 1637/* analog output readback insn */ 1638static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1639 struct comedi_insn *insn, unsigned int *data) 1640{ 1641 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; 1642 1643 return 1; 1644} 1645 1646static int labpc_calib_read_insn(struct comedi_device *dev, 1647 struct comedi_subdevice *s, 1648 struct comedi_insn *insn, unsigned int *data) 1649{ 1650 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)]; 1651 1652 return 1; 1653} 1654 1655static int labpc_calib_write_insn(struct comedi_device *dev, 1656 struct comedi_subdevice *s, 1657 struct comedi_insn *insn, unsigned int *data) 1658{ 1659 int channel = CR_CHAN(insn->chanspec); 1660 1661 write_caldac(dev, channel, data[0]); 1662 return 1; 1663} 1664 1665static int labpc_eeprom_read_insn(struct comedi_device *dev, 1666 struct comedi_subdevice *s, 1667 struct comedi_insn *insn, unsigned int *data) 1668{ 1669 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)]; 1670 1671 return 1; 1672} 1673 1674static int labpc_eeprom_write_insn(struct comedi_device *dev, 1675 struct comedi_subdevice *s, 1676 struct comedi_insn *insn, unsigned int *data) 1677{ 1678 int channel = CR_CHAN(insn->chanspec); 1679 int ret; 1680 1681 /* only allow writes to user area of eeprom */ 1682 if (channel < 16 || channel > 127) { 1683 printk 1684 ("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)"); 1685 return -EINVAL; 1686 } 1687 1688 ret = labpc_eeprom_write(dev, channel, data[0]); 1689 if (ret < 0) 1690 return ret; 1691 1692 return 1; 1693} 1694 1695/* utility function that suggests a dma transfer size in bytes */ 1696static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd) 1697{ 1698 unsigned int size; 1699 unsigned int freq; 1700 1701 if (cmd.convert_src == TRIG_TIMER) 1702 freq = 1000000000 / cmd.convert_arg; 1703 /* return some default value */ 1704 else 1705 freq = 0xffffffff; 1706 1707 /* make buffer fill in no more than 1/3 second */ 1708 size = (freq / 3) * sample_size; 1709 1710 /* set a minimum and maximum size allowed */ 1711 if (size > dma_buffer_size) 1712 size = dma_buffer_size - dma_buffer_size % sample_size; 1713 else if (size < sample_size) 1714 size = sample_size; 1715 1716 return size; 1717} 1718 1719/* figures out what counter values to use based on command */ 1720static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) 1721{ 1722 const int max_counter_value = 0x10000; /* max value for 16 bit counter in mode 2 */ 1723 const int min_counter_value = 2; /* min value for 16 bit counter in mode 2 */ 1724 unsigned int base_period; 1725 1726 /* if both convert and scan triggers are TRIG_TIMER, then they both rely on counter b0 */ 1727 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) { 1728 /* pick the lowest b0 divisor value we can (for maximum input clock speed on convert and scan counters) */ 1729 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) / 1730 (LABPC_TIMER_BASE * max_counter_value) + 1; 1731 if (devpriv->divisor_b0 < min_counter_value) 1732 devpriv->divisor_b0 = min_counter_value; 1733 if (devpriv->divisor_b0 > max_counter_value) 1734 devpriv->divisor_b0 = max_counter_value; 1735 1736 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; 1737 1738 /* set a0 for conversion frequency and b1 for scan frequency */ 1739 switch (cmd->flags & TRIG_ROUND_MASK) { 1740 default: 1741 case TRIG_ROUND_NEAREST: 1742 devpriv->divisor_a0 = 1743 (labpc_ai_convert_period(cmd) + 1744 (base_period / 2)) / base_period; 1745 devpriv->divisor_b1 = 1746 (labpc_ai_scan_period(cmd) + 1747 (base_period / 2)) / base_period; 1748 break; 1749 case TRIG_ROUND_UP: 1750 devpriv->divisor_a0 = 1751 (labpc_ai_convert_period(cmd) + (base_period - 1752 1)) / base_period; 1753 devpriv->divisor_b1 = 1754 (labpc_ai_scan_period(cmd) + (base_period - 1755 1)) / base_period; 1756 break; 1757 case TRIG_ROUND_DOWN: 1758 devpriv->divisor_a0 = 1759 labpc_ai_convert_period(cmd) / base_period; 1760 devpriv->divisor_b1 = 1761 labpc_ai_scan_period(cmd) / base_period; 1762 break; 1763 } 1764 /* make sure a0 and b1 values are acceptable */ 1765 if (devpriv->divisor_a0 < min_counter_value) 1766 devpriv->divisor_a0 = min_counter_value; 1767 if (devpriv->divisor_a0 > max_counter_value) 1768 devpriv->divisor_a0 = max_counter_value; 1769 if (devpriv->divisor_b1 < min_counter_value) 1770 devpriv->divisor_b1 = min_counter_value; 1771 if (devpriv->divisor_b1 > max_counter_value) 1772 devpriv->divisor_b1 = max_counter_value; 1773 /* write corrected timings to command */ 1774 labpc_set_ai_convert_period(cmd, 1775 base_period * devpriv->divisor_a0); 1776 labpc_set_ai_scan_period(cmd, 1777 base_period * devpriv->divisor_b1); 1778 /* if only one TRIG_TIMER is used, we can employ the generic cascaded timing functions */ 1779 } else if (labpc_ai_scan_period(cmd)) { 1780 unsigned int scan_period; 1781 1782 scan_period = labpc_ai_scan_period(cmd); 1783 /* calculate cascaded counter values that give desired scan timing */ 1784 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1785 &(devpriv->divisor_b1), 1786 &(devpriv->divisor_b0), 1787 &scan_period, 1788 cmd->flags & TRIG_ROUND_MASK); 1789 labpc_set_ai_scan_period(cmd, scan_period); 1790 } else if (labpc_ai_convert_period(cmd)) { 1791 unsigned int convert_period; 1792 1793 convert_period = labpc_ai_convert_period(cmd); 1794 /* calculate cascaded counter values that give desired conversion timing */ 1795 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1796 &(devpriv->divisor_a0), 1797 &(devpriv->divisor_b0), 1798 &convert_period, 1799 cmd->flags & TRIG_ROUND_MASK); 1800 labpc_set_ai_convert_period(cmd, convert_period); 1801 } 1802} 1803 1804static int labpc_dio_mem_callback(int dir, int port, int data, 1805 unsigned long iobase) 1806{ 1807 if (dir) { 1808 writeb(data, (void *)(iobase + port)); 1809 return 0; 1810 } else { 1811 return readb((void *)(iobase + port)); 1812 } 1813} 1814 1815/* lowlevel write to eeprom/dac */ 1816static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 1817 unsigned int value_width) 1818{ 1819 int i; 1820 1821 for (i = 1; i <= value_width; i++) { 1822 /* clear serial clock */ 1823 devpriv->command5_bits &= ~SCLOCK_BIT; 1824 /* send bits most significant bit first */ 1825 if (value & (1 << (value_width - i))) 1826 devpriv->command5_bits |= SDATA_BIT; 1827 else 1828 devpriv->command5_bits &= ~SDATA_BIT; 1829 udelay(1); 1830 devpriv->write_byte(devpriv->command5_bits, 1831 dev->iobase + COMMAND5_REG); 1832 /* set clock to load bit */ 1833 devpriv->command5_bits |= SCLOCK_BIT; 1834 udelay(1); 1835 devpriv->write_byte(devpriv->command5_bits, 1836 dev->iobase + COMMAND5_REG); 1837 } 1838} 1839 1840/* lowlevel read from eeprom */ 1841static unsigned int labpc_serial_in(struct comedi_device *dev) 1842{ 1843 unsigned int value = 0; 1844 int i; 1845 const int value_width = 8; /* number of bits wide values are */ 1846 1847 for (i = 1; i <= value_width; i++) { 1848 /* set serial clock */ 1849 devpriv->command5_bits |= SCLOCK_BIT; 1850 udelay(1); 1851 devpriv->write_byte(devpriv->command5_bits, 1852 dev->iobase + COMMAND5_REG); 1853 /* clear clock bit */ 1854 devpriv->command5_bits &= ~SCLOCK_BIT; 1855 udelay(1); 1856 devpriv->write_byte(devpriv->command5_bits, 1857 dev->iobase + COMMAND5_REG); 1858 /* read bits most significant bit first */ 1859 udelay(1); 1860 devpriv->status2_bits = 1861 devpriv->read_byte(dev->iobase + STATUS2_REG); 1862 if (devpriv->status2_bits & EEPROM_OUT_BIT) 1863 value |= 1 << (value_width - i); 1864 } 1865 1866 return value; 1867} 1868 1869static unsigned int labpc_eeprom_read(struct comedi_device *dev, 1870 unsigned int address) 1871{ 1872 unsigned int value; 1873 const int read_instruction = 0x3; /* bits to tell eeprom to expect a read */ 1874 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1875 1876 /* enable read/write to eeprom */ 1877 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1878 udelay(1); 1879 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1880 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1881 udelay(1); 1882 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1883 1884 /* send read instruction */ 1885 labpc_serial_out(dev, read_instruction, write_length); 1886 /* send 8 bit address to read from */ 1887 labpc_serial_out(dev, address, write_length); 1888 /* read result */ 1889 value = labpc_serial_in(dev); 1890 1891 /* disable read/write to eeprom */ 1892 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1893 udelay(1); 1894 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1895 1896 return value; 1897} 1898 1899static unsigned int labpc_eeprom_write(struct comedi_device *dev, 1900 unsigned int address, unsigned int value) 1901{ 1902 const int write_enable_instruction = 0x6; 1903 const int write_instruction = 0x2; 1904 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1905 const int write_in_progress_bit = 0x1; 1906 const int timeout = 10000; 1907 int i; 1908 1909 /* make sure there isn't already a write in progress */ 1910 for (i = 0; i < timeout; i++) { 1911 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == 1912 0) 1913 break; 1914 } 1915 if (i == timeout) { 1916 comedi_error(dev, "eeprom write timed out"); 1917 return -ETIME; 1918 } 1919 /* update software copy of eeprom */ 1920 devpriv->eeprom_data[address] = value; 1921 1922 /* enable read/write to eeprom */ 1923 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1924 udelay(1); 1925 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1926 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1927 udelay(1); 1928 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1929 1930 /* send write_enable instruction */ 1931 labpc_serial_out(dev, write_enable_instruction, write_length); 1932 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1933 udelay(1); 1934 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1935 1936 /* send write instruction */ 1937 devpriv->command5_bits |= EEPROM_EN_BIT; 1938 udelay(1); 1939 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1940 labpc_serial_out(dev, write_instruction, write_length); 1941 /* send 8 bit address to write to */ 1942 labpc_serial_out(dev, address, write_length); 1943 /* write value */ 1944 labpc_serial_out(dev, value, write_length); 1945 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1946 udelay(1); 1947 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1948 1949 /* disable read/write to eeprom */ 1950 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1951 udelay(1); 1952 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1953 1954 return 0; 1955} 1956 1957static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) 1958{ 1959 unsigned int value; 1960 const int read_status_instruction = 0x5; 1961 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1962 1963 /* enable read/write to eeprom */ 1964 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1965 udelay(1); 1966 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1967 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1968 udelay(1); 1969 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1970 1971 /* send read status instruction */ 1972 labpc_serial_out(dev, read_status_instruction, write_length); 1973 /* read result */ 1974 value = labpc_serial_in(dev); 1975 1976 /* disable read/write to eeprom */ 1977 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1978 udelay(1); 1979 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1980 1981 return value; 1982} 1983 1984/* writes to 8 bit calibration dacs */ 1985static void write_caldac(struct comedi_device *dev, unsigned int channel, 1986 unsigned int value) 1987{ 1988 if (value == devpriv->caldac[channel]) 1989 return; 1990 devpriv->caldac[channel] = value; 1991 1992 /* clear caldac load bit and make sure we don't write to eeprom */ 1993 devpriv->command5_bits &= 1994 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1995 udelay(1); 1996 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1997 1998 /* write 4 bit channel */ 1999 labpc_serial_out(dev, channel, 4); 2000 /* write 8 bit caldac value */ 2001 labpc_serial_out(dev, value, 8); 2002 2003 /* set and clear caldac bit to load caldac value */ 2004 devpriv->command5_bits |= CALDAC_LOAD_BIT; 2005 udelay(1); 2006 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2007 devpriv->command5_bits &= ~CALDAC_LOAD_BIT; 2008 udelay(1); 2009 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2010} 2011 2012#ifdef CONFIG_COMEDI_PCI 2013COMEDI_PCI_INITCLEANUP(driver_labpc, labpc_pci_table); 2014#else 2015COMEDI_INITCLEANUP(driver_labpc); 2016#endif 2017 2018EXPORT_SYMBOL_GPL(labpc_common_attach); 2019EXPORT_SYMBOL_GPL(labpc_common_detach); 2020EXPORT_SYMBOL_GPL(range_labpc_1200_ai); 2021EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); 2022EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar); 2023