ni_labpc.c revision 65d6d26c6bcd802ebe2b22a29d9b6bbebfd8d7f8
1/* 2 comedi/drivers/ni_labpc.c 3 Driver for National Instruments Lab-PC series boards and compatibles 4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20************************************************************************ 21*/ 22/* 23Driver: ni_labpc 24Description: National Instruments Lab-PC (& compatibles) 25Author: Frank Mori Hess <fmhess@users.sourceforge.net> 26Devices: [National Instruments] Lab-PC-1200 (labpc-1200), 27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc) 28Status: works 29 30Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges 31and analog references will work, the available ranges/arefs will 32depend on how you have configured the jumpers on your board 33(see your owner's manual). 34 35Kernel-level ISA plug-and-play support for the lab-pc-1200 36boards has not 37yet been added to the driver, mainly due to the fact that 38I don't know the device id numbers. If you have one 39of these boards, 40please file a bug report at https://bugs.comedi.org/ 41so I can get the necessary information from you. 42 43The 1200 series boards have onboard calibration dacs for correcting 44analog input/output offsets and gains. The proper settings for these 45caldacs are stored on the board's eeprom. To read the caldac values 46from the eeprom and store them into a file that can be then be used by 47comedilib, use the comedi_calibrate program. 48 49Configuration options - ISA boards: 50 [0] - I/O port base address 51 [1] - IRQ (optional, required for timed or externally triggered conversions) 52 [2] - DMA channel (optional) 53 54Configuration options - PCI boards: 55 [0] - bus (optional) 56 [1] - slot (optional) 57 58The Lab-pc+ has quirky chanlist requirements 59when scanning multiple channels. Multiple channel scan 60sequence must start at highest channel, then decrement down to 61channel 0. The rest of the cards can scan down like lab-pc+ or scan 62up from channel zero. Chanlists consisting of all one channel 63are also legal, and allow you to pace conversions in bursts. 64 65*/ 66 67/* 68 69NI manuals: 70341309a (labpc-1200 register manual) 71340914a (pci-1200) 72320502b (lab-pc+) 73 74*/ 75 76#undef LABPC_DEBUG 77/* #define LABPC_DEBUG enable debugging messages */ 78 79#include <linux/interrupt.h> 80#include "../comedidev.h" 81 82#include <linux/delay.h> 83#include <asm/dma.h> 84 85#include "8253.h" 86#include "8255.h" 87#include "mite.h" 88#include "comedi_fc.h" 89#include "ni_labpc.h" 90 91#define DRV_NAME "ni_labpc" 92 93#define LABPC_SIZE 32 /* size of io region used by board */ 94#define LABPC_TIMER_BASE 500 /* 2 MHz master clock */ 95 96/* Registers for the lab-pc+ */ 97 98/* write-only registers */ 99#define COMMAND1_REG 0x0 100#define ADC_GAIN_MASK (0x7 << 4) 101#define ADC_CHAN_BITS(x) ((x) & 0x7) 102#define ADC_SCAN_EN_BIT 0x80 /* enables multi channel scans */ 103#define COMMAND2_REG 0x1 104#define PRETRIG_BIT 0x1 /* enable pretriggering (used in conjunction with SWTRIG) */ 105#define HWTRIG_BIT 0x2 /* enable paced conversions on external trigger */ 106#define SWTRIG_BIT 0x4 /* enable paced conversions */ 107#define CASCADE_BIT 0x8 /* use two cascaded counters for pacing */ 108#define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1)) 109#define COMMAND3_REG 0x2 110#define DMA_EN_BIT 0x1 /* enable dma transfers */ 111#define DIO_INTR_EN_BIT 0x2 /* enable interrupts for 8255 */ 112#define DMATC_INTR_EN_BIT 0x4 /* enable dma terminal count interrupt */ 113#define TIMER_INTR_EN_BIT 0x8 /* enable timer interrupt */ 114#define ERR_INTR_EN_BIT 0x10 /* enable error interrupt */ 115#define ADC_FNE_INTR_EN_BIT 0x20 /* enable fifo not empty interrupt */ 116#define ADC_CONVERT_REG 0x3 117#define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1)) 118#define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1)) 119#define ADC_CLEAR_REG 0x8 120#define DMATC_CLEAR_REG 0xa 121#define TIMER_CLEAR_REG 0xc 122#define COMMAND6_REG 0xe /* 1200 boards only */ 123#define ADC_COMMON_BIT 0x1 /* select ground or common-mode reference */ 124#define ADC_UNIP_BIT 0x2 /* adc unipolar */ 125#define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) /* dac unipolar */ 126#define ADC_FHF_INTR_EN_BIT 0x20 /* enable fifo half full interrupt */ 127#define A1_INTR_EN_BIT 0x40 /* enable interrupt on end of hardware count */ 128#define ADC_SCAN_UP_BIT 0x80 /* scan up from channel zero instead of down to zero */ 129#define COMMAND4_REG 0xf 130#define INTERVAL_SCAN_EN_BIT 0x1 /* enables 'interval' scanning */ 131#define EXT_SCAN_EN_BIT 0x2 /* enables external signal on counter b1 output to trigger scan */ 132#define EXT_CONVERT_OUT_BIT 0x4 /* chooses direction (output or input) for EXTCONV* line */ 133#define ADC_DIFF_BIT 0x8 /* chooses differential inputs for adc (in conjunction with board jumper) */ 134#define EXT_CONVERT_DISABLE_BIT 0x10 135#define COMMAND5_REG 0x1c /* 1200 boards only, calibration stuff */ 136#define EEPROM_WRITE_UNPROTECT_BIT 0x4 /* enable eeprom for write */ 137#define DITHER_EN_BIT 0x8 /* enable dithering */ 138#define CALDAC_LOAD_BIT 0x10 /* load calibration dac */ 139#define SCLOCK_BIT 0x20 /* serial clock - rising edge writes, falling edge reads */ 140#define SDATA_BIT 0x40 /* serial data bit for writing to eeprom or calibration dacs */ 141#define EEPROM_EN_BIT 0x80 /* enable eeprom for read/write */ 142#define INTERVAL_COUNT_REG 0x1e 143#define INTERVAL_LOAD_REG 0x1f 144#define INTERVAL_LOAD_BITS 0x1 145 146/* read-only registers */ 147#define STATUS1_REG 0x0 148#define DATA_AVAIL_BIT 0x1 /* data is available in fifo */ 149#define OVERRUN_BIT 0x2 /* overrun has occurred */ 150#define OVERFLOW_BIT 0x4 /* fifo overflow */ 151#define TIMER_BIT 0x8 /* timer interrupt has occured */ 152#define DMATC_BIT 0x10 /* dma terminal count has occured */ 153#define EXT_TRIG_BIT 0x40 /* external trigger has occured */ 154#define STATUS2_REG 0x1d /* 1200 boards only */ 155#define EEPROM_OUT_BIT 0x1 /* programmable eeprom serial output */ 156#define A1_TC_BIT 0x2 /* counter A1 terminal count */ 157#define FNHF_BIT 0x4 /* fifo not half full */ 158#define ADC_FIFO_REG 0xa 159 160#define DIO_BASE_REG 0x10 161#define COUNTER_A_BASE_REG 0x14 162#define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3) 163#define INIT_A0_BITS 0x14 /* check modes put conversion pacer output in harmless state (a0 mode 2) */ 164#define INIT_A1_BITS 0x70 /* put hardware conversion counter output in harmless state (a1 mode 0) */ 165#define COUNTER_B_BASE_REG 0x18 166 167static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it); 168static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 169static irqreturn_t labpc_interrupt(int irq, void *d); 170static int labpc_drain_fifo(struct comedi_device *dev); 171static void labpc_drain_dma(struct comedi_device *dev); 172static void handle_isa_dma(struct comedi_device *dev); 173static void labpc_drain_dregs(struct comedi_device *dev); 174static int labpc_ai_cmdtest(struct comedi_device *dev, 175 struct comedi_subdevice *s, struct comedi_cmd *cmd); 176static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 177static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 178 struct comedi_insn *insn, unsigned int *data); 179static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 180 struct comedi_insn *insn, unsigned int *data); 181static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 182 struct comedi_insn *insn, unsigned int *data); 183static int labpc_calib_read_insn(struct comedi_device *dev, 184 struct comedi_subdevice *s, 185 struct comedi_insn *insn, unsigned int *data); 186static int labpc_calib_write_insn(struct comedi_device *dev, 187 struct comedi_subdevice *s, 188 struct comedi_insn *insn, unsigned int *data); 189static int labpc_eeprom_read_insn(struct comedi_device *dev, 190 struct comedi_subdevice *s, 191 struct comedi_insn *insn, unsigned int *data); 192static int labpc_eeprom_write_insn(struct comedi_device *dev, 193 struct comedi_subdevice *s, 194 struct comedi_insn *insn, 195 unsigned int *data); 196static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd); 197static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd); 198#ifdef CONFIG_COMEDI_PCI 199static int labpc_find_device(struct comedi_device *dev, int bus, int slot); 200#endif 201static int labpc_dio_mem_callback(int dir, int port, int data, 202 unsigned long arg); 203static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 204 unsigned int num_bits); 205static unsigned int labpc_serial_in(struct comedi_device *dev); 206static unsigned int labpc_eeprom_read(struct comedi_device *dev, 207 unsigned int address); 208static unsigned int labpc_eeprom_read_status(struct comedi_device *dev); 209static unsigned int labpc_eeprom_write(struct comedi_device *dev, 210 unsigned int address, 211 unsigned int value); 212static void write_caldac(struct comedi_device *dev, unsigned int channel, 213 unsigned int value); 214 215enum scan_mode { 216 MODE_SINGLE_CHAN, 217 MODE_SINGLE_CHAN_INTERVAL, 218 MODE_MULT_CHAN_UP, 219 MODE_MULT_CHAN_DOWN, 220}; 221 222/* analog input ranges */ 223#define NUM_LABPC_PLUS_AI_RANGES 16 224/* indicates unipolar ranges */ 225static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = { 226 0, 227 0, 228 0, 229 0, 230 0, 231 0, 232 0, 233 0, 234 1, 235 1, 236 1, 237 1, 238 1, 239 1, 240 1, 241 1, 242}; 243 244/* map range index to gain bits */ 245static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = { 246 0x00, 247 0x10, 248 0x20, 249 0x30, 250 0x40, 251 0x50, 252 0x60, 253 0x70, 254 0x00, 255 0x10, 256 0x20, 257 0x30, 258 0x40, 259 0x50, 260 0x60, 261 0x70, 262}; 263 264static const struct comedi_lrange range_labpc_plus_ai = { 265 NUM_LABPC_PLUS_AI_RANGES, 266 { 267 BIP_RANGE(5), 268 BIP_RANGE(4), 269 BIP_RANGE(2.5), 270 BIP_RANGE(1), 271 BIP_RANGE(0.5), 272 BIP_RANGE(0.25), 273 BIP_RANGE(0.1), 274 BIP_RANGE(0.05), 275 UNI_RANGE(10), 276 UNI_RANGE(8), 277 UNI_RANGE(5), 278 UNI_RANGE(2), 279 UNI_RANGE(1), 280 UNI_RANGE(0.5), 281 UNI_RANGE(0.2), 282 UNI_RANGE(0.1), 283 } 284}; 285 286#define NUM_LABPC_1200_AI_RANGES 14 287/* indicates unipolar ranges */ 288const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = { 289 0, 290 0, 291 0, 292 0, 293 0, 294 0, 295 0, 296 1, 297 1, 298 1, 299 1, 300 1, 301 1, 302 1, 303}; 304 305/* map range index to gain bits */ 306const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = { 307 0x00, 308 0x20, 309 0x30, 310 0x40, 311 0x50, 312 0x60, 313 0x70, 314 0x00, 315 0x20, 316 0x30, 317 0x40, 318 0x50, 319 0x60, 320 0x70, 321}; 322 323const struct comedi_lrange range_labpc_1200_ai = { 324 NUM_LABPC_1200_AI_RANGES, 325 { 326 BIP_RANGE(5), 327 BIP_RANGE(2.5), 328 BIP_RANGE(1), 329 BIP_RANGE(0.5), 330 BIP_RANGE(0.25), 331 BIP_RANGE(0.1), 332 BIP_RANGE(0.05), 333 UNI_RANGE(10), 334 UNI_RANGE(5), 335 UNI_RANGE(2), 336 UNI_RANGE(1), 337 UNI_RANGE(0.5), 338 UNI_RANGE(0.2), 339 UNI_RANGE(0.1), 340 } 341}; 342 343/* analog output ranges */ 344#define AO_RANGE_IS_UNIPOLAR 0x1 345static const struct comedi_lrange range_labpc_ao = { 346 2, 347 { 348 BIP_RANGE(5), 349 UNI_RANGE(10), 350 } 351}; 352 353/* functions that do inb/outb and readb/writeb so we can use 354 * function pointers to decide which to use */ 355static inline unsigned int labpc_inb(unsigned long address) 356{ 357 return inb(address); 358} 359 360static inline void labpc_outb(unsigned int byte, unsigned long address) 361{ 362 outb(byte, address); 363} 364 365static inline unsigned int labpc_readb(unsigned long address) 366{ 367 return readb((void *)address); 368} 369 370static inline void labpc_writeb(unsigned int byte, unsigned long address) 371{ 372 writeb(byte, (void *)address); 373} 374 375static const struct labpc_board_struct labpc_boards[] = { 376 { 377 .name = "lab-pc-1200", 378 .ai_speed = 10000, 379 .bustype = isa_bustype, 380 .register_layout = labpc_1200_layout, 381 .has_ao = 1, 382 .ai_range_table = &range_labpc_1200_ai, 383 .ai_range_code = labpc_1200_ai_gain_bits, 384 .ai_range_is_unipolar = labpc_1200_is_unipolar, 385 .ai_scan_up = 1, 386 .memory_mapped_io = 0, 387 }, 388 { 389 .name = "lab-pc-1200ai", 390 .ai_speed = 10000, 391 .bustype = isa_bustype, 392 .register_layout = labpc_1200_layout, 393 .has_ao = 0, 394 .ai_range_table = &range_labpc_1200_ai, 395 .ai_range_code = labpc_1200_ai_gain_bits, 396 .ai_range_is_unipolar = labpc_1200_is_unipolar, 397 .ai_scan_up = 1, 398 .memory_mapped_io = 0, 399 }, 400 { 401 .name = "lab-pc+", 402 .ai_speed = 12000, 403 .bustype = isa_bustype, 404 .register_layout = labpc_plus_layout, 405 .has_ao = 1, 406 .ai_range_table = &range_labpc_plus_ai, 407 .ai_range_code = labpc_plus_ai_gain_bits, 408 .ai_range_is_unipolar = labpc_plus_is_unipolar, 409 .ai_scan_up = 0, 410 .memory_mapped_io = 0, 411 }, 412#ifdef CONFIG_COMEDI_PCI 413 { 414 .name = "pci-1200", 415 .device_id = 0x161, 416 .ai_speed = 10000, 417 .bustype = pci_bustype, 418 .register_layout = labpc_1200_layout, 419 .has_ao = 1, 420 .ai_range_table = &range_labpc_1200_ai, 421 .ai_range_code = labpc_1200_ai_gain_bits, 422 .ai_range_is_unipolar = labpc_1200_is_unipolar, 423 .ai_scan_up = 1, 424 .memory_mapped_io = 1, 425 }, 426 /* dummy entry so pci board works when comedi_config is passed driver name */ 427 { 428 .name = DRV_NAME, 429 .bustype = pci_bustype, 430 }, 431#endif 432}; 433 434/* 435 * Useful for shorthand access to the particular board structure 436 */ 437#define thisboard ((struct labpc_board_struct *)dev->board_ptr) 438 439static const int dma_buffer_size = 0xff00; /* size in bytes of dma buffer */ 440static const int sample_size = 2; /* 2 bytes per sample */ 441 442#define devpriv ((struct labpc_private *)dev->private) 443 444static struct comedi_driver driver_labpc = { 445 .driver_name = DRV_NAME, 446 .module = THIS_MODULE, 447 .attach = labpc_attach, 448 .detach = labpc_common_detach, 449 .num_names = ARRAY_SIZE(labpc_boards), 450 .board_name = &labpc_boards[0].name, 451 .offset = sizeof(struct labpc_board_struct), 452}; 453 454#ifdef CONFIG_COMEDI_PCI 455static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = { 456 { 457 PCI_VENDOR_ID_NATINST, 0x161, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 458 0} 459}; 460 461MODULE_DEVICE_TABLE(pci, labpc_pci_table); 462#endif /* CONFIG_COMEDI_PCI */ 463 464static inline int labpc_counter_load(struct comedi_device *dev, 465 unsigned long base_address, 466 unsigned int counter_number, 467 unsigned int count, unsigned int mode) 468{ 469 if (thisboard->memory_mapped_io) 470 return i8254_mm_load((void *)base_address, 0, counter_number, 471 count, mode); 472 else 473 return i8254_load(base_address, 0, counter_number, count, mode); 474} 475 476int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, 477 unsigned int irq, unsigned int dma_chan) 478{ 479 struct comedi_subdevice *s; 480 int i; 481 unsigned long dma_flags, isr_flags; 482 short lsb, msb; 483 484 printk("comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, thisboard->name, 485 iobase); 486 if (irq) 487 printk(", irq %u", irq); 488 if (dma_chan) 489 printk(", dma %u", dma_chan); 490 printk("\n"); 491 492 if (iobase == 0) { 493 printk("io base address is zero!\n"); 494 return -EINVAL; 495 } 496 /* request io regions for isa boards */ 497 if (thisboard->bustype == isa_bustype) { 498 /* check if io addresses are available */ 499 if (!request_region(iobase, LABPC_SIZE, 500 driver_labpc.driver_name)) { 501 printk("I/O port conflict\n"); 502 return -EIO; 503 } 504 } 505 dev->iobase = iobase; 506 507 if (thisboard->memory_mapped_io) { 508 devpriv->read_byte = labpc_readb; 509 devpriv->write_byte = labpc_writeb; 510 } else { 511 devpriv->read_byte = labpc_inb; 512 devpriv->write_byte = labpc_outb; 513 } 514 /* initialize board's command registers */ 515 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 516 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 517 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 518 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 519 if (thisboard->register_layout == labpc_1200_layout) { 520 devpriv->write_byte(devpriv->command5_bits, 521 dev->iobase + COMMAND5_REG); 522 devpriv->write_byte(devpriv->command6_bits, 523 dev->iobase + COMMAND6_REG); 524 } 525 526 /* grab our IRQ */ 527 if (irq) { 528 isr_flags = 0; 529 if (thisboard->bustype == pci_bustype) 530 isr_flags |= IRQF_SHARED; 531 if (request_irq(irq, labpc_interrupt, isr_flags, 532 driver_labpc.driver_name, dev)) { 533 printk("unable to allocate irq %u\n", irq); 534 return -EINVAL; 535 } 536 } 537 dev->irq = irq; 538 539 /* grab dma channel */ 540 if (dma_chan > 3) { 541 printk(" invalid dma channel %u\n", dma_chan); 542 return -EINVAL; 543 } else if (dma_chan) { 544 /* allocate dma buffer */ 545 devpriv->dma_buffer = 546 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA); 547 if (devpriv->dma_buffer == NULL) { 548 printk(" failed to allocate dma buffer\n"); 549 return -ENOMEM; 550 } 551 if (request_dma(dma_chan, driver_labpc.driver_name)) { 552 printk(" failed to allocate dma channel %u\n", 553 dma_chan); 554 return -EINVAL; 555 } 556 devpriv->dma_chan = dma_chan; 557 dma_flags = claim_dma_lock(); 558 disable_dma(devpriv->dma_chan); 559 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); 560 release_dma_lock(dma_flags); 561 } 562 563 dev->board_name = thisboard->name; 564 565 if (alloc_subdevices(dev, 5) < 0) 566 return -ENOMEM; 567 568 /* analog input subdevice */ 569 s = dev->subdevices + 0; 570 dev->read_subdev = s; 571 s->type = COMEDI_SUBD_AI; 572 s->subdev_flags = 573 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ; 574 s->n_chan = 8; 575 s->len_chanlist = 8; 576 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 577 s->range_table = thisboard->ai_range_table; 578 s->do_cmd = labpc_ai_cmd; 579 s->do_cmdtest = labpc_ai_cmdtest; 580 s->insn_read = labpc_ai_rinsn; 581 s->cancel = labpc_cancel; 582 583 /* analog output */ 584 s = dev->subdevices + 1; 585 if (thisboard->has_ao) { 586/* Could provide command support, except it only has a one sample 587 * hardware buffer for analog output and no underrun flag. */ 588 s->type = COMEDI_SUBD_AO; 589 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; 590 s->n_chan = NUM_AO_CHAN; 591 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 592 s->range_table = &range_labpc_ao; 593 s->insn_read = labpc_ao_rinsn; 594 s->insn_write = labpc_ao_winsn; 595 /* initialize analog outputs to a known value */ 596 for (i = 0; i < s->n_chan; i++) { 597 devpriv->ao_value[i] = s->maxdata / 2; 598 lsb = devpriv->ao_value[i] & 0xff; 599 msb = (devpriv->ao_value[i] >> 8) & 0xff; 600 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); 601 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); 602 } 603 } else { 604 s->type = COMEDI_SUBD_UNUSED; 605 } 606 607 /* 8255 dio */ 608 s = dev->subdevices + 2; 609 /* if board uses io memory we have to give a custom callback function to the 8255 driver */ 610 if (thisboard->memory_mapped_io) 611 subdev_8255_init(dev, s, labpc_dio_mem_callback, 612 (unsigned long)(dev->iobase + DIO_BASE_REG)); 613 else 614 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG); 615 616 /* calibration subdevices for boards that have one */ 617 s = dev->subdevices + 3; 618 if (thisboard->register_layout == labpc_1200_layout) { 619 s->type = COMEDI_SUBD_CALIB; 620 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 621 s->n_chan = 16; 622 s->maxdata = 0xff; 623 s->insn_read = labpc_calib_read_insn; 624 s->insn_write = labpc_calib_write_insn; 625 626 for (i = 0; i < s->n_chan; i++) 627 write_caldac(dev, i, s->maxdata / 2); 628 } else 629 s->type = COMEDI_SUBD_UNUSED; 630 631 /* EEPROM */ 632 s = dev->subdevices + 4; 633 if (thisboard->register_layout == labpc_1200_layout) { 634 s->type = COMEDI_SUBD_MEMORY; 635 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 636 s->n_chan = EEPROM_SIZE; 637 s->maxdata = 0xff; 638 s->insn_read = labpc_eeprom_read_insn; 639 s->insn_write = labpc_eeprom_write_insn; 640 641 for (i = 0; i < EEPROM_SIZE; i++) 642 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); 643#ifdef LABPC_DEBUG 644 printk(" eeprom:"); 645 for (i = 0; i < EEPROM_SIZE; i++) 646 printk(" %i:0x%x ", i, devpriv->eeprom_data[i]); 647 printk("\n"); 648#endif 649 } else 650 s->type = COMEDI_SUBD_UNUSED; 651 652 return 0; 653} 654 655static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) 656{ 657 unsigned long iobase = 0; 658 unsigned int irq = 0; 659 unsigned int dma_chan = 0; 660#ifdef CONFIG_COMEDI_PCI 661 int retval; 662#endif 663 664 /* allocate and initialize dev->private */ 665 if (alloc_private(dev, sizeof(struct labpc_private)) < 0) 666 return -ENOMEM; 667 668 /* get base address, irq etc. based on bustype */ 669 switch (thisboard->bustype) { 670 case isa_bustype: 671 iobase = it->options[0]; 672 irq = it->options[1]; 673 dma_chan = it->options[2]; 674 break; 675 case pci_bustype: 676#ifdef CONFIG_COMEDI_PCI 677 retval = labpc_find_device(dev, it->options[0], it->options[1]); 678 if (retval < 0) 679 return retval; 680 retval = mite_setup(devpriv->mite); 681 if (retval < 0) 682 return retval; 683 iobase = (unsigned long)devpriv->mite->daq_io_addr; 684 irq = mite_irq(devpriv->mite); 685#else 686 printk(" this driver has not been built with PCI support.\n"); 687 return -EINVAL; 688#endif 689 break; 690 case pcmcia_bustype: 691 printk 692 (" this driver does not support pcmcia cards, use ni_labpc_cs.o\n"); 693 return -EINVAL; 694 break; 695 default: 696 printk("bug! couldn't determine board type\n"); 697 return -EINVAL; 698 break; 699 } 700 701 return labpc_common_attach(dev, iobase, irq, dma_chan); 702} 703 704/* adapted from ni_pcimio for finding mite based boards (pc-1200) */ 705#ifdef CONFIG_COMEDI_PCI 706static int labpc_find_device(struct comedi_device *dev, int bus, int slot) 707{ 708 struct mite_struct *mite; 709 int i; 710 for (mite = mite_devices; mite; mite = mite->next) { 711 if (mite->used) 712 continue; 713 /* if bus/slot are specified then make sure we have the right bus/slot */ 714 if (bus || slot) { 715 if (bus != mite->pcidev->bus->number 716 || slot != PCI_SLOT(mite->pcidev->devfn)) 717 continue; 718 } 719 for (i = 0; i < driver_labpc.num_names; i++) { 720 if (labpc_boards[i].bustype != pci_bustype) 721 continue; 722 if (mite_device_id(mite) == labpc_boards[i].device_id) { 723 devpriv->mite = mite; 724 /* fixup board pointer, in case we were using the dummy "ni_labpc" entry */ 725 dev->board_ptr = &labpc_boards[i]; 726 return 0; 727 } 728 } 729 } 730 printk("no device found\n"); 731 mite_list_devices(); 732 return -EIO; 733} 734#endif 735 736int labpc_common_detach(struct comedi_device *dev) 737{ 738 printk("comedi%d: ni_labpc: detach\n", dev->minor); 739 740 if (dev->subdevices) 741 subdev_8255_cleanup(dev, dev->subdevices + 2); 742 743 /* only free stuff if it has been allocated by _attach */ 744 if (devpriv->dma_buffer) 745 kfree(devpriv->dma_buffer); 746 if (devpriv->dma_chan) 747 free_dma(devpriv->dma_chan); 748 if (dev->irq) 749 free_irq(dev->irq, dev); 750 if (thisboard->bustype == isa_bustype && dev->iobase) 751 release_region(dev->iobase, LABPC_SIZE); 752#ifdef CONFIG_COMEDI_PCI 753 if (devpriv->mite) 754 mite_unsetup(devpriv->mite); 755#endif 756 757 return 0; 758}; 759 760static void labpc_clear_adc_fifo(const struct comedi_device *dev) 761{ 762 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 763 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 764 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 765} 766 767static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 768{ 769 unsigned long flags; 770 771 spin_lock_irqsave(&dev->spinlock, flags); 772 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 773 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 774 spin_unlock_irqrestore(&dev->spinlock, flags); 775 776 devpriv->command3_bits = 0; 777 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 778 779 return 0; 780} 781 782static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) 783{ 784 if (cmd->chanlist_len == 1) 785 return MODE_SINGLE_CHAN; 786 787 /* chanlist may be NULL during cmdtest. */ 788 if (cmd->chanlist == NULL) 789 return MODE_MULT_CHAN_UP; 790 791 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) 792 return MODE_SINGLE_CHAN_INTERVAL; 793 794 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) 795 return MODE_MULT_CHAN_UP; 796 797 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) 798 return MODE_MULT_CHAN_DOWN; 799 800 printk("ni_labpc: bug! this should never happen\n"); 801 802 return 0; 803} 804 805static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, 806 const struct comedi_cmd *cmd) 807{ 808 int mode, channel, range, aref, i; 809 810 if (cmd->chanlist == NULL) 811 return 0; 812 813 mode = labpc_ai_scan_mode(cmd); 814 815 if (mode == MODE_SINGLE_CHAN) 816 return 0; 817 818 if (mode == MODE_SINGLE_CHAN_INTERVAL) { 819 if (cmd->chanlist_len > 0xff) { 820 comedi_error(dev, 821 "ni_labpc: chanlist too long for single channel interval mode\n"); 822 return 1; 823 } 824 } 825 826 channel = CR_CHAN(cmd->chanlist[0]); 827 range = CR_RANGE(cmd->chanlist[0]); 828 aref = CR_AREF(cmd->chanlist[0]); 829 830 for (i = 0; i < cmd->chanlist_len; i++) { 831 832 switch (mode) { 833 case MODE_SINGLE_CHAN_INTERVAL: 834 if (CR_CHAN(cmd->chanlist[i]) != channel) { 835 comedi_error(dev, 836 "channel scanning order specified in chanlist is not supported by hardware.\n"); 837 return 1; 838 } 839 break; 840 case MODE_MULT_CHAN_UP: 841 if (CR_CHAN(cmd->chanlist[i]) != i) { 842 comedi_error(dev, 843 "channel scanning order specified in chanlist is not supported by hardware.\n"); 844 return 1; 845 } 846 break; 847 case MODE_MULT_CHAN_DOWN: 848 if (CR_CHAN(cmd->chanlist[i]) != 849 cmd->chanlist_len - i - 1) { 850 comedi_error(dev, 851 "channel scanning order specified in chanlist is not supported by hardware.\n"); 852 return 1; 853 } 854 break; 855 default: 856 printk("ni_labpc: bug! in chanlist check\n"); 857 return 1; 858 break; 859 } 860 861 if (CR_RANGE(cmd->chanlist[i]) != range) { 862 comedi_error(dev, 863 "entries in chanlist must all have the same range\n"); 864 return 1; 865 } 866 867 if (CR_AREF(cmd->chanlist[i]) != aref) { 868 comedi_error(dev, 869 "entries in chanlist must all have the same reference\n"); 870 return 1; 871 } 872 } 873 874 return 0; 875} 876 877static int labpc_use_continuous_mode(const struct comedi_cmd *cmd) 878{ 879 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN) 880 return 1; 881 882 if (cmd->scan_begin_src == TRIG_FOLLOW) 883 return 1; 884 885 return 0; 886} 887 888static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd) 889{ 890 if (cmd->convert_src != TRIG_TIMER) 891 return 0; 892 893 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 894 cmd->scan_begin_src == TRIG_TIMER) 895 return cmd->scan_begin_arg; 896 897 return cmd->convert_arg; 898} 899 900static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns) 901{ 902 if (cmd->convert_src != TRIG_TIMER) 903 return; 904 905 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 906 cmd->scan_begin_src == TRIG_TIMER) { 907 cmd->scan_begin_arg = ns; 908 if (cmd->convert_arg > cmd->scan_begin_arg) 909 cmd->convert_arg = cmd->scan_begin_arg; 910 } else 911 cmd->convert_arg = ns; 912} 913 914static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd) 915{ 916 if (cmd->scan_begin_src != TRIG_TIMER) 917 return 0; 918 919 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 920 cmd->convert_src == TRIG_TIMER) 921 return 0; 922 923 return cmd->scan_begin_arg; 924} 925 926static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns) 927{ 928 if (cmd->scan_begin_src != TRIG_TIMER) 929 return; 930 931 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 932 cmd->convert_src == TRIG_TIMER) 933 return; 934 935 cmd->scan_begin_arg = ns; 936} 937 938static int labpc_ai_cmdtest(struct comedi_device *dev, 939 struct comedi_subdevice *s, struct comedi_cmd *cmd) 940{ 941 int err = 0; 942 int tmp, tmp2; 943 int stop_mask; 944 945 /* step 1: make sure trigger sources are trivially valid */ 946 947 tmp = cmd->start_src; 948 cmd->start_src &= TRIG_NOW | TRIG_EXT; 949 if (!cmd->start_src || tmp != cmd->start_src) 950 err++; 951 952 tmp = cmd->scan_begin_src; 953 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT; 954 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 955 err++; 956 957 tmp = cmd->convert_src; 958 cmd->convert_src &= TRIG_TIMER | TRIG_EXT; 959 if (!cmd->convert_src || tmp != cmd->convert_src) 960 err++; 961 962 tmp = cmd->scan_end_src; 963 cmd->scan_end_src &= TRIG_COUNT; 964 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 965 err++; 966 967 tmp = cmd->stop_src; 968 stop_mask = TRIG_COUNT | TRIG_NONE; 969 if (thisboard->register_layout == labpc_1200_layout) 970 stop_mask |= TRIG_EXT; 971 cmd->stop_src &= stop_mask; 972 if (!cmd->stop_src || tmp != cmd->stop_src) 973 err++; 974 975 if (err) 976 return 1; 977 978 /* step 2: make sure trigger sources are unique and mutually compatible */ 979 980 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) 981 err++; 982 if (cmd->scan_begin_src != TRIG_TIMER && 983 cmd->scan_begin_src != TRIG_FOLLOW && 984 cmd->scan_begin_src != TRIG_EXT) 985 err++; 986 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT) 987 err++; 988 if (cmd->stop_src != TRIG_COUNT && 989 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE) 990 err++; 991 992 /* can't have external stop and start triggers at once */ 993 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) 994 err++; 995 996 if (err) 997 return 2; 998 999 /* step 3: make sure arguments are trivially compatible */ 1000 1001 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) { 1002 cmd->start_arg = 0; 1003 err++; 1004 } 1005 1006 if (!cmd->chanlist_len) 1007 err++; 1008 1009 if (cmd->scan_end_arg != cmd->chanlist_len) { 1010 cmd->scan_end_arg = cmd->chanlist_len; 1011 err++; 1012 } 1013 1014 if (cmd->convert_src == TRIG_TIMER) { 1015 if (cmd->convert_arg < thisboard->ai_speed) { 1016 cmd->convert_arg = thisboard->ai_speed; 1017 err++; 1018 } 1019 } 1020 /* make sure scan timing is not too fast */ 1021 if (cmd->scan_begin_src == TRIG_TIMER) { 1022 if (cmd->convert_src == TRIG_TIMER && 1023 cmd->scan_begin_arg < 1024 cmd->convert_arg * cmd->chanlist_len) { 1025 cmd->scan_begin_arg = 1026 cmd->convert_arg * cmd->chanlist_len; 1027 err++; 1028 } 1029 if (cmd->scan_begin_arg < 1030 thisboard->ai_speed * cmd->chanlist_len) { 1031 cmd->scan_begin_arg = 1032 thisboard->ai_speed * cmd->chanlist_len; 1033 err++; 1034 } 1035 } 1036 /* stop source */ 1037 switch (cmd->stop_src) { 1038 case TRIG_COUNT: 1039 if (!cmd->stop_arg) { 1040 cmd->stop_arg = 1; 1041 err++; 1042 } 1043 break; 1044 case TRIG_NONE: 1045 if (cmd->stop_arg != 0) { 1046 cmd->stop_arg = 0; 1047 err++; 1048 } 1049 break; 1050 /* TRIG_EXT doesn't care since it doesn't trigger off a numbered channel */ 1051 default: 1052 break; 1053 } 1054 1055 if (err) 1056 return 3; 1057 1058 /* step 4: fix up any arguments */ 1059 1060 tmp = cmd->convert_arg; 1061 tmp2 = cmd->scan_begin_arg; 1062 labpc_adc_timing(dev, cmd); 1063 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) 1064 err++; 1065 1066 if (err) 1067 return 4; 1068 1069 if (labpc_ai_chanlist_invalid(dev, cmd)) 1070 return 5; 1071 1072 return 0; 1073} 1074 1075static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 1076{ 1077 int channel, range, aref; 1078 unsigned long irq_flags; 1079 int ret; 1080 struct comedi_async *async = s->async; 1081 struct comedi_cmd *cmd = &async->cmd; 1082 enum transfer_type xfer; 1083 unsigned long flags; 1084 1085 if (!dev->irq) { 1086 comedi_error(dev, "no irq assigned, cannot perform command"); 1087 return -1; 1088 } 1089 1090 range = CR_RANGE(cmd->chanlist[0]); 1091 aref = CR_AREF(cmd->chanlist[0]); 1092 1093 /* make sure board is disabled before setting up aquisition */ 1094 spin_lock_irqsave(&dev->spinlock, flags); 1095 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1096 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1097 spin_unlock_irqrestore(&dev->spinlock, flags); 1098 1099 devpriv->command3_bits = 0; 1100 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1101 1102 /* initialize software conversion count */ 1103 if (cmd->stop_src == TRIG_COUNT) 1104 devpriv->count = cmd->stop_arg * cmd->chanlist_len; 1105 1106 /* setup hardware conversion counter */ 1107 if (cmd->stop_src == TRIG_EXT) { 1108 /* load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0 */ 1109 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1110 1, 3, 0); 1111 if (ret < 0) { 1112 comedi_error(dev, "error loading counter a1"); 1113 return -1; 1114 } 1115 } else /* otherwise, just put a1 in mode 0 with no count to set its output low */ 1116 devpriv->write_byte(INIT_A1_BITS, 1117 dev->iobase + COUNTER_A_CONTROL_REG); 1118 1119 /* figure out what method we will use to transfer data */ 1120 if (devpriv->dma_chan && /* need a dma channel allocated */ 1121 /* dma unsafe at RT priority, and too much setup time for TRIG_WAKE_EOS for */ 1122 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 && 1123 /* only available on the isa boards */ 1124 thisboard->bustype == isa_bustype) { 1125 xfer = isa_dma_transfer; 1126 } else if (thisboard->register_layout == labpc_1200_layout && /* pc-plus has no fifo-half full interrupt */ 1127 /* wake-end-of-scan should interrupt on fifo not empty */ 1128 (cmd->flags & TRIG_WAKE_EOS) == 0 && 1129 /* make sure we are taking more than just a few points */ 1130 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { 1131 xfer = fifo_half_full_transfer; 1132 } else 1133 xfer = fifo_not_empty_transfer; 1134 devpriv->current_transfer = xfer; 1135 1136 /* setup command6 register for 1200 boards */ 1137 if (thisboard->register_layout == labpc_1200_layout) { 1138 /* reference inputs to ground or common? */ 1139 if (aref != AREF_GROUND) 1140 devpriv->command6_bits |= ADC_COMMON_BIT; 1141 else 1142 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1143 /* bipolar or unipolar range? */ 1144 if (thisboard->ai_range_is_unipolar[range]) 1145 devpriv->command6_bits |= ADC_UNIP_BIT; 1146 else 1147 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1148 /* interrupt on fifo half full? */ 1149 if (xfer == fifo_half_full_transfer) 1150 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT; 1151 else 1152 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1153 /* enable interrupt on counter a1 terminal count? */ 1154 if (cmd->stop_src == TRIG_EXT) 1155 devpriv->command6_bits |= A1_INTR_EN_BIT; 1156 else 1157 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1158 /* are we scanning up or down through channels? */ 1159 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1160 devpriv->command6_bits |= ADC_SCAN_UP_BIT; 1161 else 1162 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT; 1163 /* write to register */ 1164 devpriv->write_byte(devpriv->command6_bits, 1165 dev->iobase + COMMAND6_REG); 1166 } 1167 1168 /* setup channel list, etc (command1 register) */ 1169 devpriv->command1_bits = 0; 1170 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1171 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); 1172 else 1173 channel = CR_CHAN(cmd->chanlist[0]); 1174 /* munge channel bits for differential / scan disabled mode */ 1175 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF) 1176 channel *= 2; 1177 devpriv->command1_bits |= ADC_CHAN_BITS(channel); 1178 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1179 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1180 /* manual says to set scan enable bit on second pass */ 1181 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP || 1182 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) { 1183 devpriv->command1_bits |= ADC_SCAN_EN_BIT; 1184 /* need a brief delay before enabling scan, or scan list will get screwed when you switch 1185 * between scan up to scan down mode - dunno why */ 1186 udelay(1); 1187 devpriv->write_byte(devpriv->command1_bits, 1188 dev->iobase + COMMAND1_REG); 1189 } 1190 /* setup any external triggering/pacing (command4 register) */ 1191 devpriv->command4_bits = 0; 1192 if (cmd->convert_src != TRIG_EXT) 1193 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1194 /* XXX should discard first scan when using interval scanning 1195 * since manual says it is not synced with scan clock */ 1196 if (labpc_use_continuous_mode(cmd) == 0) { 1197 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT; 1198 if (cmd->scan_begin_src == TRIG_EXT) 1199 devpriv->command4_bits |= EXT_SCAN_EN_BIT; 1200 } 1201 /* single-ended/differential */ 1202 if (aref == AREF_DIFF) 1203 devpriv->command4_bits |= ADC_DIFF_BIT; 1204 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1205 1206 devpriv->write_byte(cmd->chanlist_len, 1207 dev->iobase + INTERVAL_COUNT_REG); 1208 /* load count */ 1209 devpriv->write_byte(INTERVAL_LOAD_BITS, 1210 dev->iobase + INTERVAL_LOAD_REG); 1211 1212 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) { 1213 /* set up pacing */ 1214 labpc_adc_timing(dev, cmd); 1215 /* load counter b0 in mode 3 */ 1216 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1217 0, devpriv->divisor_b0, 3); 1218 if (ret < 0) { 1219 comedi_error(dev, "error loading counter b0"); 1220 return -1; 1221 } 1222 } 1223 /* set up conversion pacing */ 1224 if (labpc_ai_convert_period(cmd)) { 1225 /* load counter a0 in mode 2 */ 1226 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1227 0, devpriv->divisor_a0, 2); 1228 if (ret < 0) { 1229 comedi_error(dev, "error loading counter a0"); 1230 return -1; 1231 } 1232 } else 1233 devpriv->write_byte(INIT_A0_BITS, 1234 dev->iobase + COUNTER_A_CONTROL_REG); 1235 1236 /* set up scan pacing */ 1237 if (labpc_ai_scan_period(cmd)) { 1238 /* load counter b1 in mode 2 */ 1239 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1240 1, devpriv->divisor_b1, 2); 1241 if (ret < 0) { 1242 comedi_error(dev, "error loading counter b1"); 1243 return -1; 1244 } 1245 } 1246 1247 labpc_clear_adc_fifo(dev); 1248 1249 /* set up dma transfer */ 1250 if (xfer == isa_dma_transfer) { 1251 irq_flags = claim_dma_lock(); 1252 disable_dma(devpriv->dma_chan); 1253 /* clear flip-flop to make sure 2-byte registers for 1254 * count and address get set correctly */ 1255 clear_dma_ff(devpriv->dma_chan); 1256 set_dma_addr(devpriv->dma_chan, 1257 virt_to_bus(devpriv->dma_buffer)); 1258 /* set appropriate size of transfer */ 1259 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd); 1260 if (cmd->stop_src == TRIG_COUNT && 1261 devpriv->count * sample_size < devpriv->dma_transfer_size) { 1262 devpriv->dma_transfer_size = 1263 devpriv->count * sample_size; 1264 } 1265 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); 1266 enable_dma(devpriv->dma_chan); 1267 release_dma_lock(irq_flags); 1268 /* enable board's dma */ 1269 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT; 1270 } else 1271 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT; 1272 1273 /* enable error interrupts */ 1274 devpriv->command3_bits |= ERR_INTR_EN_BIT; 1275 /* enable fifo not empty interrupt? */ 1276 if (xfer == fifo_not_empty_transfer) 1277 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT; 1278 else 1279 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT; 1280 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1281 1282 /* startup aquisition */ 1283 1284 /* command2 reg */ 1285 /* use 2 cascaded counters for pacing */ 1286 spin_lock_irqsave(&dev->spinlock, flags); 1287 devpriv->command2_bits |= CASCADE_BIT; 1288 switch (cmd->start_src) { 1289 case TRIG_EXT: 1290 devpriv->command2_bits |= HWTRIG_BIT; 1291 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT; 1292 break; 1293 case TRIG_NOW: 1294 devpriv->command2_bits |= SWTRIG_BIT; 1295 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT; 1296 break; 1297 default: 1298 comedi_error(dev, "bug with start_src"); 1299 return -1; 1300 break; 1301 } 1302 switch (cmd->stop_src) { 1303 case TRIG_EXT: 1304 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT; 1305 break; 1306 case TRIG_COUNT: 1307 case TRIG_NONE: 1308 break; 1309 default: 1310 comedi_error(dev, "bug with stop_src"); 1311 return -1; 1312 } 1313 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1314 spin_unlock_irqrestore(&dev->spinlock, flags); 1315 1316 return 0; 1317} 1318 1319/* interrupt service routine */ 1320static irqreturn_t labpc_interrupt(int irq, void *d) 1321{ 1322 struct comedi_device *dev = d; 1323 struct comedi_subdevice *s = dev->read_subdev; 1324 struct comedi_async *async; 1325 struct comedi_cmd *cmd; 1326 1327 if (dev->attached == 0) { 1328 comedi_error(dev, "premature interrupt"); 1329 return IRQ_HANDLED; 1330 } 1331 1332 async = s->async; 1333 cmd = &async->cmd; 1334 async->events = 0; 1335 1336 /* read board status */ 1337 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1338 if (thisboard->register_layout == labpc_1200_layout) 1339 devpriv->status2_bits = 1340 devpriv->read_byte(dev->iobase + STATUS2_REG); 1341 1342 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT | 1343 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0 1344 && (devpriv->status2_bits & A1_TC_BIT) == 0 1345 && (devpriv->status2_bits & FNHF_BIT)) { 1346 return IRQ_NONE; 1347 } 1348 1349 if (devpriv->status1_bits & OVERRUN_BIT) { 1350 /* clear error interrupt */ 1351 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1352 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1353 comedi_event(dev, s); 1354 comedi_error(dev, "overrun"); 1355 return IRQ_HANDLED; 1356 } 1357 1358 if (devpriv->current_transfer == isa_dma_transfer) { 1359 /* if a dma terminal count of external stop trigger has occurred */ 1360 if (devpriv->status1_bits & DMATC_BIT || 1361 (thisboard->register_layout == labpc_1200_layout 1362 && devpriv->status2_bits & A1_TC_BIT)) { 1363 handle_isa_dma(dev); 1364 } 1365 } else 1366 labpc_drain_fifo(dev); 1367 1368 if (devpriv->status1_bits & TIMER_BIT) { 1369 comedi_error(dev, "handled timer interrupt?"); 1370 /* clear it */ 1371 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); 1372 } 1373 1374 if (devpriv->status1_bits & OVERFLOW_BIT) { 1375 /* clear error interrupt */ 1376 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1377 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1378 comedi_event(dev, s); 1379 comedi_error(dev, "overflow"); 1380 return IRQ_HANDLED; 1381 } 1382 /* handle external stop trigger */ 1383 if (cmd->stop_src == TRIG_EXT) { 1384 if (devpriv->status2_bits & A1_TC_BIT) { 1385 labpc_drain_dregs(dev); 1386 labpc_cancel(dev, s); 1387 async->events |= COMEDI_CB_EOA; 1388 } 1389 } 1390 1391 /* TRIG_COUNT end of acquisition */ 1392 if (cmd->stop_src == TRIG_COUNT) { 1393 if (devpriv->count == 0) { 1394 labpc_cancel(dev, s); 1395 async->events |= COMEDI_CB_EOA; 1396 } 1397 } 1398 1399 comedi_event(dev, s); 1400 return IRQ_HANDLED; 1401} 1402 1403/* read all available samples from ai fifo */ 1404static int labpc_drain_fifo(struct comedi_device *dev) 1405{ 1406 unsigned int lsb, msb; 1407 short data; 1408 struct comedi_async *async = dev->read_subdev->async; 1409 const int timeout = 10000; 1410 unsigned int i; 1411 1412 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1413 1414 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout; 1415 i++) { 1416 /* quit if we have all the data we want */ 1417 if (async->cmd.stop_src == TRIG_COUNT) { 1418 if (devpriv->count == 0) 1419 break; 1420 devpriv->count--; 1421 } 1422 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1423 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1424 data = (msb << 8) | lsb; 1425 cfc_write_to_buffer(dev->read_subdev, data); 1426 devpriv->status1_bits = 1427 devpriv->read_byte(dev->iobase + STATUS1_REG); 1428 } 1429 if (i == timeout) { 1430 comedi_error(dev, "ai timeout, fifo never empties"); 1431 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1432 return -1; 1433 } 1434 1435 return 0; 1436} 1437 1438static void labpc_drain_dma(struct comedi_device *dev) 1439{ 1440 struct comedi_subdevice *s = dev->read_subdev; 1441 struct comedi_async *async = s->async; 1442 int status; 1443 unsigned long flags; 1444 unsigned int max_points, num_points, residue, leftover; 1445 int i; 1446 1447 status = devpriv->status1_bits; 1448 1449 flags = claim_dma_lock(); 1450 disable_dma(devpriv->dma_chan); 1451 /* clear flip-flop to make sure 2-byte registers for 1452 * count and address get set correctly */ 1453 clear_dma_ff(devpriv->dma_chan); 1454 1455 /* figure out how many points to read */ 1456 max_points = devpriv->dma_transfer_size / sample_size; 1457 /* residue is the number of points left to be done on the dma 1458 * transfer. It should always be zero at this point unless 1459 * the stop_src is set to external triggering. 1460 */ 1461 residue = get_dma_residue(devpriv->dma_chan) / sample_size; 1462 num_points = max_points - residue; 1463 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) 1464 num_points = devpriv->count; 1465 1466 /* figure out how many points will be stored next time */ 1467 leftover = 0; 1468 if (async->cmd.stop_src != TRIG_COUNT) { 1469 leftover = devpriv->dma_transfer_size / sample_size; 1470 } else if (devpriv->count > num_points) { 1471 leftover = devpriv->count - num_points; 1472 if (leftover > max_points) 1473 leftover = max_points; 1474 } 1475 1476 /* write data to comedi buffer */ 1477 for (i = 0; i < num_points; i++) 1478 cfc_write_to_buffer(s, devpriv->dma_buffer[i]); 1479 1480 if (async->cmd.stop_src == TRIG_COUNT) 1481 devpriv->count -= num_points; 1482 1483 /* set address and count for next transfer */ 1484 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); 1485 set_dma_count(devpriv->dma_chan, leftover * sample_size); 1486 release_dma_lock(flags); 1487 1488 async->events |= COMEDI_CB_BLOCK; 1489} 1490 1491static void handle_isa_dma(struct comedi_device *dev) 1492{ 1493 labpc_drain_dma(dev); 1494 1495 enable_dma(devpriv->dma_chan); 1496 1497 /* clear dma tc interrupt */ 1498 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); 1499} 1500 1501/* makes sure all data aquired by board is transfered to comedi (used 1502 * when aquisition is terminated by stop_src == TRIG_EXT). */ 1503static void labpc_drain_dregs(struct comedi_device *dev) 1504{ 1505 if (devpriv->current_transfer == isa_dma_transfer) 1506 labpc_drain_dma(dev); 1507 1508 labpc_drain_fifo(dev); 1509} 1510 1511static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1512 struct comedi_insn *insn, unsigned int *data) 1513{ 1514 int i, n; 1515 int chan, range; 1516 int lsb, msb; 1517 int timeout = 1000; 1518 unsigned long flags; 1519 1520 /* disable timed conversions */ 1521 spin_lock_irqsave(&dev->spinlock, flags); 1522 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1523 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1524 spin_unlock_irqrestore(&dev->spinlock, flags); 1525 1526 /* disable interrupt generation and dma */ 1527 devpriv->command3_bits = 0; 1528 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1529 1530 /* set gain and channel */ 1531 devpriv->command1_bits = 0; 1532 chan = CR_CHAN(insn->chanspec); 1533 range = CR_RANGE(insn->chanspec); 1534 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1535 /* munge channel bits for differential/scan disabled mode */ 1536 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1537 chan *= 2; 1538 devpriv->command1_bits |= ADC_CHAN_BITS(chan); 1539 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1540 1541 /* setup command6 register for 1200 boards */ 1542 if (thisboard->register_layout == labpc_1200_layout) { 1543 /* reference inputs to ground or common? */ 1544 if (CR_AREF(insn->chanspec) != AREF_GROUND) 1545 devpriv->command6_bits |= ADC_COMMON_BIT; 1546 else 1547 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1548 /* bipolar or unipolar range? */ 1549 if (thisboard->ai_range_is_unipolar[range]) 1550 devpriv->command6_bits |= ADC_UNIP_BIT; 1551 else 1552 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1553 /* don't interrupt on fifo half full */ 1554 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1555 /* don't enable interrupt on counter a1 terminal count? */ 1556 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1557 /* write to register */ 1558 devpriv->write_byte(devpriv->command6_bits, 1559 dev->iobase + COMMAND6_REG); 1560 } 1561 /* setup command4 register */ 1562 devpriv->command4_bits = 0; 1563 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1564 /* single-ended/differential */ 1565 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1566 devpriv->command4_bits |= ADC_DIFF_BIT; 1567 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1568 1569 /* initialize pacer counter output to make sure it doesn't cause any problems */ 1570 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG); 1571 1572 labpc_clear_adc_fifo(dev); 1573 1574 for (n = 0; n < insn->n; n++) { 1575 /* trigger conversion */ 1576 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG); 1577 1578 for (i = 0; i < timeout; i++) { 1579 if (devpriv->read_byte(dev->iobase + 1580 STATUS1_REG) & DATA_AVAIL_BIT) 1581 break; 1582 udelay(1); 1583 } 1584 if (i == timeout) { 1585 comedi_error(dev, "timeout"); 1586 return -ETIME; 1587 } 1588 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1589 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1590 data[n] = (msb << 8) | lsb; 1591 } 1592 1593 return n; 1594} 1595 1596/* analog output insn */ 1597static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 1598 struct comedi_insn *insn, unsigned int *data) 1599{ 1600 int channel, range; 1601 unsigned long flags; 1602 int lsb, msb; 1603 1604 channel = CR_CHAN(insn->chanspec); 1605 1606 /* turn off pacing of analog output channel */ 1607 /* note: hardware bug in daqcard-1200 means pacing cannot 1608 * be independently enabled/disabled for its the two channels */ 1609 spin_lock_irqsave(&dev->spinlock, flags); 1610 devpriv->command2_bits &= ~DAC_PACED_BIT(channel); 1611 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1612 spin_unlock_irqrestore(&dev->spinlock, flags); 1613 1614 /* set range */ 1615 if (thisboard->register_layout == labpc_1200_layout) { 1616 range = CR_RANGE(insn->chanspec); 1617 if (range & AO_RANGE_IS_UNIPOLAR) 1618 devpriv->command6_bits |= DAC_UNIP_BIT(channel); 1619 else 1620 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel); 1621 /* write to register */ 1622 devpriv->write_byte(devpriv->command6_bits, 1623 dev->iobase + COMMAND6_REG); 1624 } 1625 /* send data */ 1626 lsb = data[0] & 0xff; 1627 msb = (data[0] >> 8) & 0xff; 1628 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); 1629 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); 1630 1631 /* remember value for readback */ 1632 devpriv->ao_value[channel] = data[0]; 1633 1634 return 1; 1635} 1636 1637/* analog output readback insn */ 1638static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1639 struct comedi_insn *insn, unsigned int *data) 1640{ 1641 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; 1642 1643 return 1; 1644} 1645 1646static int labpc_calib_read_insn(struct comedi_device *dev, 1647 struct comedi_subdevice *s, 1648 struct comedi_insn *insn, unsigned int *data) 1649{ 1650 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)]; 1651 1652 return 1; 1653} 1654 1655static int labpc_calib_write_insn(struct comedi_device *dev, 1656 struct comedi_subdevice *s, 1657 struct comedi_insn *insn, unsigned int *data) 1658{ 1659 int channel = CR_CHAN(insn->chanspec); 1660 1661 write_caldac(dev, channel, data[0]); 1662 return 1; 1663} 1664 1665static int labpc_eeprom_read_insn(struct comedi_device *dev, 1666 struct comedi_subdevice *s, 1667 struct comedi_insn *insn, unsigned int *data) 1668{ 1669 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)]; 1670 1671 return 1; 1672} 1673 1674static int labpc_eeprom_write_insn(struct comedi_device *dev, 1675 struct comedi_subdevice *s, 1676 struct comedi_insn *insn, unsigned int *data) 1677{ 1678 int channel = CR_CHAN(insn->chanspec); 1679 int ret; 1680 1681 /* only allow writes to user area of eeprom */ 1682 if (channel < 16 || channel > 127) { 1683 printk 1684 ("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)"); 1685 return -EINVAL; 1686 } 1687 1688 ret = labpc_eeprom_write(dev, channel, data[0]); 1689 if (ret < 0) 1690 return ret; 1691 1692 return 1; 1693} 1694 1695/* utility function that suggests a dma transfer size in bytes */ 1696static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd) 1697{ 1698 unsigned int size; 1699 unsigned int freq; 1700 1701 if (cmd.convert_src == TRIG_TIMER) 1702 freq = 1000000000 / cmd.convert_arg; 1703 /* return some default value */ 1704 else 1705 freq = 0xffffffff; 1706 1707 /* make buffer fill in no more than 1/3 second */ 1708 size = (freq / 3) * sample_size; 1709 1710 /* set a minimum and maximum size allowed */ 1711 if (size > dma_buffer_size) 1712 size = dma_buffer_size - dma_buffer_size % sample_size; 1713 else if (size < sample_size) 1714 size = sample_size; 1715 1716 return size; 1717} 1718 1719/* figures out what counter values to use based on command */ 1720static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) 1721{ 1722 const int max_counter_value = 0x10000; /* max value for 16 bit counter in mode 2 */ 1723 const int min_counter_value = 2; /* min value for 16 bit counter in mode 2 */ 1724 unsigned int base_period; 1725 1726 /* if both convert and scan triggers are TRIG_TIMER, then they both rely on counter b0 */ 1727 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) { 1728 /* pick the lowest b0 divisor value we can (for maximum input clock speed on convert and scan counters) */ 1729 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) / 1730 (LABPC_TIMER_BASE * max_counter_value) + 1; 1731 if (devpriv->divisor_b0 < min_counter_value) 1732 devpriv->divisor_b0 = min_counter_value; 1733 if (devpriv->divisor_b0 > max_counter_value) 1734 devpriv->divisor_b0 = max_counter_value; 1735 1736 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; 1737 1738 /* set a0 for conversion frequency and b1 for scan frequency */ 1739 switch (cmd->flags & TRIG_ROUND_MASK) { 1740 default: 1741 case TRIG_ROUND_NEAREST: 1742 devpriv->divisor_a0 = 1743 (labpc_ai_convert_period(cmd) + 1744 (base_period / 2)) / base_period; 1745 devpriv->divisor_b1 = 1746 (labpc_ai_scan_period(cmd) + 1747 (base_period / 2)) / base_period; 1748 break; 1749 case TRIG_ROUND_UP: 1750 devpriv->divisor_a0 = 1751 (labpc_ai_convert_period(cmd) + (base_period - 1752 1)) / base_period; 1753 devpriv->divisor_b1 = 1754 (labpc_ai_scan_period(cmd) + (base_period - 1755 1)) / base_period; 1756 break; 1757 case TRIG_ROUND_DOWN: 1758 devpriv->divisor_a0 = 1759 labpc_ai_convert_period(cmd) / base_period; 1760 devpriv->divisor_b1 = 1761 labpc_ai_scan_period(cmd) / base_period; 1762 break; 1763 } 1764 /* make sure a0 and b1 values are acceptable */ 1765 if (devpriv->divisor_a0 < min_counter_value) 1766 devpriv->divisor_a0 = min_counter_value; 1767 if (devpriv->divisor_a0 > max_counter_value) 1768 devpriv->divisor_a0 = max_counter_value; 1769 if (devpriv->divisor_b1 < min_counter_value) 1770 devpriv->divisor_b1 = min_counter_value; 1771 if (devpriv->divisor_b1 > max_counter_value) 1772 devpriv->divisor_b1 = max_counter_value; 1773 /* write corrected timings to command */ 1774 labpc_set_ai_convert_period(cmd, 1775 base_period * devpriv->divisor_a0); 1776 labpc_set_ai_scan_period(cmd, 1777 base_period * devpriv->divisor_b1); 1778 /* if only one TRIG_TIMER is used, we can employ the generic cascaded timing functions */ 1779 } else if (labpc_ai_scan_period(cmd)) { 1780 unsigned int scan_period; 1781 1782 scan_period = labpc_ai_scan_period(cmd); 1783 /* calculate cascaded counter values that give desired scan timing */ 1784 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1785 &(devpriv->divisor_b1), 1786 &(devpriv->divisor_b0), 1787 &scan_period, 1788 cmd->flags & TRIG_ROUND_MASK); 1789 labpc_set_ai_scan_period(cmd, scan_period); 1790 } else if (labpc_ai_convert_period(cmd)) { 1791 unsigned int convert_period; 1792 1793 convert_period = labpc_ai_convert_period(cmd); 1794 /* calculate cascaded counter values that give desired conversion timing */ 1795 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1796 &(devpriv->divisor_a0), 1797 &(devpriv->divisor_b0), 1798 &convert_period, 1799 cmd->flags & TRIG_ROUND_MASK); 1800 labpc_set_ai_convert_period(cmd, convert_period); 1801 } 1802} 1803 1804static int labpc_dio_mem_callback(int dir, int port, int data, 1805 unsigned long iobase) 1806{ 1807 if (dir) { 1808 writeb(data, (void *)(iobase + port)); 1809 return 0; 1810 } else { 1811 return readb((void *)(iobase + port)); 1812 } 1813} 1814 1815/* lowlevel write to eeprom/dac */ 1816static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 1817 unsigned int value_width) 1818{ 1819 int i; 1820 1821 for (i = 1; i <= value_width; i++) { 1822 /* clear serial clock */ 1823 devpriv->command5_bits &= ~SCLOCK_BIT; 1824 /* send bits most significant bit first */ 1825 if (value & (1 << (value_width - i))) 1826 devpriv->command5_bits |= SDATA_BIT; 1827 else 1828 devpriv->command5_bits &= ~SDATA_BIT; 1829 udelay(1); 1830 devpriv->write_byte(devpriv->command5_bits, 1831 dev->iobase + COMMAND5_REG); 1832 /* set clock to load bit */ 1833 devpriv->command5_bits |= SCLOCK_BIT; 1834 udelay(1); 1835 devpriv->write_byte(devpriv->command5_bits, 1836 dev->iobase + COMMAND5_REG); 1837 } 1838} 1839 1840/* lowlevel read from eeprom */ 1841static unsigned int labpc_serial_in(struct comedi_device *dev) 1842{ 1843 unsigned int value = 0; 1844 int i; 1845 const int value_width = 8; /* number of bits wide values are */ 1846 1847 for (i = 1; i <= value_width; i++) { 1848 /* set serial clock */ 1849 devpriv->command5_bits |= SCLOCK_BIT; 1850 udelay(1); 1851 devpriv->write_byte(devpriv->command5_bits, 1852 dev->iobase + COMMAND5_REG); 1853 /* clear clock bit */ 1854 devpriv->command5_bits &= ~SCLOCK_BIT; 1855 udelay(1); 1856 devpriv->write_byte(devpriv->command5_bits, 1857 dev->iobase + COMMAND5_REG); 1858 /* read bits most significant bit first */ 1859 udelay(1); 1860 devpriv->status2_bits = 1861 devpriv->read_byte(dev->iobase + STATUS2_REG); 1862 if (devpriv->status2_bits & EEPROM_OUT_BIT) 1863 value |= 1 << (value_width - i); 1864 1865 } 1866 1867 return value; 1868} 1869 1870static unsigned int labpc_eeprom_read(struct comedi_device *dev, 1871 unsigned int address) 1872{ 1873 unsigned int value; 1874 const int read_instruction = 0x3; /* bits to tell eeprom to expect a read */ 1875 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1876 1877 /* enable read/write to eeprom */ 1878 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1879 udelay(1); 1880 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1881 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1882 udelay(1); 1883 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1884 1885 /* send read instruction */ 1886 labpc_serial_out(dev, read_instruction, write_length); 1887 /* send 8 bit address to read from */ 1888 labpc_serial_out(dev, address, write_length); 1889 /* read result */ 1890 value = labpc_serial_in(dev); 1891 1892 /* disable read/write to eeprom */ 1893 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1894 udelay(1); 1895 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1896 1897 return value; 1898} 1899 1900static unsigned int labpc_eeprom_write(struct comedi_device *dev, 1901 unsigned int address, unsigned int value) 1902{ 1903 const int write_enable_instruction = 0x6; 1904 const int write_instruction = 0x2; 1905 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1906 const int write_in_progress_bit = 0x1; 1907 const int timeout = 10000; 1908 int i; 1909 1910 /* make sure there isn't already a write in progress */ 1911 for (i = 0; i < timeout; i++) { 1912 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == 1913 0) 1914 break; 1915 } 1916 if (i == timeout) { 1917 comedi_error(dev, "eeprom write timed out"); 1918 return -ETIME; 1919 } 1920 /* update software copy of eeprom */ 1921 devpriv->eeprom_data[address] = value; 1922 1923 /* enable read/write to eeprom */ 1924 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1925 udelay(1); 1926 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1927 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1928 udelay(1); 1929 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1930 1931 /* send write_enable instruction */ 1932 labpc_serial_out(dev, write_enable_instruction, write_length); 1933 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1934 udelay(1); 1935 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1936 1937 /* send write instruction */ 1938 devpriv->command5_bits |= EEPROM_EN_BIT; 1939 udelay(1); 1940 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1941 labpc_serial_out(dev, write_instruction, write_length); 1942 /* send 8 bit address to write to */ 1943 labpc_serial_out(dev, address, write_length); 1944 /* write value */ 1945 labpc_serial_out(dev, value, write_length); 1946 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1947 udelay(1); 1948 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1949 1950 /* disable read/write to eeprom */ 1951 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1952 udelay(1); 1953 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1954 1955 return 0; 1956} 1957 1958static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) 1959{ 1960 unsigned int value; 1961 const int read_status_instruction = 0x5; 1962 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1963 1964 /* enable read/write to eeprom */ 1965 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1966 udelay(1); 1967 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1968 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1969 udelay(1); 1970 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1971 1972 /* send read status instruction */ 1973 labpc_serial_out(dev, read_status_instruction, write_length); 1974 /* read result */ 1975 value = labpc_serial_in(dev); 1976 1977 /* disable read/write to eeprom */ 1978 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1979 udelay(1); 1980 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1981 1982 return value; 1983} 1984 1985/* writes to 8 bit calibration dacs */ 1986static void write_caldac(struct comedi_device *dev, unsigned int channel, 1987 unsigned int value) 1988{ 1989 if (value == devpriv->caldac[channel]) 1990 return; 1991 devpriv->caldac[channel] = value; 1992 1993 /* clear caldac load bit and make sure we don't write to eeprom */ 1994 devpriv->command5_bits &= 1995 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1996 udelay(1); 1997 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1998 1999 /* write 4 bit channel */ 2000 labpc_serial_out(dev, channel, 4); 2001 /* write 8 bit caldac value */ 2002 labpc_serial_out(dev, value, 8); 2003 2004 /* set and clear caldac bit to load caldac value */ 2005 devpriv->command5_bits |= CALDAC_LOAD_BIT; 2006 udelay(1); 2007 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2008 devpriv->command5_bits &= ~CALDAC_LOAD_BIT; 2009 udelay(1); 2010 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2011} 2012 2013#ifdef CONFIG_COMEDI_PCI 2014COMEDI_PCI_INITCLEANUP(driver_labpc, labpc_pci_table); 2015#else 2016COMEDI_INITCLEANUP(driver_labpc); 2017#endif 2018 2019EXPORT_SYMBOL_GPL(labpc_common_attach); 2020EXPORT_SYMBOL_GPL(labpc_common_detach); 2021EXPORT_SYMBOL_GPL(range_labpc_1200_ai); 2022EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); 2023EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar); 2024