ni_labpc.c revision 9d220c6b54f3d0b141846321814ec1c4e4fbdc67
1/* 2 comedi/drivers/ni_labpc.c 3 Driver for National Instruments Lab-PC series boards and compatibles 4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20************************************************************************ 21*/ 22/* 23Driver: ni_labpc 24Description: National Instruments Lab-PC (& compatibles) 25Author: Frank Mori Hess <fmhess@users.sourceforge.net> 26Devices: [National Instruments] Lab-PC-1200 (labpc-1200), 27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc) 28Status: works 29 30Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges 31and analog references will work, the available ranges/arefs will 32depend on how you have configured the jumpers on your board 33(see your owner's manual). 34 35Kernel-level ISA plug-and-play support for the lab-pc-1200 36boards has not 37yet been added to the driver, mainly due to the fact that 38I don't know the device id numbers. If you have one 39of these boards, 40please file a bug report at https://bugs.comedi.org/ 41so I can get the necessary information from you. 42 43The 1200 series boards have onboard calibration dacs for correcting 44analog input/output offsets and gains. The proper settings for these 45caldacs are stored on the board's eeprom. To read the caldac values 46from the eeprom and store them into a file that can be then be used by 47comedilib, use the comedi_calibrate program. 48 49Configuration options - ISA boards: 50 [0] - I/O port base address 51 [1] - IRQ (optional, required for timed or externally triggered conversions) 52 [2] - DMA channel (optional) 53 54Configuration options - PCI boards: 55 [0] - bus (optional) 56 [1] - slot (optional) 57 58The Lab-pc+ has quirky chanlist requirements 59when scanning multiple channels. Multiple channel scan 60sequence must start at highest channel, then decrement down to 61channel 0. The rest of the cards can scan down like lab-pc+ or scan 62up from channel zero. Chanlists consisting of all one channel 63are also legal, and allow you to pace conversions in bursts. 64 65*/ 66 67/* 68 69NI manuals: 70341309a (labpc-1200 register manual) 71340914a (pci-1200) 72320502b (lab-pc+) 73 74*/ 75 76#undef LABPC_DEBUG 77/* #define LABPC_DEBUG enable debugging messages */ 78 79#include <linux/interrupt.h> 80#include "../comedidev.h" 81 82#include <linux/delay.h> 83#include <asm/dma.h> 84 85#include "8253.h" 86#include "8255.h" 87#include "mite.h" 88#include "comedi_fc.h" 89#include "ni_labpc.h" 90 91#define DRV_NAME "ni_labpc" 92 93#define LABPC_SIZE 32 /* size of io region used by board */ 94#define LABPC_TIMER_BASE 500 /* 2 MHz master clock */ 95 96/* Registers for the lab-pc+ */ 97 98/* write-only registers */ 99#define COMMAND1_REG 0x0 100#define ADC_GAIN_MASK (0x7 << 4) 101#define ADC_CHAN_BITS(x) ((x) & 0x7) 102#define ADC_SCAN_EN_BIT 0x80 /* enables multi channel scans */ 103#define COMMAND2_REG 0x1 104#define PRETRIG_BIT 0x1 /* enable pretriggering (used in conjunction with SWTRIG) */ 105#define HWTRIG_BIT 0x2 /* enable paced conversions on external trigger */ 106#define SWTRIG_BIT 0x4 /* enable paced conversions */ 107#define CASCADE_BIT 0x8 /* use two cascaded counters for pacing */ 108#define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1)) 109#define COMMAND3_REG 0x2 110#define DMA_EN_BIT 0x1 /* enable dma transfers */ 111#define DIO_INTR_EN_BIT 0x2 /* enable interrupts for 8255 */ 112#define DMATC_INTR_EN_BIT 0x4 /* enable dma terminal count interrupt */ 113#define TIMER_INTR_EN_BIT 0x8 /* enable timer interrupt */ 114#define ERR_INTR_EN_BIT 0x10 /* enable error interrupt */ 115#define ADC_FNE_INTR_EN_BIT 0x20 /* enable fifo not empty interrupt */ 116#define ADC_CONVERT_REG 0x3 117#define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1)) 118#define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1)) 119#define ADC_CLEAR_REG 0x8 120#define DMATC_CLEAR_REG 0xa 121#define TIMER_CLEAR_REG 0xc 122#define COMMAND6_REG 0xe /* 1200 boards only */ 123#define ADC_COMMON_BIT 0x1 /* select ground or common-mode reference */ 124#define ADC_UNIP_BIT 0x2 /* adc unipolar */ 125#define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) /* dac unipolar */ 126#define ADC_FHF_INTR_EN_BIT 0x20 /* enable fifo half full interrupt */ 127#define A1_INTR_EN_BIT 0x40 /* enable interrupt on end of hardware count */ 128#define ADC_SCAN_UP_BIT 0x80 /* scan up from channel zero instead of down to zero */ 129#define COMMAND4_REG 0xf 130#define INTERVAL_SCAN_EN_BIT 0x1 /* enables 'interval' scanning */ 131#define EXT_SCAN_EN_BIT 0x2 /* enables external signal on counter b1 output to trigger scan */ 132#define EXT_CONVERT_OUT_BIT 0x4 /* chooses direction (output or input) for EXTCONV* line */ 133#define ADC_DIFF_BIT 0x8 /* chooses differential inputs for adc (in conjunction with board jumper) */ 134#define EXT_CONVERT_DISABLE_BIT 0x10 135#define COMMAND5_REG 0x1c /* 1200 boards only, calibration stuff */ 136#define EEPROM_WRITE_UNPROTECT_BIT 0x4 /* enable eeprom for write */ 137#define DITHER_EN_BIT 0x8 /* enable dithering */ 138#define CALDAC_LOAD_BIT 0x10 /* load calibration dac */ 139#define SCLOCK_BIT 0x20 /* serial clock - rising edge writes, falling edge reads */ 140#define SDATA_BIT 0x40 /* serial data bit for writing to eeprom or calibration dacs */ 141#define EEPROM_EN_BIT 0x80 /* enable eeprom for read/write */ 142#define INTERVAL_COUNT_REG 0x1e 143#define INTERVAL_LOAD_REG 0x1f 144#define INTERVAL_LOAD_BITS 0x1 145 146/* read-only registers */ 147#define STATUS1_REG 0x0 148#define DATA_AVAIL_BIT 0x1 /* data is available in fifo */ 149#define OVERRUN_BIT 0x2 /* overrun has occurred */ 150#define OVERFLOW_BIT 0x4 /* fifo overflow */ 151#define TIMER_BIT 0x8 /* timer interrupt has occured */ 152#define DMATC_BIT 0x10 /* dma terminal count has occured */ 153#define EXT_TRIG_BIT 0x40 /* external trigger has occured */ 154#define STATUS2_REG 0x1d /* 1200 boards only */ 155#define EEPROM_OUT_BIT 0x1 /* programmable eeprom serial output */ 156#define A1_TC_BIT 0x2 /* counter A1 terminal count */ 157#define FNHF_BIT 0x4 /* fifo not half full */ 158#define ADC_FIFO_REG 0xa 159 160#define DIO_BASE_REG 0x10 161#define COUNTER_A_BASE_REG 0x14 162#define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3) 163#define INIT_A0_BITS 0x14 /* check modes put conversion pacer output in harmless state (a0 mode 2) */ 164#define INIT_A1_BITS 0x70 /* put hardware conversion counter output in harmless state (a1 mode 0) */ 165#define COUNTER_B_BASE_REG 0x18 166 167static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it); 168static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 169static irqreturn_t labpc_interrupt(int irq, void *d); 170static int labpc_drain_fifo(struct comedi_device *dev); 171static void labpc_drain_dma(struct comedi_device *dev); 172static void handle_isa_dma(struct comedi_device *dev); 173static void labpc_drain_dregs(struct comedi_device *dev); 174static int labpc_ai_cmdtest(struct comedi_device *dev, 175 struct comedi_subdevice *s, struct comedi_cmd *cmd); 176static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 177static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 178 struct comedi_insn *insn, unsigned int *data); 179static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 180 struct comedi_insn *insn, unsigned int *data); 181static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 182 struct comedi_insn *insn, unsigned int *data); 183static int labpc_calib_read_insn(struct comedi_device *dev, 184 struct comedi_subdevice *s, 185 struct comedi_insn *insn, unsigned int *data); 186static int labpc_calib_write_insn(struct comedi_device *dev, 187 struct comedi_subdevice *s, 188 struct comedi_insn *insn, unsigned int *data); 189static int labpc_eeprom_read_insn(struct comedi_device *dev, 190 struct comedi_subdevice *s, 191 struct comedi_insn *insn, unsigned int *data); 192static int labpc_eeprom_write_insn(struct comedi_device *dev, 193 struct comedi_subdevice *s, 194 struct comedi_insn *insn, 195 unsigned int *data); 196static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd); 197static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd); 198#ifdef CONFIG_COMEDI_PCI 199static int labpc_find_device(struct comedi_device *dev, int bus, int slot); 200#endif 201static int labpc_dio_mem_callback(int dir, int port, int data, 202 unsigned long arg); 203static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 204 unsigned int num_bits); 205static unsigned int labpc_serial_in(struct comedi_device *dev); 206static unsigned int labpc_eeprom_read(struct comedi_device *dev, 207 unsigned int address); 208static unsigned int labpc_eeprom_read_status(struct comedi_device *dev); 209static unsigned int labpc_eeprom_write(struct comedi_device *dev, 210 unsigned int address, 211 unsigned int value); 212static void write_caldac(struct comedi_device *dev, unsigned int channel, 213 unsigned int value); 214 215enum scan_mode { 216 MODE_SINGLE_CHAN, 217 MODE_SINGLE_CHAN_INTERVAL, 218 MODE_MULT_CHAN_UP, 219 MODE_MULT_CHAN_DOWN, 220}; 221 222/* analog input ranges */ 223#define NUM_LABPC_PLUS_AI_RANGES 16 224/* indicates unipolar ranges */ 225static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = { 226 0, 227 0, 228 0, 229 0, 230 0, 231 0, 232 0, 233 0, 234 1, 235 1, 236 1, 237 1, 238 1, 239 1, 240 1, 241 1, 242}; 243 244/* map range index to gain bits */ 245static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = { 246 0x00, 247 0x10, 248 0x20, 249 0x30, 250 0x40, 251 0x50, 252 0x60, 253 0x70, 254 0x00, 255 0x10, 256 0x20, 257 0x30, 258 0x40, 259 0x50, 260 0x60, 261 0x70, 262}; 263 264static const struct comedi_lrange range_labpc_plus_ai = { 265 NUM_LABPC_PLUS_AI_RANGES, 266 { 267 BIP_RANGE(5), 268 BIP_RANGE(4), 269 BIP_RANGE(2.5), 270 BIP_RANGE(1), 271 BIP_RANGE(0.5), 272 BIP_RANGE(0.25), 273 BIP_RANGE(0.1), 274 BIP_RANGE(0.05), 275 UNI_RANGE(10), 276 UNI_RANGE(8), 277 UNI_RANGE(5), 278 UNI_RANGE(2), 279 UNI_RANGE(1), 280 UNI_RANGE(0.5), 281 UNI_RANGE(0.2), 282 UNI_RANGE(0.1), 283 } 284}; 285 286#define NUM_LABPC_1200_AI_RANGES 14 287/* indicates unipolar ranges */ 288const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = { 289 0, 290 0, 291 0, 292 0, 293 0, 294 0, 295 0, 296 1, 297 1, 298 1, 299 1, 300 1, 301 1, 302 1, 303}; 304 305/* map range index to gain bits */ 306const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = { 307 0x00, 308 0x20, 309 0x30, 310 0x40, 311 0x50, 312 0x60, 313 0x70, 314 0x00, 315 0x20, 316 0x30, 317 0x40, 318 0x50, 319 0x60, 320 0x70, 321}; 322 323const struct comedi_lrange range_labpc_1200_ai = { 324 NUM_LABPC_1200_AI_RANGES, 325 { 326 BIP_RANGE(5), 327 BIP_RANGE(2.5), 328 BIP_RANGE(1), 329 BIP_RANGE(0.5), 330 BIP_RANGE(0.25), 331 BIP_RANGE(0.1), 332 BIP_RANGE(0.05), 333 UNI_RANGE(10), 334 UNI_RANGE(5), 335 UNI_RANGE(2), 336 UNI_RANGE(1), 337 UNI_RANGE(0.5), 338 UNI_RANGE(0.2), 339 UNI_RANGE(0.1), 340 } 341}; 342 343/* analog output ranges */ 344#define AO_RANGE_IS_UNIPOLAR 0x1 345static const struct comedi_lrange range_labpc_ao = { 346 2, 347 { 348 BIP_RANGE(5), 349 UNI_RANGE(10), 350 } 351}; 352 353/* functions that do inb/outb and readb/writeb so we can use 354 * function pointers to decide which to use */ 355static inline unsigned int labpc_inb(unsigned long address) 356{ 357 return inb(address); 358} 359 360static inline void labpc_outb(unsigned int byte, unsigned long address) 361{ 362 outb(byte, address); 363} 364 365static inline unsigned int labpc_readb(unsigned long address) 366{ 367 return readb((void *)address); 368} 369 370static inline void labpc_writeb(unsigned int byte, unsigned long address) 371{ 372 writeb(byte, (void *)address); 373} 374 375static const struct labpc_board_struct labpc_boards[] = { 376 { 377 .name = "lab-pc-1200", 378 .ai_speed = 10000, 379 .bustype = isa_bustype, 380 .register_layout = labpc_1200_layout, 381 .has_ao = 1, 382 .ai_range_table = &range_labpc_1200_ai, 383 .ai_range_code = labpc_1200_ai_gain_bits, 384 .ai_range_is_unipolar = labpc_1200_is_unipolar, 385 .ai_scan_up = 1, 386 .memory_mapped_io = 0, 387 }, 388 { 389 .name = "lab-pc-1200ai", 390 .ai_speed = 10000, 391 .bustype = isa_bustype, 392 .register_layout = labpc_1200_layout, 393 .has_ao = 0, 394 .ai_range_table = &range_labpc_1200_ai, 395 .ai_range_code = labpc_1200_ai_gain_bits, 396 .ai_range_is_unipolar = labpc_1200_is_unipolar, 397 .ai_scan_up = 1, 398 .memory_mapped_io = 0, 399 }, 400 { 401 .name = "lab-pc+", 402 .ai_speed = 12000, 403 .bustype = isa_bustype, 404 .register_layout = labpc_plus_layout, 405 .has_ao = 1, 406 .ai_range_table = &range_labpc_plus_ai, 407 .ai_range_code = labpc_plus_ai_gain_bits, 408 .ai_range_is_unipolar = labpc_plus_is_unipolar, 409 .ai_scan_up = 0, 410 .memory_mapped_io = 0, 411 }, 412#ifdef CONFIG_COMEDI_PCI 413 { 414 .name = "pci-1200", 415 .device_id = 0x161, 416 .ai_speed = 10000, 417 .bustype = pci_bustype, 418 .register_layout = labpc_1200_layout, 419 .has_ao = 1, 420 .ai_range_table = &range_labpc_1200_ai, 421 .ai_range_code = labpc_1200_ai_gain_bits, 422 .ai_range_is_unipolar = labpc_1200_is_unipolar, 423 .ai_scan_up = 1, 424 .memory_mapped_io = 1, 425 }, 426 /* dummy entry so pci board works when comedi_config is passed driver name */ 427 { 428 .name = DRV_NAME, 429 .bustype = pci_bustype, 430 }, 431#endif 432}; 433 434/* 435 * Useful for shorthand access to the particular board structure 436 */ 437#define thisboard ((struct labpc_board_struct *)dev->board_ptr) 438 439static const int dma_buffer_size = 0xff00; /* size in bytes of dma buffer */ 440static const int sample_size = 2; /* 2 bytes per sample */ 441 442#define devpriv ((struct labpc_private *)dev->private) 443 444static struct comedi_driver driver_labpc = { 445 .driver_name = DRV_NAME, 446 .module = THIS_MODULE, 447 .attach = labpc_attach, 448 .detach = labpc_common_detach, 449 .num_names = ARRAY_SIZE(labpc_boards), 450 .board_name = &labpc_boards[0].name, 451 .offset = sizeof(struct labpc_board_struct), 452}; 453 454#ifdef CONFIG_COMEDI_PCI 455static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = { 456 { 457 PCI_VENDOR_ID_NATINST, 0x161, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 458 0} 459}; 460 461MODULE_DEVICE_TABLE(pci, labpc_pci_table); 462#endif /* CONFIG_COMEDI_PCI */ 463 464static inline int labpc_counter_load(struct comedi_device *dev, 465 unsigned long base_address, 466 unsigned int counter_number, 467 unsigned int count, unsigned int mode) 468{ 469 if (thisboard->memory_mapped_io) 470 return i8254_mm_load((void *)base_address, 0, counter_number, 471 count, mode); 472 else 473 return i8254_load(base_address, 0, counter_number, count, mode); 474} 475 476int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, 477 unsigned int irq, unsigned int dma_chan) 478{ 479 struct comedi_subdevice *s; 480 int i; 481 unsigned long dma_flags, isr_flags; 482 short lsb, msb; 483 484 printk("comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, thisboard->name, 485 iobase); 486 if (irq) { 487 printk(", irq %u", irq); 488 } 489 if (dma_chan) { 490 printk(", dma %u", dma_chan); 491 } 492 printk("\n"); 493 494 if (iobase == 0) { 495 printk("io base address is zero!\n"); 496 return -EINVAL; 497 } 498 /* request io regions for isa boards */ 499 if (thisboard->bustype == isa_bustype) { 500 /* check if io addresses are available */ 501 if (!request_region(iobase, LABPC_SIZE, 502 driver_labpc.driver_name)) { 503 printk("I/O port conflict\n"); 504 return -EIO; 505 } 506 } 507 dev->iobase = iobase; 508 509 if (thisboard->memory_mapped_io) { 510 devpriv->read_byte = labpc_readb; 511 devpriv->write_byte = labpc_writeb; 512 } else { 513 devpriv->read_byte = labpc_inb; 514 devpriv->write_byte = labpc_outb; 515 } 516 /* initialize board's command registers */ 517 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 518 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 519 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 520 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 521 if (thisboard->register_layout == labpc_1200_layout) { 522 devpriv->write_byte(devpriv->command5_bits, 523 dev->iobase + COMMAND5_REG); 524 devpriv->write_byte(devpriv->command6_bits, 525 dev->iobase + COMMAND6_REG); 526 } 527 528 /* grab our IRQ */ 529 if (irq) { 530 isr_flags = 0; 531 if (thisboard->bustype == pci_bustype) 532 isr_flags |= IRQF_SHARED; 533 if (request_irq(irq, labpc_interrupt, isr_flags, 534 driver_labpc.driver_name, dev)) { 535 printk("unable to allocate irq %u\n", irq); 536 return -EINVAL; 537 } 538 } 539 dev->irq = irq; 540 541 /* grab dma channel */ 542 if (dma_chan > 3) { 543 printk(" invalid dma channel %u\n", dma_chan); 544 return -EINVAL; 545 } else if (dma_chan) { 546 /* allocate dma buffer */ 547 devpriv->dma_buffer = 548 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA); 549 if (devpriv->dma_buffer == NULL) { 550 printk(" failed to allocate dma buffer\n"); 551 return -ENOMEM; 552 } 553 if (request_dma(dma_chan, driver_labpc.driver_name)) { 554 printk(" failed to allocate dma channel %u\n", 555 dma_chan); 556 return -EINVAL; 557 } 558 devpriv->dma_chan = dma_chan; 559 dma_flags = claim_dma_lock(); 560 disable_dma(devpriv->dma_chan); 561 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); 562 release_dma_lock(dma_flags); 563 } 564 565 dev->board_name = thisboard->name; 566 567 if (alloc_subdevices(dev, 5) < 0) 568 return -ENOMEM; 569 570 /* analog input subdevice */ 571 s = dev->subdevices + 0; 572 dev->read_subdev = s; 573 s->type = COMEDI_SUBD_AI; 574 s->subdev_flags = 575 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ; 576 s->n_chan = 8; 577 s->len_chanlist = 8; 578 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 579 s->range_table = thisboard->ai_range_table; 580 s->do_cmd = labpc_ai_cmd; 581 s->do_cmdtest = labpc_ai_cmdtest; 582 s->insn_read = labpc_ai_rinsn; 583 s->cancel = labpc_cancel; 584 585 /* analog output */ 586 s = dev->subdevices + 1; 587 if (thisboard->has_ao) { 588/* Could provide command support, except it only has a one sample 589 * hardware buffer for analog output and no underrun flag. */ 590 s->type = COMEDI_SUBD_AO; 591 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; 592 s->n_chan = NUM_AO_CHAN; 593 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 594 s->range_table = &range_labpc_ao; 595 s->insn_read = labpc_ao_rinsn; 596 s->insn_write = labpc_ao_winsn; 597 /* initialize analog outputs to a known value */ 598 for (i = 0; i < s->n_chan; i++) { 599 devpriv->ao_value[i] = s->maxdata / 2; 600 lsb = devpriv->ao_value[i] & 0xff; 601 msb = (devpriv->ao_value[i] >> 8) & 0xff; 602 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); 603 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); 604 } 605 } else { 606 s->type = COMEDI_SUBD_UNUSED; 607 } 608 609 /* 8255 dio */ 610 s = dev->subdevices + 2; 611 /* if board uses io memory we have to give a custom callback function to the 8255 driver */ 612 if (thisboard->memory_mapped_io) 613 subdev_8255_init(dev, s, labpc_dio_mem_callback, 614 (unsigned long)(dev->iobase + DIO_BASE_REG)); 615 else 616 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG); 617 618 /* calibration subdevices for boards that have one */ 619 s = dev->subdevices + 3; 620 if (thisboard->register_layout == labpc_1200_layout) { 621 s->type = COMEDI_SUBD_CALIB; 622 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 623 s->n_chan = 16; 624 s->maxdata = 0xff; 625 s->insn_read = labpc_calib_read_insn; 626 s->insn_write = labpc_calib_write_insn; 627 628 for (i = 0; i < s->n_chan; i++) 629 write_caldac(dev, i, s->maxdata / 2); 630 } else 631 s->type = COMEDI_SUBD_UNUSED; 632 633 /* EEPROM */ 634 s = dev->subdevices + 4; 635 if (thisboard->register_layout == labpc_1200_layout) { 636 s->type = COMEDI_SUBD_MEMORY; 637 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 638 s->n_chan = EEPROM_SIZE; 639 s->maxdata = 0xff; 640 s->insn_read = labpc_eeprom_read_insn; 641 s->insn_write = labpc_eeprom_write_insn; 642 643 for (i = 0; i < EEPROM_SIZE; i++) { 644 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); 645 } 646#ifdef LABPC_DEBUG 647 printk(" eeprom:"); 648 for (i = 0; i < EEPROM_SIZE; i++) { 649 printk(" %i:0x%x ", i, devpriv->eeprom_data[i]); 650 } 651 printk("\n"); 652#endif 653 } else 654 s->type = COMEDI_SUBD_UNUSED; 655 656 return 0; 657} 658 659static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) 660{ 661 unsigned long iobase = 0; 662 unsigned int irq = 0; 663 unsigned int dma_chan = 0; 664#ifdef CONFIG_COMEDI_PCI 665 int retval; 666#endif 667 668 /* allocate and initialize dev->private */ 669 if (alloc_private(dev, sizeof(struct labpc_private)) < 0) 670 return -ENOMEM; 671 672 /* get base address, irq etc. based on bustype */ 673 switch (thisboard->bustype) { 674 case isa_bustype: 675 iobase = it->options[0]; 676 irq = it->options[1]; 677 dma_chan = it->options[2]; 678 break; 679 case pci_bustype: 680#ifdef CONFIG_COMEDI_PCI 681 retval = labpc_find_device(dev, it->options[0], it->options[1]); 682 if (retval < 0) { 683 return retval; 684 } 685 retval = mite_setup(devpriv->mite); 686 if (retval < 0) 687 return retval; 688 iobase = (unsigned long)devpriv->mite->daq_io_addr; 689 irq = mite_irq(devpriv->mite); 690#else 691 printk(" this driver has not been built with PCI support.\n"); 692 return -EINVAL; 693#endif 694 break; 695 case pcmcia_bustype: 696 printk 697 (" this driver does not support pcmcia cards, use ni_labpc_cs.o\n"); 698 return -EINVAL; 699 break; 700 default: 701 printk("bug! couldn't determine board type\n"); 702 return -EINVAL; 703 break; 704 } 705 706 return labpc_common_attach(dev, iobase, irq, dma_chan); 707} 708 709/* adapted from ni_pcimio for finding mite based boards (pc-1200) */ 710#ifdef CONFIG_COMEDI_PCI 711static int labpc_find_device(struct comedi_device *dev, int bus, int slot) 712{ 713 struct mite_struct *mite; 714 int i; 715 for (mite = mite_devices; mite; mite = mite->next) { 716 if (mite->used) 717 continue; 718 /* if bus/slot are specified then make sure we have the right bus/slot */ 719 if (bus || slot) { 720 if (bus != mite->pcidev->bus->number 721 || slot != PCI_SLOT(mite->pcidev->devfn)) 722 continue; 723 } 724 for (i = 0; i < driver_labpc.num_names; i++) { 725 if (labpc_boards[i].bustype != pci_bustype) 726 continue; 727 if (mite_device_id(mite) == labpc_boards[i].device_id) { 728 devpriv->mite = mite; 729 /* fixup board pointer, in case we were using the dummy "ni_labpc" entry */ 730 dev->board_ptr = &labpc_boards[i]; 731 return 0; 732 } 733 } 734 } 735 printk("no device found\n"); 736 mite_list_devices(); 737 return -EIO; 738} 739#endif 740 741int labpc_common_detach(struct comedi_device *dev) 742{ 743 printk("comedi%d: ni_labpc: detach\n", dev->minor); 744 745 if (dev->subdevices) 746 subdev_8255_cleanup(dev, dev->subdevices + 2); 747 748 /* only free stuff if it has been allocated by _attach */ 749 if (devpriv->dma_buffer) 750 kfree(devpriv->dma_buffer); 751 if (devpriv->dma_chan) 752 free_dma(devpriv->dma_chan); 753 if (dev->irq) 754 free_irq(dev->irq, dev); 755 if (thisboard->bustype == isa_bustype && dev->iobase) 756 release_region(dev->iobase, LABPC_SIZE); 757#ifdef CONFIG_COMEDI_PCI 758 if (devpriv->mite) 759 mite_unsetup(devpriv->mite); 760#endif 761 762 return 0; 763}; 764 765static void labpc_clear_adc_fifo(const struct comedi_device *dev) 766{ 767 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 768 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 769 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 770} 771 772static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 773{ 774 unsigned long flags; 775 776 spin_lock_irqsave(&dev->spinlock, flags); 777 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 778 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 779 spin_unlock_irqrestore(&dev->spinlock, flags); 780 781 devpriv->command3_bits = 0; 782 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 783 784 return 0; 785} 786 787static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) 788{ 789 if (cmd->chanlist_len == 1) 790 return MODE_SINGLE_CHAN; 791 792 /* chanlist may be NULL during cmdtest. */ 793 if (cmd->chanlist == NULL) 794 return MODE_MULT_CHAN_UP; 795 796 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) 797 return MODE_SINGLE_CHAN_INTERVAL; 798 799 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) 800 return MODE_MULT_CHAN_UP; 801 802 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) 803 return MODE_MULT_CHAN_DOWN; 804 805 printk("ni_labpc: bug! this should never happen\n"); 806 807 return 0; 808} 809 810static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, 811 const struct comedi_cmd *cmd) 812{ 813 int mode, channel, range, aref, i; 814 815 if (cmd->chanlist == NULL) 816 return 0; 817 818 mode = labpc_ai_scan_mode(cmd); 819 820 if (mode == MODE_SINGLE_CHAN) 821 return 0; 822 823 if (mode == MODE_SINGLE_CHAN_INTERVAL) { 824 if (cmd->chanlist_len > 0xff) { 825 comedi_error(dev, 826 "ni_labpc: chanlist too long for single channel interval mode\n"); 827 return 1; 828 } 829 } 830 831 channel = CR_CHAN(cmd->chanlist[0]); 832 range = CR_RANGE(cmd->chanlist[0]); 833 aref = CR_AREF(cmd->chanlist[0]); 834 835 for (i = 0; i < cmd->chanlist_len; i++) { 836 837 switch (mode) { 838 case MODE_SINGLE_CHAN_INTERVAL: 839 if (CR_CHAN(cmd->chanlist[i]) != channel) { 840 comedi_error(dev, 841 "channel scanning order specified in chanlist is not supported by hardware.\n"); 842 return 1; 843 } 844 break; 845 case MODE_MULT_CHAN_UP: 846 if (CR_CHAN(cmd->chanlist[i]) != i) { 847 comedi_error(dev, 848 "channel scanning order specified in chanlist is not supported by hardware.\n"); 849 return 1; 850 } 851 break; 852 case MODE_MULT_CHAN_DOWN: 853 if (CR_CHAN(cmd->chanlist[i]) != 854 cmd->chanlist_len - i - 1) { 855 comedi_error(dev, 856 "channel scanning order specified in chanlist is not supported by hardware.\n"); 857 return 1; 858 } 859 break; 860 default: 861 printk("ni_labpc: bug! in chanlist check\n"); 862 return 1; 863 break; 864 } 865 866 if (CR_RANGE(cmd->chanlist[i]) != range) { 867 comedi_error(dev, 868 "entries in chanlist must all have the same range\n"); 869 return 1; 870 } 871 872 if (CR_AREF(cmd->chanlist[i]) != aref) { 873 comedi_error(dev, 874 "entries in chanlist must all have the same reference\n"); 875 return 1; 876 } 877 } 878 879 return 0; 880} 881 882static int labpc_use_continuous_mode(const struct comedi_cmd *cmd) 883{ 884 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN) 885 return 1; 886 887 if (cmd->scan_begin_src == TRIG_FOLLOW) 888 return 1; 889 890 return 0; 891} 892 893static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd) 894{ 895 if (cmd->convert_src != TRIG_TIMER) 896 return 0; 897 898 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 899 cmd->scan_begin_src == TRIG_TIMER) 900 return cmd->scan_begin_arg; 901 902 return cmd->convert_arg; 903} 904 905static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns) 906{ 907 if (cmd->convert_src != TRIG_TIMER) 908 return; 909 910 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 911 cmd->scan_begin_src == TRIG_TIMER) { 912 cmd->scan_begin_arg = ns; 913 if (cmd->convert_arg > cmd->scan_begin_arg) 914 cmd->convert_arg = cmd->scan_begin_arg; 915 } else 916 cmd->convert_arg = ns; 917} 918 919static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd) 920{ 921 if (cmd->scan_begin_src != TRIG_TIMER) 922 return 0; 923 924 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 925 cmd->convert_src == TRIG_TIMER) 926 return 0; 927 928 return cmd->scan_begin_arg; 929} 930 931static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns) 932{ 933 if (cmd->scan_begin_src != TRIG_TIMER) 934 return; 935 936 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 937 cmd->convert_src == TRIG_TIMER) 938 return; 939 940 cmd->scan_begin_arg = ns; 941} 942 943static int labpc_ai_cmdtest(struct comedi_device *dev, 944 struct comedi_subdevice *s, struct comedi_cmd *cmd) 945{ 946 int err = 0; 947 int tmp, tmp2; 948 int stop_mask; 949 950 /* step 1: make sure trigger sources are trivially valid */ 951 952 tmp = cmd->start_src; 953 cmd->start_src &= TRIG_NOW | TRIG_EXT; 954 if (!cmd->start_src || tmp != cmd->start_src) 955 err++; 956 957 tmp = cmd->scan_begin_src; 958 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT; 959 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 960 err++; 961 962 tmp = cmd->convert_src; 963 cmd->convert_src &= TRIG_TIMER | TRIG_EXT; 964 if (!cmd->convert_src || tmp != cmd->convert_src) 965 err++; 966 967 tmp = cmd->scan_end_src; 968 cmd->scan_end_src &= TRIG_COUNT; 969 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 970 err++; 971 972 tmp = cmd->stop_src; 973 stop_mask = TRIG_COUNT | TRIG_NONE; 974 if (thisboard->register_layout == labpc_1200_layout) 975 stop_mask |= TRIG_EXT; 976 cmd->stop_src &= stop_mask; 977 if (!cmd->stop_src || tmp != cmd->stop_src) 978 err++; 979 980 if (err) 981 return 1; 982 983 /* step 2: make sure trigger sources are unique and mutually compatible */ 984 985 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) 986 err++; 987 if (cmd->scan_begin_src != TRIG_TIMER && 988 cmd->scan_begin_src != TRIG_FOLLOW && 989 cmd->scan_begin_src != TRIG_EXT) 990 err++; 991 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT) 992 err++; 993 if (cmd->stop_src != TRIG_COUNT && 994 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE) 995 err++; 996 997 /* can't have external stop and start triggers at once */ 998 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) 999 err++; 1000 1001 if (err) 1002 return 2; 1003 1004 /* step 3: make sure arguments are trivially compatible */ 1005 1006 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) { 1007 cmd->start_arg = 0; 1008 err++; 1009 } 1010 1011 if (!cmd->chanlist_len) { 1012 err++; 1013 } 1014 if (cmd->scan_end_arg != cmd->chanlist_len) { 1015 cmd->scan_end_arg = cmd->chanlist_len; 1016 err++; 1017 } 1018 1019 if (cmd->convert_src == TRIG_TIMER) { 1020 if (cmd->convert_arg < thisboard->ai_speed) { 1021 cmd->convert_arg = thisboard->ai_speed; 1022 err++; 1023 } 1024 } 1025 /* make sure scan timing is not too fast */ 1026 if (cmd->scan_begin_src == TRIG_TIMER) { 1027 if (cmd->convert_src == TRIG_TIMER && 1028 cmd->scan_begin_arg < 1029 cmd->convert_arg * cmd->chanlist_len) { 1030 cmd->scan_begin_arg = 1031 cmd->convert_arg * cmd->chanlist_len; 1032 err++; 1033 } 1034 if (cmd->scan_begin_arg < 1035 thisboard->ai_speed * cmd->chanlist_len) { 1036 cmd->scan_begin_arg = 1037 thisboard->ai_speed * cmd->chanlist_len; 1038 err++; 1039 } 1040 } 1041 /* stop source */ 1042 switch (cmd->stop_src) { 1043 case TRIG_COUNT: 1044 if (!cmd->stop_arg) { 1045 cmd->stop_arg = 1; 1046 err++; 1047 } 1048 break; 1049 case TRIG_NONE: 1050 if (cmd->stop_arg != 0) { 1051 cmd->stop_arg = 0; 1052 err++; 1053 } 1054 break; 1055 /* TRIG_EXT doesn't care since it doesn't trigger off a numbered channel */ 1056 default: 1057 break; 1058 } 1059 1060 if (err) 1061 return 3; 1062 1063 /* step 4: fix up any arguments */ 1064 1065 tmp = cmd->convert_arg; 1066 tmp2 = cmd->scan_begin_arg; 1067 labpc_adc_timing(dev, cmd); 1068 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) 1069 err++; 1070 1071 if (err) 1072 return 4; 1073 1074 if (labpc_ai_chanlist_invalid(dev, cmd)) 1075 return 5; 1076 1077 return 0; 1078} 1079 1080static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 1081{ 1082 int channel, range, aref; 1083 unsigned long irq_flags; 1084 int ret; 1085 struct comedi_async *async = s->async; 1086 struct comedi_cmd *cmd = &async->cmd; 1087 enum transfer_type xfer; 1088 unsigned long flags; 1089 1090 if (!dev->irq) { 1091 comedi_error(dev, "no irq assigned, cannot perform command"); 1092 return -1; 1093 } 1094 1095 range = CR_RANGE(cmd->chanlist[0]); 1096 aref = CR_AREF(cmd->chanlist[0]); 1097 1098 /* make sure board is disabled before setting up aquisition */ 1099 spin_lock_irqsave(&dev->spinlock, flags); 1100 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1101 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1102 spin_unlock_irqrestore(&dev->spinlock, flags); 1103 1104 devpriv->command3_bits = 0; 1105 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1106 1107 /* initialize software conversion count */ 1108 if (cmd->stop_src == TRIG_COUNT) { 1109 devpriv->count = cmd->stop_arg * cmd->chanlist_len; 1110 } 1111 /* setup hardware conversion counter */ 1112 if (cmd->stop_src == TRIG_EXT) { 1113 /* load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0 */ 1114 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1115 1, 3, 0); 1116 if (ret < 0) { 1117 comedi_error(dev, "error loading counter a1"); 1118 return -1; 1119 } 1120 } else /* otherwise, just put a1 in mode 0 with no count to set its output low */ 1121 devpriv->write_byte(INIT_A1_BITS, 1122 dev->iobase + COUNTER_A_CONTROL_REG); 1123 1124 /* figure out what method we will use to transfer data */ 1125 if (devpriv->dma_chan && /* need a dma channel allocated */ 1126 /* dma unsafe at RT priority, and too much setup time for TRIG_WAKE_EOS for */ 1127 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 && 1128 /* only available on the isa boards */ 1129 thisboard->bustype == isa_bustype) { 1130 xfer = isa_dma_transfer; 1131 } else if (thisboard->register_layout == labpc_1200_layout && /* pc-plus has no fifo-half full interrupt */ 1132 /* wake-end-of-scan should interrupt on fifo not empty */ 1133 (cmd->flags & TRIG_WAKE_EOS) == 0 && 1134 /* make sure we are taking more than just a few points */ 1135 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { 1136 xfer = fifo_half_full_transfer; 1137 } else 1138 xfer = fifo_not_empty_transfer; 1139 devpriv->current_transfer = xfer; 1140 1141 /* setup command6 register for 1200 boards */ 1142 if (thisboard->register_layout == labpc_1200_layout) { 1143 /* reference inputs to ground or common? */ 1144 if (aref != AREF_GROUND) 1145 devpriv->command6_bits |= ADC_COMMON_BIT; 1146 else 1147 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1148 /* bipolar or unipolar range? */ 1149 if (thisboard->ai_range_is_unipolar[range]) 1150 devpriv->command6_bits |= ADC_UNIP_BIT; 1151 else 1152 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1153 /* interrupt on fifo half full? */ 1154 if (xfer == fifo_half_full_transfer) 1155 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT; 1156 else 1157 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1158 /* enable interrupt on counter a1 terminal count? */ 1159 if (cmd->stop_src == TRIG_EXT) 1160 devpriv->command6_bits |= A1_INTR_EN_BIT; 1161 else 1162 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1163 /* are we scanning up or down through channels? */ 1164 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1165 devpriv->command6_bits |= ADC_SCAN_UP_BIT; 1166 else 1167 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT; 1168 /* write to register */ 1169 devpriv->write_byte(devpriv->command6_bits, 1170 dev->iobase + COMMAND6_REG); 1171 } 1172 1173 /* setup channel list, etc (command1 register) */ 1174 devpriv->command1_bits = 0; 1175 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1176 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); 1177 else 1178 channel = CR_CHAN(cmd->chanlist[0]); 1179 /* munge channel bits for differential / scan disabled mode */ 1180 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF) 1181 channel *= 2; 1182 devpriv->command1_bits |= ADC_CHAN_BITS(channel); 1183 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1184 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1185 /* manual says to set scan enable bit on second pass */ 1186 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP || 1187 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) { 1188 devpriv->command1_bits |= ADC_SCAN_EN_BIT; 1189 /* need a brief delay before enabling scan, or scan list will get screwed when you switch 1190 * between scan up to scan down mode - dunno why */ 1191 udelay(1); 1192 devpriv->write_byte(devpriv->command1_bits, 1193 dev->iobase + COMMAND1_REG); 1194 } 1195 /* setup any external triggering/pacing (command4 register) */ 1196 devpriv->command4_bits = 0; 1197 if (cmd->convert_src != TRIG_EXT) 1198 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1199 /* XXX should discard first scan when using interval scanning 1200 * since manual says it is not synced with scan clock */ 1201 if (labpc_use_continuous_mode(cmd) == 0) { 1202 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT; 1203 if (cmd->scan_begin_src == TRIG_EXT) 1204 devpriv->command4_bits |= EXT_SCAN_EN_BIT; 1205 } 1206 /* single-ended/differential */ 1207 if (aref == AREF_DIFF) 1208 devpriv->command4_bits |= ADC_DIFF_BIT; 1209 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1210 1211 devpriv->write_byte(cmd->chanlist_len, 1212 dev->iobase + INTERVAL_COUNT_REG); 1213 /* load count */ 1214 devpriv->write_byte(INTERVAL_LOAD_BITS, 1215 dev->iobase + INTERVAL_LOAD_REG); 1216 1217 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) { 1218 /* set up pacing */ 1219 labpc_adc_timing(dev, cmd); 1220 /* load counter b0 in mode 3 */ 1221 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1222 0, devpriv->divisor_b0, 3); 1223 if (ret < 0) { 1224 comedi_error(dev, "error loading counter b0"); 1225 return -1; 1226 } 1227 } 1228 /* set up conversion pacing */ 1229 if (labpc_ai_convert_period(cmd)) { 1230 /* load counter a0 in mode 2 */ 1231 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1232 0, devpriv->divisor_a0, 2); 1233 if (ret < 0) { 1234 comedi_error(dev, "error loading counter a0"); 1235 return -1; 1236 } 1237 } else 1238 devpriv->write_byte(INIT_A0_BITS, 1239 dev->iobase + COUNTER_A_CONTROL_REG); 1240 1241 /* set up scan pacing */ 1242 if (labpc_ai_scan_period(cmd)) { 1243 /* load counter b1 in mode 2 */ 1244 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1245 1, devpriv->divisor_b1, 2); 1246 if (ret < 0) { 1247 comedi_error(dev, "error loading counter b1"); 1248 return -1; 1249 } 1250 } 1251 1252 labpc_clear_adc_fifo(dev); 1253 1254 /* set up dma transfer */ 1255 if (xfer == isa_dma_transfer) { 1256 irq_flags = claim_dma_lock(); 1257 disable_dma(devpriv->dma_chan); 1258 /* clear flip-flop to make sure 2-byte registers for 1259 * count and address get set correctly */ 1260 clear_dma_ff(devpriv->dma_chan); 1261 set_dma_addr(devpriv->dma_chan, 1262 virt_to_bus(devpriv->dma_buffer)); 1263 /* set appropriate size of transfer */ 1264 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd); 1265 if (cmd->stop_src == TRIG_COUNT && 1266 devpriv->count * sample_size < devpriv->dma_transfer_size) { 1267 devpriv->dma_transfer_size = 1268 devpriv->count * sample_size; 1269 } 1270 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); 1271 enable_dma(devpriv->dma_chan); 1272 release_dma_lock(irq_flags); 1273 /* enable board's dma */ 1274 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT; 1275 } else 1276 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT; 1277 1278 /* enable error interrupts */ 1279 devpriv->command3_bits |= ERR_INTR_EN_BIT; 1280 /* enable fifo not empty interrupt? */ 1281 if (xfer == fifo_not_empty_transfer) 1282 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT; 1283 else 1284 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT; 1285 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1286 1287 /* startup aquisition */ 1288 1289 /* command2 reg */ 1290 /* use 2 cascaded counters for pacing */ 1291 spin_lock_irqsave(&dev->spinlock, flags); 1292 devpriv->command2_bits |= CASCADE_BIT; 1293 switch (cmd->start_src) { 1294 case TRIG_EXT: 1295 devpriv->command2_bits |= HWTRIG_BIT; 1296 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT; 1297 break; 1298 case TRIG_NOW: 1299 devpriv->command2_bits |= SWTRIG_BIT; 1300 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT; 1301 break; 1302 default: 1303 comedi_error(dev, "bug with start_src"); 1304 return -1; 1305 break; 1306 } 1307 switch (cmd->stop_src) { 1308 case TRIG_EXT: 1309 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT; 1310 break; 1311 case TRIG_COUNT: 1312 case TRIG_NONE: 1313 break; 1314 default: 1315 comedi_error(dev, "bug with stop_src"); 1316 return -1; 1317 } 1318 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1319 spin_unlock_irqrestore(&dev->spinlock, flags); 1320 1321 return 0; 1322} 1323 1324/* interrupt service routine */ 1325static irqreturn_t labpc_interrupt(int irq, void *d) 1326{ 1327 struct comedi_device *dev = d; 1328 struct comedi_subdevice *s = dev->read_subdev; 1329 struct comedi_async *async; 1330 struct comedi_cmd *cmd; 1331 1332 if (dev->attached == 0) { 1333 comedi_error(dev, "premature interrupt"); 1334 return IRQ_HANDLED; 1335 } 1336 1337 async = s->async; 1338 cmd = &async->cmd; 1339 async->events = 0; 1340 1341 /* read board status */ 1342 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1343 if (thisboard->register_layout == labpc_1200_layout) 1344 devpriv->status2_bits = 1345 devpriv->read_byte(dev->iobase + STATUS2_REG); 1346 1347 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT | 1348 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0 1349 && (devpriv->status2_bits & A1_TC_BIT) == 0 1350 && (devpriv->status2_bits & FNHF_BIT)) { 1351 return IRQ_NONE; 1352 } 1353 1354 if (devpriv->status1_bits & OVERRUN_BIT) { 1355 /* clear error interrupt */ 1356 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1357 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1358 comedi_event(dev, s); 1359 comedi_error(dev, "overrun"); 1360 return IRQ_HANDLED; 1361 } 1362 1363 if (devpriv->current_transfer == isa_dma_transfer) { 1364 /* if a dma terminal count of external stop trigger has occurred */ 1365 if (devpriv->status1_bits & DMATC_BIT || 1366 (thisboard->register_layout == labpc_1200_layout 1367 && devpriv->status2_bits & A1_TC_BIT)) { 1368 handle_isa_dma(dev); 1369 } 1370 } else 1371 labpc_drain_fifo(dev); 1372 1373 if (devpriv->status1_bits & TIMER_BIT) { 1374 comedi_error(dev, "handled timer interrupt?"); 1375 /* clear it */ 1376 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); 1377 } 1378 1379 if (devpriv->status1_bits & OVERFLOW_BIT) { 1380 /* clear error interrupt */ 1381 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1382 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1383 comedi_event(dev, s); 1384 comedi_error(dev, "overflow"); 1385 return IRQ_HANDLED; 1386 } 1387 /* handle external stop trigger */ 1388 if (cmd->stop_src == TRIG_EXT) { 1389 if (devpriv->status2_bits & A1_TC_BIT) { 1390 labpc_drain_dregs(dev); 1391 labpc_cancel(dev, s); 1392 async->events |= COMEDI_CB_EOA; 1393 } 1394 } 1395 1396 /* TRIG_COUNT end of acquisition */ 1397 if (cmd->stop_src == TRIG_COUNT) { 1398 if (devpriv->count == 0) { 1399 labpc_cancel(dev, s); 1400 async->events |= COMEDI_CB_EOA; 1401 } 1402 } 1403 1404 comedi_event(dev, s); 1405 return IRQ_HANDLED; 1406} 1407 1408/* read all available samples from ai fifo */ 1409static int labpc_drain_fifo(struct comedi_device *dev) 1410{ 1411 unsigned int lsb, msb; 1412 short data; 1413 struct comedi_async *async = dev->read_subdev->async; 1414 const int timeout = 10000; 1415 unsigned int i; 1416 1417 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1418 1419 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout; 1420 i++) { 1421 /* quit if we have all the data we want */ 1422 if (async->cmd.stop_src == TRIG_COUNT) { 1423 if (devpriv->count == 0) 1424 break; 1425 devpriv->count--; 1426 } 1427 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1428 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1429 data = (msb << 8) | lsb; 1430 cfc_write_to_buffer(dev->read_subdev, data); 1431 devpriv->status1_bits = 1432 devpriv->read_byte(dev->iobase + STATUS1_REG); 1433 } 1434 if (i == timeout) { 1435 comedi_error(dev, "ai timeout, fifo never empties"); 1436 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1437 return -1; 1438 } 1439 1440 return 0; 1441} 1442 1443static void labpc_drain_dma(struct comedi_device *dev) 1444{ 1445 struct comedi_subdevice *s = dev->read_subdev; 1446 struct comedi_async *async = s->async; 1447 int status; 1448 unsigned long flags; 1449 unsigned int max_points, num_points, residue, leftover; 1450 int i; 1451 1452 status = devpriv->status1_bits; 1453 1454 flags = claim_dma_lock(); 1455 disable_dma(devpriv->dma_chan); 1456 /* clear flip-flop to make sure 2-byte registers for 1457 * count and address get set correctly */ 1458 clear_dma_ff(devpriv->dma_chan); 1459 1460 /* figure out how many points to read */ 1461 max_points = devpriv->dma_transfer_size / sample_size; 1462 /* residue is the number of points left to be done on the dma 1463 * transfer. It should always be zero at this point unless 1464 * the stop_src is set to external triggering. 1465 */ 1466 residue = get_dma_residue(devpriv->dma_chan) / sample_size; 1467 num_points = max_points - residue; 1468 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) 1469 num_points = devpriv->count; 1470 1471 /* figure out how many points will be stored next time */ 1472 leftover = 0; 1473 if (async->cmd.stop_src != TRIG_COUNT) { 1474 leftover = devpriv->dma_transfer_size / sample_size; 1475 } else if (devpriv->count > num_points) { 1476 leftover = devpriv->count - num_points; 1477 if (leftover > max_points) 1478 leftover = max_points; 1479 } 1480 1481 /* write data to comedi buffer */ 1482 for (i = 0; i < num_points; i++) { 1483 cfc_write_to_buffer(s, devpriv->dma_buffer[i]); 1484 } 1485 if (async->cmd.stop_src == TRIG_COUNT) 1486 devpriv->count -= num_points; 1487 1488 /* set address and count for next transfer */ 1489 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); 1490 set_dma_count(devpriv->dma_chan, leftover * sample_size); 1491 release_dma_lock(flags); 1492 1493 async->events |= COMEDI_CB_BLOCK; 1494} 1495 1496static void handle_isa_dma(struct comedi_device *dev) 1497{ 1498 labpc_drain_dma(dev); 1499 1500 enable_dma(devpriv->dma_chan); 1501 1502 /* clear dma tc interrupt */ 1503 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); 1504} 1505 1506/* makes sure all data acquired by board is transfered to comedi (used 1507 * when aquisition is terminated by stop_src == TRIG_EXT). */ 1508static void labpc_drain_dregs(struct comedi_device *dev) 1509{ 1510 if (devpriv->current_transfer == isa_dma_transfer) 1511 labpc_drain_dma(dev); 1512 1513 labpc_drain_fifo(dev); 1514} 1515 1516static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1517 struct comedi_insn *insn, unsigned int *data) 1518{ 1519 int i, n; 1520 int chan, range; 1521 int lsb, msb; 1522 int timeout = 1000; 1523 unsigned long flags; 1524 1525 /* disable timed conversions */ 1526 spin_lock_irqsave(&dev->spinlock, flags); 1527 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1528 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1529 spin_unlock_irqrestore(&dev->spinlock, flags); 1530 1531 /* disable interrupt generation and dma */ 1532 devpriv->command3_bits = 0; 1533 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1534 1535 /* set gain and channel */ 1536 devpriv->command1_bits = 0; 1537 chan = CR_CHAN(insn->chanspec); 1538 range = CR_RANGE(insn->chanspec); 1539 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1540 /* munge channel bits for differential/scan disabled mode */ 1541 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1542 chan *= 2; 1543 devpriv->command1_bits |= ADC_CHAN_BITS(chan); 1544 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1545 1546 /* setup command6 register for 1200 boards */ 1547 if (thisboard->register_layout == labpc_1200_layout) { 1548 /* reference inputs to ground or common? */ 1549 if (CR_AREF(insn->chanspec) != AREF_GROUND) 1550 devpriv->command6_bits |= ADC_COMMON_BIT; 1551 else 1552 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1553 /* bipolar or unipolar range? */ 1554 if (thisboard->ai_range_is_unipolar[range]) 1555 devpriv->command6_bits |= ADC_UNIP_BIT; 1556 else 1557 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1558 /* don't interrupt on fifo half full */ 1559 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1560 /* don't enable interrupt on counter a1 terminal count? */ 1561 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1562 /* write to register */ 1563 devpriv->write_byte(devpriv->command6_bits, 1564 dev->iobase + COMMAND6_REG); 1565 } 1566 /* setup command4 register */ 1567 devpriv->command4_bits = 0; 1568 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1569 /* single-ended/differential */ 1570 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1571 devpriv->command4_bits |= ADC_DIFF_BIT; 1572 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1573 1574 /* initialize pacer counter output to make sure it doesn't cause any problems */ 1575 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG); 1576 1577 labpc_clear_adc_fifo(dev); 1578 1579 for (n = 0; n < insn->n; n++) { 1580 /* trigger conversion */ 1581 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG); 1582 1583 for (i = 0; i < timeout; i++) { 1584 if (devpriv->read_byte(dev->iobase + 1585 STATUS1_REG) & DATA_AVAIL_BIT) 1586 break; 1587 udelay(1); 1588 } 1589 if (i == timeout) { 1590 comedi_error(dev, "timeout"); 1591 return -ETIME; 1592 } 1593 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1594 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1595 data[n] = (msb << 8) | lsb; 1596 } 1597 1598 return n; 1599} 1600 1601/* analog output insn */ 1602static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 1603 struct comedi_insn *insn, unsigned int *data) 1604{ 1605 int channel, range; 1606 unsigned long flags; 1607 int lsb, msb; 1608 1609 channel = CR_CHAN(insn->chanspec); 1610 1611 /* turn off pacing of analog output channel */ 1612 /* note: hardware bug in daqcard-1200 means pacing cannot 1613 * be independently enabled/disabled for its the two channels */ 1614 spin_lock_irqsave(&dev->spinlock, flags); 1615 devpriv->command2_bits &= ~DAC_PACED_BIT(channel); 1616 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1617 spin_unlock_irqrestore(&dev->spinlock, flags); 1618 1619 /* set range */ 1620 if (thisboard->register_layout == labpc_1200_layout) { 1621 range = CR_RANGE(insn->chanspec); 1622 if (range & AO_RANGE_IS_UNIPOLAR) 1623 devpriv->command6_bits |= DAC_UNIP_BIT(channel); 1624 else 1625 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel); 1626 /* write to register */ 1627 devpriv->write_byte(devpriv->command6_bits, 1628 dev->iobase + COMMAND6_REG); 1629 } 1630 /* send data */ 1631 lsb = data[0] & 0xff; 1632 msb = (data[0] >> 8) & 0xff; 1633 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); 1634 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); 1635 1636 /* remember value for readback */ 1637 devpriv->ao_value[channel] = data[0]; 1638 1639 return 1; 1640} 1641 1642/* analog output readback insn */ 1643static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1644 struct comedi_insn *insn, unsigned int *data) 1645{ 1646 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; 1647 1648 return 1; 1649} 1650 1651static int labpc_calib_read_insn(struct comedi_device *dev, 1652 struct comedi_subdevice *s, 1653 struct comedi_insn *insn, unsigned int *data) 1654{ 1655 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)]; 1656 1657 return 1; 1658} 1659 1660static int labpc_calib_write_insn(struct comedi_device *dev, 1661 struct comedi_subdevice *s, 1662 struct comedi_insn *insn, unsigned int *data) 1663{ 1664 int channel = CR_CHAN(insn->chanspec); 1665 1666 write_caldac(dev, channel, data[0]); 1667 return 1; 1668} 1669 1670static int labpc_eeprom_read_insn(struct comedi_device *dev, 1671 struct comedi_subdevice *s, 1672 struct comedi_insn *insn, unsigned int *data) 1673{ 1674 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)]; 1675 1676 return 1; 1677} 1678 1679static int labpc_eeprom_write_insn(struct comedi_device *dev, 1680 struct comedi_subdevice *s, 1681 struct comedi_insn *insn, unsigned int *data) 1682{ 1683 int channel = CR_CHAN(insn->chanspec); 1684 int ret; 1685 1686 /* only allow writes to user area of eeprom */ 1687 if (channel < 16 || channel > 127) { 1688 printk 1689 ("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)"); 1690 return -EINVAL; 1691 } 1692 1693 ret = labpc_eeprom_write(dev, channel, data[0]); 1694 if (ret < 0) 1695 return ret; 1696 1697 return 1; 1698} 1699 1700/* utility function that suggests a dma transfer size in bytes */ 1701static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd) 1702{ 1703 unsigned int size; 1704 unsigned int freq; 1705 1706 if (cmd.convert_src == TRIG_TIMER) 1707 freq = 1000000000 / cmd.convert_arg; 1708 /* return some default value */ 1709 else 1710 freq = 0xffffffff; 1711 1712 /* make buffer fill in no more than 1/3 second */ 1713 size = (freq / 3) * sample_size; 1714 1715 /* set a minimum and maximum size allowed */ 1716 if (size > dma_buffer_size) 1717 size = dma_buffer_size - dma_buffer_size % sample_size; 1718 else if (size < sample_size) 1719 size = sample_size; 1720 1721 return size; 1722} 1723 1724/* figures out what counter values to use based on command */ 1725static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) 1726{ 1727 const int max_counter_value = 0x10000; /* max value for 16 bit counter in mode 2 */ 1728 const int min_counter_value = 2; /* min value for 16 bit counter in mode 2 */ 1729 unsigned int base_period; 1730 1731 /* if both convert and scan triggers are TRIG_TIMER, then they both rely on counter b0 */ 1732 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) { 1733 /* pick the lowest b0 divisor value we can (for maximum input clock speed on convert and scan counters) */ 1734 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) / 1735 (LABPC_TIMER_BASE * max_counter_value) + 1; 1736 if (devpriv->divisor_b0 < min_counter_value) 1737 devpriv->divisor_b0 = min_counter_value; 1738 if (devpriv->divisor_b0 > max_counter_value) 1739 devpriv->divisor_b0 = max_counter_value; 1740 1741 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; 1742 1743 /* set a0 for conversion frequency and b1 for scan frequency */ 1744 switch (cmd->flags & TRIG_ROUND_MASK) { 1745 default: 1746 case TRIG_ROUND_NEAREST: 1747 devpriv->divisor_a0 = 1748 (labpc_ai_convert_period(cmd) + 1749 (base_period / 2)) / base_period; 1750 devpriv->divisor_b1 = 1751 (labpc_ai_scan_period(cmd) + 1752 (base_period / 2)) / base_period; 1753 break; 1754 case TRIG_ROUND_UP: 1755 devpriv->divisor_a0 = 1756 (labpc_ai_convert_period(cmd) + (base_period - 1757 1)) / base_period; 1758 devpriv->divisor_b1 = 1759 (labpc_ai_scan_period(cmd) + (base_period - 1760 1)) / base_period; 1761 break; 1762 case TRIG_ROUND_DOWN: 1763 devpriv->divisor_a0 = 1764 labpc_ai_convert_period(cmd) / base_period; 1765 devpriv->divisor_b1 = 1766 labpc_ai_scan_period(cmd) / base_period; 1767 break; 1768 } 1769 /* make sure a0 and b1 values are acceptable */ 1770 if (devpriv->divisor_a0 < min_counter_value) 1771 devpriv->divisor_a0 = min_counter_value; 1772 if (devpriv->divisor_a0 > max_counter_value) 1773 devpriv->divisor_a0 = max_counter_value; 1774 if (devpriv->divisor_b1 < min_counter_value) 1775 devpriv->divisor_b1 = min_counter_value; 1776 if (devpriv->divisor_b1 > max_counter_value) 1777 devpriv->divisor_b1 = max_counter_value; 1778 /* write corrected timings to command */ 1779 labpc_set_ai_convert_period(cmd, 1780 base_period * devpriv->divisor_a0); 1781 labpc_set_ai_scan_period(cmd, 1782 base_period * devpriv->divisor_b1); 1783 /* if only one TRIG_TIMER is used, we can employ the generic cascaded timing functions */ 1784 } else if (labpc_ai_scan_period(cmd)) { 1785 unsigned int scan_period; 1786 1787 scan_period = labpc_ai_scan_period(cmd); 1788 /* calculate cascaded counter values that give desired scan timing */ 1789 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1790 &(devpriv->divisor_b1), 1791 &(devpriv->divisor_b0), 1792 &scan_period, 1793 cmd->flags & TRIG_ROUND_MASK); 1794 labpc_set_ai_scan_period(cmd, scan_period); 1795 } else if (labpc_ai_convert_period(cmd)) { 1796 unsigned int convert_period; 1797 1798 convert_period = labpc_ai_convert_period(cmd); 1799 /* calculate cascaded counter values that give desired conversion timing */ 1800 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1801 &(devpriv->divisor_a0), 1802 &(devpriv->divisor_b0), 1803 &convert_period, 1804 cmd->flags & TRIG_ROUND_MASK); 1805 labpc_set_ai_convert_period(cmd, convert_period); 1806 } 1807} 1808 1809static int labpc_dio_mem_callback(int dir, int port, int data, 1810 unsigned long iobase) 1811{ 1812 if (dir) { 1813 writeb(data, (void *)(iobase + port)); 1814 return 0; 1815 } else { 1816 return readb((void *)(iobase + port)); 1817 } 1818} 1819 1820/* lowlevel write to eeprom/dac */ 1821static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 1822 unsigned int value_width) 1823{ 1824 int i; 1825 1826 for (i = 1; i <= value_width; i++) { 1827 /* clear serial clock */ 1828 devpriv->command5_bits &= ~SCLOCK_BIT; 1829 /* send bits most significant bit first */ 1830 if (value & (1 << (value_width - i))) 1831 devpriv->command5_bits |= SDATA_BIT; 1832 else 1833 devpriv->command5_bits &= ~SDATA_BIT; 1834 udelay(1); 1835 devpriv->write_byte(devpriv->command5_bits, 1836 dev->iobase + COMMAND5_REG); 1837 /* set clock to load bit */ 1838 devpriv->command5_bits |= SCLOCK_BIT; 1839 udelay(1); 1840 devpriv->write_byte(devpriv->command5_bits, 1841 dev->iobase + COMMAND5_REG); 1842 } 1843} 1844 1845/* lowlevel read from eeprom */ 1846static unsigned int labpc_serial_in(struct comedi_device *dev) 1847{ 1848 unsigned int value = 0; 1849 int i; 1850 const int value_width = 8; /* number of bits wide values are */ 1851 1852 for (i = 1; i <= value_width; i++) { 1853 /* set serial clock */ 1854 devpriv->command5_bits |= SCLOCK_BIT; 1855 udelay(1); 1856 devpriv->write_byte(devpriv->command5_bits, 1857 dev->iobase + COMMAND5_REG); 1858 /* clear clock bit */ 1859 devpriv->command5_bits &= ~SCLOCK_BIT; 1860 udelay(1); 1861 devpriv->write_byte(devpriv->command5_bits, 1862 dev->iobase + COMMAND5_REG); 1863 /* read bits most significant bit first */ 1864 udelay(1); 1865 devpriv->status2_bits = 1866 devpriv->read_byte(dev->iobase + STATUS2_REG); 1867 if (devpriv->status2_bits & EEPROM_OUT_BIT) { 1868 value |= 1 << (value_width - i); 1869 } 1870 } 1871 1872 return value; 1873} 1874 1875static unsigned int labpc_eeprom_read(struct comedi_device *dev, 1876 unsigned int address) 1877{ 1878 unsigned int value; 1879 const int read_instruction = 0x3; /* bits to tell eeprom to expect a read */ 1880 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1881 1882 /* enable read/write to eeprom */ 1883 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1884 udelay(1); 1885 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1886 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1887 udelay(1); 1888 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1889 1890 /* send read instruction */ 1891 labpc_serial_out(dev, read_instruction, write_length); 1892 /* send 8 bit address to read from */ 1893 labpc_serial_out(dev, address, write_length); 1894 /* read result */ 1895 value = labpc_serial_in(dev); 1896 1897 /* disable read/write to eeprom */ 1898 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1899 udelay(1); 1900 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1901 1902 return value; 1903} 1904 1905static unsigned int labpc_eeprom_write(struct comedi_device *dev, 1906 unsigned int address, unsigned int value) 1907{ 1908 const int write_enable_instruction = 0x6; 1909 const int write_instruction = 0x2; 1910 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1911 const int write_in_progress_bit = 0x1; 1912 const int timeout = 10000; 1913 int i; 1914 1915 /* make sure there isn't already a write in progress */ 1916 for (i = 0; i < timeout; i++) { 1917 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == 1918 0) 1919 break; 1920 } 1921 if (i == timeout) { 1922 comedi_error(dev, "eeprom write timed out"); 1923 return -ETIME; 1924 } 1925 /* update software copy of eeprom */ 1926 devpriv->eeprom_data[address] = value; 1927 1928 /* enable read/write to eeprom */ 1929 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1930 udelay(1); 1931 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1932 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1933 udelay(1); 1934 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1935 1936 /* send write_enable instruction */ 1937 labpc_serial_out(dev, write_enable_instruction, write_length); 1938 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1939 udelay(1); 1940 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1941 1942 /* send write instruction */ 1943 devpriv->command5_bits |= EEPROM_EN_BIT; 1944 udelay(1); 1945 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1946 labpc_serial_out(dev, write_instruction, write_length); 1947 /* send 8 bit address to write to */ 1948 labpc_serial_out(dev, address, write_length); 1949 /* write value */ 1950 labpc_serial_out(dev, value, write_length); 1951 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1952 udelay(1); 1953 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1954 1955 /* disable read/write to eeprom */ 1956 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1957 udelay(1); 1958 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1959 1960 return 0; 1961} 1962 1963static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) 1964{ 1965 unsigned int value; 1966 const int read_status_instruction = 0x5; 1967 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1968 1969 /* enable read/write to eeprom */ 1970 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1971 udelay(1); 1972 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1973 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1974 udelay(1); 1975 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1976 1977 /* send read status instruction */ 1978 labpc_serial_out(dev, read_status_instruction, write_length); 1979 /* read result */ 1980 value = labpc_serial_in(dev); 1981 1982 /* disable read/write to eeprom */ 1983 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1984 udelay(1); 1985 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1986 1987 return value; 1988} 1989 1990/* writes to 8 bit calibration dacs */ 1991static void write_caldac(struct comedi_device *dev, unsigned int channel, 1992 unsigned int value) 1993{ 1994 if (value == devpriv->caldac[channel]) 1995 return; 1996 devpriv->caldac[channel] = value; 1997 1998 /* clear caldac load bit and make sure we don't write to eeprom */ 1999 devpriv->command5_bits &= 2000 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 2001 udelay(1); 2002 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2003 2004 /* write 4 bit channel */ 2005 labpc_serial_out(dev, channel, 4); 2006 /* write 8 bit caldac value */ 2007 labpc_serial_out(dev, value, 8); 2008 2009 /* set and clear caldac bit to load caldac value */ 2010 devpriv->command5_bits |= CALDAC_LOAD_BIT; 2011 udelay(1); 2012 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2013 devpriv->command5_bits &= ~CALDAC_LOAD_BIT; 2014 udelay(1); 2015 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2016} 2017 2018#ifdef CONFIG_COMEDI_PCI 2019COMEDI_PCI_INITCLEANUP(driver_labpc, labpc_pci_table); 2020#else 2021COMEDI_INITCLEANUP(driver_labpc); 2022#endif 2023 2024EXPORT_SYMBOL_GPL(labpc_common_attach); 2025EXPORT_SYMBOL_GPL(labpc_common_detach); 2026EXPORT_SYMBOL_GPL(range_labpc_1200_ai); 2027EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); 2028EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar); 2029