ni_labpc.c revision e41a6f6d9cb7404420d596f27609a3f4f55dcaf5
1/* 2 comedi/drivers/ni_labpc.c 3 Driver for National Instruments Lab-PC series boards and compatibles 4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20************************************************************************ 21*/ 22/* 23Driver: ni_labpc 24Description: National Instruments Lab-PC (& compatibles) 25Author: Frank Mori Hess <fmhess@users.sourceforge.net> 26Devices: [National Instruments] Lab-PC-1200 (labpc-1200), 27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc) 28Status: works 29 30Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges 31and analog references will work, the available ranges/arefs will 32depend on how you have configured the jumpers on your board 33(see your owner's manual). 34 35Kernel-level ISA plug-and-play support for the lab-pc-1200 36boards has not 37yet been added to the driver, mainly due to the fact that 38I don't know the device id numbers. If you have one 39of these boards, 40please file a bug report at https://bugs.comedi.org/ 41so I can get the necessary information from you. 42 43The 1200 series boards have onboard calibration dacs for correcting 44analog input/output offsets and gains. The proper settings for these 45caldacs are stored on the board's eeprom. To read the caldac values 46from the eeprom and store them into a file that can be then be used by 47comedilib, use the comedi_calibrate program. 48 49Configuration options - ISA boards: 50 [0] - I/O port base address 51 [1] - IRQ (optional, required for timed or externally triggered conversions) 52 [2] - DMA channel (optional) 53 54Configuration options - PCI boards: 55 [0] - bus (optional) 56 [1] - slot (optional) 57 58The Lab-pc+ has quirky chanlist requirements 59when scanning multiple channels. Multiple channel scan 60sequence must start at highest channel, then decrement down to 61channel 0. The rest of the cards can scan down like lab-pc+ or scan 62up from channel zero. Chanlists consisting of all one channel 63are also legal, and allow you to pace conversions in bursts. 64 65*/ 66 67/* 68 69NI manuals: 70341309a (labpc-1200 register manual) 71340914a (pci-1200) 72320502b (lab-pc+) 73 74*/ 75 76#undef LABPC_DEBUG 77/* #define LABPC_DEBUG enable debugging messages */ 78 79#include <linux/interrupt.h> 80#include "../comedidev.h" 81 82#include <linux/delay.h> 83#include <asm/dma.h> 84 85#include "8253.h" 86#include "8255.h" 87#include "mite.h" 88#include "comedi_fc.h" 89#include "ni_labpc.h" 90 91#define DRV_NAME "ni_labpc" 92 93/* size of io region used by board */ 94#define LABPC_SIZE 32 95/* 2 MHz master clock */ 96#define LABPC_TIMER_BASE 500 97 98/* Registers for the lab-pc+ */ 99 100/* write-only registers */ 101#define COMMAND1_REG 0x0 102#define ADC_GAIN_MASK (0x7 << 4) 103#define ADC_CHAN_BITS(x) ((x) & 0x7) 104/* enables multi channel scans */ 105#define ADC_SCAN_EN_BIT 0x80 106#define COMMAND2_REG 0x1 107/* enable pretriggering (used in conjunction with SWTRIG) */ 108#define PRETRIG_BIT 0x1 109/* enable paced conversions on external trigger */ 110#define HWTRIG_BIT 0x2 111/* enable paced conversions */ 112#define SWTRIG_BIT 0x4 113/* use two cascaded counters for pacing */ 114#define CASCADE_BIT 0x8 115#define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1)) 116#define COMMAND3_REG 0x2 117/* enable dma transfers */ 118#define DMA_EN_BIT 0x1 119/* enable interrupts for 8255 */ 120#define DIO_INTR_EN_BIT 0x2 121/* enable dma terminal count interrupt */ 122#define DMATC_INTR_EN_BIT 0x4 123/* enable timer interrupt */ 124#define TIMER_INTR_EN_BIT 0x8 125/* enable error interrupt */ 126#define ERR_INTR_EN_BIT 0x10 127/* enable fifo not empty interrupt */ 128#define ADC_FNE_INTR_EN_BIT 0x20 129#define ADC_CONVERT_REG 0x3 130#define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1)) 131#define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1)) 132#define ADC_CLEAR_REG 0x8 133#define DMATC_CLEAR_REG 0xa 134#define TIMER_CLEAR_REG 0xc 135/* 1200 boards only */ 136#define COMMAND6_REG 0xe 137/* select ground or common-mode reference */ 138#define ADC_COMMON_BIT 0x1 139/* adc unipolar */ 140#define ADC_UNIP_BIT 0x2 141/* dac unipolar */ 142#define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) 143/* enable fifo half full interrupt */ 144#define ADC_FHF_INTR_EN_BIT 0x20 145/* enable interrupt on end of hardware count */ 146#define A1_INTR_EN_BIT 0x40 147/* scan up from channel zero instead of down to zero */ 148#define ADC_SCAN_UP_BIT 0x80 149#define COMMAND4_REG 0xf 150/* enables 'interval' scanning */ 151#define INTERVAL_SCAN_EN_BIT 0x1 152/* enables external signal on counter b1 output to trigger scan */ 153#define EXT_SCAN_EN_BIT 0x2 154/* chooses direction (output or input) for EXTCONV* line */ 155#define EXT_CONVERT_OUT_BIT 0x4 156/* chooses differential inputs for adc (in conjunction with board jumper) */ 157#define ADC_DIFF_BIT 0x8 158#define EXT_CONVERT_DISABLE_BIT 0x10 159/* 1200 boards only, calibration stuff */ 160#define COMMAND5_REG 0x1c 161/* enable eeprom for write */ 162#define EEPROM_WRITE_UNPROTECT_BIT 0x4 163/* enable dithering */ 164#define DITHER_EN_BIT 0x8 165/* load calibration dac */ 166#define CALDAC_LOAD_BIT 0x10 167/* serial clock - rising edge writes, falling edge reads */ 168#define SCLOCK_BIT 0x20 169/* serial data bit for writing to eeprom or calibration dacs */ 170#define SDATA_BIT 0x40 171/* enable eeprom for read/write */ 172#define EEPROM_EN_BIT 0x80 173#define INTERVAL_COUNT_REG 0x1e 174#define INTERVAL_LOAD_REG 0x1f 175#define INTERVAL_LOAD_BITS 0x1 176 177/* read-only registers */ 178#define STATUS1_REG 0x0 179/* data is available in fifo */ 180#define DATA_AVAIL_BIT 0x1 181/* overrun has occurred */ 182#define OVERRUN_BIT 0x2 183/* fifo overflow */ 184#define OVERFLOW_BIT 0x4 185/* timer interrupt has occured */ 186#define TIMER_BIT 0x8 187/* dma terminal count has occured */ 188#define DMATC_BIT 0x10 189/* external trigger has occured */ 190#define EXT_TRIG_BIT 0x40 191/* 1200 boards only */ 192#define STATUS2_REG 0x1d 193/* programmable eeprom serial output */ 194#define EEPROM_OUT_BIT 0x1 195/* counter A1 terminal count */ 196#define A1_TC_BIT 0x2 197/* fifo not half full */ 198#define FNHF_BIT 0x4 199#define ADC_FIFO_REG 0xa 200 201#define DIO_BASE_REG 0x10 202#define COUNTER_A_BASE_REG 0x14 203#define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3) 204/* check modes put conversion pacer output in harmless state (a0 mode 2) */ 205#define INIT_A0_BITS 0x14 206/* put hardware conversion counter output in harmless state (a1 mode 0) */ 207#define INIT_A1_BITS 0x70 208#define COUNTER_B_BASE_REG 0x18 209 210static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it); 211static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 212static irqreturn_t labpc_interrupt(int irq, void *d); 213static int labpc_drain_fifo(struct comedi_device *dev); 214static void labpc_drain_dma(struct comedi_device *dev); 215static void handle_isa_dma(struct comedi_device *dev); 216static void labpc_drain_dregs(struct comedi_device *dev); 217static int labpc_ai_cmdtest(struct comedi_device *dev, 218 struct comedi_subdevice *s, struct comedi_cmd *cmd); 219static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 220static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 221 struct comedi_insn *insn, unsigned int *data); 222static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 223 struct comedi_insn *insn, unsigned int *data); 224static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 225 struct comedi_insn *insn, unsigned int *data); 226static int labpc_calib_read_insn(struct comedi_device *dev, 227 struct comedi_subdevice *s, 228 struct comedi_insn *insn, unsigned int *data); 229static int labpc_calib_write_insn(struct comedi_device *dev, 230 struct comedi_subdevice *s, 231 struct comedi_insn *insn, unsigned int *data); 232static int labpc_eeprom_read_insn(struct comedi_device *dev, 233 struct comedi_subdevice *s, 234 struct comedi_insn *insn, unsigned int *data); 235static int labpc_eeprom_write_insn(struct comedi_device *dev, 236 struct comedi_subdevice *s, 237 struct comedi_insn *insn, 238 unsigned int *data); 239static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd); 240static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd); 241#ifdef CONFIG_COMEDI_PCI 242static int labpc_find_device(struct comedi_device *dev, int bus, int slot); 243#endif 244static int labpc_dio_mem_callback(int dir, int port, int data, 245 unsigned long arg); 246static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 247 unsigned int num_bits); 248static unsigned int labpc_serial_in(struct comedi_device *dev); 249static unsigned int labpc_eeprom_read(struct comedi_device *dev, 250 unsigned int address); 251static unsigned int labpc_eeprom_read_status(struct comedi_device *dev); 252static unsigned int labpc_eeprom_write(struct comedi_device *dev, 253 unsigned int address, 254 unsigned int value); 255static void write_caldac(struct comedi_device *dev, unsigned int channel, 256 unsigned int value); 257 258enum scan_mode { 259 MODE_SINGLE_CHAN, 260 MODE_SINGLE_CHAN_INTERVAL, 261 MODE_MULT_CHAN_UP, 262 MODE_MULT_CHAN_DOWN, 263}; 264 265/* analog input ranges */ 266#define NUM_LABPC_PLUS_AI_RANGES 16 267/* indicates unipolar ranges */ 268static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = { 269 0, 270 0, 271 0, 272 0, 273 0, 274 0, 275 0, 276 0, 277 1, 278 1, 279 1, 280 1, 281 1, 282 1, 283 1, 284 1, 285}; 286 287/* map range index to gain bits */ 288static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = { 289 0x00, 290 0x10, 291 0x20, 292 0x30, 293 0x40, 294 0x50, 295 0x60, 296 0x70, 297 0x00, 298 0x10, 299 0x20, 300 0x30, 301 0x40, 302 0x50, 303 0x60, 304 0x70, 305}; 306 307static const struct comedi_lrange range_labpc_plus_ai = { 308 NUM_LABPC_PLUS_AI_RANGES, 309 { 310 BIP_RANGE(5), 311 BIP_RANGE(4), 312 BIP_RANGE(2.5), 313 BIP_RANGE(1), 314 BIP_RANGE(0.5), 315 BIP_RANGE(0.25), 316 BIP_RANGE(0.1), 317 BIP_RANGE(0.05), 318 UNI_RANGE(10), 319 UNI_RANGE(8), 320 UNI_RANGE(5), 321 UNI_RANGE(2), 322 UNI_RANGE(1), 323 UNI_RANGE(0.5), 324 UNI_RANGE(0.2), 325 UNI_RANGE(0.1), 326 } 327}; 328 329#define NUM_LABPC_1200_AI_RANGES 14 330/* indicates unipolar ranges */ 331const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = { 332 0, 333 0, 334 0, 335 0, 336 0, 337 0, 338 0, 339 1, 340 1, 341 1, 342 1, 343 1, 344 1, 345 1, 346}; 347 348/* map range index to gain bits */ 349const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = { 350 0x00, 351 0x20, 352 0x30, 353 0x40, 354 0x50, 355 0x60, 356 0x70, 357 0x00, 358 0x20, 359 0x30, 360 0x40, 361 0x50, 362 0x60, 363 0x70, 364}; 365 366const struct comedi_lrange range_labpc_1200_ai = { 367 NUM_LABPC_1200_AI_RANGES, 368 { 369 BIP_RANGE(5), 370 BIP_RANGE(2.5), 371 BIP_RANGE(1), 372 BIP_RANGE(0.5), 373 BIP_RANGE(0.25), 374 BIP_RANGE(0.1), 375 BIP_RANGE(0.05), 376 UNI_RANGE(10), 377 UNI_RANGE(5), 378 UNI_RANGE(2), 379 UNI_RANGE(1), 380 UNI_RANGE(0.5), 381 UNI_RANGE(0.2), 382 UNI_RANGE(0.1), 383 } 384}; 385 386/* analog output ranges */ 387#define AO_RANGE_IS_UNIPOLAR 0x1 388static const struct comedi_lrange range_labpc_ao = { 389 2, 390 { 391 BIP_RANGE(5), 392 UNI_RANGE(10), 393 } 394}; 395 396/* functions that do inb/outb and readb/writeb so we can use 397 * function pointers to decide which to use */ 398static inline unsigned int labpc_inb(unsigned long address) 399{ 400 return inb(address); 401} 402 403static inline void labpc_outb(unsigned int byte, unsigned long address) 404{ 405 outb(byte, address); 406} 407 408static inline unsigned int labpc_readb(unsigned long address) 409{ 410 return readb((void *)address); 411} 412 413static inline void labpc_writeb(unsigned int byte, unsigned long address) 414{ 415 writeb(byte, (void *)address); 416} 417 418static const struct labpc_board_struct labpc_boards[] = { 419 { 420 .name = "lab-pc-1200", 421 .ai_speed = 10000, 422 .bustype = isa_bustype, 423 .register_layout = labpc_1200_layout, 424 .has_ao = 1, 425 .ai_range_table = &range_labpc_1200_ai, 426 .ai_range_code = labpc_1200_ai_gain_bits, 427 .ai_range_is_unipolar = labpc_1200_is_unipolar, 428 .ai_scan_up = 1, 429 .memory_mapped_io = 0, 430 }, 431 { 432 .name = "lab-pc-1200ai", 433 .ai_speed = 10000, 434 .bustype = isa_bustype, 435 .register_layout = labpc_1200_layout, 436 .has_ao = 0, 437 .ai_range_table = &range_labpc_1200_ai, 438 .ai_range_code = labpc_1200_ai_gain_bits, 439 .ai_range_is_unipolar = labpc_1200_is_unipolar, 440 .ai_scan_up = 1, 441 .memory_mapped_io = 0, 442 }, 443 { 444 .name = "lab-pc+", 445 .ai_speed = 12000, 446 .bustype = isa_bustype, 447 .register_layout = labpc_plus_layout, 448 .has_ao = 1, 449 .ai_range_table = &range_labpc_plus_ai, 450 .ai_range_code = labpc_plus_ai_gain_bits, 451 .ai_range_is_unipolar = labpc_plus_is_unipolar, 452 .ai_scan_up = 0, 453 .memory_mapped_io = 0, 454 }, 455#ifdef CONFIG_COMEDI_PCI 456 { 457 .name = "pci-1200", 458 .device_id = 0x161, 459 .ai_speed = 10000, 460 .bustype = pci_bustype, 461 .register_layout = labpc_1200_layout, 462 .has_ao = 1, 463 .ai_range_table = &range_labpc_1200_ai, 464 .ai_range_code = labpc_1200_ai_gain_bits, 465 .ai_range_is_unipolar = labpc_1200_is_unipolar, 466 .ai_scan_up = 1, 467 .memory_mapped_io = 1, 468 }, 469/* dummy entry so pci board works when comedi_config is passed driver name */ 470 { 471 .name = DRV_NAME, 472 .bustype = pci_bustype, 473 }, 474#endif 475}; 476 477/* 478 * Useful for shorthand access to the particular board structure 479 */ 480#define thisboard ((struct labpc_board_struct *)dev->board_ptr) 481 482/* size in bytes of dma buffer */ 483static const int dma_buffer_size = 0xff00; 484/* 2 bytes per sample */ 485static const int sample_size = 2; 486 487#define devpriv ((struct labpc_private *)dev->private) 488 489static struct comedi_driver driver_labpc = { 490 .driver_name = DRV_NAME, 491 .module = THIS_MODULE, 492 .attach = labpc_attach, 493 .detach = labpc_common_detach, 494 .num_names = ARRAY_SIZE(labpc_boards), 495 .board_name = &labpc_boards[0].name, 496 .offset = sizeof(struct labpc_board_struct), 497}; 498 499#ifdef CONFIG_COMEDI_PCI 500static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = { 501 { 502 PCI_VENDOR_ID_NATINST, 0x161, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 503 0} 504}; 505 506MODULE_DEVICE_TABLE(pci, labpc_pci_table); 507#endif /* CONFIG_COMEDI_PCI */ 508 509static inline int labpc_counter_load(struct comedi_device *dev, 510 unsigned long base_address, 511 unsigned int counter_number, 512 unsigned int count, unsigned int mode) 513{ 514 if (thisboard->memory_mapped_io) 515 return i8254_mm_load((void *)base_address, 0, counter_number, 516 count, mode); 517 else 518 return i8254_load(base_address, 0, counter_number, count, mode); 519} 520 521int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, 522 unsigned int irq, unsigned int dma_chan) 523{ 524 struct comedi_subdevice *s; 525 int i; 526 unsigned long dma_flags, isr_flags; 527 short lsb, msb; 528 529 printk("comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, thisboard->name, 530 iobase); 531 if (irq) 532 printk(", irq %u", irq); 533 if (dma_chan) 534 printk(", dma %u", dma_chan); 535 printk("\n"); 536 537 if (iobase == 0) { 538 printk("io base address is zero!\n"); 539 return -EINVAL; 540 } 541 /* request io regions for isa boards */ 542 if (thisboard->bustype == isa_bustype) { 543 /* check if io addresses are available */ 544 if (!request_region(iobase, LABPC_SIZE, 545 driver_labpc.driver_name)) { 546 printk("I/O port conflict\n"); 547 return -EIO; 548 } 549 } 550 dev->iobase = iobase; 551 552 if (thisboard->memory_mapped_io) { 553 devpriv->read_byte = labpc_readb; 554 devpriv->write_byte = labpc_writeb; 555 } else { 556 devpriv->read_byte = labpc_inb; 557 devpriv->write_byte = labpc_outb; 558 } 559 /* initialize board's command registers */ 560 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 561 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 562 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 563 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 564 if (thisboard->register_layout == labpc_1200_layout) { 565 devpriv->write_byte(devpriv->command5_bits, 566 dev->iobase + COMMAND5_REG); 567 devpriv->write_byte(devpriv->command6_bits, 568 dev->iobase + COMMAND6_REG); 569 } 570 571 /* grab our IRQ */ 572 if (irq) { 573 isr_flags = 0; 574 if (thisboard->bustype == pci_bustype) 575 isr_flags |= IRQF_SHARED; 576 if (request_irq(irq, labpc_interrupt, isr_flags, 577 driver_labpc.driver_name, dev)) { 578 printk("unable to allocate irq %u\n", irq); 579 return -EINVAL; 580 } 581 } 582 dev->irq = irq; 583 584 /* grab dma channel */ 585 if (dma_chan > 3) { 586 printk(" invalid dma channel %u\n", dma_chan); 587 return -EINVAL; 588 } else if (dma_chan) { 589 /* allocate dma buffer */ 590 devpriv->dma_buffer = 591 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA); 592 if (devpriv->dma_buffer == NULL) { 593 printk(" failed to allocate dma buffer\n"); 594 return -ENOMEM; 595 } 596 if (request_dma(dma_chan, driver_labpc.driver_name)) { 597 printk(" failed to allocate dma channel %u\n", 598 dma_chan); 599 return -EINVAL; 600 } 601 devpriv->dma_chan = dma_chan; 602 dma_flags = claim_dma_lock(); 603 disable_dma(devpriv->dma_chan); 604 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); 605 release_dma_lock(dma_flags); 606 } 607 608 dev->board_name = thisboard->name; 609 610 if (alloc_subdevices(dev, 5) < 0) 611 return -ENOMEM; 612 613 /* analog input subdevice */ 614 s = dev->subdevices + 0; 615 dev->read_subdev = s; 616 s->type = COMEDI_SUBD_AI; 617 s->subdev_flags = 618 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ; 619 s->n_chan = 8; 620 s->len_chanlist = 8; 621 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 622 s->range_table = thisboard->ai_range_table; 623 s->do_cmd = labpc_ai_cmd; 624 s->do_cmdtest = labpc_ai_cmdtest; 625 s->insn_read = labpc_ai_rinsn; 626 s->cancel = labpc_cancel; 627 628 /* analog output */ 629 s = dev->subdevices + 1; 630 if (thisboard->has_ao) { 631 /* Could provide command support, except it only has a 632 * one sample hardware buffer for analog output and no 633 * underrun flag. */ 634 s->type = COMEDI_SUBD_AO; 635 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; 636 s->n_chan = NUM_AO_CHAN; 637 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 638 s->range_table = &range_labpc_ao; 639 s->insn_read = labpc_ao_rinsn; 640 s->insn_write = labpc_ao_winsn; 641 /* initialize analog outputs to a known value */ 642 for (i = 0; i < s->n_chan; i++) { 643 devpriv->ao_value[i] = s->maxdata / 2; 644 lsb = devpriv->ao_value[i] & 0xff; 645 msb = (devpriv->ao_value[i] >> 8) & 0xff; 646 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); 647 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); 648 } 649 } else { 650 s->type = COMEDI_SUBD_UNUSED; 651 } 652 653 /* 8255 dio */ 654 s = dev->subdevices + 2; 655 /* if board uses io memory we have to give a custom callback 656 * function to the 8255 driver */ 657 if (thisboard->memory_mapped_io) 658 subdev_8255_init(dev, s, labpc_dio_mem_callback, 659 (unsigned long)(dev->iobase + DIO_BASE_REG)); 660 else 661 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG); 662 663 /* calibration subdevices for boards that have one */ 664 s = dev->subdevices + 3; 665 if (thisboard->register_layout == labpc_1200_layout) { 666 s->type = COMEDI_SUBD_CALIB; 667 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 668 s->n_chan = 16; 669 s->maxdata = 0xff; 670 s->insn_read = labpc_calib_read_insn; 671 s->insn_write = labpc_calib_write_insn; 672 673 for (i = 0; i < s->n_chan; i++) 674 write_caldac(dev, i, s->maxdata / 2); 675 } else 676 s->type = COMEDI_SUBD_UNUSED; 677 678 /* EEPROM */ 679 s = dev->subdevices + 4; 680 if (thisboard->register_layout == labpc_1200_layout) { 681 s->type = COMEDI_SUBD_MEMORY; 682 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 683 s->n_chan = EEPROM_SIZE; 684 s->maxdata = 0xff; 685 s->insn_read = labpc_eeprom_read_insn; 686 s->insn_write = labpc_eeprom_write_insn; 687 688 for (i = 0; i < EEPROM_SIZE; i++) 689 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); 690#ifdef LABPC_DEBUG 691 printk(" eeprom:"); 692 for (i = 0; i < EEPROM_SIZE; i++) 693 printk(" %i:0x%x ", i, devpriv->eeprom_data[i]); 694 printk("\n"); 695#endif 696 } else 697 s->type = COMEDI_SUBD_UNUSED; 698 699 return 0; 700} 701 702static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) 703{ 704 unsigned long iobase = 0; 705 unsigned int irq = 0; 706 unsigned int dma_chan = 0; 707#ifdef CONFIG_COMEDI_PCI 708 int retval; 709#endif 710 711 /* allocate and initialize dev->private */ 712 if (alloc_private(dev, sizeof(struct labpc_private)) < 0) 713 return -ENOMEM; 714 715 /* get base address, irq etc. based on bustype */ 716 switch (thisboard->bustype) { 717 case isa_bustype: 718 iobase = it->options[0]; 719 irq = it->options[1]; 720 dma_chan = it->options[2]; 721 break; 722 case pci_bustype: 723#ifdef CONFIG_COMEDI_PCI 724 retval = labpc_find_device(dev, it->options[0], it->options[1]); 725 if (retval < 0) 726 return retval; 727 retval = mite_setup(devpriv->mite); 728 if (retval < 0) 729 return retval; 730 iobase = (unsigned long)devpriv->mite->daq_io_addr; 731 irq = mite_irq(devpriv->mite); 732#else 733 printk(" this driver has not been built with PCI support.\n"); 734 return -EINVAL; 735#endif 736 break; 737 case pcmcia_bustype: 738 printk 739 (" this driver does not support pcmcia cards, use ni_labpc_cs.o\n"); 740 return -EINVAL; 741 break; 742 default: 743 printk("bug! couldn't determine board type\n"); 744 return -EINVAL; 745 break; 746 } 747 748 return labpc_common_attach(dev, iobase, irq, dma_chan); 749} 750 751/* adapted from ni_pcimio for finding mite based boards (pc-1200) */ 752#ifdef CONFIG_COMEDI_PCI 753static int labpc_find_device(struct comedi_device *dev, int bus, int slot) 754{ 755 struct mite_struct *mite; 756 int i; 757 for (mite = mite_devices; mite; mite = mite->next) { 758 if (mite->used) 759 continue; 760/* if bus/slot are specified then make sure we have the right bus/slot */ 761 if (bus || slot) { 762 if (bus != mite->pcidev->bus->number 763 || slot != PCI_SLOT(mite->pcidev->devfn)) 764 continue; 765 } 766 for (i = 0; i < driver_labpc.num_names; i++) { 767 if (labpc_boards[i].bustype != pci_bustype) 768 continue; 769 if (mite_device_id(mite) == labpc_boards[i].device_id) { 770 devpriv->mite = mite; 771/* fixup board pointer, in case we were using the dummy "ni_labpc" entry */ 772 dev->board_ptr = &labpc_boards[i]; 773 return 0; 774 } 775 } 776 } 777 printk("no device found\n"); 778 mite_list_devices(); 779 return -EIO; 780} 781#endif 782 783int labpc_common_detach(struct comedi_device *dev) 784{ 785 printk("comedi%d: ni_labpc: detach\n", dev->minor); 786 787 if (dev->subdevices) 788 subdev_8255_cleanup(dev, dev->subdevices + 2); 789 790 /* only free stuff if it has been allocated by _attach */ 791 if (devpriv->dma_buffer) 792 kfree(devpriv->dma_buffer); 793 if (devpriv->dma_chan) 794 free_dma(devpriv->dma_chan); 795 if (dev->irq) 796 free_irq(dev->irq, dev); 797 if (thisboard->bustype == isa_bustype && dev->iobase) 798 release_region(dev->iobase, LABPC_SIZE); 799#ifdef CONFIG_COMEDI_PCI 800 if (devpriv->mite) 801 mite_unsetup(devpriv->mite); 802#endif 803 804 return 0; 805}; 806 807static void labpc_clear_adc_fifo(const struct comedi_device *dev) 808{ 809 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 810 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 811 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 812} 813 814static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 815{ 816 unsigned long flags; 817 818 spin_lock_irqsave(&dev->spinlock, flags); 819 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 820 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 821 spin_unlock_irqrestore(&dev->spinlock, flags); 822 823 devpriv->command3_bits = 0; 824 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 825 826 return 0; 827} 828 829static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) 830{ 831 if (cmd->chanlist_len == 1) 832 return MODE_SINGLE_CHAN; 833 834 /* chanlist may be NULL during cmdtest. */ 835 if (cmd->chanlist == NULL) 836 return MODE_MULT_CHAN_UP; 837 838 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) 839 return MODE_SINGLE_CHAN_INTERVAL; 840 841 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) 842 return MODE_MULT_CHAN_UP; 843 844 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) 845 return MODE_MULT_CHAN_DOWN; 846 847 printk("ni_labpc: bug! this should never happen\n"); 848 849 return 0; 850} 851 852static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, 853 const struct comedi_cmd *cmd) 854{ 855 int mode, channel, range, aref, i; 856 857 if (cmd->chanlist == NULL) 858 return 0; 859 860 mode = labpc_ai_scan_mode(cmd); 861 862 if (mode == MODE_SINGLE_CHAN) 863 return 0; 864 865 if (mode == MODE_SINGLE_CHAN_INTERVAL) { 866 if (cmd->chanlist_len > 0xff) { 867 comedi_error(dev, 868 "ni_labpc: chanlist too long for single channel interval mode\n"); 869 return 1; 870 } 871 } 872 873 channel = CR_CHAN(cmd->chanlist[0]); 874 range = CR_RANGE(cmd->chanlist[0]); 875 aref = CR_AREF(cmd->chanlist[0]); 876 877 for (i = 0; i < cmd->chanlist_len; i++) { 878 879 switch (mode) { 880 case MODE_SINGLE_CHAN_INTERVAL: 881 if (CR_CHAN(cmd->chanlist[i]) != channel) { 882 comedi_error(dev, 883 "channel scanning order specified in chanlist is not supported by hardware.\n"); 884 return 1; 885 } 886 break; 887 case MODE_MULT_CHAN_UP: 888 if (CR_CHAN(cmd->chanlist[i]) != i) { 889 comedi_error(dev, 890 "channel scanning order specified in chanlist is not supported by hardware.\n"); 891 return 1; 892 } 893 break; 894 case MODE_MULT_CHAN_DOWN: 895 if (CR_CHAN(cmd->chanlist[i]) != 896 cmd->chanlist_len - i - 1) { 897 comedi_error(dev, 898 "channel scanning order specified in chanlist is not supported by hardware.\n"); 899 return 1; 900 } 901 break; 902 default: 903 printk("ni_labpc: bug! in chanlist check\n"); 904 return 1; 905 break; 906 } 907 908 if (CR_RANGE(cmd->chanlist[i]) != range) { 909 comedi_error(dev, 910 "entries in chanlist must all have the same range\n"); 911 return 1; 912 } 913 914 if (CR_AREF(cmd->chanlist[i]) != aref) { 915 comedi_error(dev, 916 "entries in chanlist must all have the same reference\n"); 917 return 1; 918 } 919 } 920 921 return 0; 922} 923 924static int labpc_use_continuous_mode(const struct comedi_cmd *cmd) 925{ 926 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN) 927 return 1; 928 929 if (cmd->scan_begin_src == TRIG_FOLLOW) 930 return 1; 931 932 return 0; 933} 934 935static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd) 936{ 937 if (cmd->convert_src != TRIG_TIMER) 938 return 0; 939 940 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 941 cmd->scan_begin_src == TRIG_TIMER) 942 return cmd->scan_begin_arg; 943 944 return cmd->convert_arg; 945} 946 947static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns) 948{ 949 if (cmd->convert_src != TRIG_TIMER) 950 return; 951 952 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 953 cmd->scan_begin_src == TRIG_TIMER) { 954 cmd->scan_begin_arg = ns; 955 if (cmd->convert_arg > cmd->scan_begin_arg) 956 cmd->convert_arg = cmd->scan_begin_arg; 957 } else 958 cmd->convert_arg = ns; 959} 960 961static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd) 962{ 963 if (cmd->scan_begin_src != TRIG_TIMER) 964 return 0; 965 966 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 967 cmd->convert_src == TRIG_TIMER) 968 return 0; 969 970 return cmd->scan_begin_arg; 971} 972 973static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns) 974{ 975 if (cmd->scan_begin_src != TRIG_TIMER) 976 return; 977 978 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 979 cmd->convert_src == TRIG_TIMER) 980 return; 981 982 cmd->scan_begin_arg = ns; 983} 984 985static int labpc_ai_cmdtest(struct comedi_device *dev, 986 struct comedi_subdevice *s, struct comedi_cmd *cmd) 987{ 988 int err = 0; 989 int tmp, tmp2; 990 int stop_mask; 991 992 /* step 1: make sure trigger sources are trivially valid */ 993 994 tmp = cmd->start_src; 995 cmd->start_src &= TRIG_NOW | TRIG_EXT; 996 if (!cmd->start_src || tmp != cmd->start_src) 997 err++; 998 999 tmp = cmd->scan_begin_src; 1000 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT; 1001 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 1002 err++; 1003 1004 tmp = cmd->convert_src; 1005 cmd->convert_src &= TRIG_TIMER | TRIG_EXT; 1006 if (!cmd->convert_src || tmp != cmd->convert_src) 1007 err++; 1008 1009 tmp = cmd->scan_end_src; 1010 cmd->scan_end_src &= TRIG_COUNT; 1011 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 1012 err++; 1013 1014 tmp = cmd->stop_src; 1015 stop_mask = TRIG_COUNT | TRIG_NONE; 1016 if (thisboard->register_layout == labpc_1200_layout) 1017 stop_mask |= TRIG_EXT; 1018 cmd->stop_src &= stop_mask; 1019 if (!cmd->stop_src || tmp != cmd->stop_src) 1020 err++; 1021 1022 if (err) 1023 return 1; 1024 1025 /* step 2: make sure trigger sources are unique and mutually compatible */ 1026 1027 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) 1028 err++; 1029 if (cmd->scan_begin_src != TRIG_TIMER && 1030 cmd->scan_begin_src != TRIG_FOLLOW && 1031 cmd->scan_begin_src != TRIG_EXT) 1032 err++; 1033 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT) 1034 err++; 1035 if (cmd->stop_src != TRIG_COUNT && 1036 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE) 1037 err++; 1038 1039 /* can't have external stop and start triggers at once */ 1040 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) 1041 err++; 1042 1043 if (err) 1044 return 2; 1045 1046 /* step 3: make sure arguments are trivially compatible */ 1047 1048 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) { 1049 cmd->start_arg = 0; 1050 err++; 1051 } 1052 1053 if (!cmd->chanlist_len) 1054 err++; 1055 1056 if (cmd->scan_end_arg != cmd->chanlist_len) { 1057 cmd->scan_end_arg = cmd->chanlist_len; 1058 err++; 1059 } 1060 1061 if (cmd->convert_src == TRIG_TIMER) { 1062 if (cmd->convert_arg < thisboard->ai_speed) { 1063 cmd->convert_arg = thisboard->ai_speed; 1064 err++; 1065 } 1066 } 1067 /* make sure scan timing is not too fast */ 1068 if (cmd->scan_begin_src == TRIG_TIMER) { 1069 if (cmd->convert_src == TRIG_TIMER && 1070 cmd->scan_begin_arg < 1071 cmd->convert_arg * cmd->chanlist_len) { 1072 cmd->scan_begin_arg = 1073 cmd->convert_arg * cmd->chanlist_len; 1074 err++; 1075 } 1076 if (cmd->scan_begin_arg < 1077 thisboard->ai_speed * cmd->chanlist_len) { 1078 cmd->scan_begin_arg = 1079 thisboard->ai_speed * cmd->chanlist_len; 1080 err++; 1081 } 1082 } 1083 /* stop source */ 1084 switch (cmd->stop_src) { 1085 case TRIG_COUNT: 1086 if (!cmd->stop_arg) { 1087 cmd->stop_arg = 1; 1088 err++; 1089 } 1090 break; 1091 case TRIG_NONE: 1092 if (cmd->stop_arg != 0) { 1093 cmd->stop_arg = 0; 1094 err++; 1095 } 1096 break; 1097 /* TRIG_EXT doesn't care since it doesn't trigger off a numbered channel */ 1098 default: 1099 break; 1100 } 1101 1102 if (err) 1103 return 3; 1104 1105 /* step 4: fix up any arguments */ 1106 1107 tmp = cmd->convert_arg; 1108 tmp2 = cmd->scan_begin_arg; 1109 labpc_adc_timing(dev, cmd); 1110 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) 1111 err++; 1112 1113 if (err) 1114 return 4; 1115 1116 if (labpc_ai_chanlist_invalid(dev, cmd)) 1117 return 5; 1118 1119 return 0; 1120} 1121 1122static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 1123{ 1124 int channel, range, aref; 1125 unsigned long irq_flags; 1126 int ret; 1127 struct comedi_async *async = s->async; 1128 struct comedi_cmd *cmd = &async->cmd; 1129 enum transfer_type xfer; 1130 unsigned long flags; 1131 1132 if (!dev->irq) { 1133 comedi_error(dev, "no irq assigned, cannot perform command"); 1134 return -1; 1135 } 1136 1137 range = CR_RANGE(cmd->chanlist[0]); 1138 aref = CR_AREF(cmd->chanlist[0]); 1139 1140 /* make sure board is disabled before setting up aquisition */ 1141 spin_lock_irqsave(&dev->spinlock, flags); 1142 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1143 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1144 spin_unlock_irqrestore(&dev->spinlock, flags); 1145 1146 devpriv->command3_bits = 0; 1147 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1148 1149 /* initialize software conversion count */ 1150 if (cmd->stop_src == TRIG_COUNT) 1151 devpriv->count = cmd->stop_arg * cmd->chanlist_len; 1152 /* setup hardware conversion counter */ 1153 if (cmd->stop_src == TRIG_EXT) { 1154 /* load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0 */ 1155 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1156 1, 3, 0); 1157 if (ret < 0) { 1158 comedi_error(dev, "error loading counter a1"); 1159 return -1; 1160 } 1161 } else /* otherwise, just put a1 in mode 0 with no count to set its output low */ 1162 devpriv->write_byte(INIT_A1_BITS, 1163 dev->iobase + COUNTER_A_CONTROL_REG); 1164 1165 /* figure out what method we will use to transfer data */ 1166 if (devpriv->dma_chan && /* need a dma channel allocated */ 1167 /* dma unsafe at RT priority, and too much setup time for TRIG_WAKE_EOS for */ 1168 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 && 1169 /* only available on the isa boards */ 1170 thisboard->bustype == isa_bustype) { 1171 xfer = isa_dma_transfer; 1172 } else if (thisboard->register_layout == labpc_1200_layout && /* pc-plus has no fifo-half full interrupt */ 1173 /* wake-end-of-scan should interrupt on fifo not empty */ 1174 (cmd->flags & TRIG_WAKE_EOS) == 0 && 1175 /* make sure we are taking more than just a few points */ 1176 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { 1177 xfer = fifo_half_full_transfer; 1178 } else 1179 xfer = fifo_not_empty_transfer; 1180 devpriv->current_transfer = xfer; 1181 1182 /* setup command6 register for 1200 boards */ 1183 if (thisboard->register_layout == labpc_1200_layout) { 1184 /* reference inputs to ground or common? */ 1185 if (aref != AREF_GROUND) 1186 devpriv->command6_bits |= ADC_COMMON_BIT; 1187 else 1188 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1189 /* bipolar or unipolar range? */ 1190 if (thisboard->ai_range_is_unipolar[range]) 1191 devpriv->command6_bits |= ADC_UNIP_BIT; 1192 else 1193 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1194 /* interrupt on fifo half full? */ 1195 if (xfer == fifo_half_full_transfer) 1196 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT; 1197 else 1198 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1199 /* enable interrupt on counter a1 terminal count? */ 1200 if (cmd->stop_src == TRIG_EXT) 1201 devpriv->command6_bits |= A1_INTR_EN_BIT; 1202 else 1203 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1204 /* are we scanning up or down through channels? */ 1205 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1206 devpriv->command6_bits |= ADC_SCAN_UP_BIT; 1207 else 1208 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT; 1209 /* write to register */ 1210 devpriv->write_byte(devpriv->command6_bits, 1211 dev->iobase + COMMAND6_REG); 1212 } 1213 1214 /* setup channel list, etc (command1 register) */ 1215 devpriv->command1_bits = 0; 1216 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1217 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); 1218 else 1219 channel = CR_CHAN(cmd->chanlist[0]); 1220 /* munge channel bits for differential / scan disabled mode */ 1221 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF) 1222 channel *= 2; 1223 devpriv->command1_bits |= ADC_CHAN_BITS(channel); 1224 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1225 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1226 /* manual says to set scan enable bit on second pass */ 1227 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP || 1228 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) { 1229 devpriv->command1_bits |= ADC_SCAN_EN_BIT; 1230 /* need a brief delay before enabling scan, or scan 1231 * list will get screwed when you switch 1232 * between scan up to scan down mode - dunno why */ 1233 udelay(1); 1234 devpriv->write_byte(devpriv->command1_bits, 1235 dev->iobase + COMMAND1_REG); 1236 } 1237 /* setup any external triggering/pacing (command4 register) */ 1238 devpriv->command4_bits = 0; 1239 if (cmd->convert_src != TRIG_EXT) 1240 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1241 /* XXX should discard first scan when using interval scanning 1242 * since manual says it is not synced with scan clock */ 1243 if (labpc_use_continuous_mode(cmd) == 0) { 1244 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT; 1245 if (cmd->scan_begin_src == TRIG_EXT) 1246 devpriv->command4_bits |= EXT_SCAN_EN_BIT; 1247 } 1248 /* single-ended/differential */ 1249 if (aref == AREF_DIFF) 1250 devpriv->command4_bits |= ADC_DIFF_BIT; 1251 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1252 1253 devpriv->write_byte(cmd->chanlist_len, 1254 dev->iobase + INTERVAL_COUNT_REG); 1255 /* load count */ 1256 devpriv->write_byte(INTERVAL_LOAD_BITS, 1257 dev->iobase + INTERVAL_LOAD_REG); 1258 1259 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) { 1260 /* set up pacing */ 1261 labpc_adc_timing(dev, cmd); 1262 /* load counter b0 in mode 3 */ 1263 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1264 0, devpriv->divisor_b0, 3); 1265 if (ret < 0) { 1266 comedi_error(dev, "error loading counter b0"); 1267 return -1; 1268 } 1269 } 1270 /* set up conversion pacing */ 1271 if (labpc_ai_convert_period(cmd)) { 1272 /* load counter a0 in mode 2 */ 1273 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1274 0, devpriv->divisor_a0, 2); 1275 if (ret < 0) { 1276 comedi_error(dev, "error loading counter a0"); 1277 return -1; 1278 } 1279 } else 1280 devpriv->write_byte(INIT_A0_BITS, 1281 dev->iobase + COUNTER_A_CONTROL_REG); 1282 1283 /* set up scan pacing */ 1284 if (labpc_ai_scan_period(cmd)) { 1285 /* load counter b1 in mode 2 */ 1286 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1287 1, devpriv->divisor_b1, 2); 1288 if (ret < 0) { 1289 comedi_error(dev, "error loading counter b1"); 1290 return -1; 1291 } 1292 } 1293 1294 labpc_clear_adc_fifo(dev); 1295 1296 /* set up dma transfer */ 1297 if (xfer == isa_dma_transfer) { 1298 irq_flags = claim_dma_lock(); 1299 disable_dma(devpriv->dma_chan); 1300 /* clear flip-flop to make sure 2-byte registers for 1301 * count and address get set correctly */ 1302 clear_dma_ff(devpriv->dma_chan); 1303 set_dma_addr(devpriv->dma_chan, 1304 virt_to_bus(devpriv->dma_buffer)); 1305 /* set appropriate size of transfer */ 1306 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd); 1307 if (cmd->stop_src == TRIG_COUNT && 1308 devpriv->count * sample_size < devpriv->dma_transfer_size) { 1309 devpriv->dma_transfer_size = 1310 devpriv->count * sample_size; 1311 } 1312 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); 1313 enable_dma(devpriv->dma_chan); 1314 release_dma_lock(irq_flags); 1315 /* enable board's dma */ 1316 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT; 1317 } else 1318 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT; 1319 1320 /* enable error interrupts */ 1321 devpriv->command3_bits |= ERR_INTR_EN_BIT; 1322 /* enable fifo not empty interrupt? */ 1323 if (xfer == fifo_not_empty_transfer) 1324 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT; 1325 else 1326 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT; 1327 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1328 1329 /* startup aquisition */ 1330 1331 /* command2 reg */ 1332 /* use 2 cascaded counters for pacing */ 1333 spin_lock_irqsave(&dev->spinlock, flags); 1334 devpriv->command2_bits |= CASCADE_BIT; 1335 switch (cmd->start_src) { 1336 case TRIG_EXT: 1337 devpriv->command2_bits |= HWTRIG_BIT; 1338 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT; 1339 break; 1340 case TRIG_NOW: 1341 devpriv->command2_bits |= SWTRIG_BIT; 1342 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT; 1343 break; 1344 default: 1345 comedi_error(dev, "bug with start_src"); 1346 return -1; 1347 break; 1348 } 1349 switch (cmd->stop_src) { 1350 case TRIG_EXT: 1351 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT; 1352 break; 1353 case TRIG_COUNT: 1354 case TRIG_NONE: 1355 break; 1356 default: 1357 comedi_error(dev, "bug with stop_src"); 1358 return -1; 1359 } 1360 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1361 spin_unlock_irqrestore(&dev->spinlock, flags); 1362 1363 return 0; 1364} 1365 1366/* interrupt service routine */ 1367static irqreturn_t labpc_interrupt(int irq, void *d) 1368{ 1369 struct comedi_device *dev = d; 1370 struct comedi_subdevice *s = dev->read_subdev; 1371 struct comedi_async *async; 1372 struct comedi_cmd *cmd; 1373 1374 if (dev->attached == 0) { 1375 comedi_error(dev, "premature interrupt"); 1376 return IRQ_HANDLED; 1377 } 1378 1379 async = s->async; 1380 cmd = &async->cmd; 1381 async->events = 0; 1382 1383 /* read board status */ 1384 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1385 if (thisboard->register_layout == labpc_1200_layout) 1386 devpriv->status2_bits = 1387 devpriv->read_byte(dev->iobase + STATUS2_REG); 1388 1389 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT | 1390 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0 1391 && (devpriv->status2_bits & A1_TC_BIT) == 0 1392 && (devpriv->status2_bits & FNHF_BIT)) { 1393 return IRQ_NONE; 1394 } 1395 1396 if (devpriv->status1_bits & OVERRUN_BIT) { 1397 /* clear error interrupt */ 1398 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1399 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1400 comedi_event(dev, s); 1401 comedi_error(dev, "overrun"); 1402 return IRQ_HANDLED; 1403 } 1404 1405 if (devpriv->current_transfer == isa_dma_transfer) { 1406 /* if a dma terminal count of external stop trigger has occurred */ 1407 if (devpriv->status1_bits & DMATC_BIT || 1408 (thisboard->register_layout == labpc_1200_layout 1409 && devpriv->status2_bits & A1_TC_BIT)) { 1410 handle_isa_dma(dev); 1411 } 1412 } else 1413 labpc_drain_fifo(dev); 1414 1415 if (devpriv->status1_bits & TIMER_BIT) { 1416 comedi_error(dev, "handled timer interrupt?"); 1417 /* clear it */ 1418 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); 1419 } 1420 1421 if (devpriv->status1_bits & OVERFLOW_BIT) { 1422 /* clear error interrupt */ 1423 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1424 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1425 comedi_event(dev, s); 1426 comedi_error(dev, "overflow"); 1427 return IRQ_HANDLED; 1428 } 1429 /* handle external stop trigger */ 1430 if (cmd->stop_src == TRIG_EXT) { 1431 if (devpriv->status2_bits & A1_TC_BIT) { 1432 labpc_drain_dregs(dev); 1433 labpc_cancel(dev, s); 1434 async->events |= COMEDI_CB_EOA; 1435 } 1436 } 1437 1438 /* TRIG_COUNT end of acquisition */ 1439 if (cmd->stop_src == TRIG_COUNT) { 1440 if (devpriv->count == 0) { 1441 labpc_cancel(dev, s); 1442 async->events |= COMEDI_CB_EOA; 1443 } 1444 } 1445 1446 comedi_event(dev, s); 1447 return IRQ_HANDLED; 1448} 1449 1450/* read all available samples from ai fifo */ 1451static int labpc_drain_fifo(struct comedi_device *dev) 1452{ 1453 unsigned int lsb, msb; 1454 short data; 1455 struct comedi_async *async = dev->read_subdev->async; 1456 const int timeout = 10000; 1457 unsigned int i; 1458 1459 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1460 1461 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout; 1462 i++) { 1463 /* quit if we have all the data we want */ 1464 if (async->cmd.stop_src == TRIG_COUNT) { 1465 if (devpriv->count == 0) 1466 break; 1467 devpriv->count--; 1468 } 1469 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1470 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1471 data = (msb << 8) | lsb; 1472 cfc_write_to_buffer(dev->read_subdev, data); 1473 devpriv->status1_bits = 1474 devpriv->read_byte(dev->iobase + STATUS1_REG); 1475 } 1476 if (i == timeout) { 1477 comedi_error(dev, "ai timeout, fifo never empties"); 1478 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1479 return -1; 1480 } 1481 1482 return 0; 1483} 1484 1485static void labpc_drain_dma(struct comedi_device *dev) 1486{ 1487 struct comedi_subdevice *s = dev->read_subdev; 1488 struct comedi_async *async = s->async; 1489 int status; 1490 unsigned long flags; 1491 unsigned int max_points, num_points, residue, leftover; 1492 int i; 1493 1494 status = devpriv->status1_bits; 1495 1496 flags = claim_dma_lock(); 1497 disable_dma(devpriv->dma_chan); 1498 /* clear flip-flop to make sure 2-byte registers for 1499 * count and address get set correctly */ 1500 clear_dma_ff(devpriv->dma_chan); 1501 1502 /* figure out how many points to read */ 1503 max_points = devpriv->dma_transfer_size / sample_size; 1504 /* residue is the number of points left to be done on the dma 1505 * transfer. It should always be zero at this point unless 1506 * the stop_src is set to external triggering. 1507 */ 1508 residue = get_dma_residue(devpriv->dma_chan) / sample_size; 1509 num_points = max_points - residue; 1510 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) 1511 num_points = devpriv->count; 1512 1513 /* figure out how many points will be stored next time */ 1514 leftover = 0; 1515 if (async->cmd.stop_src != TRIG_COUNT) { 1516 leftover = devpriv->dma_transfer_size / sample_size; 1517 } else if (devpriv->count > num_points) { 1518 leftover = devpriv->count - num_points; 1519 if (leftover > max_points) 1520 leftover = max_points; 1521 } 1522 1523 /* write data to comedi buffer */ 1524 for (i = 0; i < num_points; i++) 1525 cfc_write_to_buffer(s, devpriv->dma_buffer[i]); 1526 if (async->cmd.stop_src == TRIG_COUNT) 1527 devpriv->count -= num_points; 1528 1529 /* set address and count for next transfer */ 1530 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); 1531 set_dma_count(devpriv->dma_chan, leftover * sample_size); 1532 release_dma_lock(flags); 1533 1534 async->events |= COMEDI_CB_BLOCK; 1535} 1536 1537static void handle_isa_dma(struct comedi_device *dev) 1538{ 1539 labpc_drain_dma(dev); 1540 1541 enable_dma(devpriv->dma_chan); 1542 1543 /* clear dma tc interrupt */ 1544 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); 1545} 1546 1547/* makes sure all data acquired by board is transfered to comedi (used 1548 * when aquisition is terminated by stop_src == TRIG_EXT). */ 1549static void labpc_drain_dregs(struct comedi_device *dev) 1550{ 1551 if (devpriv->current_transfer == isa_dma_transfer) 1552 labpc_drain_dma(dev); 1553 1554 labpc_drain_fifo(dev); 1555} 1556 1557static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1558 struct comedi_insn *insn, unsigned int *data) 1559{ 1560 int i, n; 1561 int chan, range; 1562 int lsb, msb; 1563 int timeout = 1000; 1564 unsigned long flags; 1565 1566 /* disable timed conversions */ 1567 spin_lock_irqsave(&dev->spinlock, flags); 1568 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1569 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1570 spin_unlock_irqrestore(&dev->spinlock, flags); 1571 1572 /* disable interrupt generation and dma */ 1573 devpriv->command3_bits = 0; 1574 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1575 1576 /* set gain and channel */ 1577 devpriv->command1_bits = 0; 1578 chan = CR_CHAN(insn->chanspec); 1579 range = CR_RANGE(insn->chanspec); 1580 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1581 /* munge channel bits for differential/scan disabled mode */ 1582 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1583 chan *= 2; 1584 devpriv->command1_bits |= ADC_CHAN_BITS(chan); 1585 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1586 1587 /* setup command6 register for 1200 boards */ 1588 if (thisboard->register_layout == labpc_1200_layout) { 1589 /* reference inputs to ground or common? */ 1590 if (CR_AREF(insn->chanspec) != AREF_GROUND) 1591 devpriv->command6_bits |= ADC_COMMON_BIT; 1592 else 1593 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1594 /* bipolar or unipolar range? */ 1595 if (thisboard->ai_range_is_unipolar[range]) 1596 devpriv->command6_bits |= ADC_UNIP_BIT; 1597 else 1598 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1599 /* don't interrupt on fifo half full */ 1600 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1601 /* don't enable interrupt on counter a1 terminal count? */ 1602 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1603 /* write to register */ 1604 devpriv->write_byte(devpriv->command6_bits, 1605 dev->iobase + COMMAND6_REG); 1606 } 1607 /* setup command4 register */ 1608 devpriv->command4_bits = 0; 1609 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1610 /* single-ended/differential */ 1611 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1612 devpriv->command4_bits |= ADC_DIFF_BIT; 1613 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1614 1615 /* initialize pacer counter output to make sure it doesn't cause any problems */ 1616 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG); 1617 1618 labpc_clear_adc_fifo(dev); 1619 1620 for (n = 0; n < insn->n; n++) { 1621 /* trigger conversion */ 1622 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG); 1623 1624 for (i = 0; i < timeout; i++) { 1625 if (devpriv->read_byte(dev->iobase + 1626 STATUS1_REG) & DATA_AVAIL_BIT) 1627 break; 1628 udelay(1); 1629 } 1630 if (i == timeout) { 1631 comedi_error(dev, "timeout"); 1632 return -ETIME; 1633 } 1634 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1635 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1636 data[n] = (msb << 8) | lsb; 1637 } 1638 1639 return n; 1640} 1641 1642/* analog output insn */ 1643static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 1644 struct comedi_insn *insn, unsigned int *data) 1645{ 1646 int channel, range; 1647 unsigned long flags; 1648 int lsb, msb; 1649 1650 channel = CR_CHAN(insn->chanspec); 1651 1652 /* turn off pacing of analog output channel */ 1653 /* note: hardware bug in daqcard-1200 means pacing cannot 1654 * be independently enabled/disabled for its the two channels */ 1655 spin_lock_irqsave(&dev->spinlock, flags); 1656 devpriv->command2_bits &= ~DAC_PACED_BIT(channel); 1657 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1658 spin_unlock_irqrestore(&dev->spinlock, flags); 1659 1660 /* set range */ 1661 if (thisboard->register_layout == labpc_1200_layout) { 1662 range = CR_RANGE(insn->chanspec); 1663 if (range & AO_RANGE_IS_UNIPOLAR) 1664 devpriv->command6_bits |= DAC_UNIP_BIT(channel); 1665 else 1666 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel); 1667 /* write to register */ 1668 devpriv->write_byte(devpriv->command6_bits, 1669 dev->iobase + COMMAND6_REG); 1670 } 1671 /* send data */ 1672 lsb = data[0] & 0xff; 1673 msb = (data[0] >> 8) & 0xff; 1674 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); 1675 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); 1676 1677 /* remember value for readback */ 1678 devpriv->ao_value[channel] = data[0]; 1679 1680 return 1; 1681} 1682 1683/* analog output readback insn */ 1684static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1685 struct comedi_insn *insn, unsigned int *data) 1686{ 1687 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; 1688 1689 return 1; 1690} 1691 1692static int labpc_calib_read_insn(struct comedi_device *dev, 1693 struct comedi_subdevice *s, 1694 struct comedi_insn *insn, unsigned int *data) 1695{ 1696 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)]; 1697 1698 return 1; 1699} 1700 1701static int labpc_calib_write_insn(struct comedi_device *dev, 1702 struct comedi_subdevice *s, 1703 struct comedi_insn *insn, unsigned int *data) 1704{ 1705 int channel = CR_CHAN(insn->chanspec); 1706 1707 write_caldac(dev, channel, data[0]); 1708 return 1; 1709} 1710 1711static int labpc_eeprom_read_insn(struct comedi_device *dev, 1712 struct comedi_subdevice *s, 1713 struct comedi_insn *insn, unsigned int *data) 1714{ 1715 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)]; 1716 1717 return 1; 1718} 1719 1720static int labpc_eeprom_write_insn(struct comedi_device *dev, 1721 struct comedi_subdevice *s, 1722 struct comedi_insn *insn, unsigned int *data) 1723{ 1724 int channel = CR_CHAN(insn->chanspec); 1725 int ret; 1726 1727 /* only allow writes to user area of eeprom */ 1728 if (channel < 16 || channel > 127) { 1729 printk 1730 ("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)"); 1731 return -EINVAL; 1732 } 1733 1734 ret = labpc_eeprom_write(dev, channel, data[0]); 1735 if (ret < 0) 1736 return ret; 1737 1738 return 1; 1739} 1740 1741/* utility function that suggests a dma transfer size in bytes */ 1742static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd) 1743{ 1744 unsigned int size; 1745 unsigned int freq; 1746 1747 if (cmd.convert_src == TRIG_TIMER) 1748 freq = 1000000000 / cmd.convert_arg; 1749 /* return some default value */ 1750 else 1751 freq = 0xffffffff; 1752 1753 /* make buffer fill in no more than 1/3 second */ 1754 size = (freq / 3) * sample_size; 1755 1756 /* set a minimum and maximum size allowed */ 1757 if (size > dma_buffer_size) 1758 size = dma_buffer_size - dma_buffer_size % sample_size; 1759 else if (size < sample_size) 1760 size = sample_size; 1761 1762 return size; 1763} 1764 1765/* figures out what counter values to use based on command */ 1766static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) 1767{ 1768 /* max value for 16 bit counter in mode 2 */ 1769 const int max_counter_value = 0x10000; 1770 /* min value for 16 bit counter in mode 2 */ 1771 const int min_counter_value = 2; 1772 unsigned int base_period; 1773 1774 /* 1775 * if both convert and scan triggers are TRIG_TIMER, then they 1776 * both rely on counter b0 1777 */ 1778 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) { 1779 /* 1780 * pick the lowest b0 divisor value we can (for maximum input 1781 * clock speed on convert and scan counters) 1782 */ 1783 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) / 1784 (LABPC_TIMER_BASE * max_counter_value) + 1; 1785 if (devpriv->divisor_b0 < min_counter_value) 1786 devpriv->divisor_b0 = min_counter_value; 1787 if (devpriv->divisor_b0 > max_counter_value) 1788 devpriv->divisor_b0 = max_counter_value; 1789 1790 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; 1791 1792 /* set a0 for conversion frequency and b1 for scan frequency */ 1793 switch (cmd->flags & TRIG_ROUND_MASK) { 1794 default: 1795 case TRIG_ROUND_NEAREST: 1796 devpriv->divisor_a0 = 1797 (labpc_ai_convert_period(cmd) + 1798 (base_period / 2)) / base_period; 1799 devpriv->divisor_b1 = 1800 (labpc_ai_scan_period(cmd) + 1801 (base_period / 2)) / base_period; 1802 break; 1803 case TRIG_ROUND_UP: 1804 devpriv->divisor_a0 = 1805 (labpc_ai_convert_period(cmd) + (base_period - 1806 1)) / base_period; 1807 devpriv->divisor_b1 = 1808 (labpc_ai_scan_period(cmd) + (base_period - 1809 1)) / base_period; 1810 break; 1811 case TRIG_ROUND_DOWN: 1812 devpriv->divisor_a0 = 1813 labpc_ai_convert_period(cmd) / base_period; 1814 devpriv->divisor_b1 = 1815 labpc_ai_scan_period(cmd) / base_period; 1816 break; 1817 } 1818 /* make sure a0 and b1 values are acceptable */ 1819 if (devpriv->divisor_a0 < min_counter_value) 1820 devpriv->divisor_a0 = min_counter_value; 1821 if (devpriv->divisor_a0 > max_counter_value) 1822 devpriv->divisor_a0 = max_counter_value; 1823 if (devpriv->divisor_b1 < min_counter_value) 1824 devpriv->divisor_b1 = min_counter_value; 1825 if (devpriv->divisor_b1 > max_counter_value) 1826 devpriv->divisor_b1 = max_counter_value; 1827 /* write corrected timings to command */ 1828 labpc_set_ai_convert_period(cmd, 1829 base_period * devpriv->divisor_a0); 1830 labpc_set_ai_scan_period(cmd, 1831 base_period * devpriv->divisor_b1); 1832 /* 1833 * if only one TRIG_TIMER is used, we can employ the generic 1834 * cascaded timing functions 1835 */ 1836 } else if (labpc_ai_scan_period(cmd)) { 1837 unsigned int scan_period; 1838 1839 scan_period = labpc_ai_scan_period(cmd); 1840 /* calculate cascaded counter values that give desired scan timing */ 1841 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1842 &(devpriv->divisor_b1), 1843 &(devpriv->divisor_b0), 1844 &scan_period, 1845 cmd->flags & TRIG_ROUND_MASK); 1846 labpc_set_ai_scan_period(cmd, scan_period); 1847 } else if (labpc_ai_convert_period(cmd)) { 1848 unsigned int convert_period; 1849 1850 convert_period = labpc_ai_convert_period(cmd); 1851 /* calculate cascaded counter values that give desired conversion timing */ 1852 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1853 &(devpriv->divisor_a0), 1854 &(devpriv->divisor_b0), 1855 &convert_period, 1856 cmd->flags & TRIG_ROUND_MASK); 1857 labpc_set_ai_convert_period(cmd, convert_period); 1858 } 1859} 1860 1861static int labpc_dio_mem_callback(int dir, int port, int data, 1862 unsigned long iobase) 1863{ 1864 if (dir) { 1865 writeb(data, (void *)(iobase + port)); 1866 return 0; 1867 } else { 1868 return readb((void *)(iobase + port)); 1869 } 1870} 1871 1872/* lowlevel write to eeprom/dac */ 1873static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 1874 unsigned int value_width) 1875{ 1876 int i; 1877 1878 for (i = 1; i <= value_width; i++) { 1879 /* clear serial clock */ 1880 devpriv->command5_bits &= ~SCLOCK_BIT; 1881 /* send bits most significant bit first */ 1882 if (value & (1 << (value_width - i))) 1883 devpriv->command5_bits |= SDATA_BIT; 1884 else 1885 devpriv->command5_bits &= ~SDATA_BIT; 1886 udelay(1); 1887 devpriv->write_byte(devpriv->command5_bits, 1888 dev->iobase + COMMAND5_REG); 1889 /* set clock to load bit */ 1890 devpriv->command5_bits |= SCLOCK_BIT; 1891 udelay(1); 1892 devpriv->write_byte(devpriv->command5_bits, 1893 dev->iobase + COMMAND5_REG); 1894 } 1895} 1896 1897/* lowlevel read from eeprom */ 1898static unsigned int labpc_serial_in(struct comedi_device *dev) 1899{ 1900 unsigned int value = 0; 1901 int i; 1902 const int value_width = 8; /* number of bits wide values are */ 1903 1904 for (i = 1; i <= value_width; i++) { 1905 /* set serial clock */ 1906 devpriv->command5_bits |= SCLOCK_BIT; 1907 udelay(1); 1908 devpriv->write_byte(devpriv->command5_bits, 1909 dev->iobase + COMMAND5_REG); 1910 /* clear clock bit */ 1911 devpriv->command5_bits &= ~SCLOCK_BIT; 1912 udelay(1); 1913 devpriv->write_byte(devpriv->command5_bits, 1914 dev->iobase + COMMAND5_REG); 1915 /* read bits most significant bit first */ 1916 udelay(1); 1917 devpriv->status2_bits = 1918 devpriv->read_byte(dev->iobase + STATUS2_REG); 1919 if (devpriv->status2_bits & EEPROM_OUT_BIT) 1920 value |= 1 << (value_width - i); 1921 } 1922 1923 return value; 1924} 1925 1926static unsigned int labpc_eeprom_read(struct comedi_device *dev, 1927 unsigned int address) 1928{ 1929 unsigned int value; 1930 /* bits to tell eeprom to expect a read */ 1931 const int read_instruction = 0x3; 1932 /* 8 bit write lengths to eeprom */ 1933 const int write_length = 8; 1934 1935 /* enable read/write to eeprom */ 1936 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1937 udelay(1); 1938 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1939 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1940 udelay(1); 1941 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1942 1943 /* send read instruction */ 1944 labpc_serial_out(dev, read_instruction, write_length); 1945 /* send 8 bit address to read from */ 1946 labpc_serial_out(dev, address, write_length); 1947 /* read result */ 1948 value = labpc_serial_in(dev); 1949 1950 /* disable read/write to eeprom */ 1951 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1952 udelay(1); 1953 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1954 1955 return value; 1956} 1957 1958static unsigned int labpc_eeprom_write(struct comedi_device *dev, 1959 unsigned int address, unsigned int value) 1960{ 1961 const int write_enable_instruction = 0x6; 1962 const int write_instruction = 0x2; 1963 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1964 const int write_in_progress_bit = 0x1; 1965 const int timeout = 10000; 1966 int i; 1967 1968 /* make sure there isn't already a write in progress */ 1969 for (i = 0; i < timeout; i++) { 1970 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == 1971 0) 1972 break; 1973 } 1974 if (i == timeout) { 1975 comedi_error(dev, "eeprom write timed out"); 1976 return -ETIME; 1977 } 1978 /* update software copy of eeprom */ 1979 devpriv->eeprom_data[address] = value; 1980 1981 /* enable read/write to eeprom */ 1982 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1983 udelay(1); 1984 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1985 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1986 udelay(1); 1987 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1988 1989 /* send write_enable instruction */ 1990 labpc_serial_out(dev, write_enable_instruction, write_length); 1991 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1992 udelay(1); 1993 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1994 1995 /* send write instruction */ 1996 devpriv->command5_bits |= EEPROM_EN_BIT; 1997 udelay(1); 1998 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1999 labpc_serial_out(dev, write_instruction, write_length); 2000 /* send 8 bit address to write to */ 2001 labpc_serial_out(dev, address, write_length); 2002 /* write value */ 2003 labpc_serial_out(dev, value, write_length); 2004 devpriv->command5_bits &= ~EEPROM_EN_BIT; 2005 udelay(1); 2006 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2007 2008 /* disable read/write to eeprom */ 2009 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 2010 udelay(1); 2011 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2012 2013 return 0; 2014} 2015 2016static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) 2017{ 2018 unsigned int value; 2019 const int read_status_instruction = 0x5; 2020 const int write_length = 8; /* 8 bit write lengths to eeprom */ 2021 2022 /* enable read/write to eeprom */ 2023 devpriv->command5_bits &= ~EEPROM_EN_BIT; 2024 udelay(1); 2025 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2026 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 2027 udelay(1); 2028 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2029 2030 /* send read status instruction */ 2031 labpc_serial_out(dev, read_status_instruction, write_length); 2032 /* read result */ 2033 value = labpc_serial_in(dev); 2034 2035 /* disable read/write to eeprom */ 2036 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 2037 udelay(1); 2038 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2039 2040 return value; 2041} 2042 2043/* writes to 8 bit calibration dacs */ 2044static void write_caldac(struct comedi_device *dev, unsigned int channel, 2045 unsigned int value) 2046{ 2047 if (value == devpriv->caldac[channel]) 2048 return; 2049 devpriv->caldac[channel] = value; 2050 2051 /* clear caldac load bit and make sure we don't write to eeprom */ 2052 devpriv->command5_bits &= 2053 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 2054 udelay(1); 2055 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2056 2057 /* write 4 bit channel */ 2058 labpc_serial_out(dev, channel, 4); 2059 /* write 8 bit caldac value */ 2060 labpc_serial_out(dev, value, 8); 2061 2062 /* set and clear caldac bit to load caldac value */ 2063 devpriv->command5_bits |= CALDAC_LOAD_BIT; 2064 udelay(1); 2065 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2066 devpriv->command5_bits &= ~CALDAC_LOAD_BIT; 2067 udelay(1); 2068 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2069} 2070 2071#ifdef CONFIG_COMEDI_PCI 2072COMEDI_PCI_INITCLEANUP(driver_labpc, labpc_pci_table); 2073#else 2074COMEDI_INITCLEANUP(driver_labpc); 2075#endif 2076 2077EXPORT_SYMBOL_GPL(labpc_common_attach); 2078EXPORT_SYMBOL_GPL(labpc_common_detach); 2079EXPORT_SYMBOL_GPL(range_labpc_1200_ai); 2080EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); 2081EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar); 2082