ni_mio_common.c revision 25436dc9d84f1be60ff549c9ab712bba2835f284
1/* 2 comedi/drivers/ni_mio_common.c 3 Hardware driver for DAQ-STC based boards 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> 7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 23*/ 24 25/* 26 This file is meant to be included by another file, e.g., 27 ni_atmio.c or ni_pcimio.c. 28 29 Interrupt support originally added by Truxton Fulton 30 <trux@truxton.com> 31 32 References (from ftp://ftp.natinst.com/support/manuals): 33 34 340747b.pdf AT-MIO E series Register Level Programmer Manual 35 341079b.pdf PCI E Series RLPM 36 340934b.pdf DAQ-STC reference manual 37 67xx and 611x registers (from http://www.ni.com/pdf/daq/us) 38 release_ni611x.pdf 39 release_ni67xx.pdf 40 Other possibly relevant info: 41 42 320517c.pdf User manual (obsolete) 43 320517f.pdf User manual (new) 44 320889a.pdf delete 45 320906c.pdf maximum signal ratings 46 321066a.pdf about 16x 47 321791a.pdf discontinuation of at-mio-16e-10 rev. c 48 321808a.pdf about at-mio-16e-10 rev P 49 321837a.pdf discontinuation of at-mio-16de-10 rev d 50 321838a.pdf about at-mio-16de-10 rev N 51 52 ISSUES: 53 54 - the interrupt routine needs to be cleaned up 55 56 2006-02-07: S-Series PCI-6143: Support has been added but is not 57 fully tested as yet. Terry Barnaby, BEAM Ltd. 58*/ 59 60/* #define DEBUG_INTERRUPT */ 61/* #define DEBUG_STATUS_A */ 62/* #define DEBUG_STATUS_B */ 63 64#include <linux/interrupt.h> 65#include "8255.h" 66#include "mite.h" 67#include "comedi_fc.h" 68 69#ifndef MDPRINTK 70#define MDPRINTK(format, args...) 71#endif 72 73/* A timeout count */ 74#define NI_TIMEOUT 1000 75static const unsigned old_RTSI_clock_channel = 7; 76 77/* Note: this table must match the ai_gain_* definitions */ 78static const short ni_gainlkup[][16] = { 79 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7, 80 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107}, 81 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107}, 82 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7, 83 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107}, 84 [ai_gain_4] = {0, 1, 4, 7}, 85 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002, 86 0x003, 0x004, 0x005, 0x006}, 87 [ai_gain_622x] = {0, 1, 4, 5}, 88 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7}, 89 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 90}; 91 92static const struct comedi_lrange range_ni_E_ai = { 16, { 93 RANGE(-10, 10), 94 RANGE(-5, 5), 95 RANGE(-2.5, 2.5), 96 RANGE(-1, 1), 97 RANGE(-0.5, 0.5), 98 RANGE(-0.25, 0.25), 99 RANGE(-0.1, 0.1), 100 RANGE(-0.05, 0.05), 101 RANGE(0, 20), 102 RANGE(0, 10), 103 RANGE(0, 5), 104 RANGE(0, 2), 105 RANGE(0, 1), 106 RANGE(0, 0.5), 107 RANGE(0, 0.2), 108 RANGE(0, 0.1), 109 } 110}; 111static const struct comedi_lrange range_ni_E_ai_limited = { 8, { 112 RANGE(-10, 10), 113 RANGE(-5, 5), 114 RANGE(-1, 1), 115 RANGE(-0.1, 0.1), 116 RANGE(0, 10), 117 RANGE(0, 5), 118 RANGE(0, 1), 119 RANGE(0, 0.1), 120 } 121}; 122static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, { 123 RANGE(-10, 10), 124 RANGE(-5, 5), 125 RANGE(-2, 2), 126 RANGE(-1, 1), 127 RANGE(-0.5, 0.5), 128 RANGE(-0.2, 0.2), 129 RANGE(-0.1, 0.1), 130 RANGE(0, 10), 131 RANGE(0, 5), 132 RANGE(0, 2), 133 RANGE(0, 1), 134 RANGE(0, 0.5), 135 RANGE(0, 0.2), 136 RANGE(0, 0.1), 137 } 138}; 139static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, { 140 RANGE(-10, 10), 141 RANGE(-5, 5), 142 RANGE(-0.5, 0.5), 143 RANGE(-0.05, 0.05), 144 } 145}; 146static const struct comedi_lrange range_ni_E_ai_611x = { 8, { 147 RANGE(-50, 50), 148 RANGE(-20, 20), 149 RANGE(-10, 10), 150 RANGE(-5, 5), 151 RANGE(-2, 2), 152 RANGE(-1, 1), 153 RANGE(-0.5, 0.5), 154 RANGE(-0.2, 0.2), 155 } 156}; 157static const struct comedi_lrange range_ni_M_ai_622x = { 4, { 158 RANGE(-10, 10), 159 RANGE(-5, 5), 160 RANGE(-1, 1), 161 RANGE(-0.2, 0.2), 162 } 163}; 164static const struct comedi_lrange range_ni_M_ai_628x = { 7, { 165 RANGE(-10, 10), 166 RANGE(-5, 5), 167 RANGE(-2, 2), 168 RANGE(-1, 1), 169 RANGE(-0.5, 0.5), 170 RANGE(-0.2, 0.2), 171 RANGE(-0.1, 0.1), 172 } 173}; 174static const struct comedi_lrange range_ni_S_ai_6143 = { 1, { 175 RANGE(-5, +5), 176 } 177}; 178static const struct comedi_lrange range_ni_E_ao_ext = { 4, { 179 RANGE(-10, 10), 180 RANGE(0, 10), 181 RANGE_ext(-1, 1), 182 RANGE_ext(0, 1), 183 } 184}; 185 186static const struct comedi_lrange *const ni_range_lkup[] = { 187 [ai_gain_16] = &range_ni_E_ai, 188 [ai_gain_8] = &range_ni_E_ai_limited, 189 [ai_gain_14] = &range_ni_E_ai_limited14, 190 [ai_gain_4] = &range_ni_E_ai_bipolar4, 191 [ai_gain_611x] = &range_ni_E_ai_611x, 192 [ai_gain_622x] = &range_ni_M_ai_622x, 193 [ai_gain_628x] = &range_ni_M_ai_628x, 194 [ai_gain_6143] = &range_ni_S_ai_6143 195}; 196 197static int ni_dio_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 198 struct comedi_insn *insn, unsigned int *data); 199static int ni_dio_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, 200 struct comedi_insn *insn, unsigned int *data); 201static int ni_cdio_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 202 struct comedi_cmd *cmd); 203static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 204static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 205static void handle_cdio_interrupt(struct comedi_device *dev); 206static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 207 unsigned int trignum); 208 209static int ni_serial_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 210 struct comedi_insn *insn, unsigned int *data); 211static int ni_serial_hw_readwrite8(struct comedi_device *dev, struct comedi_subdevice *s, 212 unsigned char data_out, unsigned char *data_in); 213static int ni_serial_sw_readwrite8(struct comedi_device *dev, struct comedi_subdevice *s, 214 unsigned char data_out, unsigned char *data_in); 215 216static int ni_calib_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 217 struct comedi_insn *insn, unsigned int *data); 218static int ni_calib_insn_write(struct comedi_device *dev, struct comedi_subdevice *s, 219 struct comedi_insn *insn, unsigned int *data); 220 221static int ni_eeprom_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 222 struct comedi_insn *insn, unsigned int *data); 223static int ni_m_series_eeprom_insn_read(struct comedi_device *dev, 224 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data); 225 226static int ni_pfi_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, 227 struct comedi_insn *insn, unsigned int *data); 228static int ni_pfi_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 229 struct comedi_insn *insn, unsigned int *data); 230static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan); 231 232static void ni_rtsi_init(struct comedi_device *dev); 233static int ni_rtsi_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, 234 struct comedi_insn *insn, unsigned int *data); 235static int ni_rtsi_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 236 struct comedi_insn *insn, unsigned int *data); 237 238static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s); 239static int ni_read_eeprom(struct comedi_device *dev, int addr); 240 241#ifdef DEBUG_STATUS_A 242static void ni_mio_print_status_a(int status); 243#else 244#define ni_mio_print_status_a(a) 245#endif 246#ifdef DEBUG_STATUS_B 247static void ni_mio_print_status_b(int status); 248#else 249#define ni_mio_print_status_b(a) 250#endif 251 252static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s); 253#ifndef PCIDMA 254static void ni_handle_fifo_half_full(struct comedi_device *dev); 255static int ni_ao_fifo_half_empty(struct comedi_device *dev, struct comedi_subdevice *s); 256#endif 257static void ni_handle_fifo_dregs(struct comedi_device *dev); 258static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 259 unsigned int trignum); 260static void ni_load_channelgain_list(struct comedi_device *dev, unsigned int n_chan, 261 unsigned int *list); 262static void shutdown_ai_command(struct comedi_device *dev); 263 264static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 265 unsigned int trignum); 266 267static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s); 268 269static int ni_8255_callback(int dir, int port, int data, unsigned long arg); 270 271static int ni_gpct_insn_write(struct comedi_device *dev, struct comedi_subdevice *s, 272 struct comedi_insn *insn, unsigned int *data); 273static int ni_gpct_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 274 struct comedi_insn *insn, unsigned int *data); 275static int ni_gpct_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 276 struct comedi_insn *insn, unsigned int *data); 277static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 278static int ni_gpct_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 279 struct comedi_cmd *cmd); 280static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 281static void handle_gpct_interrupt(struct comedi_device *dev, 282 unsigned short counter_index); 283 284static int init_cs5529(struct comedi_device *dev); 285static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data); 286static int cs5529_ai_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 287 struct comedi_insn *insn, unsigned int *data); 288#ifdef NI_CS5529_DEBUG 289static unsigned int cs5529_config_read(struct comedi_device *dev, 290 unsigned int reg_select_bits); 291#endif 292static void cs5529_config_write(struct comedi_device *dev, unsigned int value, 293 unsigned int reg_select_bits); 294 295static int ni_m_series_pwm_config(struct comedi_device *dev, struct comedi_subdevice *s, 296 struct comedi_insn *insn, unsigned int *data); 297static int ni_6143_pwm_config(struct comedi_device *dev, struct comedi_subdevice *s, 298 struct comedi_insn *insn, unsigned int *data); 299 300static int ni_set_master_clock(struct comedi_device *dev, unsigned source, 301 unsigned period_ns); 302static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status); 303static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status); 304 305enum aimodes { 306 AIMODE_NONE = 0, 307 AIMODE_HALF_FULL = 1, 308 AIMODE_SCAN = 2, 309 AIMODE_SAMPLE = 3, 310}; 311 312enum ni_common_subdevices { 313 NI_AI_SUBDEV, 314 NI_AO_SUBDEV, 315 NI_DIO_SUBDEV, 316 NI_8255_DIO_SUBDEV, 317 NI_UNUSED_SUBDEV, 318 NI_CALIBRATION_SUBDEV, 319 NI_EEPROM_SUBDEV, 320 NI_PFI_DIO_SUBDEV, 321 NI_CS5529_CALIBRATION_SUBDEV, 322 NI_SERIAL_SUBDEV, 323 NI_RTSI_SUBDEV, 324 NI_GPCT0_SUBDEV, 325 NI_GPCT1_SUBDEV, 326 NI_FREQ_OUT_SUBDEV, 327 NI_NUM_SUBDEVICES 328}; 329static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index) 330{ 331 switch (counter_index) { 332 case 0: 333 return NI_GPCT0_SUBDEV; 334 break; 335 case 1: 336 return NI_GPCT1_SUBDEV; 337 break; 338 default: 339 break; 340 } 341 BUG(); 342 return NI_GPCT0_SUBDEV; 343} 344 345enum timebase_nanoseconds { 346 TIMEBASE_1_NS = 50, 347 TIMEBASE_2_NS = 10000 348}; 349 350#define SERIAL_DISABLED 0 351#define SERIAL_600NS 600 352#define SERIAL_1_2US 1200 353#define SERIAL_10US 10000 354 355static const int num_adc_stages_611x = 3; 356 357static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, 358 unsigned ai_mite_status); 359static void handle_b_interrupt(struct comedi_device *dev, unsigned short status, 360 unsigned ao_mite_status); 361static void get_last_sample_611x(struct comedi_device *dev); 362static void get_last_sample_6143(struct comedi_device *dev); 363 364static inline void ni_set_bitfield(struct comedi_device *dev, int reg, 365 unsigned bit_mask, unsigned bit_values) 366{ 367 unsigned long flags; 368 369 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); 370 switch (reg) { 371 case Interrupt_A_Enable_Register: 372 devpriv->int_a_enable_reg &= ~bit_mask; 373 devpriv->int_a_enable_reg |= bit_values & bit_mask; 374 devpriv->stc_writew(dev, devpriv->int_a_enable_reg, 375 Interrupt_A_Enable_Register); 376 break; 377 case Interrupt_B_Enable_Register: 378 devpriv->int_b_enable_reg &= ~bit_mask; 379 devpriv->int_b_enable_reg |= bit_values & bit_mask; 380 devpriv->stc_writew(dev, devpriv->int_b_enable_reg, 381 Interrupt_B_Enable_Register); 382 break; 383 case IO_Bidirection_Pin_Register: 384 devpriv->io_bidirection_pin_reg &= ~bit_mask; 385 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask; 386 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg, 387 IO_Bidirection_Pin_Register); 388 break; 389 case AI_AO_Select: 390 devpriv->ai_ao_select_reg &= ~bit_mask; 391 devpriv->ai_ao_select_reg |= bit_values & bit_mask; 392 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select); 393 break; 394 case G0_G1_Select: 395 devpriv->g0_g1_select_reg &= ~bit_mask; 396 devpriv->g0_g1_select_reg |= bit_values & bit_mask; 397 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select); 398 break; 399 default: 400 printk("Warning %s() called with invalid register\n", 401 __func__); 402 printk("reg is %d\n", reg); 403 break; 404 } 405 mmiowb(); 406 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); 407} 408 409#ifdef PCIDMA 410static int ni_ai_drain_dma(struct comedi_device *dev); 411 412/* DMA channel setup */ 413 414/* negative channel means no channel */ 415static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel) 416{ 417 unsigned bitfield; 418 419 if (channel >= 0) { 420 bitfield = 421 (ni_stc_dma_channel_select_bitfield(channel) << 422 AI_DMA_Select_Shift) & AI_DMA_Select_Mask; 423 } else { 424 bitfield = 0; 425 } 426 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield); 427} 428 429/* negative channel means no channel */ 430static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel) 431{ 432 unsigned bitfield; 433 434 if (channel >= 0) { 435 bitfield = 436 (ni_stc_dma_channel_select_bitfield(channel) << 437 AO_DMA_Select_Shift) & AO_DMA_Select_Mask; 438 } else { 439 bitfield = 0; 440 } 441 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield); 442} 443 444/* negative mite_channel means no channel */ 445static inline void ni_set_gpct_dma_channel(struct comedi_device *dev, 446 unsigned gpct_index, int mite_channel) 447{ 448 unsigned bitfield; 449 450 if (mite_channel >= 0) { 451 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel); 452 } else { 453 bitfield = 0; 454 } 455 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index), 456 bitfield); 457} 458 459/* negative mite_channel means no channel */ 460static inline void ni_set_cdo_dma_channel(struct comedi_device *dev, int mite_channel) 461{ 462 unsigned long flags; 463 464 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); 465 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask; 466 if (mite_channel >= 0) { 467 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits, 468 under the assumption the cdio dma selection works just like ai/ao/gpct. 469 Definitely works for dma channels 0 and 1. */ 470 devpriv->cdio_dma_select_reg |= 471 (ni_stc_dma_channel_select_bitfield(mite_channel) << 472 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask; 473 } 474 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select); 475 mmiowb(); 476 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); 477} 478 479static int ni_request_ai_mite_channel(struct comedi_device *dev) 480{ 481 unsigned long flags; 482 483 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 484 BUG_ON(devpriv->ai_mite_chan); 485 devpriv->ai_mite_chan = 486 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); 487 if (devpriv->ai_mite_chan == NULL) { 488 spin_unlock_irqrestore(&devpriv->mite_channel_lock, 489 flags); 490 comedi_error(dev, 491 "failed to reserve mite dma channel for analog input."); 492 return -EBUSY; 493 } 494 devpriv->ai_mite_chan->dir = COMEDI_INPUT; 495 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel); 496 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 497 return 0; 498} 499 500static int ni_request_ao_mite_channel(struct comedi_device *dev) 501{ 502 unsigned long flags; 503 504 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 505 BUG_ON(devpriv->ao_mite_chan); 506 devpriv->ao_mite_chan = 507 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); 508 if (devpriv->ao_mite_chan == NULL) { 509 spin_unlock_irqrestore(&devpriv->mite_channel_lock, 510 flags); 511 comedi_error(dev, 512 "failed to reserve mite dma channel for analog outut."); 513 return -EBUSY; 514 } 515 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT; 516 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel); 517 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 518 return 0; 519} 520 521static int ni_request_gpct_mite_channel(struct comedi_device *dev, 522 unsigned gpct_index, enum comedi_io_direction direction) 523{ 524 unsigned long flags; 525 struct mite_channel *mite_chan; 526 527 BUG_ON(gpct_index >= NUM_GPCT); 528 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 529 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan); 530 mite_chan = 531 mite_request_channel(devpriv->mite, 532 devpriv->gpct_mite_ring[gpct_index]); 533 if (mite_chan == NULL) { 534 spin_unlock_irqrestore(&devpriv->mite_channel_lock, 535 flags); 536 comedi_error(dev, 537 "failed to reserve mite dma channel for counter."); 538 return -EBUSY; 539 } 540 mite_chan->dir = direction; 541 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index], 542 mite_chan); 543 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel); 544 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 545 return 0; 546} 547 548#endif /* PCIDMA */ 549 550static int ni_request_cdo_mite_channel(struct comedi_device *dev) 551{ 552#ifdef PCIDMA 553 unsigned long flags; 554 555 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 556 BUG_ON(devpriv->cdo_mite_chan); 557 devpriv->cdo_mite_chan = 558 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); 559 if (devpriv->cdo_mite_chan == NULL) { 560 spin_unlock_irqrestore(&devpriv->mite_channel_lock, 561 flags); 562 comedi_error(dev, 563 "failed to reserve mite dma channel for correlated digital outut."); 564 return -EBUSY; 565 } 566 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT; 567 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel); 568 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 569#endif /* PCIDMA */ 570 return 0; 571} 572 573static void ni_release_ai_mite_channel(struct comedi_device *dev) 574{ 575#ifdef PCIDMA 576 unsigned long flags; 577 578 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 579 if (devpriv->ai_mite_chan) { 580 ni_set_ai_dma_channel(dev, -1); 581 mite_release_channel(devpriv->ai_mite_chan); 582 devpriv->ai_mite_chan = NULL; 583 } 584 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 585#endif /* PCIDMA */ 586} 587 588static void ni_release_ao_mite_channel(struct comedi_device *dev) 589{ 590#ifdef PCIDMA 591 unsigned long flags; 592 593 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 594 if (devpriv->ao_mite_chan) { 595 ni_set_ao_dma_channel(dev, -1); 596 mite_release_channel(devpriv->ao_mite_chan); 597 devpriv->ao_mite_chan = NULL; 598 } 599 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 600#endif /* PCIDMA */ 601} 602 603void ni_release_gpct_mite_channel(struct comedi_device *dev, unsigned gpct_index) 604{ 605#ifdef PCIDMA 606 unsigned long flags; 607 608 BUG_ON(gpct_index >= NUM_GPCT); 609 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 610 if (devpriv->counter_dev->counters[gpct_index].mite_chan) { 611 struct mite_channel *mite_chan = 612 devpriv->counter_dev->counters[gpct_index].mite_chan; 613 614 ni_set_gpct_dma_channel(dev, gpct_index, -1); 615 ni_tio_set_mite_channel(&devpriv->counter_dev-> 616 counters[gpct_index], NULL); 617 mite_release_channel(mite_chan); 618 } 619 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 620#endif /* PCIDMA */ 621} 622 623static void ni_release_cdo_mite_channel(struct comedi_device *dev) 624{ 625#ifdef PCIDMA 626 unsigned long flags; 627 628 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 629 if (devpriv->cdo_mite_chan) { 630 ni_set_cdo_dma_channel(dev, -1); 631 mite_release_channel(devpriv->cdo_mite_chan); 632 devpriv->cdo_mite_chan = NULL; 633 } 634 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 635#endif /* PCIDMA */ 636} 637 638/* e-series boards use the second irq signals to generate dma requests for their counters */ 639#ifdef PCIDMA 640static void ni_e_series_enable_second_irq(struct comedi_device *dev, 641 unsigned gpct_index, short enable) 642{ 643 if (boardtype.reg_type & ni_reg_m_series_mask) 644 return; 645 switch (gpct_index) { 646 case 0: 647 if (enable) { 648 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable, 649 Second_IRQ_A_Enable_Register); 650 } else { 651 devpriv->stc_writew(dev, 0, 652 Second_IRQ_A_Enable_Register); 653 } 654 break; 655 case 1: 656 if (enable) { 657 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable, 658 Second_IRQ_B_Enable_Register); 659 } else { 660 devpriv->stc_writew(dev, 0, 661 Second_IRQ_B_Enable_Register); 662 } 663 break; 664 default: 665 BUG(); 666 break; 667 } 668} 669#endif /* PCIDMA */ 670 671static void ni_clear_ai_fifo(struct comedi_device *dev) 672{ 673 if (boardtype.reg_type == ni_reg_6143) { 674 /* Flush the 6143 data FIFO */ 675 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */ 676 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */ 677 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */ 678 } else { 679 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear); 680 if (boardtype.reg_type == ni_reg_625x) { 681 ni_writeb(0, M_Offset_Static_AI_Control(0)); 682 ni_writeb(1, M_Offset_Static_AI_Control(0)); 683#if 0 684 /* the NI example code does 3 convert pulses for 625x boards, 685 but that appears to be wrong in practice. */ 686 devpriv->stc_writew(dev, AI_CONVERT_Pulse, 687 AI_Command_1_Register); 688 devpriv->stc_writew(dev, AI_CONVERT_Pulse, 689 AI_Command_1_Register); 690 devpriv->stc_writew(dev, AI_CONVERT_Pulse, 691 AI_Command_1_Register); 692#endif 693 } 694 } 695} 696 697static void win_out2(struct comedi_device *dev, uint32_t data, int reg) 698{ 699 devpriv->stc_writew(dev, data >> 16, reg); 700 devpriv->stc_writew(dev, data & 0xffff, reg + 1); 701} 702 703static uint32_t win_in2(struct comedi_device *dev, int reg) 704{ 705 uint32_t bits; 706 bits = devpriv->stc_readw(dev, reg) << 16; 707 bits |= devpriv->stc_readw(dev, reg + 1); 708 return bits; 709} 710 711#define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr) 712static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data, int addr) 713{ 714 unsigned long flags; 715 716 spin_lock_irqsave(&devpriv->window_lock, flags); 717 ni_writew(addr, AO_Window_Address_611x); 718 ni_writew(data, AO_Window_Data_611x); 719 spin_unlock_irqrestore(&devpriv->window_lock, flags); 720} 721 722static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data, int addr) 723{ 724 unsigned long flags; 725 726 spin_lock_irqsave(&devpriv->window_lock, flags); 727 ni_writew(addr, AO_Window_Address_611x); 728 ni_writel(data, AO_Window_Data_611x); 729 spin_unlock_irqrestore(&devpriv->window_lock, flags); 730} 731 732static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr) 733{ 734 unsigned long flags; 735 unsigned short data; 736 737 spin_lock_irqsave(&devpriv->window_lock, flags); 738 ni_writew(addr, AO_Window_Address_611x); 739 data = ni_readw(AO_Window_Data_611x); 740 spin_unlock_irqrestore(&devpriv->window_lock, flags); 741 return data; 742} 743 744/* ni_set_bits( ) allows different parts of the ni_mio_common driver to 745* share registers (such as Interrupt_A_Register) without interfering with 746* each other. 747* 748* NOTE: the switch/case statements are optimized out for a constant argument 749* so this is actually quite fast--- If you must wrap another function around this 750* make it inline to avoid a large speed penalty. 751* 752* value should only be 1 or 0. 753*/ 754static inline void ni_set_bits(struct comedi_device *dev, int reg, unsigned bits, 755 unsigned value) 756{ 757 unsigned bit_values; 758 759 if (value) 760 bit_values = bits; 761 else 762 bit_values = 0; 763 ni_set_bitfield(dev, reg, bits, bit_values); 764} 765 766static irqreturn_t ni_E_interrupt(int irq, void *d) 767{ 768 struct comedi_device *dev = d; 769 unsigned short a_status; 770 unsigned short b_status; 771 unsigned int ai_mite_status = 0; 772 unsigned int ao_mite_status = 0; 773 unsigned long flags; 774#ifdef PCIDMA 775 struct mite_struct *mite = devpriv->mite; 776#endif 777 778 if (dev->attached == 0) 779 return IRQ_NONE; 780 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */ 781 782 /* lock to avoid race with comedi_poll */ 783 spin_lock_irqsave(&dev->spinlock, flags); 784 a_status = devpriv->stc_readw(dev, AI_Status_1_Register); 785 b_status = devpriv->stc_readw(dev, AO_Status_1_Register); 786#ifdef PCIDMA 787 if (mite) { 788 unsigned long flags_too; 789 790 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too); 791 if (devpriv->ai_mite_chan) { 792 ai_mite_status = mite_get_status(devpriv->ai_mite_chan); 793 if (ai_mite_status & CHSR_LINKC) 794 writel(CHOR_CLRLC, 795 devpriv->mite->mite_io_addr + 796 MITE_CHOR(devpriv->ai_mite_chan-> 797 channel)); 798 } 799 if (devpriv->ao_mite_chan) { 800 ao_mite_status = mite_get_status(devpriv->ao_mite_chan); 801 if (ao_mite_status & CHSR_LINKC) 802 writel(CHOR_CLRLC, 803 mite->mite_io_addr + 804 MITE_CHOR(devpriv->ao_mite_chan-> 805 channel)); 806 } 807 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too); 808 } 809#endif 810 ack_a_interrupt(dev, a_status); 811 ack_b_interrupt(dev, b_status); 812 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT)) 813 handle_a_interrupt(dev, a_status, ai_mite_status); 814 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT)) 815 handle_b_interrupt(dev, b_status, ao_mite_status); 816 handle_gpct_interrupt(dev, 0); 817 handle_gpct_interrupt(dev, 1); 818 handle_cdio_interrupt(dev); 819 820 spin_unlock_irqrestore(&dev->spinlock, flags); 821 return IRQ_HANDLED; 822} 823 824#ifdef PCIDMA 825static void ni_sync_ai_dma(struct comedi_device *dev) 826{ 827 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 828 unsigned long flags; 829 830 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 831 if (devpriv->ai_mite_chan) 832 mite_sync_input_dma(devpriv->ai_mite_chan, s->async); 833 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 834} 835 836static void mite_handle_b_linkc(struct mite_struct *mite, struct comedi_device * dev) 837{ 838 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV; 839 unsigned long flags; 840 841 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 842 if (devpriv->ao_mite_chan) { 843 mite_sync_output_dma(devpriv->ao_mite_chan, s->async); 844 } 845 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 846} 847 848static int ni_ao_wait_for_dma_load(struct comedi_device *dev) 849{ 850 static const int timeout = 10000; 851 int i; 852 for (i = 0; i < timeout; i++) { 853 unsigned short b_status; 854 855 b_status = devpriv->stc_readw(dev, AO_Status_1_Register); 856 if (b_status & AO_FIFO_Half_Full_St) 857 break; 858 /* if we poll too often, the pci bus activity seems 859 to slow the dma transfer down */ 860 udelay(10); 861 } 862 if (i == timeout) { 863 comedi_error(dev, "timed out waiting for dma load"); 864 return -EPIPE; 865 } 866 return 0; 867} 868 869#endif /* PCIDMA */ 870static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s) 871{ 872 if (devpriv->aimode == AIMODE_SCAN) { 873#ifdef PCIDMA 874 static const int timeout = 10; 875 int i; 876 877 for (i = 0; i < timeout; i++) { 878 ni_sync_ai_dma(dev); 879 if ((s->async->events & COMEDI_CB_EOS)) 880 break; 881 udelay(1); 882 } 883#else 884 ni_handle_fifo_dregs(dev); 885 s->async->events |= COMEDI_CB_EOS; 886#endif 887 } 888 /* handle special case of single scan using AI_End_On_End_Of_Scan */ 889 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) { 890 shutdown_ai_command(dev); 891 } 892} 893 894static void shutdown_ai_command(struct comedi_device *dev) 895{ 896 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 897 898#ifdef PCIDMA 899 ni_ai_drain_dma(dev); 900#endif 901 ni_handle_fifo_dregs(dev); 902 get_last_sample_611x(dev); 903 get_last_sample_6143(dev); 904 905 s->async->events |= COMEDI_CB_EOA; 906} 907 908static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s) 909{ 910 if (s->async-> 911 events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW | COMEDI_CB_EOA)) 912 { 913 switch (s - dev->subdevices) { 914 case NI_AI_SUBDEV: 915 ni_ai_reset(dev, s); 916 break; 917 case NI_AO_SUBDEV: 918 ni_ao_reset(dev, s); 919 break; 920 case NI_GPCT0_SUBDEV: 921 case NI_GPCT1_SUBDEV: 922 ni_gpct_cancel(dev, s); 923 break; 924 case NI_DIO_SUBDEV: 925 ni_cdio_cancel(dev, s); 926 break; 927 default: 928 break; 929 } 930 } 931 comedi_event(dev, s); 932} 933 934static void handle_gpct_interrupt(struct comedi_device *dev, 935 unsigned short counter_index) 936{ 937#ifdef PCIDMA 938 struct comedi_subdevice *s = dev->subdevices + NI_GPCT_SUBDEV(counter_index); 939 940 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index], 941 s); 942 if (s->async->events) 943 ni_event(dev, s); 944#endif 945} 946 947static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status) 948{ 949 unsigned short ack = 0; 950 951 if (a_status & AI_SC_TC_St) { 952 ack |= AI_SC_TC_Interrupt_Ack; 953 } 954 if (a_status & AI_START1_St) { 955 ack |= AI_START1_Interrupt_Ack; 956 } 957 if (a_status & AI_START_St) { 958 ack |= AI_START_Interrupt_Ack; 959 } 960 if (a_status & AI_STOP_St) { 961 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */ 962 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ; 963 } 964 if (ack) 965 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register); 966} 967 968static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, 969 unsigned ai_mite_status) 970{ 971 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 972 973 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */ 974 if (s->type == COMEDI_SUBD_UNUSED) 975 return; 976 977#ifdef DEBUG_INTERRUPT 978 printk 979 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n", 980 status, ai_mite_status); 981 ni_mio_print_status_a(status); 982#endif 983#ifdef PCIDMA 984 if (ai_mite_status & CHSR_LINKC) { 985 ni_sync_ai_dma(dev); 986 } 987 988 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | 989 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | 990 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { 991 printk 992 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n", 993 ai_mite_status); 994 /* mite_print_chsr(ai_mite_status); */ 995 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 996 /* disable_irq(dev->irq); */ 997 } 998#endif 999 1000 /* test for all uncommon interrupt events at the same time */ 1001 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St | 1002 AI_SC_TC_St | AI_START1_St)) { 1003 if (status == 0xffff) { 1004 printk 1005 ("ni_mio_common: a_status=0xffff. Card removed?\n"); 1006 /* we probably aren't even running a command now, 1007 * so it's a good idea to be careful. */ 1008 if (comedi_get_subdevice_runflags(s) & SRF_RUNNING) { 1009 s->async->events |= 1010 COMEDI_CB_ERROR | COMEDI_CB_EOA; 1011 ni_event(dev, s); 1012 } 1013 return; 1014 } 1015 if (status & (AI_Overrun_St | AI_Overflow_St | 1016 AI_SC_TC_Error_St)) { 1017 printk("ni_mio_common: ai error a_status=%04x\n", 1018 status); 1019 ni_mio_print_status_a(status); 1020 1021 shutdown_ai_command(dev); 1022 1023 s->async->events |= COMEDI_CB_ERROR; 1024 if (status & (AI_Overrun_St | AI_Overflow_St)) 1025 s->async->events |= COMEDI_CB_OVERFLOW; 1026 1027 ni_event(dev, s); 1028 1029 return; 1030 } 1031 if (status & AI_SC_TC_St) { 1032#ifdef DEBUG_INTERRUPT 1033 printk("ni_mio_common: SC_TC interrupt\n"); 1034#endif 1035 if (!devpriv->ai_continuous) { 1036 shutdown_ai_command(dev); 1037 } 1038 } 1039 } 1040#ifndef PCIDMA 1041 if (status & AI_FIFO_Half_Full_St) { 1042 int i; 1043 static const int timeout = 10; 1044 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we 1045 *fail to get the fifo less than half full, so loop to be sure.*/ 1046 for (i = 0; i < timeout; ++i) { 1047 ni_handle_fifo_half_full(dev); 1048 if ((devpriv->stc_readw(dev, 1049 AI_Status_1_Register) & 1050 AI_FIFO_Half_Full_St) == 0) 1051 break; 1052 } 1053 } 1054#endif /* !PCIDMA */ 1055 1056 if ((status & AI_STOP_St)) { 1057 ni_handle_eos(dev, s); 1058 } 1059 1060 ni_event(dev, s); 1061 1062#ifdef DEBUG_INTERRUPT 1063 status = devpriv->stc_readw(dev, AI_Status_1_Register); 1064 if (status & Interrupt_A_St) { 1065 printk 1066 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n", 1067 status); 1068 } 1069#endif 1070} 1071 1072static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status) 1073{ 1074 unsigned short ack = 0; 1075 if (b_status & AO_BC_TC_St) { 1076 ack |= AO_BC_TC_Interrupt_Ack; 1077 } 1078 if (b_status & AO_Overrun_St) { 1079 ack |= AO_Error_Interrupt_Ack; 1080 } 1081 if (b_status & AO_START_St) { 1082 ack |= AO_START_Interrupt_Ack; 1083 } 1084 if (b_status & AO_START1_St) { 1085 ack |= AO_START1_Interrupt_Ack; 1086 } 1087 if (b_status & AO_UC_TC_St) { 1088 ack |= AO_UC_TC_Interrupt_Ack; 1089 } 1090 if (b_status & AO_UI2_TC_St) { 1091 ack |= AO_UI2_TC_Interrupt_Ack; 1092 } 1093 if (b_status & AO_UPDATE_St) { 1094 ack |= AO_UPDATE_Interrupt_Ack; 1095 } 1096 if (ack) 1097 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register); 1098} 1099 1100static void handle_b_interrupt(struct comedi_device *dev, unsigned short b_status, 1101 unsigned ao_mite_status) 1102{ 1103 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV; 1104 /* unsigned short ack=0; */ 1105#ifdef DEBUG_INTERRUPT 1106 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n", 1107 b_status, ao_mite_status); 1108 ni_mio_print_status_b(b_status); 1109#endif 1110 1111#ifdef PCIDMA 1112 /* Currently, mite.c requires us to handle LINKC */ 1113 if (ao_mite_status & CHSR_LINKC) { 1114 mite_handle_b_linkc(devpriv->mite, dev); 1115 } 1116 1117 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | 1118 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | 1119 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { 1120 printk 1121 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n", 1122 ao_mite_status); 1123 /* mite_print_chsr(ao_mite_status); */ 1124 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 1125 } 1126#endif 1127 1128 if (b_status == 0xffff) 1129 return; 1130 if (b_status & AO_Overrun_St) { 1131 printk 1132 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n", 1133 b_status, devpriv->stc_readw(dev, 1134 AO_Status_2_Register)); 1135 s->async->events |= COMEDI_CB_OVERFLOW; 1136 } 1137 1138 if (b_status & AO_BC_TC_St) { 1139 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n", b_status, devpriv->stc_readw(dev, AO_Status_2_Register)); 1140 s->async->events |= COMEDI_CB_EOA; 1141 } 1142#ifndef PCIDMA 1143 if (b_status & AO_FIFO_Request_St) { 1144 int ret; 1145 1146 ret = ni_ao_fifo_half_empty(dev, s); 1147 if (!ret) { 1148 printk("ni_mio_common: AO buffer underrun\n"); 1149 ni_set_bits(dev, Interrupt_B_Enable_Register, 1150 AO_FIFO_Interrupt_Enable | 1151 AO_Error_Interrupt_Enable, 0); 1152 s->async->events |= COMEDI_CB_OVERFLOW; 1153 } 1154 } 1155#endif 1156 1157 ni_event(dev, s); 1158} 1159 1160#ifdef DEBUG_STATUS_A 1161static const char *const status_a_strings[] = { 1162 "passthru0", "fifo", "G0_gate", "G0_TC", 1163 "stop", "start", "sc_tc", "start1", 1164 "start2", "sc_tc_error", "overflow", "overrun", 1165 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a" 1166}; 1167 1168static void ni_mio_print_status_a(int status) 1169{ 1170 int i; 1171 1172 printk("A status:"); 1173 for (i = 15; i >= 0; i--) { 1174 if (status & (1 << i)) { 1175 printk(" %s", status_a_strings[i]); 1176 } 1177 } 1178 printk("\n"); 1179} 1180#endif 1181 1182#ifdef DEBUG_STATUS_B 1183static const char *const status_b_strings[] = { 1184 "passthru1", "fifo", "G1_gate", "G1_TC", 1185 "UI2_TC", "UPDATE", "UC_TC", "BC_TC", 1186 "start1", "overrun", "start", "bc_tc_error", 1187 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b" 1188}; 1189 1190static void ni_mio_print_status_b(int status) 1191{ 1192 int i; 1193 1194 printk("B status:"); 1195 for (i = 15; i >= 0; i--) { 1196 if (status & (1 << i)) { 1197 printk(" %s", status_b_strings[i]); 1198 } 1199 } 1200 printk("\n"); 1201} 1202#endif 1203 1204#ifndef PCIDMA 1205 1206static void ni_ao_fifo_load(struct comedi_device *dev, struct comedi_subdevice *s, int n) 1207{ 1208 struct comedi_async *async = s->async; 1209 struct comedi_cmd *cmd = &async->cmd; 1210 int chan; 1211 int i; 1212 short d; 1213 u32 packed_data; 1214 int range; 1215 int err = 1; 1216 1217 chan = async->cur_chan; 1218 for (i = 0; i < n; i++) { 1219 err &= comedi_buf_get(async, &d); 1220 if (err == 0) 1221 break; 1222 1223 range = CR_RANGE(cmd->chanlist[chan]); 1224 1225 if (boardtype.reg_type & ni_reg_6xxx_mask) { 1226 packed_data = d & 0xffff; 1227 /* 6711 only has 16 bit wide ao fifo */ 1228 if (boardtype.reg_type != ni_reg_6711) { 1229 err &= comedi_buf_get(async, &d); 1230 if (err == 0) 1231 break; 1232 chan++; 1233 i++; 1234 packed_data |= (d << 16) & 0xffff0000; 1235 } 1236 ni_writel(packed_data, DAC_FIFO_Data_611x); 1237 } else { 1238 ni_writew(d, DAC_FIFO_Data); 1239 } 1240 chan++; 1241 chan %= cmd->chanlist_len; 1242 } 1243 async->cur_chan = chan; 1244 if (err == 0) { 1245 async->events |= COMEDI_CB_OVERFLOW; 1246 } 1247} 1248 1249/* 1250 * There's a small problem if the FIFO gets really low and we 1251 * don't have the data to fill it. Basically, if after we fill 1252 * the FIFO with all the data available, the FIFO is _still_ 1253 * less than half full, we never clear the interrupt. If the 1254 * IRQ is in edge mode, we never get another interrupt, because 1255 * this one wasn't cleared. If in level mode, we get flooded 1256 * with interrupts that we can't fulfill, because nothing ever 1257 * gets put into the buffer. 1258 * 1259 * This kind of situation is recoverable, but it is easier to 1260 * just pretend we had a FIFO underrun, since there is a good 1261 * chance it will happen anyway. This is _not_ the case for 1262 * RT code, as RT code might purposely be running close to the 1263 * metal. Needs to be fixed eventually. 1264 */ 1265static int ni_ao_fifo_half_empty(struct comedi_device *dev, struct comedi_subdevice *s) 1266{ 1267 int n; 1268 1269 n = comedi_buf_read_n_available(s->async); 1270 if (n == 0) { 1271 s->async->events |= COMEDI_CB_OVERFLOW; 1272 return 0; 1273 } 1274 1275 n /= sizeof(short); 1276 if (n > boardtype.ao_fifo_depth / 2) 1277 n = boardtype.ao_fifo_depth / 2; 1278 1279 ni_ao_fifo_load(dev, s, n); 1280 1281 s->async->events |= COMEDI_CB_BLOCK; 1282 1283 return 1; 1284} 1285 1286static int ni_ao_prep_fifo(struct comedi_device *dev, struct comedi_subdevice *s) 1287{ 1288 int n; 1289 1290 /* reset fifo */ 1291 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear); 1292 if (boardtype.reg_type & ni_reg_6xxx_mask) 1293 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x); 1294 1295 /* load some data */ 1296 n = comedi_buf_read_n_available(s->async); 1297 if (n == 0) 1298 return 0; 1299 1300 n /= sizeof(short); 1301 if (n > boardtype.ao_fifo_depth) 1302 n = boardtype.ao_fifo_depth; 1303 1304 ni_ao_fifo_load(dev, s, n); 1305 1306 return n; 1307} 1308 1309static void ni_ai_fifo_read(struct comedi_device *dev, struct comedi_subdevice *s, int n) 1310{ 1311 struct comedi_async *async = s->async; 1312 int i; 1313 1314 if (boardtype.reg_type == ni_reg_611x) { 1315 short data[2]; 1316 u32 dl; 1317 1318 for (i = 0; i < n / 2; i++) { 1319 dl = ni_readl(ADC_FIFO_Data_611x); 1320 /* This may get the hi/lo data in the wrong order */ 1321 data[0] = (dl >> 16) & 0xffff; 1322 data[1] = dl & 0xffff; 1323 cfc_write_array_to_buffer(s, data, sizeof(data)); 1324 } 1325 /* Check if there's a single sample stuck in the FIFO */ 1326 if (n % 2) { 1327 dl = ni_readl(ADC_FIFO_Data_611x); 1328 data[0] = dl & 0xffff; 1329 cfc_write_to_buffer(s, data[0]); 1330 } 1331 } else if (boardtype.reg_type == ni_reg_6143) { 1332 short data[2]; 1333 u32 dl; 1334 1335 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */ 1336 for (i = 0; i < n / 2; i++) { 1337 dl = ni_readl(AIFIFO_Data_6143); 1338 1339 data[0] = (dl >> 16) & 0xffff; 1340 data[1] = dl & 0xffff; 1341 cfc_write_array_to_buffer(s, data, sizeof(data)); 1342 } 1343 if (n % 2) { 1344 /* Assume there is a single sample stuck in the FIFO */ 1345 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 1346 dl = ni_readl(AIFIFO_Data_6143); 1347 data[0] = (dl >> 16) & 0xffff; 1348 cfc_write_to_buffer(s, data[0]); 1349 } 1350 } else { 1351 if (n > sizeof(devpriv->ai_fifo_buffer) / 1352 sizeof(devpriv->ai_fifo_buffer[0])) { 1353 comedi_error(dev, "bug! ai_fifo_buffer too small"); 1354 async->events |= COMEDI_CB_ERROR; 1355 return; 1356 } 1357 for (i = 0; i < n; i++) { 1358 devpriv->ai_fifo_buffer[i] = 1359 ni_readw(ADC_FIFO_Data_Register); 1360 } 1361 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer, 1362 n * sizeof(devpriv->ai_fifo_buffer[0])); 1363 } 1364} 1365 1366static void ni_handle_fifo_half_full(struct comedi_device *dev) 1367{ 1368 int n; 1369 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 1370 1371 n = boardtype.ai_fifo_depth / 2; 1372 1373 ni_ai_fifo_read(dev, s, n); 1374} 1375#endif 1376 1377#ifdef PCIDMA 1378static int ni_ai_drain_dma(struct comedi_device *dev) 1379{ 1380 int i; 1381 static const int timeout = 10000; 1382 unsigned long flags; 1383 int retval = 0; 1384 1385 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1386 if (devpriv->ai_mite_chan) { 1387 for (i = 0; i < timeout; i++) { 1388 if ((devpriv->stc_readw(dev, 1389 AI_Status_1_Register) & 1390 AI_FIFO_Empty_St) 1391 && mite_bytes_in_transit(devpriv-> 1392 ai_mite_chan) == 0) 1393 break; 1394 udelay(5); 1395 } 1396 if (i == timeout) { 1397 printk 1398 ("ni_mio_common: wait for dma drain timed out\n"); 1399 printk 1400 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n", 1401 mite_bytes_in_transit(devpriv->ai_mite_chan), 1402 devpriv->stc_readw(dev, AI_Status_1_Register)); 1403 retval = -1; 1404 } 1405 } 1406 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1407 1408 ni_sync_ai_dma(dev); 1409 1410 return retval; 1411} 1412#endif 1413/* 1414 Empties the AI fifo 1415*/ 1416static void ni_handle_fifo_dregs(struct comedi_device *dev) 1417{ 1418 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 1419 short data[2]; 1420 u32 dl; 1421 short fifo_empty; 1422 int i; 1423 1424 if (boardtype.reg_type == ni_reg_611x) { 1425 while ((devpriv->stc_readw(dev, 1426 AI_Status_1_Register) & 1427 AI_FIFO_Empty_St) == 0) { 1428 dl = ni_readl(ADC_FIFO_Data_611x); 1429 1430 /* This may get the hi/lo data in the wrong order */ 1431 data[0] = (dl >> 16); 1432 data[1] = (dl & 0xffff); 1433 cfc_write_array_to_buffer(s, data, sizeof(data)); 1434 } 1435 } else if (boardtype.reg_type == ni_reg_6143) { 1436 i = 0; 1437 while (ni_readl(AIFIFO_Status_6143) & 0x04) { 1438 dl = ni_readl(AIFIFO_Data_6143); 1439 1440 /* This may get the hi/lo data in the wrong order */ 1441 data[0] = (dl >> 16); 1442 data[1] = (dl & 0xffff); 1443 cfc_write_array_to_buffer(s, data, sizeof(data)); 1444 i += 2; 1445 } 1446 /* Check if stranded sample is present */ 1447 if (ni_readl(AIFIFO_Status_6143) & 0x01) { 1448 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 1449 dl = ni_readl(AIFIFO_Data_6143); 1450 data[0] = (dl >> 16) & 0xffff; 1451 cfc_write_to_buffer(s, data[0]); 1452 } 1453 1454 } else { 1455 fifo_empty = 1456 devpriv->stc_readw(dev, 1457 AI_Status_1_Register) & AI_FIFO_Empty_St; 1458 while (fifo_empty == 0) { 1459 for (i = 0; 1460 i < 1461 sizeof(devpriv->ai_fifo_buffer) / 1462 sizeof(devpriv->ai_fifo_buffer[0]); i++) { 1463 fifo_empty = 1464 devpriv->stc_readw(dev, 1465 AI_Status_1_Register) & 1466 AI_FIFO_Empty_St; 1467 if (fifo_empty) 1468 break; 1469 devpriv->ai_fifo_buffer[i] = 1470 ni_readw(ADC_FIFO_Data_Register); 1471 } 1472 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer, 1473 i * sizeof(devpriv->ai_fifo_buffer[0])); 1474 } 1475 } 1476} 1477 1478static void get_last_sample_611x(struct comedi_device *dev) 1479{ 1480 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 1481 short data; 1482 u32 dl; 1483 1484 if (boardtype.reg_type != ni_reg_611x) 1485 return; 1486 1487 /* Check if there's a single sample stuck in the FIFO */ 1488 if (ni_readb(XXX_Status) & 0x80) { 1489 dl = ni_readl(ADC_FIFO_Data_611x); 1490 data = (dl & 0xffff); 1491 cfc_write_to_buffer(s, data); 1492 } 1493} 1494 1495static void get_last_sample_6143(struct comedi_device *dev) 1496{ 1497 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 1498 short data; 1499 u32 dl; 1500 1501 if (boardtype.reg_type != ni_reg_6143) 1502 return; 1503 1504 /* Check if there's a single sample stuck in the FIFO */ 1505 if (ni_readl(AIFIFO_Status_6143) & 0x01) { 1506 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 1507 dl = ni_readl(AIFIFO_Data_6143); 1508 1509 /* This may get the hi/lo data in the wrong order */ 1510 data = (dl >> 16) & 0xffff; 1511 cfc_write_to_buffer(s, data); 1512 } 1513} 1514 1515static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s, 1516 void *data, unsigned int num_bytes, unsigned int chan_index) 1517{ 1518 struct comedi_async *async = s->async; 1519 unsigned int i; 1520 unsigned int length = num_bytes / bytes_per_sample(s); 1521 short *array = data; 1522 unsigned int *larray = data; 1523 for (i = 0; i < length; i++) { 1524#ifdef PCIDMA 1525 if (s->subdev_flags & SDF_LSAMPL) 1526 larray[i] = le32_to_cpu(larray[i]); 1527 else 1528 array[i] = le16_to_cpu(array[i]); 1529#endif 1530 if (s->subdev_flags & SDF_LSAMPL) 1531 larray[i] += devpriv->ai_offset[chan_index]; 1532 else 1533 array[i] += devpriv->ai_offset[chan_index]; 1534 chan_index++; 1535 chan_index %= async->cmd.chanlist_len; 1536 } 1537} 1538 1539#ifdef PCIDMA 1540 1541static int ni_ai_setup_MITE_dma(struct comedi_device *dev) 1542{ 1543 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 1544 int retval; 1545 unsigned long flags; 1546 1547 retval = ni_request_ai_mite_channel(dev); 1548 if (retval) 1549 return retval; 1550/* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */ 1551 1552 /* write alloc the entire buffer */ 1553 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz); 1554 1555 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1556 if (devpriv->ai_mite_chan == NULL) { 1557 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1558 return -EIO; 1559 } 1560 1561 switch (boardtype.reg_type) { 1562 case ni_reg_611x: 1563 case ni_reg_6143: 1564 mite_prep_dma(devpriv->ai_mite_chan, 32, 16); 1565 break; 1566 case ni_reg_628x: 1567 mite_prep_dma(devpriv->ai_mite_chan, 32, 32); 1568 break; 1569 default: 1570 mite_prep_dma(devpriv->ai_mite_chan, 16, 16); 1571 break; 1572 }; 1573 /*start the MITE */ 1574 mite_dma_arm(devpriv->ai_mite_chan); 1575 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1576 1577 return 0; 1578} 1579 1580static int ni_ao_setup_MITE_dma(struct comedi_device *dev) 1581{ 1582 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV; 1583 int retval; 1584 unsigned long flags; 1585 1586 retval = ni_request_ao_mite_channel(dev); 1587 if (retval) 1588 return retval; 1589 1590 /* read alloc the entire buffer */ 1591 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz); 1592 1593 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1594 if (devpriv->ao_mite_chan) { 1595 if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) { 1596 mite_prep_dma(devpriv->ao_mite_chan, 32, 32); 1597 } else { 1598 /* doing 32 instead of 16 bit wide transfers from memory 1599 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */ 1600 mite_prep_dma(devpriv->ao_mite_chan, 16, 32); 1601 } 1602 mite_dma_arm(devpriv->ao_mite_chan); 1603 } else 1604 retval = -EIO; 1605 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1606 1607 return retval; 1608} 1609 1610#endif /* PCIDMA */ 1611 1612/* 1613 used for both cancel ioctl and board initialization 1614 1615 this is pretty harsh for a cancel, but it works... 1616 */ 1617 1618static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) 1619{ 1620 ni_release_ai_mite_channel(dev); 1621 /* ai configuration */ 1622 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, 1623 Joint_Reset_Register); 1624 1625 ni_set_bits(dev, Interrupt_A_Enable_Register, 1626 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable | 1627 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable | 1628 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable | 1629 AI_FIFO_Interrupt_Enable, 0); 1630 1631 ni_clear_ai_fifo(dev); 1632 1633 if (boardtype.reg_type != ni_reg_6143) 1634 ni_writeb(0, Misc_Command); 1635 1636 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */ 1637 devpriv->stc_writew(dev, 1638 AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */ , 1639 AI_Mode_1_Register); 1640 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register); 1641 /* generate FIFO interrupts on non-empty */ 1642 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register); 1643 if (boardtype.reg_type == ni_reg_611x) { 1644 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width | 1645 AI_SOC_Polarity | 1646 AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register); 1647 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) | 1648 AI_EXTMUX_CLK_Output_Select(0) | 1649 AI_LOCALMUX_CLK_Output_Select(2) | 1650 AI_SC_TC_Output_Select(3) | 1651 AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High), 1652 AI_Output_Control_Register); 1653 } else if (boardtype.reg_type == ni_reg_6143) { 1654 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width | 1655 AI_SOC_Polarity | 1656 AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register); 1657 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) | 1658 AI_EXTMUX_CLK_Output_Select(0) | 1659 AI_LOCALMUX_CLK_Output_Select(2) | 1660 AI_SC_TC_Output_Select(3) | 1661 AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low), 1662 AI_Output_Control_Register); 1663 } else { 1664 unsigned ai_output_control_bits; 1665 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width | 1666 AI_SOC_Polarity | 1667 AI_CONVERT_Pulse_Width | 1668 AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register); 1669 ai_output_control_bits = AI_SCAN_IN_PROG_Output_Select(3) | 1670 AI_EXTMUX_CLK_Output_Select(0) | 1671 AI_LOCALMUX_CLK_Output_Select(2) | 1672 AI_SC_TC_Output_Select(3); 1673 if (boardtype.reg_type == ni_reg_622x) 1674 ai_output_control_bits |= 1675 AI_CONVERT_Output_Select 1676 (AI_CONVERT_Output_Enable_High); 1677 else 1678 ai_output_control_bits |= 1679 AI_CONVERT_Output_Select 1680 (AI_CONVERT_Output_Enable_Low); 1681 devpriv->stc_writew(dev, ai_output_control_bits, 1682 AI_Output_Control_Register); 1683 } 1684 /* the following registers should not be changed, because there 1685 * are no backup registers in devpriv. If you want to change 1686 * any of these, add a backup register and other appropriate code: 1687 * AI_Mode_1_Register 1688 * AI_Mode_3_Register 1689 * AI_Personal_Register 1690 * AI_Output_Control_Register 1691 */ 1692 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */ 1693 1694 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); 1695 1696 return 0; 1697} 1698 1699static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s) 1700{ 1701 unsigned long flags = 0; 1702 int count; 1703 1704 /* lock to avoid race with interrupt handler */ 1705 if (in_interrupt() == 0) 1706 spin_lock_irqsave(&dev->spinlock, flags); 1707#ifndef PCIDMA 1708 ni_handle_fifo_dregs(dev); 1709#else 1710 ni_sync_ai_dma(dev); 1711#endif 1712 count = s->async->buf_write_count - s->async->buf_read_count; 1713 if (in_interrupt() == 0) 1714 spin_unlock_irqrestore(&dev->spinlock, flags); 1715 1716 return count; 1717} 1718 1719static int ni_ai_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 1720 struct comedi_insn *insn, unsigned int *data) 1721{ 1722 int i, n; 1723 const unsigned int mask = (1 << boardtype.adbits) - 1; 1724 unsigned signbits; 1725 unsigned short d; 1726 unsigned long dl; 1727 1728 ni_load_channelgain_list(dev, 1, &insn->chanspec); 1729 1730 ni_clear_ai_fifo(dev); 1731 1732 signbits = devpriv->ai_offset[0]; 1733 if (boardtype.reg_type == ni_reg_611x) { 1734 for (n = 0; n < num_adc_stages_611x; n++) { 1735 devpriv->stc_writew(dev, AI_CONVERT_Pulse, 1736 AI_Command_1_Register); 1737 udelay(1); 1738 } 1739 for (n = 0; n < insn->n; n++) { 1740 devpriv->stc_writew(dev, AI_CONVERT_Pulse, 1741 AI_Command_1_Register); 1742 /* The 611x has screwy 32-bit FIFOs. */ 1743 d = 0; 1744 for (i = 0; i < NI_TIMEOUT; i++) { 1745 if (ni_readb(XXX_Status) & 0x80) { 1746 d = (ni_readl(ADC_FIFO_Data_611x) >> 16) 1747 & 0xffff; 1748 break; 1749 } 1750 if (!(devpriv->stc_readw(dev, 1751 AI_Status_1_Register) & 1752 AI_FIFO_Empty_St)) { 1753 d = ni_readl(ADC_FIFO_Data_611x) & 1754 0xffff; 1755 break; 1756 } 1757 } 1758 if (i == NI_TIMEOUT) { 1759 printk 1760 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n"); 1761 return -ETIME; 1762 } 1763 d += signbits; 1764 data[n] = d; 1765 } 1766 } else if (boardtype.reg_type == ni_reg_6143) { 1767 for (n = 0; n < insn->n; n++) { 1768 devpriv->stc_writew(dev, AI_CONVERT_Pulse, 1769 AI_Command_1_Register); 1770 1771 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */ 1772 dl = 0; 1773 for (i = 0; i < NI_TIMEOUT; i++) { 1774 if (ni_readl(AIFIFO_Status_6143) & 0x01) { 1775 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 1776 dl = ni_readl(AIFIFO_Data_6143); 1777 break; 1778 } 1779 } 1780 if (i == NI_TIMEOUT) { 1781 printk 1782 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n"); 1783 return -ETIME; 1784 } 1785 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF; 1786 } 1787 } else { 1788 for (n = 0; n < insn->n; n++) { 1789 devpriv->stc_writew(dev, AI_CONVERT_Pulse, 1790 AI_Command_1_Register); 1791 for (i = 0; i < NI_TIMEOUT; i++) { 1792 if (!(devpriv->stc_readw(dev, 1793 AI_Status_1_Register) & 1794 AI_FIFO_Empty_St)) 1795 break; 1796 } 1797 if (i == NI_TIMEOUT) { 1798 printk 1799 ("ni_mio_common: timeout in ni_ai_insn_read\n"); 1800 return -ETIME; 1801 } 1802 if (boardtype.reg_type & ni_reg_m_series_mask) { 1803 data[n] = 1804 ni_readl(M_Offset_AI_FIFO_Data) & mask; 1805 } else { 1806 d = ni_readw(ADC_FIFO_Data_Register); 1807 d += signbits; /* subtle: needs to be short addition */ 1808 data[n] = d; 1809 } 1810 } 1811 } 1812 return insn->n; 1813} 1814 1815void ni_prime_channelgain_list(struct comedi_device *dev) 1816{ 1817 int i; 1818 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register); 1819 for (i = 0; i < NI_TIMEOUT; ++i) { 1820 if (!(devpriv->stc_readw(dev, 1821 AI_Status_1_Register) & 1822 AI_FIFO_Empty_St)) { 1823 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear); 1824 return; 1825 } 1826 udelay(1); 1827 } 1828 printk("ni_mio_common: timeout loading channel/gain list\n"); 1829} 1830 1831static void ni_m_series_load_channelgain_list(struct comedi_device *dev, 1832 unsigned int n_chan, unsigned int *list) 1833{ 1834 unsigned int chan, range, aref; 1835 unsigned int i; 1836 unsigned offset; 1837 unsigned int dither; 1838 unsigned range_code; 1839 1840 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear); 1841 1842/* offset = 1 << (boardtype.adbits - 1); */ 1843 if ((list[0] & CR_ALT_SOURCE)) { 1844 unsigned bypass_bits; 1845 chan = CR_CHAN(list[0]); 1846 range = CR_RANGE(list[0]); 1847 range_code = ni_gainlkup[boardtype.gainlkup][range]; 1848 dither = ((list[0] & CR_ALT_FILTER) != 0); 1849 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit; 1850 bypass_bits |= chan; 1851 bypass_bits |= 1852 (devpriv-> 1853 ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask | 1854 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | 1855 MSeries_AI_Bypass_Mode_Mux_Mask | 1856 MSeries_AO_Bypass_AO_Cal_Sel_Mask); 1857 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code); 1858 if (dither) 1859 bypass_bits |= MSeries_AI_Bypass_Dither_Bit; 1860 /* don't use 2's complement encoding */ 1861 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit; 1862 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass); 1863 } else { 1864 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass); 1865 } 1866 offset = 0; 1867 for (i = 0; i < n_chan; i++) { 1868 unsigned config_bits = 0; 1869 chan = CR_CHAN(list[i]); 1870 aref = CR_AREF(list[i]); 1871 range = CR_RANGE(list[i]); 1872 dither = ((list[i] & CR_ALT_FILTER) != 0); 1873 1874 range_code = ni_gainlkup[boardtype.gainlkup][range]; 1875 devpriv->ai_offset[i] = offset; 1876 switch (aref) { 1877 case AREF_DIFF: 1878 config_bits |= 1879 MSeries_AI_Config_Channel_Type_Differential_Bits; 1880 break; 1881 case AREF_COMMON: 1882 config_bits |= 1883 MSeries_AI_Config_Channel_Type_Common_Ref_Bits; 1884 break; 1885 case AREF_GROUND: 1886 config_bits |= 1887 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits; 1888 break; 1889 case AREF_OTHER: 1890 break; 1891 } 1892 config_bits |= MSeries_AI_Config_Channel_Bits(chan); 1893 config_bits |= 1894 MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan); 1895 config_bits |= MSeries_AI_Config_Gain_Bits(range_code); 1896 if (i == n_chan - 1) 1897 config_bits |= MSeries_AI_Config_Last_Channel_Bit; 1898 if (dither) 1899 config_bits |= MSeries_AI_Config_Dither_Bit; 1900 /* don't use 2's complement encoding */ 1901 config_bits |= MSeries_AI_Config_Polarity_Bit; 1902 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data); 1903 } 1904 ni_prime_channelgain_list(dev); 1905} 1906 1907/* 1908 * Notes on the 6110 and 6111: 1909 * These boards a slightly different than the rest of the series, since 1910 * they have multiple A/D converters. 1911 * From the driver side, the configuration memory is a 1912 * little different. 1913 * Configuration Memory Low: 1914 * bits 15-9: same 1915 * bit 8: unipolar/bipolar (should be 0 for bipolar) 1916 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards 1917 * 1001 gain=0.1 (+/- 50) 1918 * 1010 0.2 1919 * 1011 0.1 1920 * 0001 1 1921 * 0010 2 1922 * 0011 5 1923 * 0100 10 1924 * 0101 20 1925 * 0110 50 1926 * Configuration Memory High: 1927 * bits 12-14: Channel Type 1928 * 001 for differential 1929 * 000 for calibration 1930 * bit 11: coupling (this is not currently handled) 1931 * 1 AC coupling 1932 * 0 DC coupling 1933 * bits 0-2: channel 1934 * valid channels are 0-3 1935 */ 1936static void ni_load_channelgain_list(struct comedi_device *dev, unsigned int n_chan, 1937 unsigned int *list) 1938{ 1939 unsigned int chan, range, aref; 1940 unsigned int i; 1941 unsigned int hi, lo; 1942 unsigned offset; 1943 unsigned int dither; 1944 1945 if (boardtype.reg_type & ni_reg_m_series_mask) { 1946 ni_m_series_load_channelgain_list(dev, n_chan, list); 1947 return; 1948 } 1949 if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x) 1950 && (boardtype.reg_type != ni_reg_6143)) { 1951 if (devpriv->changain_state 1952 && devpriv->changain_spec == list[0]) { 1953 /* ready to go. */ 1954 return; 1955 } 1956 devpriv->changain_state = 1; 1957 devpriv->changain_spec = list[0]; 1958 } else { 1959 devpriv->changain_state = 0; 1960 } 1961 1962 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear); 1963 1964 /* Set up Calibration mode if required */ 1965 if (boardtype.reg_type == ni_reg_6143) { 1966 if ((list[0] & CR_ALT_SOURCE) 1967 && !devpriv->ai_calib_source_enabled) { 1968 /* Strobe Relay enable bit */ 1969 ni_writew(devpriv-> 1970 ai_calib_source | 1971 Calibration_Channel_6143_RelayOn, 1972 Calibration_Channel_6143); 1973 ni_writew(devpriv->ai_calib_source, 1974 Calibration_Channel_6143); 1975 devpriv->ai_calib_source_enabled = 1; 1976 msleep_interruptible(100); /* Allow relays to change */ 1977 } else if (!(list[0] & CR_ALT_SOURCE) 1978 && devpriv->ai_calib_source_enabled) { 1979 /* Strobe Relay disable bit */ 1980 ni_writew(devpriv-> 1981 ai_calib_source | 1982 Calibration_Channel_6143_RelayOff, 1983 Calibration_Channel_6143); 1984 ni_writew(devpriv->ai_calib_source, 1985 Calibration_Channel_6143); 1986 devpriv->ai_calib_source_enabled = 0; 1987 msleep_interruptible(100); /* Allow relays to change */ 1988 } 1989 } 1990 1991 offset = 1 << (boardtype.adbits - 1); 1992 for (i = 0; i < n_chan; i++) { 1993 if ((boardtype.reg_type != ni_reg_6143) 1994 && (list[i] & CR_ALT_SOURCE)) { 1995 chan = devpriv->ai_calib_source; 1996 } else { 1997 chan = CR_CHAN(list[i]); 1998 } 1999 aref = CR_AREF(list[i]); 2000 range = CR_RANGE(list[i]); 2001 dither = ((list[i] & CR_ALT_FILTER) != 0); 2002 2003 /* fix the external/internal range differences */ 2004 range = ni_gainlkup[boardtype.gainlkup][range]; 2005 if (boardtype.reg_type == ni_reg_611x) 2006 devpriv->ai_offset[i] = offset; 2007 else 2008 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset; 2009 2010 hi = 0; 2011 if ((list[i] & CR_ALT_SOURCE)) { 2012 if (boardtype.reg_type == ni_reg_611x) 2013 ni_writew(CR_CHAN(list[i]) & 0x0003, 2014 Calibration_Channel_Select_611x); 2015 } else { 2016 if (boardtype.reg_type == ni_reg_611x) 2017 aref = AREF_DIFF; 2018 else if (boardtype.reg_type == ni_reg_6143) 2019 aref = AREF_OTHER; 2020 switch (aref) { 2021 case AREF_DIFF: 2022 hi |= AI_DIFFERENTIAL; 2023 break; 2024 case AREF_COMMON: 2025 hi |= AI_COMMON; 2026 break; 2027 case AREF_GROUND: 2028 hi |= AI_GROUND; 2029 break; 2030 case AREF_OTHER: 2031 break; 2032 } 2033 } 2034 hi |= AI_CONFIG_CHANNEL(chan); 2035 2036 ni_writew(hi, Configuration_Memory_High); 2037 2038 if (boardtype.reg_type != ni_reg_6143) { 2039 lo = range; 2040 if (i == n_chan - 1) 2041 lo |= AI_LAST_CHANNEL; 2042 if (dither) 2043 lo |= AI_DITHER; 2044 2045 ni_writew(lo, Configuration_Memory_Low); 2046 } 2047 } 2048 2049 /* prime the channel/gain list */ 2050 if ((boardtype.reg_type != ni_reg_611x) 2051 && (boardtype.reg_type != ni_reg_6143)) { 2052 ni_prime_channelgain_list(dev); 2053 } 2054} 2055 2056static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec, 2057 int round_mode) 2058{ 2059 int divider; 2060 switch (round_mode) { 2061 case TRIG_ROUND_NEAREST: 2062 default: 2063 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns; 2064 break; 2065 case TRIG_ROUND_DOWN: 2066 divider = (nanosec) / devpriv->clock_ns; 2067 break; 2068 case TRIG_ROUND_UP: 2069 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns; 2070 break; 2071 } 2072 return divider - 1; 2073} 2074 2075static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer) 2076{ 2077 return devpriv->clock_ns * (timer + 1); 2078} 2079 2080static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev, 2081 unsigned num_channels) 2082{ 2083 switch (boardtype.reg_type) { 2084 case ni_reg_611x: 2085 case ni_reg_6143: 2086 /* simultaneously-sampled inputs */ 2087 return boardtype.ai_speed; 2088 break; 2089 default: 2090 /* multiplexed inputs */ 2091 break; 2092 }; 2093 return boardtype.ai_speed * num_channels; 2094} 2095 2096static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 2097 struct comedi_cmd *cmd) 2098{ 2099 int err = 0; 2100 int tmp; 2101 int sources; 2102 2103 /* step 1: make sure trigger sources are trivially valid */ 2104 2105 if ((cmd->flags & CMDF_WRITE)) { 2106 cmd->flags &= ~CMDF_WRITE; 2107 } 2108 2109 tmp = cmd->start_src; 2110 cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT; 2111 if (!cmd->start_src || tmp != cmd->start_src) 2112 err++; 2113 2114 tmp = cmd->scan_begin_src; 2115 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; 2116 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 2117 err++; 2118 2119 tmp = cmd->convert_src; 2120 sources = TRIG_TIMER | TRIG_EXT; 2121 if ((boardtype.reg_type == ni_reg_611x) 2122 || (boardtype.reg_type == ni_reg_6143)) 2123 sources |= TRIG_NOW; 2124 cmd->convert_src &= sources; 2125 if (!cmd->convert_src || tmp != cmd->convert_src) 2126 err++; 2127 2128 tmp = cmd->scan_end_src; 2129 cmd->scan_end_src &= TRIG_COUNT; 2130 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 2131 err++; 2132 2133 tmp = cmd->stop_src; 2134 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 2135 if (!cmd->stop_src || tmp != cmd->stop_src) 2136 err++; 2137 2138 if (err) 2139 return 1; 2140 2141 /* step 2: make sure trigger sources are unique and mutually compatible */ 2142 2143 /* note that mutual compatiblity is not an issue here */ 2144 if (cmd->start_src != TRIG_NOW && 2145 cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT) 2146 err++; 2147 if (cmd->scan_begin_src != TRIG_TIMER && 2148 cmd->scan_begin_src != TRIG_EXT && 2149 cmd->scan_begin_src != TRIG_OTHER) 2150 err++; 2151 if (cmd->convert_src != TRIG_TIMER && 2152 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW) 2153 err++; 2154 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 2155 err++; 2156 2157 if (err) 2158 return 2; 2159 2160 /* step 3: make sure arguments are trivially compatible */ 2161 2162 if (cmd->start_src == TRIG_EXT) { 2163 /* external trigger */ 2164 unsigned int tmp = CR_CHAN(cmd->start_arg); 2165 2166 if (tmp > 16) 2167 tmp = 16; 2168 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE)); 2169 if (cmd->start_arg != tmp) { 2170 cmd->start_arg = tmp; 2171 err++; 2172 } 2173 } else { 2174 if (cmd->start_arg != 0) { 2175 /* true for both TRIG_NOW and TRIG_INT */ 2176 cmd->start_arg = 0; 2177 err++; 2178 } 2179 } 2180 if (cmd->scan_begin_src == TRIG_TIMER) { 2181 if (cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev, 2182 cmd->chanlist_len)) { 2183 cmd->scan_begin_arg = 2184 ni_min_ai_scan_period_ns(dev, 2185 cmd->chanlist_len); 2186 err++; 2187 } 2188 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) { 2189 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff; 2190 err++; 2191 } 2192 } else if (cmd->scan_begin_src == TRIG_EXT) { 2193 /* external trigger */ 2194 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg); 2195 2196 if (tmp > 16) 2197 tmp = 16; 2198 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE)); 2199 if (cmd->scan_begin_arg != tmp) { 2200 cmd->scan_begin_arg = tmp; 2201 err++; 2202 } 2203 } else { /* TRIG_OTHER */ 2204 if (cmd->scan_begin_arg) { 2205 cmd->scan_begin_arg = 0; 2206 err++; 2207 } 2208 } 2209 if (cmd->convert_src == TRIG_TIMER) { 2210 if ((boardtype.reg_type == ni_reg_611x) 2211 || (boardtype.reg_type == ni_reg_6143)) { 2212 if (cmd->convert_arg != 0) { 2213 cmd->convert_arg = 0; 2214 err++; 2215 } 2216 } else { 2217 if (cmd->convert_arg < boardtype.ai_speed) { 2218 cmd->convert_arg = boardtype.ai_speed; 2219 err++; 2220 } 2221 if (cmd->convert_arg > devpriv->clock_ns * 0xffff) { 2222 cmd->convert_arg = devpriv->clock_ns * 0xffff; 2223 err++; 2224 } 2225 } 2226 } else if (cmd->convert_src == TRIG_EXT) { 2227 /* external trigger */ 2228 unsigned int tmp = CR_CHAN(cmd->convert_arg); 2229 2230 if (tmp > 16) 2231 tmp = 16; 2232 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT)); 2233 if (cmd->convert_arg != tmp) { 2234 cmd->convert_arg = tmp; 2235 err++; 2236 } 2237 } else if (cmd->convert_src == TRIG_NOW) { 2238 if (cmd->convert_arg != 0) { 2239 cmd->convert_arg = 0; 2240 err++; 2241 } 2242 } 2243 2244 if (cmd->scan_end_arg != cmd->chanlist_len) { 2245 cmd->scan_end_arg = cmd->chanlist_len; 2246 err++; 2247 } 2248 if (cmd->stop_src == TRIG_COUNT) { 2249 unsigned int max_count = 0x01000000; 2250 2251 if (boardtype.reg_type == ni_reg_611x) 2252 max_count -= num_adc_stages_611x; 2253 if (cmd->stop_arg > max_count) { 2254 cmd->stop_arg = max_count; 2255 err++; 2256 } 2257 if (cmd->stop_arg < 1) { 2258 cmd->stop_arg = 1; 2259 err++; 2260 } 2261 } else { 2262 /* TRIG_NONE */ 2263 if (cmd->stop_arg != 0) { 2264 cmd->stop_arg = 0; 2265 err++; 2266 } 2267 } 2268 2269 if (err) 2270 return 3; 2271 2272 /* step 4: fix up any arguments */ 2273 2274 if (cmd->scan_begin_src == TRIG_TIMER) { 2275 tmp = cmd->scan_begin_arg; 2276 cmd->scan_begin_arg = 2277 ni_timer_to_ns(dev, ni_ns_to_timer(dev, 2278 cmd->scan_begin_arg, 2279 cmd->flags & TRIG_ROUND_MASK)); 2280 if (tmp != cmd->scan_begin_arg) 2281 err++; 2282 } 2283 if (cmd->convert_src == TRIG_TIMER) { 2284 if ((boardtype.reg_type != ni_reg_611x) 2285 && (boardtype.reg_type != ni_reg_6143)) { 2286 tmp = cmd->convert_arg; 2287 cmd->convert_arg = 2288 ni_timer_to_ns(dev, ni_ns_to_timer(dev, 2289 cmd->convert_arg, 2290 cmd->flags & TRIG_ROUND_MASK)); 2291 if (tmp != cmd->convert_arg) 2292 err++; 2293 if (cmd->scan_begin_src == TRIG_TIMER && 2294 cmd->scan_begin_arg < 2295 cmd->convert_arg * cmd->scan_end_arg) { 2296 cmd->scan_begin_arg = 2297 cmd->convert_arg * cmd->scan_end_arg; 2298 err++; 2299 } 2300 } 2301 } 2302 2303 if (err) 2304 return 4; 2305 2306 return 0; 2307} 2308 2309static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 2310{ 2311 const struct comedi_cmd *cmd = &s->async->cmd; 2312 int timer; 2313 int mode1 = 0; /* mode1 is needed for both stop and convert */ 2314 int mode2 = 0; 2315 int start_stop_select = 0; 2316 unsigned int stop_count; 2317 int interrupt_a_enable = 0; 2318 2319 MDPRINTK("ni_ai_cmd\n"); 2320 if (dev->irq == 0) { 2321 comedi_error(dev, "cannot run command without an irq"); 2322 return -EIO; 2323 } 2324 ni_clear_ai_fifo(dev); 2325 2326 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist); 2327 2328 /* start configuration */ 2329 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register); 2330 2331 /* disable analog triggering for now, since it 2332 * interferes with the use of pfi0 */ 2333 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable; 2334 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, 2335 Analog_Trigger_Etc_Register); 2336 2337 switch (cmd->start_src) { 2338 case TRIG_INT: 2339 case TRIG_NOW: 2340 devpriv->stc_writew(dev, AI_START2_Select(0) | 2341 AI_START1_Sync | AI_START1_Edge | AI_START1_Select(0), 2342 AI_Trigger_Select_Register); 2343 break; 2344 case TRIG_EXT: 2345 { 2346 int chan = CR_CHAN(cmd->start_arg); 2347 unsigned int bits = AI_START2_Select(0) | 2348 AI_START1_Sync | AI_START1_Select(chan + 1); 2349 2350 if (cmd->start_arg & CR_INVERT) 2351 bits |= AI_START1_Polarity; 2352 if (cmd->start_arg & CR_EDGE) 2353 bits |= AI_START1_Edge; 2354 devpriv->stc_writew(dev, bits, 2355 AI_Trigger_Select_Register); 2356 break; 2357 } 2358 } 2359 2360 mode2 &= ~AI_Pre_Trigger; 2361 mode2 &= ~AI_SC_Initial_Load_Source; 2362 mode2 &= ~AI_SC_Reload_Mode; 2363 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); 2364 2365 if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x) 2366 || (boardtype.reg_type == ni_reg_6143)) { 2367 start_stop_select |= AI_STOP_Polarity; 2368 start_stop_select |= AI_STOP_Select(31); /* logic low */ 2369 start_stop_select |= AI_STOP_Sync; 2370 } else { 2371 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */ 2372 } 2373 devpriv->stc_writew(dev, start_stop_select, 2374 AI_START_STOP_Select_Register); 2375 2376 devpriv->ai_cmd2 = 0; 2377 switch (cmd->stop_src) { 2378 case TRIG_COUNT: 2379 stop_count = cmd->stop_arg - 1; 2380 2381 if (boardtype.reg_type == ni_reg_611x) { 2382 /* have to take 3 stage adc pipeline into account */ 2383 stop_count += num_adc_stages_611x; 2384 } 2385 /* stage number of scans */ 2386 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers); 2387 2388 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once; 2389 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register); 2390 /* load SC (Scan Count) */ 2391 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register); 2392 2393 devpriv->ai_continuous = 0; 2394 if (stop_count == 0) { 2395 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan; 2396 interrupt_a_enable |= AI_STOP_Interrupt_Enable; 2397 /* this is required to get the last sample for chanlist_len > 1, not sure why */ 2398 if (cmd->chanlist_len > 1) 2399 start_stop_select |= 2400 AI_STOP_Polarity | AI_STOP_Edge; 2401 } 2402 break; 2403 case TRIG_NONE: 2404 /* stage number of scans */ 2405 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers); 2406 2407 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous; 2408 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register); 2409 2410 /* load SC (Scan Count) */ 2411 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register); 2412 2413 devpriv->ai_continuous = 1; 2414 2415 break; 2416 } 2417 2418 switch (cmd->scan_begin_src) { 2419 case TRIG_TIMER: 2420 /* 2421 stop bits for non 611x boards 2422 AI_SI_Special_Trigger_Delay=0 2423 AI_Pre_Trigger=0 2424 AI_START_STOP_Select_Register: 2425 AI_START_Polarity=0 (?) rising edge 2426 AI_START_Edge=1 edge triggered 2427 AI_START_Sync=1 (?) 2428 AI_START_Select=0 SI_TC 2429 AI_STOP_Polarity=0 rising edge 2430 AI_STOP_Edge=0 level 2431 AI_STOP_Sync=1 2432 AI_STOP_Select=19 external pin (configuration mem) 2433 */ 2434 start_stop_select |= AI_START_Edge | AI_START_Sync; 2435 devpriv->stc_writew(dev, start_stop_select, 2436 AI_START_STOP_Select_Register); 2437 2438 mode2 |= AI_SI_Reload_Mode(0); 2439 /* AI_SI_Initial_Load_Source=A */ 2440 mode2 &= ~AI_SI_Initial_Load_Source; 2441 /* mode2 |= AI_SC_Reload_Mode; */ 2442 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); 2443 2444 /* load SI */ 2445 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg, 2446 TRIG_ROUND_NEAREST); 2447 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers); 2448 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register); 2449 break; 2450 case TRIG_EXT: 2451 if (cmd->scan_begin_arg & CR_EDGE) 2452 start_stop_select |= AI_START_Edge; 2453 /* AI_START_Polarity==1 is falling edge */ 2454 if (cmd->scan_begin_arg & CR_INVERT) 2455 start_stop_select |= AI_START_Polarity; 2456 if (cmd->scan_begin_src != cmd->convert_src || 2457 (cmd->scan_begin_arg & ~CR_EDGE) != 2458 (cmd->convert_arg & ~CR_EDGE)) 2459 start_stop_select |= AI_START_Sync; 2460 start_stop_select |= 2461 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg)); 2462 devpriv->stc_writew(dev, start_stop_select, 2463 AI_START_STOP_Select_Register); 2464 break; 2465 } 2466 2467 switch (cmd->convert_src) { 2468 case TRIG_TIMER: 2469 case TRIG_NOW: 2470 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW) 2471 timer = 1; 2472 else 2473 timer = ni_ns_to_timer(dev, cmd->convert_arg, 2474 TRIG_ROUND_NEAREST); 2475 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */ 2476 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register); 2477 2478 /* AI_SI2_Reload_Mode = alternate */ 2479 /* AI_SI2_Initial_Load_Source = A */ 2480 mode2 &= ~AI_SI2_Initial_Load_Source; 2481 mode2 |= AI_SI2_Reload_Mode; 2482 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); 2483 2484 /* AI_SI2_Load */ 2485 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register); 2486 2487 mode2 |= AI_SI2_Reload_Mode; /* alternate */ 2488 mode2 |= AI_SI2_Initial_Load_Source; /* B */ 2489 2490 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); 2491 break; 2492 case TRIG_EXT: 2493 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg); 2494 if ((cmd->convert_arg & CR_INVERT) == 0) 2495 mode1 |= AI_CONVERT_Source_Polarity; 2496 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register); 2497 2498 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable; 2499 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); 2500 2501 break; 2502 } 2503 2504 if (dev->irq) { 2505 2506 /* interrupt on FIFO, errors, SC_TC */ 2507 interrupt_a_enable |= AI_Error_Interrupt_Enable | 2508 AI_SC_TC_Interrupt_Enable; 2509 2510#ifndef PCIDMA 2511 interrupt_a_enable |= AI_FIFO_Interrupt_Enable; 2512#endif 2513 2514 if (cmd->flags & TRIG_WAKE_EOS 2515 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) { 2516 /* wake on end-of-scan */ 2517 devpriv->aimode = AIMODE_SCAN; 2518 } else { 2519 devpriv->aimode = AIMODE_HALF_FULL; 2520 } 2521 2522 switch (devpriv->aimode) { 2523 case AIMODE_HALF_FULL: 2524 /*generate FIFO interrupts and DMA requests on half-full */ 2525#ifdef PCIDMA 2526 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, 2527 AI_Mode_3_Register); 2528#else 2529 devpriv->stc_writew(dev, AI_FIFO_Mode_HF, 2530 AI_Mode_3_Register); 2531#endif 2532 break; 2533 case AIMODE_SAMPLE: 2534 /*generate FIFO interrupts on non-empty */ 2535 devpriv->stc_writew(dev, AI_FIFO_Mode_NE, 2536 AI_Mode_3_Register); 2537 break; 2538 case AIMODE_SCAN: 2539#ifdef PCIDMA 2540 devpriv->stc_writew(dev, AI_FIFO_Mode_NE, 2541 AI_Mode_3_Register); 2542#else 2543 devpriv->stc_writew(dev, AI_FIFO_Mode_HF, 2544 AI_Mode_3_Register); 2545#endif 2546 interrupt_a_enable |= AI_STOP_Interrupt_Enable; 2547 break; 2548 default: 2549 break; 2550 } 2551 2552 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */ 2553 2554 ni_set_bits(dev, Interrupt_A_Enable_Register, 2555 interrupt_a_enable, 1); 2556 2557 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n", 2558 devpriv->int_a_enable_reg); 2559 } else { 2560 /* interrupt on nothing */ 2561 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0); 2562 2563 /* XXX start polling if necessary */ 2564 MDPRINTK("interrupting on nothing\n"); 2565 } 2566 2567 /* end configuration */ 2568 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); 2569 2570 switch (cmd->scan_begin_src) { 2571 case TRIG_TIMER: 2572 devpriv->stc_writew(dev, 2573 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm, 2574 AI_Command_1_Register); 2575 break; 2576 case TRIG_EXT: 2577 /* XXX AI_SI_Arm? */ 2578 devpriv->stc_writew(dev, 2579 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm, 2580 AI_Command_1_Register); 2581 break; 2582 } 2583 2584#ifdef PCIDMA 2585 { 2586 int retval = ni_ai_setup_MITE_dma(dev); 2587 if (retval) 2588 return retval; 2589 } 2590 /* mite_dump_regs(devpriv->mite); */ 2591#endif 2592 2593 switch (cmd->start_src) { 2594 case TRIG_NOW: 2595 /* AI_START1_Pulse */ 2596 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, 2597 AI_Command_2_Register); 2598 s->async->inttrig = NULL; 2599 break; 2600 case TRIG_EXT: 2601 s->async->inttrig = NULL; 2602 break; 2603 case TRIG_INT: 2604 s->async->inttrig = &ni_ai_inttrig; 2605 break; 2606 } 2607 2608 MDPRINTK("exit ni_ai_cmd\n"); 2609 2610 return 0; 2611} 2612 2613static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 2614 unsigned int trignum) 2615{ 2616 if (trignum != 0) 2617 return -EINVAL; 2618 2619 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, 2620 AI_Command_2_Register); 2621 s->async->inttrig = NULL; 2622 2623 return 1; 2624} 2625 2626static int ni_ai_config_analog_trig(struct comedi_device *dev, struct comedi_subdevice *s, 2627 struct comedi_insn *insn, unsigned int *data); 2628 2629static int ni_ai_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 2630 struct comedi_insn *insn, unsigned int *data) 2631{ 2632 if (insn->n < 1) 2633 return -EINVAL; 2634 2635 switch (data[0]) { 2636 case INSN_CONFIG_ANALOG_TRIG: 2637 return ni_ai_config_analog_trig(dev, s, insn, data); 2638 case INSN_CONFIG_ALT_SOURCE: 2639 if (boardtype.reg_type & ni_reg_m_series_mask) { 2640 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask | 2641 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | 2642 MSeries_AI_Bypass_Mode_Mux_Mask | 2643 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) { 2644 return -EINVAL; 2645 } 2646 devpriv->ai_calib_source = data[1]; 2647 } else if (boardtype.reg_type == ni_reg_6143) { 2648 unsigned int calib_source; 2649 2650 calib_source = data[1] & 0xf; 2651 2652 if (calib_source > 0xF) 2653 return -EINVAL; 2654 2655 devpriv->ai_calib_source = calib_source; 2656 ni_writew(calib_source, Calibration_Channel_6143); 2657 } else { 2658 unsigned int calib_source; 2659 unsigned int calib_source_adjust; 2660 2661 calib_source = data[1] & 0xf; 2662 calib_source_adjust = (data[1] >> 4) & 0xff; 2663 2664 if (calib_source >= 8) 2665 return -EINVAL; 2666 devpriv->ai_calib_source = calib_source; 2667 if (boardtype.reg_type == ni_reg_611x) { 2668 ni_writeb(calib_source_adjust, 2669 Cal_Gain_Select_611x); 2670 } 2671 } 2672 return 2; 2673 default: 2674 break; 2675 } 2676 2677 return -EINVAL; 2678} 2679 2680static int ni_ai_config_analog_trig(struct comedi_device *dev, struct comedi_subdevice *s, 2681 struct comedi_insn *insn, unsigned int *data) 2682{ 2683 unsigned int a, b, modebits; 2684 int err = 0; 2685 2686 /* data[1] is flags 2687 * data[2] is analog line 2688 * data[3] is set level 2689 * data[4] is reset level */ 2690 if (!boardtype.has_analog_trig) 2691 return -EINVAL; 2692 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) { 2693 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff); 2694 err++; 2695 } 2696 if (data[2] >= boardtype.n_adchan) { 2697 data[2] = boardtype.n_adchan - 1; 2698 err++; 2699 } 2700 if (data[3] > 255) { /* a */ 2701 data[3] = 255; 2702 err++; 2703 } 2704 if (data[4] > 255) { /* b */ 2705 data[4] = 255; 2706 err++; 2707 } 2708 /* 2709 * 00 ignore 2710 * 01 set 2711 * 10 reset 2712 * 2713 * modes: 2714 * 1 level: +b- +a- 2715 * high mode 00 00 01 10 2716 * low mode 00 00 10 01 2717 * 2 level: (a<b) 2718 * hysteresis low mode 10 00 00 01 2719 * hysteresis high mode 01 00 00 10 2720 * middle mode 10 01 01 10 2721 */ 2722 2723 a = data[3]; 2724 b = data[4]; 2725 modebits = data[1] & 0xff; 2726 if (modebits & 0xf0) { 2727 /* two level mode */ 2728 if (b < a) { 2729 /* swap order */ 2730 a = data[4]; 2731 b = data[3]; 2732 modebits = 2733 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 2734 4); 2735 } 2736 devpriv->atrig_low = a; 2737 devpriv->atrig_high = b; 2738 switch (modebits) { 2739 case 0x81: /* low hysteresis mode */ 2740 devpriv->atrig_mode = 6; 2741 break; 2742 case 0x42: /* high hysteresis mode */ 2743 devpriv->atrig_mode = 3; 2744 break; 2745 case 0x96: /* middle window mode */ 2746 devpriv->atrig_mode = 2; 2747 break; 2748 default: 2749 data[1] &= ~0xff; 2750 err++; 2751 } 2752 } else { 2753 /* one level mode */ 2754 if (b != 0) { 2755 data[4] = 0; 2756 err++; 2757 } 2758 switch (modebits) { 2759 case 0x06: /* high window mode */ 2760 devpriv->atrig_high = a; 2761 devpriv->atrig_mode = 0; 2762 break; 2763 case 0x09: /* low window mode */ 2764 devpriv->atrig_low = a; 2765 devpriv->atrig_mode = 1; 2766 break; 2767 default: 2768 data[1] &= ~0xff; 2769 err++; 2770 } 2771 } 2772 if (err) 2773 return -EAGAIN; 2774 return 5; 2775} 2776 2777/* munge data from unsigned to 2's complement for analog output bipolar modes */ 2778static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s, 2779 void *data, unsigned int num_bytes, unsigned int chan_index) 2780{ 2781 struct comedi_async *async = s->async; 2782 unsigned int range; 2783 unsigned int i; 2784 unsigned int offset; 2785 unsigned int length = num_bytes / sizeof(short); 2786 short *array = data; 2787 2788 offset = 1 << (boardtype.aobits - 1); 2789 for (i = 0; i < length; i++) { 2790 range = CR_RANGE(async->cmd.chanlist[chan_index]); 2791 if (boardtype.ao_unipolar == 0 || (range & 1) == 0) 2792 array[i] -= offset; 2793#ifdef PCIDMA 2794 array[i] = cpu_to_le16(array[i]); 2795#endif 2796 chan_index++; 2797 chan_index %= async->cmd.chanlist_len; 2798 } 2799} 2800 2801static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, 2802 struct comedi_subdevice *s, unsigned int chanspec[], unsigned int n_chans, 2803 int timed) 2804{ 2805 unsigned int range; 2806 unsigned int chan; 2807 unsigned int conf; 2808 int i; 2809 int invert = 0; 2810 2811 if (timed) { 2812 for (i = 0; i < boardtype.n_aochan; ++i) { 2813 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit; 2814 ni_writeb(devpriv->ao_conf[i], M_Offset_AO_Config_Bank(i)); 2815 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i)); 2816 } 2817 } 2818 for (i = 0; i < n_chans; i++) { 2819 const struct comedi_krange *krange; 2820 chan = CR_CHAN(chanspec[i]); 2821 range = CR_RANGE(chanspec[i]); 2822 krange = s->range_table->range + range; 2823 invert = 0; 2824 conf = 0; 2825 switch (krange->max - krange->min) { 2826 case 20000000: 2827 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; 2828 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan)); 2829 break; 2830 case 10000000: 2831 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; 2832 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan)); 2833 break; 2834 case 4000000: 2835 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; 2836 ni_writeb(MSeries_Attenuate_x5_Bit, 2837 M_Offset_AO_Reference_Attenuation(chan)); 2838 break; 2839 case 2000000: 2840 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; 2841 ni_writeb(MSeries_Attenuate_x5_Bit, 2842 M_Offset_AO_Reference_Attenuation(chan)); 2843 break; 2844 default: 2845 printk("%s: bug! unhandled ao reference voltage\n", 2846 __func__); 2847 break; 2848 } 2849 switch (krange->max + krange->min) { 2850 case 0: 2851 conf |= MSeries_AO_DAC_Offset_0V_Bits; 2852 break; 2853 case 10000000: 2854 conf |= MSeries_AO_DAC_Offset_5V_Bits; 2855 break; 2856 default: 2857 printk("%s: bug! unhandled ao offset voltage\n", 2858 __func__); 2859 break; 2860 } 2861 if (timed) 2862 conf |= MSeries_AO_Update_Timed_Bit; 2863 ni_writeb(conf, M_Offset_AO_Config_Bank(chan)); 2864 devpriv->ao_conf[chan] = conf; 2865 ni_writeb(i, M_Offset_AO_Waveform_Order(chan)); 2866 } 2867 return invert; 2868} 2869 2870static int ni_old_ao_config_chanlist(struct comedi_device *dev, struct comedi_subdevice *s, 2871 unsigned int chanspec[], unsigned int n_chans) 2872{ 2873 unsigned int range; 2874 unsigned int chan; 2875 unsigned int conf; 2876 int i; 2877 int invert = 0; 2878 2879 for (i = 0; i < n_chans; i++) { 2880 chan = CR_CHAN(chanspec[i]); 2881 range = CR_RANGE(chanspec[i]); 2882 conf = AO_Channel(chan); 2883 2884 if (boardtype.ao_unipolar) { 2885 if ((range & 1) == 0) { 2886 conf |= AO_Bipolar; 2887 invert = (1 << (boardtype.aobits - 1)); 2888 } else { 2889 invert = 0; 2890 } 2891 if (range & 2) 2892 conf |= AO_Ext_Ref; 2893 } else { 2894 conf |= AO_Bipolar; 2895 invert = (1 << (boardtype.aobits - 1)); 2896 } 2897 2898 /* not all boards can deglitch, but this shouldn't hurt */ 2899 if (chanspec[i] & CR_DEGLITCH) 2900 conf |= AO_Deglitch; 2901 2902 /* analog reference */ 2903 /* AREF_OTHER connects AO ground to AI ground, i think */ 2904 conf |= (CR_AREF(chanspec[i]) == 2905 AREF_OTHER) ? AO_Ground_Ref : 0; 2906 2907 ni_writew(conf, AO_Configuration); 2908 devpriv->ao_conf[chan] = conf; 2909 } 2910 return invert; 2911} 2912 2913static int ni_ao_config_chanlist(struct comedi_device *dev, struct comedi_subdevice *s, 2914 unsigned int chanspec[], unsigned int n_chans, int timed) 2915{ 2916 if (boardtype.reg_type & ni_reg_m_series_mask) 2917 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans, 2918 timed); 2919 else 2920 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans); 2921} 2922static int ni_ao_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 2923 struct comedi_insn *insn, unsigned int *data) 2924{ 2925 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)]; 2926 2927 return 1; 2928} 2929 2930static int ni_ao_insn_write(struct comedi_device *dev, struct comedi_subdevice *s, 2931 struct comedi_insn *insn, unsigned int *data) 2932{ 2933 unsigned int chan = CR_CHAN(insn->chanspec); 2934 unsigned int invert; 2935 2936 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0); 2937 2938 devpriv->ao[chan] = data[0]; 2939 2940 if (boardtype.reg_type & ni_reg_m_series_mask) { 2941 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan)); 2942 } else 2943 ni_writew(data[0] ^ invert, 2944 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data); 2945 2946 return 1; 2947} 2948 2949static int ni_ao_insn_write_671x(struct comedi_device *dev, struct comedi_subdevice *s, 2950 struct comedi_insn *insn, unsigned int *data) 2951{ 2952 unsigned int chan = CR_CHAN(insn->chanspec); 2953 unsigned int invert; 2954 2955 ao_win_out(1 << chan, AO_Immediate_671x); 2956 invert = 1 << (boardtype.aobits - 1); 2957 2958 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0); 2959 2960 devpriv->ao[chan] = data[0]; 2961 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan)); 2962 2963 return 1; 2964} 2965 2966static int ni_ao_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 2967 struct comedi_insn *insn, unsigned int *data) 2968{ 2969 switch (data[0]) { 2970 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE: 2971 switch (data[1]) 2972 { 2973 case COMEDI_OUTPUT: 2974 data[2] = 1 + boardtype.ao_fifo_depth * sizeof(short); 2975 if (devpriv->mite) data[2] += devpriv->mite->fifo_size; 2976 break; 2977 case COMEDI_INPUT: 2978 data[2] = 0; 2979 break; 2980 default: 2981 return -EINVAL; 2982 break; 2983 } 2984 return 0; 2985 default: 2986 break; 2987 } 2988 2989 return -EINVAL; 2990} 2991 2992static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 2993 unsigned int trignum) 2994{ 2995 int ret; 2996 int interrupt_b_bits; 2997 int i; 2998 static const int timeout = 1000; 2999 3000 if (trignum != 0) 3001 return -EINVAL; 3002 3003 /* Null trig at beginning prevent ao start trigger from executing more than 3004 once per command (and doing things like trying to allocate the ao dma channel 3005 multiple times) */ 3006 s->async->inttrig = NULL; 3007 3008 ni_set_bits(dev, Interrupt_B_Enable_Register, 3009 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0); 3010 interrupt_b_bits = AO_Error_Interrupt_Enable; 3011#ifdef PCIDMA 3012 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear); 3013 if (boardtype.reg_type & ni_reg_6xxx_mask) 3014 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x); 3015 ret = ni_ao_setup_MITE_dma(dev); 3016 if (ret) 3017 return ret; 3018 ret = ni_ao_wait_for_dma_load(dev); 3019 if (ret < 0) 3020 return ret; 3021#else 3022 ret = ni_ao_prep_fifo(dev, s); 3023 if (ret == 0) 3024 return -EPIPE; 3025 3026 interrupt_b_bits |= AO_FIFO_Interrupt_Enable; 3027#endif 3028 3029 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE, 3030 AO_Mode_3_Register); 3031 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3032 /* wait for DACs to be loaded */ 3033 for (i = 0; i < timeout; i++) { 3034 udelay(1); 3035 if ((devpriv->stc_readw(dev, 3036 Joint_Status_2_Register) & 3037 AO_TMRDACWRs_In_Progress_St) == 0) 3038 break; 3039 } 3040 if (i == timeout) { 3041 comedi_error(dev, 3042 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear"); 3043 return -EIO; 3044 } 3045 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */ 3046 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, 3047 Interrupt_B_Ack_Register); 3048 3049 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1); 3050 3051 devpriv->stc_writew(dev, 3052 devpriv-> 3053 ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm | 3054 AO_DAC1_Update_Mode | AO_DAC0_Update_Mode, 3055 AO_Command_1_Register); 3056 3057 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse, 3058 AO_Command_2_Register); 3059 3060 return 0; 3061} 3062 3063static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 3064{ 3065 const struct comedi_cmd *cmd = &s->async->cmd; 3066 int bits; 3067 int i; 3068 unsigned trigvar; 3069 3070 if (dev->irq == 0) { 3071 comedi_error(dev, "cannot run command without an irq"); 3072 return -EIO; 3073 } 3074 3075 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); 3076 3077 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register); 3078 3079 if (boardtype.reg_type & ni_reg_6xxx_mask) { 3080 ao_win_out(CLEAR_WG, AO_Misc_611x); 3081 3082 bits = 0; 3083 for (i = 0; i < cmd->chanlist_len; i++) { 3084 int chan; 3085 3086 chan = CR_CHAN(cmd->chanlist[i]); 3087 bits |= 1 << chan; 3088 ao_win_out(chan, AO_Waveform_Generation_611x); 3089 } 3090 ao_win_out(bits, AO_Timed_611x); 3091 } 3092 3093 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1); 3094 3095 if (cmd->stop_src == TRIG_NONE) { 3096 devpriv->ao_mode1 |= AO_Continuous; 3097 devpriv->ao_mode1 &= ~AO_Trigger_Once; 3098 } else { 3099 devpriv->ao_mode1 &= ~AO_Continuous; 3100 devpriv->ao_mode1 |= AO_Trigger_Once; 3101 } 3102 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3103 switch (cmd->start_src) { 3104 case TRIG_INT: 3105 case TRIG_NOW: 3106 devpriv->ao_trigger_select &= 3107 ~(AO_START1_Polarity | AO_START1_Select(-1)); 3108 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync; 3109 devpriv->stc_writew(dev, devpriv->ao_trigger_select, 3110 AO_Trigger_Select_Register); 3111 break; 3112 case TRIG_EXT: 3113 devpriv->ao_trigger_select = AO_START1_Select(CR_CHAN(cmd->start_arg)+1); 3114 if (cmd->start_arg & CR_INVERT) 3115 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */ 3116 if (cmd->start_arg & CR_EDGE) 3117 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */ 3118 devpriv->stc_writew(dev, devpriv->ao_trigger_select, AO_Trigger_Select_Register); 3119 break; 3120 default: 3121 BUG(); 3122 break; 3123 } 3124 devpriv->ao_mode3 &= ~AO_Trigger_Length; 3125 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3126 3127 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3128 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source; 3129 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3130 if (cmd->stop_src == TRIG_NONE) { 3131 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register); 3132 } else { 3133 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register); 3134 } 3135 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register); 3136 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source; 3137 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3138 switch (cmd->stop_src) { 3139 case TRIG_COUNT: 3140 if (boardtype.reg_type & ni_reg_m_series_mask) 3141 { 3142 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */ 3143 devpriv->stc_writel(dev, cmd->stop_arg - 1, AO_UC_Load_A_Register); 3144 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register); 3145 }else 3146 { 3147 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register); 3148 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register); 3149 devpriv->stc_writel(dev, cmd->stop_arg - 1, 3150 AO_UC_Load_A_Register); 3151 } 3152 break; 3153 case TRIG_NONE: 3154 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); 3155 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register); 3156 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); 3157 break; 3158 default: 3159 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register); 3160 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register); 3161 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register); 3162 } 3163 3164 devpriv->ao_mode1 &= 3165 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity | 3166 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity); 3167 switch (cmd->scan_begin_src) { 3168 case TRIG_TIMER: 3169 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable; 3170 trigvar = 3171 ni_ns_to_timer(dev, cmd->scan_begin_arg, 3172 TRIG_ROUND_NEAREST); 3173 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register); 3174 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register); 3175 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register); 3176 break; 3177 case TRIG_EXT: 3178 devpriv->ao_mode1 |= 3179 AO_UPDATE_Source_Select(cmd->scan_begin_arg); 3180 if (cmd->scan_begin_arg & CR_INVERT) 3181 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity; 3182 devpriv->ao_cmd2 |= AO_BC_Gate_Enable; 3183 break; 3184 default: 3185 BUG(); 3186 break; 3187 } 3188 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); 3189 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3190 devpriv->ao_mode2 &= 3191 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source); 3192 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3193 3194 if (cmd->scan_end_arg > 1) { 3195 devpriv->ao_mode1 |= AO_Multiple_Channels; 3196 devpriv->stc_writew(dev, 3197 AO_Number_Of_Channels(cmd->scan_end_arg - 3198 1) | 3199 AO_UPDATE_Output_Select 3200 (AO_Update_Output_High_Z), 3201 AO_Output_Control_Register); 3202 } else { 3203 unsigned bits; 3204 devpriv->ao_mode1 &= ~AO_Multiple_Channels; 3205 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z); 3206 if (boardtype.reg_type & (ni_reg_m_series_mask | ni_reg_6xxx_mask)) { 3207 bits |= AO_Number_Of_Channels(0); 3208 } else { 3209 bits |= AO_Number_Of_Channels(CR_CHAN(cmd-> 3210 chanlist[0])); 3211 } 3212 devpriv->stc_writew(dev, bits, 3213 AO_Output_Control_Register); 3214 } 3215 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3216 3217 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode, 3218 AO_Command_1_Register); 3219 3220 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error; 3221 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3222 3223 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask; 3224#ifdef PCIDMA 3225 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F; 3226#else 3227 devpriv->ao_mode2 |= AO_FIFO_Mode_HF; 3228#endif 3229 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable; 3230 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3231 3232 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width | 3233 AO_TMRDACWR_Pulse_Width; 3234 if (boardtype.ao_fifo_depth) 3235 bits |= AO_FIFO_Enable; 3236 else 3237 bits |= AO_DMA_PIO_Control; 3238#if 0 3239 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281, 3240 verified with bus analyzer. */ 3241 if (boardtype.reg_type & ni_reg_m_series_mask) 3242 bits |= AO_Number_Of_DAC_Packages; 3243#endif 3244 devpriv->stc_writew(dev, bits, AO_Personal_Register); 3245 /* enable sending of ao dma requests */ 3246 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register); 3247 3248 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); 3249 3250 if (cmd->stop_src == TRIG_COUNT) { 3251 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack, 3252 Interrupt_B_Ack_Register); 3253 ni_set_bits(dev, Interrupt_B_Enable_Register, 3254 AO_BC_TC_Interrupt_Enable, 1); 3255 } 3256 3257 s->async->inttrig = &ni_ao_inttrig; 3258 3259 return 0; 3260} 3261 3262static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 3263 struct comedi_cmd *cmd) 3264{ 3265 int err = 0; 3266 int tmp; 3267 3268 /* step 1: make sure trigger sources are trivially valid */ 3269 3270 if ((cmd->flags & CMDF_WRITE) == 0) { 3271 cmd->flags |= CMDF_WRITE; 3272 } 3273 3274 tmp = cmd->start_src; 3275 cmd->start_src &= TRIG_INT | TRIG_EXT; 3276 if (!cmd->start_src || tmp != cmd->start_src) 3277 err++; 3278 3279 tmp = cmd->scan_begin_src; 3280 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; 3281 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 3282 err++; 3283 3284 tmp = cmd->convert_src; 3285 cmd->convert_src &= TRIG_NOW; 3286 if (!cmd->convert_src || tmp != cmd->convert_src) 3287 err++; 3288 3289 tmp = cmd->scan_end_src; 3290 cmd->scan_end_src &= TRIG_COUNT; 3291 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 3292 err++; 3293 3294 tmp = cmd->stop_src; 3295 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 3296 if (!cmd->stop_src || tmp != cmd->stop_src) 3297 err++; 3298 3299 if (err) 3300 return 1; 3301 3302 /* step 2: make sure trigger sources are unique and mutually compatible */ 3303 3304 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 3305 err++; 3306 3307 if (err) 3308 return 2; 3309 3310 /* step 3: make sure arguments are trivially compatible */ 3311 3312 if (cmd->start_src == TRIG_EXT) { 3313 /* external trigger */ 3314 unsigned int tmp = CR_CHAN(cmd->start_arg); 3315 3316 if (tmp > 18) 3317 tmp = 18; 3318 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE)); 3319 if (cmd->start_arg != tmp) { 3320 cmd->start_arg = tmp; 3321 err++; 3322 } 3323 } else { 3324 if (cmd->start_arg != 0) { 3325 /* true for both TRIG_NOW and TRIG_INT */ 3326 cmd->start_arg = 0; 3327 err++; 3328 } 3329 } 3330 if (cmd->scan_begin_src == TRIG_TIMER) { 3331 if (cmd->scan_begin_arg < boardtype.ao_speed) { 3332 cmd->scan_begin_arg = boardtype.ao_speed; 3333 err++; 3334 } 3335 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) { /* XXX check */ 3336 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff; 3337 err++; 3338 } 3339 } 3340 if (cmd->convert_arg != 0) { 3341 cmd->convert_arg = 0; 3342 err++; 3343 } 3344 if (cmd->scan_end_arg != cmd->chanlist_len) { 3345 cmd->scan_end_arg = cmd->chanlist_len; 3346 err++; 3347 } 3348 if (cmd->stop_src == TRIG_COUNT) { /* XXX check */ 3349 if (cmd->stop_arg > 0x00ffffff) { 3350 cmd->stop_arg = 0x00ffffff; 3351 err++; 3352 } 3353 } else { 3354 /* TRIG_NONE */ 3355 if (cmd->stop_arg != 0) { 3356 cmd->stop_arg = 0; 3357 err++; 3358 } 3359 } 3360 3361 if (err) 3362 return 3; 3363 3364 /* step 4: fix up any arguments */ 3365 if (cmd->scan_begin_src == TRIG_TIMER) { 3366 tmp = cmd->scan_begin_arg; 3367 cmd->scan_begin_arg = 3368 ni_timer_to_ns(dev, ni_ns_to_timer(dev, 3369 cmd->scan_begin_arg, 3370 cmd->flags & TRIG_ROUND_MASK)); 3371 if (tmp != cmd->scan_begin_arg) 3372 err++; 3373 } 3374 if (err) 3375 return 4; 3376 3377 /* step 5: fix up chanlist */ 3378 3379 if (err) 3380 return 5; 3381 3382 return 0; 3383} 3384 3385static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) 3386{ 3387 /* devpriv->ao0p=0x0000; */ 3388 /* ni_writew(devpriv->ao0p,AO_Configuration); */ 3389 3390 /* devpriv->ao1p=AO_Channel(1); */ 3391 /* ni_writew(devpriv->ao1p,AO_Configuration); */ 3392 3393 ni_release_ao_mite_channel(dev); 3394 3395 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); 3396 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register); 3397 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0); 3398 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register); 3399 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register); 3400 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width | 3401 AO_TMRDACWR_Pulse_Width, AO_Personal_Register); 3402 devpriv->stc_writew(dev, 0, AO_Output_Control_Register); 3403 devpriv->stc_writew(dev, 0, AO_Start_Select_Register); 3404 devpriv->ao_cmd1 = 0; 3405 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register); 3406 devpriv->ao_cmd2 = 0; 3407 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); 3408 devpriv->ao_mode1 = 0; 3409 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3410 devpriv->ao_mode2 = 0; 3411 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3412 if (boardtype.reg_type & ni_reg_m_series_mask) 3413 devpriv->ao_mode3 = AO_Last_Gate_Disable; 3414 else 3415 devpriv->ao_mode3 = 0; 3416 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3417 devpriv->ao_trigger_select = 0; 3418 devpriv->stc_writew(dev, devpriv->ao_trigger_select, 3419 AO_Trigger_Select_Register); 3420 if (boardtype.reg_type & ni_reg_6xxx_mask) { 3421 unsigned immediate_bits = 0; 3422 unsigned i; 3423 for (i = 0; i < s->n_chan; ++i) 3424 { 3425 immediate_bits |= 1 << i; 3426 } 3427 ao_win_out(immediate_bits, AO_Immediate_671x); 3428 ao_win_out(CLEAR_WG, AO_Misc_611x); 3429 } 3430 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); 3431 3432 return 0; 3433} 3434 3435/* digital io */ 3436 3437static int ni_dio_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 3438 struct comedi_insn *insn, unsigned int *data) 3439{ 3440#ifdef DEBUG_DIO 3441 printk("ni_dio_insn_config() chan=%d io=%d\n", 3442 CR_CHAN(insn->chanspec), data[0]); 3443#endif 3444 switch (data[0]) { 3445 case INSN_CONFIG_DIO_OUTPUT: 3446 s->io_bits |= 1 << CR_CHAN(insn->chanspec); 3447 break; 3448 case INSN_CONFIG_DIO_INPUT: 3449 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec)); 3450 break; 3451 case INSN_CONFIG_DIO_QUERY: 3452 data[1] = 3453 (s->io_bits & (1 << CR_CHAN(insn-> 3454 chanspec))) ? COMEDI_OUTPUT : 3455 COMEDI_INPUT; 3456 return insn->n; 3457 break; 3458 default: 3459 return -EINVAL; 3460 } 3461 3462 devpriv->dio_control &= ~DIO_Pins_Dir_Mask; 3463 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits); 3464 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 3465 3466 return 1; 3467} 3468 3469static int ni_dio_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, 3470 struct comedi_insn *insn, unsigned int *data) 3471{ 3472#ifdef DEBUG_DIO 3473 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]); 3474#endif 3475 if (insn->n != 2) 3476 return -EINVAL; 3477 if (data[0]) { 3478 /* Perform check to make sure we're not using the 3479 serial part of the dio */ 3480 if ((data[0] & (DIO_SDIN | DIO_SDOUT)) 3481 && devpriv->serial_interval_ns) 3482 return -EBUSY; 3483 3484 s->state &= ~data[0]; 3485 s->state |= (data[0] & data[1]); 3486 devpriv->dio_output &= ~DIO_Parallel_Data_Mask; 3487 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state); 3488 devpriv->stc_writew(dev, devpriv->dio_output, 3489 DIO_Output_Register); 3490 } 3491 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register); 3492 3493 return 2; 3494} 3495 3496static int ni_m_series_dio_insn_config(struct comedi_device *dev, 3497 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) 3498{ 3499#ifdef DEBUG_DIO 3500 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n", 3501 CR_CHAN(insn->chanspec), data[0]); 3502#endif 3503 switch (data[0]) { 3504 case INSN_CONFIG_DIO_OUTPUT: 3505 s->io_bits |= 1 << CR_CHAN(insn->chanspec); 3506 break; 3507 case INSN_CONFIG_DIO_INPUT: 3508 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec)); 3509 break; 3510 case INSN_CONFIG_DIO_QUERY: 3511 data[1] = 3512 (s->io_bits & (1 << CR_CHAN(insn-> 3513 chanspec))) ? COMEDI_OUTPUT : 3514 COMEDI_INPUT; 3515 return insn->n; 3516 break; 3517 default: 3518 return -EINVAL; 3519 } 3520 3521 ni_writel(s->io_bits, M_Offset_DIO_Direction); 3522 3523 return 1; 3524} 3525 3526static int ni_m_series_dio_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, 3527 struct comedi_insn *insn, unsigned int *data) 3528{ 3529#ifdef DEBUG_DIO 3530 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], 3531 data[1]); 3532#endif 3533 if (insn->n != 2) 3534 return -EINVAL; 3535 if (data[0]) { 3536 s->state &= ~data[0]; 3537 s->state |= (data[0] & data[1]); 3538 ni_writel(s->state, M_Offset_Static_Digital_Output); 3539 } 3540 data[1] = ni_readl(M_Offset_Static_Digital_Input); 3541 3542 return 2; 3543} 3544 3545static int ni_cdio_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 3546 struct comedi_cmd *cmd) 3547{ 3548 int err = 0; 3549 int tmp; 3550 int sources; 3551 unsigned i; 3552 3553 /* step 1: make sure trigger sources are trivially valid */ 3554 3555 tmp = cmd->start_src; 3556 sources = TRIG_INT; 3557 cmd->start_src &= sources; 3558 if (!cmd->start_src || tmp != cmd->start_src) 3559 err++; 3560 3561 tmp = cmd->scan_begin_src; 3562 cmd->scan_begin_src &= TRIG_EXT; 3563 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 3564 err++; 3565 3566 tmp = cmd->convert_src; 3567 cmd->convert_src &= TRIG_NOW; 3568 if (!cmd->convert_src || tmp != cmd->convert_src) 3569 err++; 3570 3571 tmp = cmd->scan_end_src; 3572 cmd->scan_end_src &= TRIG_COUNT; 3573 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 3574 err++; 3575 3576 tmp = cmd->stop_src; 3577 cmd->stop_src &= TRIG_NONE; 3578 if (!cmd->stop_src || tmp != cmd->stop_src) 3579 err++; 3580 3581 if (err) 3582 return 1; 3583 3584 /* step 2: make sure trigger sources are unique... */ 3585 3586 if (cmd->start_src != TRIG_INT) 3587 err++; 3588 if (cmd->scan_begin_src != TRIG_EXT) 3589 err++; 3590 if (cmd->convert_src != TRIG_NOW) 3591 err++; 3592 if (cmd->stop_src != TRIG_NONE) 3593 err++; 3594 /* ... and mutually compatible */ 3595 3596 if (err) 3597 return 2; 3598 3599 /* step 3: make sure arguments are trivially compatible */ 3600 if (cmd->start_src == TRIG_INT) { 3601 if (cmd->start_arg != 0) { 3602 cmd->start_arg = 0; 3603 err++; 3604 } 3605 } 3606 if (cmd->scan_begin_src == TRIG_EXT) { 3607 tmp = cmd->scan_begin_arg; 3608 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, 3609 CR_INVERT); 3610 if (tmp != cmd->scan_begin_arg) { 3611 err++; 3612 } 3613 } 3614 if (cmd->convert_src == TRIG_NOW) { 3615 if (cmd->convert_arg) { 3616 cmd->convert_arg = 0; 3617 err++; 3618 } 3619 } 3620 3621 if (cmd->scan_end_arg != cmd->chanlist_len) { 3622 cmd->scan_end_arg = cmd->chanlist_len; 3623 err++; 3624 } 3625 3626 if (cmd->stop_src == TRIG_NONE) { 3627 if (cmd->stop_arg != 0) { 3628 cmd->stop_arg = 0; 3629 err++; 3630 } 3631 } 3632 3633 if (err) 3634 return 3; 3635 3636 /* step 4: fix up any arguments */ 3637 3638 if (err) 3639 return 4; 3640 3641 /* step 5: check chanlist */ 3642 3643 for (i = 0; i < cmd->chanlist_len; ++i) { 3644 if (cmd->chanlist[i] != i) 3645 err = 1; 3646 } 3647 3648 if (err) 3649 return 5; 3650 3651 return 0; 3652} 3653 3654static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 3655{ 3656 const struct comedi_cmd *cmd = &s->async->cmd; 3657 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit; 3658 int retval; 3659 3660 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command); 3661 switch (cmd->scan_begin_src) { 3662 case TRIG_EXT: 3663 cdo_mode_bits |= 3664 CR_CHAN(cmd-> 3665 scan_begin_arg) & CDO_Sample_Source_Select_Mask; 3666 break; 3667 default: 3668 BUG(); 3669 break; 3670 } 3671 if (cmd->scan_begin_arg & CR_INVERT) 3672 cdo_mode_bits |= CDO_Polarity_Bit; 3673 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode); 3674 if (s->io_bits) { 3675 ni_writel(s->state, M_Offset_CDO_FIFO_Data); 3676 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command); 3677 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable); 3678 } else { 3679 comedi_error(dev, 3680 "attempted to run digital output command with no lines configured as outputs"); 3681 return -EIO; 3682 } 3683 retval = ni_request_cdo_mite_channel(dev); 3684 if (retval < 0) { 3685 return retval; 3686 } 3687 s->async->inttrig = &ni_cdo_inttrig; 3688 return 0; 3689} 3690 3691static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 3692 unsigned int trignum) 3693{ 3694#ifdef PCIDMA 3695 unsigned long flags; 3696#endif 3697 int retval = 0; 3698 unsigned i; 3699 const unsigned timeout = 100; 3700 3701 s->async->inttrig = NULL; 3702 3703 /* read alloc the entire buffer */ 3704 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz); 3705 3706#ifdef PCIDMA 3707 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 3708 if (devpriv->cdo_mite_chan) { 3709 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32); 3710 mite_dma_arm(devpriv->cdo_mite_chan); 3711 } else { 3712 comedi_error(dev, "BUG: no cdo mite channel?"); 3713 retval = -EIO; 3714 } 3715 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 3716 if (retval < 0) 3717 return retval; 3718#endif 3719/* 3720* XXX not sure what interrupt C group does 3721* ni_writeb(Interrupt_Group_C_Enable_Bit, 3722* M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo 3723*/ 3724 for (i = 0; i < timeout; ++i) { 3725 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit) 3726 break; 3727 udelay(10); 3728 } 3729 if (i == timeout) { 3730 comedi_error(dev, "dma failed to fill cdo fifo!"); 3731 ni_cdio_cancel(dev, s); 3732 return -EIO; 3733 } 3734 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit | 3735 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit, M_Offset_CDIO_Command); 3736 return retval; 3737} 3738 3739static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 3740{ 3741 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit | 3742 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit | 3743 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit, 3744 M_Offset_CDIO_Command); 3745/* 3746* XXX not sure what interrupt C group does ni_writeb(0, 3747* M_Offset_Interrupt_C_Enable); 3748*/ 3749 ni_writel(0, M_Offset_CDO_Mask_Enable); 3750 ni_release_cdo_mite_channel(dev); 3751 return 0; 3752} 3753 3754static void handle_cdio_interrupt(struct comedi_device *dev) 3755{ 3756 unsigned cdio_status; 3757 struct comedi_subdevice *s = dev->subdevices + NI_DIO_SUBDEV; 3758#ifdef PCIDMA 3759 unsigned long flags; 3760#endif 3761 3762 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) { 3763 return; 3764 } 3765#ifdef PCIDMA 3766 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 3767 if (devpriv->cdo_mite_chan) { 3768 unsigned cdo_mite_status = 3769 mite_get_status(devpriv->cdo_mite_chan); 3770 if (cdo_mite_status & CHSR_LINKC) { 3771 writel(CHOR_CLRLC, 3772 devpriv->mite->mite_io_addr + 3773 MITE_CHOR(devpriv->cdo_mite_chan->channel)); 3774 } 3775 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async); 3776 } 3777 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 3778#endif 3779 3780 cdio_status = ni_readl(M_Offset_CDIO_Status); 3781 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) { 3782/* printk("cdio error: statux=0x%x\n", cdio_status); */ 3783 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */ 3784 s->async->events |= COMEDI_CB_OVERFLOW; 3785 } 3786 if (cdio_status & CDO_FIFO_Empty_Bit) { 3787/* printk("cdio fifo empty\n"); */ 3788 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit, 3789 M_Offset_CDIO_Command); 3790/* s->async->events |= COMEDI_CB_EOA; */ 3791 } 3792 ni_event(dev, s); 3793} 3794 3795static int ni_serial_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 3796 struct comedi_insn *insn, unsigned int *data) 3797{ 3798 int err = insn->n; 3799 unsigned char byte_out, byte_in = 0; 3800 3801 if (insn->n != 2) 3802 return -EINVAL; 3803 3804 switch (data[0]) { 3805 case INSN_CONFIG_SERIAL_CLOCK: 3806 3807#ifdef DEBUG_DIO 3808 printk("SPI serial clock Config cd\n", data[1]); 3809#endif 3810 devpriv->serial_hw_mode = 1; 3811 devpriv->dio_control |= DIO_HW_Serial_Enable; 3812 3813 if (data[1] == SERIAL_DISABLED) { 3814 devpriv->serial_hw_mode = 0; 3815 devpriv->dio_control &= ~(DIO_HW_Serial_Enable | 3816 DIO_Software_Serial_Control); 3817 data[1] = SERIAL_DISABLED; 3818 devpriv->serial_interval_ns = data[1]; 3819 } else if (data[1] <= SERIAL_600NS) { 3820 /* Warning: this clock speed is too fast to reliably 3821 control SCXI. */ 3822 devpriv->dio_control &= ~DIO_HW_Serial_Timebase; 3823 devpriv->clock_and_fout |= Slow_Internal_Timebase; 3824 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2; 3825 data[1] = SERIAL_600NS; 3826 devpriv->serial_interval_ns = data[1]; 3827 } else if (data[1] <= SERIAL_1_2US) { 3828 devpriv->dio_control &= ~DIO_HW_Serial_Timebase; 3829 devpriv->clock_and_fout |= Slow_Internal_Timebase | 3830 DIO_Serial_Out_Divide_By_2; 3831 data[1] = SERIAL_1_2US; 3832 devpriv->serial_interval_ns = data[1]; 3833 } else if (data[1] <= SERIAL_10US) { 3834 devpriv->dio_control |= DIO_HW_Serial_Timebase; 3835 devpriv->clock_and_fout |= Slow_Internal_Timebase | 3836 DIO_Serial_Out_Divide_By_2; 3837 /* Note: DIO_Serial_Out_Divide_By_2 only affects 3838 600ns/1.2us. If you turn divide_by_2 off with the 3839 slow clock, you will still get 10us, except then 3840 all your delays are wrong. */ 3841 data[1] = SERIAL_10US; 3842 devpriv->serial_interval_ns = data[1]; 3843 } else { 3844 devpriv->dio_control &= ~(DIO_HW_Serial_Enable | 3845 DIO_Software_Serial_Control); 3846 devpriv->serial_hw_mode = 0; 3847 data[1] = (data[1] / 1000) * 1000; 3848 devpriv->serial_interval_ns = data[1]; 3849 } 3850 3851 devpriv->stc_writew(dev, devpriv->dio_control, 3852 DIO_Control_Register); 3853 devpriv->stc_writew(dev, devpriv->clock_and_fout, 3854 Clock_and_FOUT_Register); 3855 return 1; 3856 3857 break; 3858 3859 case INSN_CONFIG_BIDIRECTIONAL_DATA: 3860 3861 if (devpriv->serial_interval_ns == 0) { 3862 return -EINVAL; 3863 } 3864 3865 byte_out = data[1] & 0xFF; 3866 3867 if (devpriv->serial_hw_mode) { 3868 err = ni_serial_hw_readwrite8(dev, s, byte_out, 3869 &byte_in); 3870 } else if (devpriv->serial_interval_ns > 0) { 3871 err = ni_serial_sw_readwrite8(dev, s, byte_out, 3872 &byte_in); 3873 } else { 3874 printk("ni_serial_insn_config: serial disabled!\n"); 3875 return -EINVAL; 3876 } 3877 if (err < 0) 3878 return err; 3879 data[1] = byte_in & 0xFF; 3880 return insn->n; 3881 3882 break; 3883 default: 3884 return -EINVAL; 3885 } 3886 3887} 3888 3889static int ni_serial_hw_readwrite8(struct comedi_device *dev, struct comedi_subdevice *s, 3890 unsigned char data_out, unsigned char *data_in) 3891{ 3892 unsigned int status1; 3893 int err = 0, count = 20; 3894 3895#ifdef DEBUG_DIO 3896 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out); 3897#endif 3898 3899 devpriv->dio_output &= ~DIO_Serial_Data_Mask; 3900 devpriv->dio_output |= DIO_Serial_Data_Out(data_out); 3901 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register); 3902 3903 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register); 3904 if (status1 & DIO_Serial_IO_In_Progress_St) { 3905 err = -EBUSY; 3906 goto Error; 3907 } 3908 3909 devpriv->dio_control |= DIO_HW_Serial_Start; 3910 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 3911 devpriv->dio_control &= ~DIO_HW_Serial_Start; 3912 3913 /* Wait until STC says we're done, but don't loop infinitely. */ 3914 while ((status1 = 3915 devpriv->stc_readw(dev, 3916 Joint_Status_1_Register)) & 3917 DIO_Serial_IO_In_Progress_St) { 3918 /* Delay one bit per loop */ 3919 udelay((devpriv->serial_interval_ns + 999) / 1000); 3920 if (--count < 0) { 3921 printk 3922 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n"); 3923 err = -ETIME; 3924 goto Error; 3925 } 3926 } 3927 3928 /* Delay for last bit. This delay is absolutely necessary, because 3929 DIO_Serial_IO_In_Progress_St goes high one bit too early. */ 3930 udelay((devpriv->serial_interval_ns + 999) / 1000); 3931 3932 if (data_in != NULL) { 3933 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register); 3934#ifdef DEBUG_DIO 3935 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in); 3936#endif 3937 } 3938 3939 Error: 3940 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 3941 3942 return err; 3943} 3944 3945static int ni_serial_sw_readwrite8(struct comedi_device *dev, struct comedi_subdevice *s, 3946 unsigned char data_out, unsigned char *data_in) 3947{ 3948 unsigned char mask, input = 0; 3949 3950#ifdef DEBUG_DIO 3951 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out); 3952#endif 3953 3954 /* Wait for one bit before transfer */ 3955 udelay((devpriv->serial_interval_ns + 999) / 1000); 3956 3957 for (mask = 0x80; mask; mask >>= 1) { 3958 /* Output current bit; note that we cannot touch s->state 3959 because it is a per-subdevice field, and serial is 3960 a separate subdevice from DIO. */ 3961 devpriv->dio_output &= ~DIO_SDOUT; 3962 if (data_out & mask) { 3963 devpriv->dio_output |= DIO_SDOUT; 3964 } 3965 devpriv->stc_writew(dev, devpriv->dio_output, 3966 DIO_Output_Register); 3967 3968 /* Assert SDCLK (active low, inverted), wait for half of 3969 the delay, deassert SDCLK, and wait for the other half. */ 3970 devpriv->dio_control |= DIO_Software_Serial_Control; 3971 devpriv->stc_writew(dev, devpriv->dio_control, 3972 DIO_Control_Register); 3973 3974 udelay((devpriv->serial_interval_ns + 999) / 2000); 3975 3976 devpriv->dio_control &= ~DIO_Software_Serial_Control; 3977 devpriv->stc_writew(dev, devpriv->dio_control, 3978 DIO_Control_Register); 3979 3980 udelay((devpriv->serial_interval_ns + 999) / 2000); 3981 3982 /* Input current bit */ 3983 if (devpriv->stc_readw(dev, 3984 DIO_Parallel_Input_Register) & DIO_SDIN) { 3985/* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */ 3986 input |= mask; 3987 } 3988 } 3989#ifdef DEBUG_DIO 3990 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input); 3991#endif 3992 if (data_in) 3993 *data_in = input; 3994 3995 return 0; 3996} 3997 3998static void mio_common_detach(struct comedi_device *dev) 3999{ 4000 if (dev->private) { 4001 if (devpriv->counter_dev) { 4002 ni_gpct_device_destroy(devpriv->counter_dev); 4003 } 4004 } 4005 if (dev->subdevices && boardtype.has_8255) 4006 subdev_8255_cleanup(dev, dev->subdevices + NI_8255_DIO_SUBDEV); 4007} 4008 4009static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s) 4010{ 4011 int i; 4012 4013 for (i = 0; i < s->n_chan; i++) 4014 { 4015 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, 4016 AO_Configuration_2_67xx); 4017 } 4018 ao_win_out(0x0, AO_Later_Single_Point_Updates); 4019} 4020 4021static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg) 4022{ 4023 unsigned stc_register; 4024 switch (reg) { 4025 case NITIO_G0_Autoincrement_Reg: 4026 stc_register = G_Autoincrement_Register(0); 4027 break; 4028 case NITIO_G1_Autoincrement_Reg: 4029 stc_register = G_Autoincrement_Register(1); 4030 break; 4031 case NITIO_G0_Command_Reg: 4032 stc_register = G_Command_Register(0); 4033 break; 4034 case NITIO_G1_Command_Reg: 4035 stc_register = G_Command_Register(1); 4036 break; 4037 case NITIO_G0_HW_Save_Reg: 4038 stc_register = G_HW_Save_Register(0); 4039 break; 4040 case NITIO_G1_HW_Save_Reg: 4041 stc_register = G_HW_Save_Register(1); 4042 break; 4043 case NITIO_G0_SW_Save_Reg: 4044 stc_register = G_Save_Register(0); 4045 break; 4046 case NITIO_G1_SW_Save_Reg: 4047 stc_register = G_Save_Register(1); 4048 break; 4049 case NITIO_G0_Mode_Reg: 4050 stc_register = G_Mode_Register(0); 4051 break; 4052 case NITIO_G1_Mode_Reg: 4053 stc_register = G_Mode_Register(1); 4054 break; 4055 case NITIO_G0_LoadA_Reg: 4056 stc_register = G_Load_A_Register(0); 4057 break; 4058 case NITIO_G1_LoadA_Reg: 4059 stc_register = G_Load_A_Register(1); 4060 break; 4061 case NITIO_G0_LoadB_Reg: 4062 stc_register = G_Load_B_Register(0); 4063 break; 4064 case NITIO_G1_LoadB_Reg: 4065 stc_register = G_Load_B_Register(1); 4066 break; 4067 case NITIO_G0_Input_Select_Reg: 4068 stc_register = G_Input_Select_Register(0); 4069 break; 4070 case NITIO_G1_Input_Select_Reg: 4071 stc_register = G_Input_Select_Register(1); 4072 break; 4073 case NITIO_G01_Status_Reg: 4074 stc_register = G_Status_Register; 4075 break; 4076 case NITIO_G01_Joint_Reset_Reg: 4077 stc_register = Joint_Reset_Register; 4078 break; 4079 case NITIO_G01_Joint_Status1_Reg: 4080 stc_register = Joint_Status_1_Register; 4081 break; 4082 case NITIO_G01_Joint_Status2_Reg: 4083 stc_register = Joint_Status_2_Register; 4084 break; 4085 case NITIO_G0_Interrupt_Acknowledge_Reg: 4086 stc_register = Interrupt_A_Ack_Register; 4087 break; 4088 case NITIO_G1_Interrupt_Acknowledge_Reg: 4089 stc_register = Interrupt_B_Ack_Register; 4090 break; 4091 case NITIO_G0_Status_Reg: 4092 stc_register = AI_Status_1_Register; 4093 break; 4094 case NITIO_G1_Status_Reg: 4095 stc_register = AO_Status_1_Register; 4096 break; 4097 case NITIO_G0_Interrupt_Enable_Reg: 4098 stc_register = Interrupt_A_Enable_Register; 4099 break; 4100 case NITIO_G1_Interrupt_Enable_Reg: 4101 stc_register = Interrupt_B_Enable_Register; 4102 break; 4103 default: 4104 printk("%s: unhandled register 0x%x in switch.\n", 4105 __func__, reg); 4106 BUG(); 4107 return 0; 4108 break; 4109 } 4110 return stc_register; 4111} 4112 4113static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, 4114 enum ni_gpct_register reg) 4115{ 4116 struct comedi_device *dev = counter->counter_dev->dev; 4117 unsigned stc_register; 4118 /* bits in the join reset register which are relevant to counters */ 4119 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset; 4120 static const unsigned gpct_interrupt_a_enable_mask = 4121 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable; 4122 static const unsigned gpct_interrupt_b_enable_mask = 4123 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable; 4124 4125 switch (reg) { 4126 /* m-series-only registers */ 4127 case NITIO_G0_Counting_Mode_Reg: 4128 ni_writew(bits, M_Offset_G0_Counting_Mode); 4129 break; 4130 case NITIO_G1_Counting_Mode_Reg: 4131 ni_writew(bits, M_Offset_G1_Counting_Mode); 4132 break; 4133 case NITIO_G0_Second_Gate_Reg: 4134 ni_writew(bits, M_Offset_G0_Second_Gate); 4135 break; 4136 case NITIO_G1_Second_Gate_Reg: 4137 ni_writew(bits, M_Offset_G1_Second_Gate); 4138 break; 4139 case NITIO_G0_DMA_Config_Reg: 4140 ni_writew(bits, M_Offset_G0_DMA_Config); 4141 break; 4142 case NITIO_G1_DMA_Config_Reg: 4143 ni_writew(bits, M_Offset_G1_DMA_Config); 4144 break; 4145 case NITIO_G0_ABZ_Reg: 4146 ni_writew(bits, M_Offset_G0_MSeries_ABZ); 4147 break; 4148 case NITIO_G1_ABZ_Reg: 4149 ni_writew(bits, M_Offset_G1_MSeries_ABZ); 4150 break; 4151 4152 /* 32 bit registers */ 4153 case NITIO_G0_LoadA_Reg: 4154 case NITIO_G1_LoadA_Reg: 4155 case NITIO_G0_LoadB_Reg: 4156 case NITIO_G1_LoadB_Reg: 4157 stc_register = ni_gpct_to_stc_register(reg); 4158 devpriv->stc_writel(dev, bits, stc_register); 4159 break; 4160 4161 /* 16 bit registers */ 4162 case NITIO_G0_Interrupt_Enable_Reg: 4163 BUG_ON(bits & ~gpct_interrupt_a_enable_mask); 4164 ni_set_bitfield(dev, Interrupt_A_Enable_Register, 4165 gpct_interrupt_a_enable_mask, bits); 4166 break; 4167 case NITIO_G1_Interrupt_Enable_Reg: 4168 BUG_ON(bits & ~gpct_interrupt_b_enable_mask); 4169 ni_set_bitfield(dev, Interrupt_B_Enable_Register, 4170 gpct_interrupt_b_enable_mask, bits); 4171 break; 4172 case NITIO_G01_Joint_Reset_Reg: 4173 BUG_ON(bits & ~gpct_joint_reset_mask); 4174 /* fall-through */ 4175 default: 4176 stc_register = ni_gpct_to_stc_register(reg); 4177 devpriv->stc_writew(dev, bits, stc_register); 4178 } 4179} 4180 4181static unsigned ni_gpct_read_register(struct ni_gpct *counter, 4182 enum ni_gpct_register reg) 4183{ 4184 struct comedi_device *dev = counter->counter_dev->dev; 4185 unsigned stc_register; 4186 switch (reg) { 4187 /* m-series only registers */ 4188 case NITIO_G0_DMA_Status_Reg: 4189 return ni_readw(M_Offset_G0_DMA_Status); 4190 break; 4191 case NITIO_G1_DMA_Status_Reg: 4192 return ni_readw(M_Offset_G1_DMA_Status); 4193 break; 4194 4195 /* 32 bit registers */ 4196 case NITIO_G0_HW_Save_Reg: 4197 case NITIO_G1_HW_Save_Reg: 4198 case NITIO_G0_SW_Save_Reg: 4199 case NITIO_G1_SW_Save_Reg: 4200 stc_register = ni_gpct_to_stc_register(reg); 4201 return devpriv->stc_readl(dev, stc_register); 4202 break; 4203 4204 /* 16 bit registers */ 4205 default: 4206 stc_register = ni_gpct_to_stc_register(reg); 4207 return devpriv->stc_readw(dev, stc_register); 4208 break; 4209 } 4210 return 0; 4211} 4212 4213static int ni_freq_out_insn_read(struct comedi_device *dev, 4214 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) 4215{ 4216 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask; 4217 return 1; 4218} 4219 4220static int ni_freq_out_insn_write(struct comedi_device *dev, 4221 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) 4222{ 4223 devpriv->clock_and_fout &= ~FOUT_Enable; 4224 devpriv->stc_writew(dev, devpriv->clock_and_fout, 4225 Clock_and_FOUT_Register); 4226 devpriv->clock_and_fout &= ~FOUT_Divider_mask; 4227 devpriv->clock_and_fout |= FOUT_Divider(data[0]); 4228 devpriv->clock_and_fout |= FOUT_Enable; 4229 devpriv->stc_writew(dev, devpriv->clock_and_fout, 4230 Clock_and_FOUT_Register); 4231 return insn->n; 4232} 4233 4234static int ni_set_freq_out_clock(struct comedi_device *dev, unsigned int clock_source) 4235{ 4236 switch (clock_source) { 4237 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC: 4238 devpriv->clock_and_fout &= ~FOUT_Timebase_Select; 4239 break; 4240 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC: 4241 devpriv->clock_and_fout |= FOUT_Timebase_Select; 4242 break; 4243 default: 4244 return -EINVAL; 4245 } 4246 devpriv->stc_writew(dev, devpriv->clock_and_fout, 4247 Clock_and_FOUT_Register); 4248 return 3; 4249} 4250 4251static void ni_get_freq_out_clock(struct comedi_device *dev, unsigned int *clock_source, 4252 unsigned int *clock_period_ns) 4253{ 4254 if (devpriv->clock_and_fout & FOUT_Timebase_Select) { 4255 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC; 4256 *clock_period_ns = TIMEBASE_2_NS; 4257 } else { 4258 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC; 4259 *clock_period_ns = TIMEBASE_1_NS * 2; 4260 } 4261} 4262 4263static int ni_freq_out_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 4264 struct comedi_insn *insn, unsigned int *data) 4265{ 4266 switch (data[0]) { 4267 case INSN_CONFIG_SET_CLOCK_SRC: 4268 return ni_set_freq_out_clock(dev, data[1]); 4269 break; 4270 case INSN_CONFIG_GET_CLOCK_SRC: 4271 ni_get_freq_out_clock(dev, &data[1], &data[2]); 4272 return 3; 4273 default: 4274 break; 4275 } 4276 return -EINVAL; 4277} 4278 4279static int ni_alloc_private(struct comedi_device *dev) 4280{ 4281 int ret; 4282 4283 ret = alloc_private(dev, sizeof(struct ni_private)); 4284 if (ret < 0) 4285 return ret; 4286 4287 spin_lock_init(&devpriv->window_lock); 4288 spin_lock_init(&devpriv->soft_reg_copy_lock); 4289 spin_lock_init(&devpriv->mite_channel_lock); 4290 4291 return 0; 4292}; 4293 4294static int ni_E_init(struct comedi_device *dev, struct comedi_devconfig *it) 4295{ 4296 struct comedi_subdevice *s; 4297 unsigned j; 4298 enum ni_gpct_variant counter_variant; 4299 4300 if (boardtype.n_aochan > MAX_N_AO_CHAN) { 4301 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n"); 4302 return -EINVAL; 4303 } 4304 4305 if (alloc_subdevices(dev, NI_NUM_SUBDEVICES) < 0) 4306 return -ENOMEM; 4307 4308 /* analog input subdevice */ 4309 4310 s = dev->subdevices + NI_AI_SUBDEV; 4311 dev->read_subdev = s; 4312 if (boardtype.n_adchan) { 4313 s->type = COMEDI_SUBD_AI; 4314 s->subdev_flags = 4315 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ; 4316 if (boardtype.reg_type != ni_reg_611x) 4317 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER; 4318 if (boardtype.adbits > 16) 4319 s->subdev_flags |= SDF_LSAMPL; 4320 if (boardtype.reg_type & ni_reg_m_series_mask) 4321 s->subdev_flags |= SDF_SOFT_CALIBRATED; 4322 s->n_chan = boardtype.n_adchan; 4323 s->len_chanlist = 512; 4324 s->maxdata = (1 << boardtype.adbits) - 1; 4325 s->range_table = ni_range_lkup[boardtype.gainlkup]; 4326 s->insn_read = &ni_ai_insn_read; 4327 s->insn_config = &ni_ai_insn_config; 4328 s->do_cmdtest = &ni_ai_cmdtest; 4329 s->do_cmd = &ni_ai_cmd; 4330 s->cancel = &ni_ai_reset; 4331 s->poll = &ni_ai_poll; 4332 s->munge = &ni_ai_munge; 4333#ifdef PCIDMA 4334 s->async_dma_dir = DMA_FROM_DEVICE; 4335#endif 4336 } else { 4337 s->type = COMEDI_SUBD_UNUSED; 4338 } 4339 4340 /* analog output subdevice */ 4341 4342 s = dev->subdevices + NI_AO_SUBDEV; 4343 if (boardtype.n_aochan) { 4344 s->type = COMEDI_SUBD_AO; 4345 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND; 4346 if (boardtype.reg_type & ni_reg_m_series_mask) 4347 s->subdev_flags |= SDF_SOFT_CALIBRATED; 4348 s->n_chan = boardtype.n_aochan; 4349 s->maxdata = (1 << boardtype.aobits) - 1; 4350 s->range_table = boardtype.ao_range_table; 4351 s->insn_read = &ni_ao_insn_read; 4352 if (boardtype.reg_type & ni_reg_6xxx_mask) { 4353 s->insn_write = &ni_ao_insn_write_671x; 4354 } else { 4355 s->insn_write = &ni_ao_insn_write; 4356 } 4357 s->insn_config = &ni_ao_insn_config; 4358#ifdef PCIDMA 4359 if (boardtype.n_aochan) { 4360 s->async_dma_dir = DMA_TO_DEVICE; 4361#else 4362 if (boardtype.ao_fifo_depth) { 4363#endif 4364 dev->write_subdev = s; 4365 s->subdev_flags |= SDF_CMD_WRITE; 4366 s->do_cmd = &ni_ao_cmd; 4367 s->do_cmdtest = &ni_ao_cmdtest; 4368 s->len_chanlist = boardtype.n_aochan; 4369 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) 4370 s->munge = ni_ao_munge; 4371 } 4372 s->cancel = &ni_ao_reset; 4373 } else { 4374 s->type = COMEDI_SUBD_UNUSED; 4375 } 4376 if ((boardtype.reg_type & ni_reg_67xx_mask)) 4377 init_ao_67xx(dev, s); 4378 4379 /* digital i/o subdevice */ 4380 4381 s = dev->subdevices + NI_DIO_SUBDEV; 4382 s->type = COMEDI_SUBD_DIO; 4383 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 4384 s->maxdata = 1; 4385 s->io_bits = 0; /* all bits input */ 4386 s->range_table = &range_digital; 4387 s->n_chan = boardtype.num_p0_dio_channels; 4388 if (boardtype.reg_type & ni_reg_m_series_mask) { 4389 s->subdev_flags |= 4390 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ; 4391 s->insn_bits = &ni_m_series_dio_insn_bits; 4392 s->insn_config = &ni_m_series_dio_insn_config; 4393 s->do_cmd = &ni_cdio_cmd; 4394 s->do_cmdtest = &ni_cdio_cmdtest; 4395 s->cancel = &ni_cdio_cancel; 4396 s->async_dma_dir = DMA_BIDIRECTIONAL; 4397 s->len_chanlist = s->n_chan; 4398 4399 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command); 4400 ni_writel(s->io_bits, M_Offset_DIO_Direction); 4401 } else { 4402 s->insn_bits = &ni_dio_insn_bits; 4403 s->insn_config = &ni_dio_insn_config; 4404 devpriv->dio_control = DIO_Pins_Dir(s->io_bits); 4405 ni_writew(devpriv->dio_control, DIO_Control_Register); 4406 } 4407 4408 /* 8255 device */ 4409 s = dev->subdevices + NI_8255_DIO_SUBDEV; 4410 if (boardtype.has_8255) { 4411 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev); 4412 } else { 4413 s->type = COMEDI_SUBD_UNUSED; 4414 } 4415 4416 /* formerly general purpose counter/timer device, but no longer used */ 4417 s = dev->subdevices + NI_UNUSED_SUBDEV; 4418 s->type = COMEDI_SUBD_UNUSED; 4419 4420 /* calibration subdevice -- ai and ao */ 4421 s = dev->subdevices + NI_CALIBRATION_SUBDEV; 4422 s->type = COMEDI_SUBD_CALIB; 4423 if (boardtype.reg_type & ni_reg_m_series_mask) { 4424 /* internal PWM analog output used for AI nonlinearity calibration */ 4425 s->subdev_flags = SDF_INTERNAL; 4426 s->insn_config = &ni_m_series_pwm_config; 4427 s->n_chan = 1; 4428 s->maxdata = 0; 4429 ni_writel(0x0, M_Offset_Cal_PWM); 4430 } else if (boardtype.reg_type == ni_reg_6143) { 4431 /* internal PWM analog output used for AI nonlinearity calibration */ 4432 s->subdev_flags = SDF_INTERNAL; 4433 s->insn_config = &ni_6143_pwm_config; 4434 s->n_chan = 1; 4435 s->maxdata = 0; 4436 } else { 4437 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL; 4438 s->insn_read = &ni_calib_insn_read; 4439 s->insn_write = &ni_calib_insn_write; 4440 caldac_setup(dev, s); 4441 } 4442 4443 /* EEPROM */ 4444 s = dev->subdevices + NI_EEPROM_SUBDEV; 4445 s->type = COMEDI_SUBD_MEMORY; 4446 s->subdev_flags = SDF_READABLE | SDF_INTERNAL; 4447 s->maxdata = 0xff; 4448 if (boardtype.reg_type & ni_reg_m_series_mask) { 4449 s->n_chan = M_SERIES_EEPROM_SIZE; 4450 s->insn_read = &ni_m_series_eeprom_insn_read; 4451 } else { 4452 s->n_chan = 512; 4453 s->insn_read = &ni_eeprom_insn_read; 4454 } 4455 4456 /* PFI */ 4457 s = dev->subdevices + NI_PFI_DIO_SUBDEV; 4458 s->type = COMEDI_SUBD_DIO; 4459 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 4460 if (boardtype.reg_type & ni_reg_m_series_mask) { 4461 unsigned i; 4462 s->n_chan = 16; 4463 ni_writew(s->state, M_Offset_PFI_DO); 4464 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) { 4465 ni_writew(devpriv->pfi_output_select_reg[i], 4466 M_Offset_PFI_Output_Select(i + 1)); 4467 } 4468 } else { 4469 s->n_chan = 10; 4470 } 4471 s->maxdata = 1; 4472 if (boardtype.reg_type & ni_reg_m_series_mask) { 4473 s->insn_bits = &ni_pfi_insn_bits; 4474 } 4475 s->insn_config = &ni_pfi_insn_config; 4476 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0); 4477 4478 /* cs5529 calibration adc */ 4479 s = dev->subdevices + NI_CS5529_CALIBRATION_SUBDEV; 4480 if (boardtype.reg_type & ni_reg_67xx_mask) { 4481 s->type = COMEDI_SUBD_AI; 4482 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL; 4483 /* one channel for each analog output channel */ 4484 s->n_chan = boardtype.n_aochan; 4485 s->maxdata = (1 << 16) - 1; 4486 s->range_table = &range_unknown; /* XXX */ 4487 s->insn_read = cs5529_ai_insn_read; 4488 s->insn_config = NULL; 4489 init_cs5529(dev); 4490 } else { 4491 s->type = COMEDI_SUBD_UNUSED; 4492 } 4493 4494 /* Serial */ 4495 s = dev->subdevices + NI_SERIAL_SUBDEV; 4496 s->type = COMEDI_SUBD_SERIAL; 4497 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 4498 s->n_chan = 1; 4499 s->maxdata = 0xff; 4500 s->insn_config = ni_serial_insn_config; 4501 devpriv->serial_interval_ns = 0; 4502 devpriv->serial_hw_mode = 0; 4503 4504 /* RTSI */ 4505 s = dev->subdevices + NI_RTSI_SUBDEV; 4506 s->type = COMEDI_SUBD_DIO; 4507 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 4508 s->n_chan = 8; 4509 s->maxdata = 1; 4510 s->insn_bits = ni_rtsi_insn_bits; 4511 s->insn_config = ni_rtsi_insn_config; 4512 ni_rtsi_init(dev); 4513 4514 if (boardtype.reg_type & ni_reg_m_series_mask) { 4515 counter_variant = ni_gpct_variant_m_series; 4516 } else { 4517 counter_variant = ni_gpct_variant_e_series; 4518 } 4519 devpriv->counter_dev = ni_gpct_device_construct(dev, 4520 &ni_gpct_write_register, &ni_gpct_read_register, 4521 counter_variant, NUM_GPCT); 4522 /* General purpose counters */ 4523 for (j = 0; j < NUM_GPCT; ++j) { 4524 s = dev->subdevices + NI_GPCT_SUBDEV(j); 4525 s->type = COMEDI_SUBD_COUNTER; 4526 s->subdev_flags = 4527 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ 4528 /* | SDF_CMD_WRITE */ ; 4529 s->n_chan = 3; 4530 if (boardtype.reg_type & ni_reg_m_series_mask) 4531 s->maxdata = 0xffffffff; 4532 else 4533 s->maxdata = 0xffffff; 4534 s->insn_read = &ni_gpct_insn_read; 4535 s->insn_write = &ni_gpct_insn_write; 4536 s->insn_config = &ni_gpct_insn_config; 4537 s->do_cmd = &ni_gpct_cmd; 4538 s->len_chanlist = 1; 4539 s->do_cmdtest = &ni_gpct_cmdtest; 4540 s->cancel = &ni_gpct_cancel; 4541 s->async_dma_dir = DMA_BIDIRECTIONAL; 4542 s->private = &devpriv->counter_dev->counters[j]; 4543 4544 devpriv->counter_dev->counters[j].chip_index = 0; 4545 devpriv->counter_dev->counters[j].counter_index = j; 4546 ni_tio_init_counter(&devpriv->counter_dev->counters[j]); 4547 } 4548 4549 /* Frequency output */ 4550 s = dev->subdevices + NI_FREQ_OUT_SUBDEV; 4551 s->type = COMEDI_SUBD_COUNTER; 4552 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; 4553 s->n_chan = 1; 4554 s->maxdata = 0xf; 4555 s->insn_read = &ni_freq_out_insn_read; 4556 s->insn_write = &ni_freq_out_insn_write; 4557 s->insn_config = &ni_freq_out_insn_config; 4558 4559 /* ai configuration */ 4560 ni_ai_reset(dev, dev->subdevices + NI_AI_SUBDEV); 4561 if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) { 4562 /* BEAM is this needed for PCI-6143 ?? */ 4563 devpriv->clock_and_fout = 4564 Slow_Internal_Time_Divide_By_2 | 4565 Slow_Internal_Timebase | 4566 Clock_To_Board_Divide_By_2 | 4567 Clock_To_Board | 4568 AI_Output_Divide_By_2 | AO_Output_Divide_By_2; 4569 } else { 4570 devpriv->clock_and_fout = 4571 Slow_Internal_Time_Divide_By_2 | 4572 Slow_Internal_Timebase | 4573 Clock_To_Board_Divide_By_2 | Clock_To_Board; 4574 } 4575 devpriv->stc_writew(dev, devpriv->clock_and_fout, 4576 Clock_and_FOUT_Register); 4577 4578 /* analog output configuration */ 4579 ni_ao_reset(dev, dev->subdevices + NI_AO_SUBDEV); 4580 4581 if (dev->irq) { 4582 devpriv->stc_writew(dev, 4583 (IRQ_POLARITY ? Interrupt_Output_Polarity : 0) | 4584 (Interrupt_Output_On_3_Pins & 0) | Interrupt_A_Enable | 4585 Interrupt_B_Enable | 4586 Interrupt_A_Output_Select(interrupt_pin(dev-> 4587 irq)) | 4588 Interrupt_B_Output_Select(interrupt_pin(dev->irq)), 4589 Interrupt_Control_Register); 4590 } 4591 4592 /* DMA setup */ 4593 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select); 4594 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select); 4595 4596 if (boardtype.reg_type & ni_reg_6xxx_mask) { 4597 ni_writeb(0, Magic_611x); 4598 } else if (boardtype.reg_type & ni_reg_m_series_mask) { 4599 int channel; 4600 for (channel = 0; channel < boardtype.n_aochan; ++channel) { 4601 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel)); 4602 ni_writeb(0x0, 4603 M_Offset_AO_Reference_Attenuation(channel)); 4604 } 4605 ni_writeb(0x0, M_Offset_AO_Calibration); 4606 } 4607 4608 printk("\n"); 4609 return 0; 4610} 4611 4612static int ni_8255_callback(int dir, int port, int data, unsigned long arg) 4613{ 4614 struct comedi_device *dev = (struct comedi_device *) arg; 4615 4616 if (dir) { 4617 ni_writeb(data, Port_A + 2 * port); 4618 return 0; 4619 } else { 4620 return ni_readb(Port_A + 2 * port); 4621 } 4622} 4623 4624/* 4625 presents the EEPROM as a subdevice 4626*/ 4627 4628static int ni_eeprom_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 4629 struct comedi_insn *insn, unsigned int *data) 4630{ 4631 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec)); 4632 4633 return 1; 4634} 4635 4636/* 4637 reads bytes out of eeprom 4638*/ 4639 4640static int ni_read_eeprom(struct comedi_device *dev, int addr) 4641{ 4642 int bit; 4643 int bitstring; 4644 4645 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff); 4646 ni_writeb(0x04, Serial_Command); 4647 for (bit = 0x8000; bit; bit >>= 1) { 4648 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0), 4649 Serial_Command); 4650 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0), 4651 Serial_Command); 4652 } 4653 bitstring = 0; 4654 for (bit = 0x80; bit; bit >>= 1) { 4655 ni_writeb(0x04, Serial_Command); 4656 ni_writeb(0x05, Serial_Command); 4657 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0); 4658 } 4659 ni_writeb(0x00, Serial_Command); 4660 4661 return bitstring; 4662} 4663 4664static int ni_m_series_eeprom_insn_read(struct comedi_device *dev, 4665 struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) 4666{ 4667 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)]; 4668 4669 return 1; 4670} 4671 4672static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data) 4673{ 4674 data[1] = devpriv->pwm_up_count * devpriv->clock_ns; 4675 data[2] = devpriv->pwm_down_count * devpriv->clock_ns; 4676 return 3; 4677} 4678 4679static int ni_m_series_pwm_config(struct comedi_device *dev, struct comedi_subdevice *s, 4680 struct comedi_insn *insn, unsigned int *data) 4681{ 4682 unsigned up_count, down_count; 4683 switch (data[0]) { 4684 case INSN_CONFIG_PWM_OUTPUT: 4685 switch (data[1]) { 4686 case TRIG_ROUND_NEAREST: 4687 up_count = 4688 (data[2] + 4689 devpriv->clock_ns / 2) / devpriv->clock_ns; 4690 break; 4691 case TRIG_ROUND_DOWN: 4692 up_count = data[2] / devpriv->clock_ns; 4693 break; 4694 case TRIG_ROUND_UP: 4695 up_count = 4696 (data[2] + devpriv->clock_ns - 4697 1) / devpriv->clock_ns; 4698 break; 4699 default: 4700 return -EINVAL; 4701 break; 4702 } 4703 switch (data[3]) { 4704 case TRIG_ROUND_NEAREST: 4705 down_count = 4706 (data[4] + 4707 devpriv->clock_ns / 2) / devpriv->clock_ns; 4708 break; 4709 case TRIG_ROUND_DOWN: 4710 down_count = data[4] / devpriv->clock_ns; 4711 break; 4712 case TRIG_ROUND_UP: 4713 down_count = 4714 (data[4] + devpriv->clock_ns - 4715 1) / devpriv->clock_ns; 4716 break; 4717 default: 4718 return -EINVAL; 4719 break; 4720 } 4721 if (up_count * devpriv->clock_ns != data[2] || 4722 down_count * devpriv->clock_ns != data[4]) { 4723 data[2] = up_count * devpriv->clock_ns; 4724 data[4] = down_count * devpriv->clock_ns; 4725 return -EAGAIN; 4726 } 4727 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | 4728 MSeries_Cal_PWM_Low_Time_Bits(down_count), 4729 M_Offset_Cal_PWM); 4730 devpriv->pwm_up_count = up_count; 4731 devpriv->pwm_down_count = down_count; 4732 return 5; 4733 break; 4734 case INSN_CONFIG_GET_PWM_OUTPUT: 4735 return ni_get_pwm_config(dev, data); 4736 break; 4737 default: 4738 return -EINVAL; 4739 break; 4740 } 4741 return 0; 4742} 4743 4744static int ni_6143_pwm_config(struct comedi_device *dev, struct comedi_subdevice *s, 4745 struct comedi_insn *insn, unsigned int *data) 4746{ 4747 unsigned up_count, down_count; 4748 switch (data[0]) { 4749 case INSN_CONFIG_PWM_OUTPUT: 4750 switch (data[1]) { 4751 case TRIG_ROUND_NEAREST: 4752 up_count = 4753 (data[2] + 4754 devpriv->clock_ns / 2) / devpriv->clock_ns; 4755 break; 4756 case TRIG_ROUND_DOWN: 4757 up_count = data[2] / devpriv->clock_ns; 4758 break; 4759 case TRIG_ROUND_UP: 4760 up_count = 4761 (data[2] + devpriv->clock_ns - 4762 1) / devpriv->clock_ns; 4763 break; 4764 default: 4765 return -EINVAL; 4766 break; 4767 } 4768 switch (data[3]) { 4769 case TRIG_ROUND_NEAREST: 4770 down_count = 4771 (data[4] + 4772 devpriv->clock_ns / 2) / devpriv->clock_ns; 4773 break; 4774 case TRIG_ROUND_DOWN: 4775 down_count = data[4] / devpriv->clock_ns; 4776 break; 4777 case TRIG_ROUND_UP: 4778 down_count = 4779 (data[4] + devpriv->clock_ns - 4780 1) / devpriv->clock_ns; 4781 break; 4782 default: 4783 return -EINVAL; 4784 break; 4785 } 4786 if (up_count * devpriv->clock_ns != data[2] || 4787 down_count * devpriv->clock_ns != data[4]) { 4788 data[2] = up_count * devpriv->clock_ns; 4789 data[4] = down_count * devpriv->clock_ns; 4790 return -EAGAIN; 4791 } 4792 ni_writel(up_count, Calibration_HighTime_6143); 4793 devpriv->pwm_up_count = up_count; 4794 ni_writel(down_count, Calibration_LowTime_6143); 4795 devpriv->pwm_down_count = down_count; 4796 return 5; 4797 break; 4798 case INSN_CONFIG_GET_PWM_OUTPUT: 4799 return ni_get_pwm_config(dev, data); 4800 default: 4801 return -EINVAL; 4802 break; 4803 } 4804 return 0; 4805} 4806 4807static void ni_write_caldac(struct comedi_device *dev, int addr, int val); 4808/* 4809 calibration subdevice 4810*/ 4811static int ni_calib_insn_write(struct comedi_device *dev, struct comedi_subdevice *s, 4812 struct comedi_insn *insn, unsigned int *data) 4813{ 4814 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]); 4815 4816 return 1; 4817} 4818 4819static int ni_calib_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 4820 struct comedi_insn *insn, unsigned int *data) 4821{ 4822 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)]; 4823 4824 return 1; 4825} 4826 4827static int pack_mb88341(int addr, int val, int *bitstring); 4828static int pack_dac8800(int addr, int val, int *bitstring); 4829static int pack_dac8043(int addr, int val, int *bitstring); 4830static int pack_ad8522(int addr, int val, int *bitstring); 4831static int pack_ad8804(int addr, int val, int *bitstring); 4832static int pack_ad8842(int addr, int val, int *bitstring); 4833 4834struct caldac_struct { 4835 int n_chans; 4836 int n_bits; 4837 int (*packbits) (int, int, int *); 4838}; 4839 4840static struct caldac_struct caldacs[] = { 4841 [mb88341] = {12, 8, pack_mb88341}, 4842 [dac8800] = {8, 8, pack_dac8800}, 4843 [dac8043] = {1, 12, pack_dac8043}, 4844 [ad8522] = {2, 12, pack_ad8522}, 4845 [ad8804] = {12, 8, pack_ad8804}, 4846 [ad8842] = {8, 8, pack_ad8842}, 4847 [ad8804_debug] = {16, 8, pack_ad8804}, 4848}; 4849 4850static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s) 4851{ 4852 int i, j; 4853 int n_dacs; 4854 int n_chans = 0; 4855 int n_bits; 4856 int diffbits = 0; 4857 int type; 4858 int chan; 4859 4860 type = boardtype.caldac[0]; 4861 if (type == caldac_none) 4862 return; 4863 n_bits = caldacs[type].n_bits; 4864 for (i = 0; i < 3; i++) { 4865 type = boardtype.caldac[i]; 4866 if (type == caldac_none) 4867 break; 4868 if (caldacs[type].n_bits != n_bits) 4869 diffbits = 1; 4870 n_chans += caldacs[type].n_chans; 4871 } 4872 n_dacs = i; 4873 s->n_chan = n_chans; 4874 4875 if (diffbits) { 4876 unsigned int *maxdata_list; 4877 4878 if (n_chans > MAX_N_CALDACS) { 4879 printk("BUG! MAX_N_CALDACS too small\n"); 4880 } 4881 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list; 4882 chan = 0; 4883 for (i = 0; i < n_dacs; i++) { 4884 type = boardtype.caldac[i]; 4885 for (j = 0; j < caldacs[type].n_chans; j++) { 4886 maxdata_list[chan] = 4887 (1 << caldacs[type].n_bits) - 1; 4888 chan++; 4889 } 4890 } 4891 4892 for (chan = 0; chan < s->n_chan; chan++) 4893 ni_write_caldac(dev, i, s->maxdata_list[i] / 2); 4894 } else { 4895 type = boardtype.caldac[0]; 4896 s->maxdata = (1 << caldacs[type].n_bits) - 1; 4897 4898 for (chan = 0; chan < s->n_chan; chan++) 4899 ni_write_caldac(dev, i, s->maxdata / 2); 4900 } 4901} 4902 4903static void ni_write_caldac(struct comedi_device *dev, int addr, int val) 4904{ 4905 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0; 4906 int i; 4907 int type; 4908 4909 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */ 4910 if (devpriv->caldacs[addr] == val) 4911 return; 4912 devpriv->caldacs[addr] = val; 4913 4914 for (i = 0; i < 3; i++) { 4915 type = boardtype.caldac[i]; 4916 if (type == caldac_none) 4917 break; 4918 if (addr < caldacs[type].n_chans) { 4919 bits = caldacs[type].packbits(addr, val, &bitstring); 4920 loadbit = SerDacLd(i); 4921 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */ 4922 break; 4923 } 4924 addr -= caldacs[type].n_chans; 4925 } 4926 4927 for (bit = 1 << (bits - 1); bit; bit >>= 1) { 4928 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command); 4929 udelay(1); 4930 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command); 4931 udelay(1); 4932 } 4933 ni_writeb(loadbit, Serial_Command); 4934 udelay(1); 4935 ni_writeb(0, Serial_Command); 4936} 4937 4938static int pack_mb88341(int addr, int val, int *bitstring) 4939{ 4940 /* 4941 Fujitsu MB 88341 4942 Note that address bits are reversed. Thanks to 4943 Ingo Keen for noticing this. 4944 4945 Note also that the 88341 expects address values from 4946 1-12, whereas we use channel numbers 0-11. The NI 4947 docs use 1-12, also, so be careful here. 4948 */ 4949 addr++; 4950 *bitstring = ((addr & 0x1) << 11) | 4951 ((addr & 0x2) << 9) | 4952 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff); 4953 return 12; 4954} 4955 4956static int pack_dac8800(int addr, int val, int *bitstring) 4957{ 4958 *bitstring = ((addr & 0x7) << 8) | (val & 0xff); 4959 return 11; 4960} 4961 4962static int pack_dac8043(int addr, int val, int *bitstring) 4963{ 4964 *bitstring = val & 0xfff; 4965 return 12; 4966} 4967 4968static int pack_ad8522(int addr, int val, int *bitstring) 4969{ 4970 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000); 4971 return 16; 4972} 4973 4974static int pack_ad8804(int addr, int val, int *bitstring) 4975{ 4976 *bitstring = ((addr & 0xf) << 8) | (val & 0xff); 4977 return 12; 4978} 4979 4980static int pack_ad8842(int addr, int val, int *bitstring) 4981{ 4982 *bitstring = ((addr + 1) << 8) | (val & 0xff); 4983 return 12; 4984} 4985 4986#if 0 4987/* 4988 * Read the GPCTs current value. 4989 */ 4990static int GPCT_G_Watch(struct comedi_device *dev, int chan) 4991{ 4992 unsigned int hi1, hi2, lo; 4993 4994 devpriv->gpct_command[chan] &= ~G_Save_Trace; 4995 devpriv->stc_writew(dev, devpriv->gpct_command[chan], 4996 G_Command_Register(chan)); 4997 4998 devpriv->gpct_command[chan] |= G_Save_Trace; 4999 devpriv->stc_writew(dev, devpriv->gpct_command[chan], 5000 G_Command_Register(chan)); 5001 5002 /* This procedure is used because the two registers cannot 5003 * be read atomically. */ 5004 do { 5005 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan)); 5006 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan)); 5007 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan)); 5008 } while (hi1 != hi2); 5009 5010 return (hi1 << 16) | lo; 5011} 5012 5013static void GPCT_Reset(struct comedi_device *dev, int chan) 5014{ 5015 int temp_ack_reg = 0; 5016 5017 /* printk("GPCT_Reset..."); */ 5018 devpriv->gpct_cur_operation[chan] = GPCT_RESET; 5019 5020 switch (chan) { 5021 case 0: 5022 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register); 5023 ni_set_bits(dev, Interrupt_A_Enable_Register, 5024 G0_TC_Interrupt_Enable, 0); 5025 ni_set_bits(dev, Interrupt_A_Enable_Register, 5026 G0_Gate_Interrupt_Enable, 0); 5027 temp_ack_reg |= G0_Gate_Error_Confirm; 5028 temp_ack_reg |= G0_TC_Error_Confirm; 5029 temp_ack_reg |= G0_TC_Interrupt_Ack; 5030 temp_ack_reg |= G0_Gate_Interrupt_Ack; 5031 devpriv->stc_writew(dev, temp_ack_reg, 5032 Interrupt_A_Ack_Register); 5033 5034 /* problem...this interferes with the other ctr... */ 5035 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable; 5036 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, 5037 Analog_Trigger_Etc_Register); 5038 break; 5039 case 1: 5040 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register); 5041 ni_set_bits(dev, Interrupt_B_Enable_Register, 5042 G1_TC_Interrupt_Enable, 0); 5043 ni_set_bits(dev, Interrupt_B_Enable_Register, 5044 G0_Gate_Interrupt_Enable, 0); 5045 temp_ack_reg |= G1_Gate_Error_Confirm; 5046 temp_ack_reg |= G1_TC_Error_Confirm; 5047 temp_ack_reg |= G1_TC_Interrupt_Ack; 5048 temp_ack_reg |= G1_Gate_Interrupt_Ack; 5049 devpriv->stc_writew(dev, temp_ack_reg, 5050 Interrupt_B_Ack_Register); 5051 5052 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable; 5053 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, 5054 Analog_Trigger_Etc_Register); 5055 break; 5056 }; 5057 5058 devpriv->gpct_mode[chan] = 0; 5059 devpriv->gpct_input_select[chan] = 0; 5060 devpriv->gpct_command[chan] = 0; 5061 5062 devpriv->gpct_command[chan] |= G_Synchronized_Gate; 5063 5064 devpriv->stc_writew(dev, devpriv->gpct_mode[chan], 5065 G_Mode_Register(chan)); 5066 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], 5067 G_Input_Select_Register(chan)); 5068 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan)); 5069 5070 /* printk("exit GPCT_Reset\n"); */ 5071} 5072 5073#endif 5074 5075static int ni_gpct_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 5076 struct comedi_insn *insn, unsigned int *data) 5077{ 5078 struct ni_gpct *counter = s->private; 5079 return ni_tio_insn_config(counter, insn, data); 5080} 5081 5082static int ni_gpct_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 5083 struct comedi_insn *insn, unsigned int *data) 5084{ 5085 struct ni_gpct *counter = s->private; 5086 return ni_tio_rinsn(counter, insn, data); 5087} 5088 5089static int ni_gpct_insn_write(struct comedi_device *dev, struct comedi_subdevice *s, 5090 struct comedi_insn *insn, unsigned int *data) 5091{ 5092 struct ni_gpct *counter = s->private; 5093 return ni_tio_winsn(counter, insn, data); 5094} 5095 5096static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 5097{ 5098 int retval; 5099#ifdef PCIDMA 5100 struct ni_gpct *counter = s->private; 5101/* const struct comedi_cmd *cmd = &s->async->cmd; */ 5102 5103 retval = ni_request_gpct_mite_channel(dev, counter->counter_index, 5104 COMEDI_INPUT); 5105 if (retval) { 5106 comedi_error(dev, 5107 "no dma channel available for use by counter"); 5108 return retval; 5109 } 5110 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL); 5111 ni_e_series_enable_second_irq(dev, counter->counter_index, 1); 5112 retval = ni_tio_cmd(counter, s->async); 5113#else 5114 retval = -ENOTSUPP; 5115#endif 5116 return retval; 5117} 5118 5119static int ni_gpct_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 5120 struct comedi_cmd *cmd) 5121{ 5122#ifdef PCIDMA 5123 struct ni_gpct *counter = s->private; 5124 5125 return ni_tio_cmdtest(counter, cmd); 5126#else 5127 return -ENOTSUPP; 5128#endif 5129} 5130 5131static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 5132{ 5133#ifdef PCIDMA 5134 struct ni_gpct *counter = s->private; 5135 int retval; 5136 5137 retval = ni_tio_cancel(counter); 5138 ni_e_series_enable_second_irq(dev, counter->counter_index, 0); 5139 ni_release_gpct_mite_channel(dev, counter->counter_index); 5140 return retval; 5141#else 5142 return 0; 5143#endif 5144} 5145 5146/* 5147 * 5148 * Programmable Function Inputs 5149 * 5150 */ 5151 5152static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan, 5153 unsigned source) 5154{ 5155 unsigned pfi_reg_index; 5156 unsigned array_offset; 5157 if ((source & 0x1f) != source) 5158 return -EINVAL; 5159 pfi_reg_index = 1 + chan / 3; 5160 array_offset = pfi_reg_index - 1; 5161 devpriv->pfi_output_select_reg[array_offset] &= 5162 ~MSeries_PFI_Output_Select_Mask(chan); 5163 devpriv->pfi_output_select_reg[array_offset] |= 5164 MSeries_PFI_Output_Select_Bits(chan, source); 5165 ni_writew(devpriv->pfi_output_select_reg[array_offset], 5166 M_Offset_PFI_Output_Select(pfi_reg_index)); 5167 return 2; 5168} 5169 5170static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan, 5171 unsigned source) 5172{ 5173 /* pre-m-series boards have fixed signals on pfi pins */ 5174 if (source != ni_old_get_pfi_routing(dev, chan)) 5175 return -EINVAL; 5176 return 2; 5177} 5178 5179static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan, 5180 unsigned source) 5181{ 5182 if (boardtype.reg_type & ni_reg_m_series_mask) 5183 return ni_m_series_set_pfi_routing(dev, chan, source); 5184 else 5185 return ni_old_set_pfi_routing(dev, chan, source); 5186} 5187 5188static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev, unsigned chan) 5189{ 5190 const unsigned array_offset = chan / 3; 5191 return MSeries_PFI_Output_Select_Source(chan, 5192 devpriv->pfi_output_select_reg[array_offset]); 5193} 5194 5195static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan) 5196{ 5197 /* pre-m-series boards have fixed signals on pfi pins */ 5198 switch (chan) { 5199 case 0: 5200 return NI_PFI_OUTPUT_AI_START1; 5201 break; 5202 case 1: 5203 return NI_PFI_OUTPUT_AI_START2; 5204 break; 5205 case 2: 5206 return NI_PFI_OUTPUT_AI_CONVERT; 5207 break; 5208 case 3: 5209 return NI_PFI_OUTPUT_G_SRC1; 5210 break; 5211 case 4: 5212 return NI_PFI_OUTPUT_G_GATE1; 5213 break; 5214 case 5: 5215 return NI_PFI_OUTPUT_AO_UPDATE_N; 5216 break; 5217 case 6: 5218 return NI_PFI_OUTPUT_AO_START1; 5219 break; 5220 case 7: 5221 return NI_PFI_OUTPUT_AI_START_PULSE; 5222 break; 5223 case 8: 5224 return NI_PFI_OUTPUT_G_SRC0; 5225 break; 5226 case 9: 5227 return NI_PFI_OUTPUT_G_GATE0; 5228 break; 5229 default: 5230 printk("%s: bug, unhandled case in switch.\n", __func__); 5231 break; 5232 } 5233 return 0; 5234} 5235 5236static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan) 5237{ 5238 if (boardtype.reg_type & ni_reg_m_series_mask) 5239 return ni_m_series_get_pfi_routing(dev, chan); 5240 else 5241 return ni_old_get_pfi_routing(dev, chan); 5242} 5243 5244static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel, 5245 enum ni_pfi_filter_select filter) 5246{ 5247 unsigned bits; 5248 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) { 5249 return -ENOTSUPP; 5250 } 5251 bits = ni_readl(M_Offset_PFI_Filter); 5252 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel); 5253 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter); 5254 ni_writel(bits, M_Offset_PFI_Filter); 5255 return 0; 5256} 5257 5258static int ni_pfi_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, 5259 struct comedi_insn *insn, unsigned int *data) 5260{ 5261 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) { 5262 return -ENOTSUPP; 5263 } 5264 if (data[0]) { 5265 s->state &= ~data[0]; 5266 s->state |= (data[0] & data[1]); 5267 ni_writew(s->state, M_Offset_PFI_DO); 5268 } 5269 data[1] = ni_readw(M_Offset_PFI_DI); 5270 return 2; 5271} 5272 5273static int ni_pfi_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 5274 struct comedi_insn *insn, unsigned int *data) 5275{ 5276 unsigned int chan; 5277 5278 if (insn->n < 1) 5279 return -EINVAL; 5280 5281 chan = CR_CHAN(insn->chanspec); 5282 5283 switch (data[0]) { 5284 case COMEDI_OUTPUT: 5285 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1); 5286 break; 5287 case COMEDI_INPUT: 5288 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0); 5289 break; 5290 case INSN_CONFIG_DIO_QUERY: 5291 data[1] = 5292 (devpriv-> 5293 io_bidirection_pin_reg & (1 << chan)) ? COMEDI_OUTPUT : 5294 COMEDI_INPUT; 5295 return 0; 5296 break; 5297 case INSN_CONFIG_SET_ROUTING: 5298 return ni_set_pfi_routing(dev, chan, data[1]); 5299 break; 5300 case INSN_CONFIG_GET_ROUTING: 5301 data[1] = ni_get_pfi_routing(dev, chan); 5302 break; 5303 case INSN_CONFIG_FILTER: 5304 return ni_config_filter(dev, chan, data[1]); 5305 break; 5306 default: 5307 return -EINVAL; 5308 } 5309 return 0; 5310} 5311 5312/* 5313 * 5314 * NI RTSI Bus Functions 5315 * 5316 */ 5317static void ni_rtsi_init(struct comedi_device *dev) 5318{ 5319 /* Initialises the RTSI bus signal switch to a default state */ 5320 5321 /* Set clock mode to internal */ 5322 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit; 5323 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) { 5324 printk("ni_set_master_clock failed, bug?"); 5325 } 5326 /* default internal lines routing to RTSI bus lines */ 5327 devpriv->rtsi_trig_a_output_reg = 5328 RTSI_Trig_Output_Bits(0, 5329 NI_RTSI_OUTPUT_ADR_START1) | RTSI_Trig_Output_Bits(1, 5330 NI_RTSI_OUTPUT_ADR_START2) | RTSI_Trig_Output_Bits(2, 5331 NI_RTSI_OUTPUT_SCLKG) | RTSI_Trig_Output_Bits(3, 5332 NI_RTSI_OUTPUT_DACUPDN); 5333 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg, 5334 RTSI_Trig_A_Output_Register); 5335 devpriv->rtsi_trig_b_output_reg = 5336 RTSI_Trig_Output_Bits(4, 5337 NI_RTSI_OUTPUT_DA_START1) | RTSI_Trig_Output_Bits(5, 5338 NI_RTSI_OUTPUT_G_SRC0) | RTSI_Trig_Output_Bits(6, 5339 NI_RTSI_OUTPUT_G_GATE0); 5340 if (boardtype.reg_type & ni_reg_m_series_mask) 5341 devpriv->rtsi_trig_b_output_reg |= 5342 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC); 5343 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg, 5344 RTSI_Trig_B_Output_Register); 5345 5346/* 5347* Sets the source and direction of the 4 on board lines 5348* devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register); 5349*/ 5350} 5351 5352static int ni_rtsi_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, 5353 struct comedi_insn *insn, unsigned int *data) 5354{ 5355 if (insn->n != 2) 5356 return -EINVAL; 5357 5358 data[1] = 0; 5359 5360 return 2; 5361} 5362 5363/* Find best multiplier/divider to try and get the PLL running at 80 MHz 5364 * given an arbitrary frequency input clock */ 5365static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, 5366 unsigned *freq_divider, unsigned *freq_multiplier, 5367 unsigned *actual_period_ns) 5368{ 5369 unsigned div; 5370 unsigned best_div = 1; 5371 static const unsigned max_div = 0x10; 5372 unsigned mult; 5373 unsigned best_mult = 1; 5374 static const unsigned max_mult = 0x100; 5375 static const unsigned pico_per_nano = 1000; 5376 5377 const unsigned reference_picosec = reference_period_ns * pico_per_nano; 5378 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to 5379 * 20 MHz for most timing clocks */ 5380 static const unsigned target_picosec = 12500; 5381 static const unsigned fudge_factor_80_to_20Mhz = 4; 5382 int best_period_picosec = 0; 5383 for (div = 1; div <= max_div; ++div) { 5384 for (mult = 1; mult <= max_mult; ++mult) { 5385 unsigned new_period_ps = 5386 (reference_picosec * div) / mult; 5387 if (abs(new_period_ps - target_picosec) < 5388 abs(best_period_picosec - target_picosec)) { 5389 best_period_picosec = new_period_ps; 5390 best_div = div; 5391 best_mult = mult; 5392 } 5393 } 5394 } 5395 if (best_period_picosec == 0) { 5396 printk("%s: bug, failed to find pll parameters\n", 5397 __func__); 5398 return -EIO; 5399 } 5400 *freq_divider = best_div; 5401 *freq_multiplier = best_mult; 5402 *actual_period_ns = 5403 (best_period_picosec * fudge_factor_80_to_20Mhz + 5404 (pico_per_nano / 2)) / pico_per_nano; 5405 return 0; 5406} 5407 5408static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev) 5409{ 5410 if (boardtype.reg_type & ni_reg_m_series_mask) 5411 return 8; 5412 else 5413 return 7; 5414} 5415 5416static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, unsigned source, 5417 unsigned period_ns) 5418{ 5419 static const unsigned min_period_ns = 50; 5420 static const unsigned max_period_ns = 1000; 5421 static const unsigned timeout = 1000; 5422 unsigned pll_control_bits; 5423 unsigned freq_divider; 5424 unsigned freq_multiplier; 5425 unsigned i; 5426 int retval; 5427 if (source == NI_MIO_PLL_PXI10_CLOCK) 5428 period_ns = 100; 5429 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */ 5430 if (period_ns < min_period_ns || period_ns > max_period_ns) { 5431 printk 5432 ("%s: you must specify an input clock frequency between %i and %i nanosec " 5433 "for the phased-lock loop.\n", __func__, 5434 min_period_ns, max_period_ns); 5435 return -EINVAL; 5436 } 5437 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit; 5438 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, 5439 RTSI_Trig_Direction_Register); 5440 pll_control_bits = 5441 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits; 5442 devpriv->clock_and_fout2 |= 5443 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit; 5444 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask; 5445 switch (source) { 5446 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK: 5447 devpriv->clock_and_fout2 |= 5448 MSeries_PLL_In_Source_Select_Star_Trigger_Bits; 5449 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider, 5450 &freq_multiplier, &devpriv->clock_ns); 5451 if (retval < 0) 5452 return retval; 5453 break; 5454 case NI_MIO_PLL_PXI10_CLOCK: 5455 /* pxi clock is 10MHz */ 5456 devpriv->clock_and_fout2 |= 5457 MSeries_PLL_In_Source_Select_PXI_Clock10; 5458 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider, 5459 &freq_multiplier, &devpriv->clock_ns); 5460 if (retval < 0) 5461 return retval; 5462 break; 5463 default: 5464 { 5465 unsigned rtsi_channel; 5466 static const unsigned max_rtsi_channel = 7; 5467 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; 5468 ++rtsi_channel) { 5469 if (source == 5470 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) { 5471 devpriv->clock_and_fout2 |= 5472 MSeries_PLL_In_Source_Select_RTSI_Bits 5473 (rtsi_channel); 5474 break; 5475 } 5476 } 5477 if (rtsi_channel > max_rtsi_channel) 5478 return -EINVAL; 5479 retval = ni_mseries_get_pll_parameters(period_ns, 5480 &freq_divider, &freq_multiplier, 5481 &devpriv->clock_ns); 5482 if (retval < 0) 5483 return retval; 5484 } 5485 break; 5486 } 5487 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2); 5488 pll_control_bits |= 5489 MSeries_PLL_Divisor_Bits(freq_divider) | 5490 MSeries_PLL_Multiplier_Bits(freq_multiplier); 5491 5492 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n", 5493 * freq_divider, freq_multiplier, pll_control_bits); */ 5494 /* printk("clock_ns=%d\n", devpriv->clock_ns); */ 5495 ni_writew(pll_control_bits, M_Offset_PLL_Control); 5496 devpriv->clock_source = source; 5497 /* it seems to typically take a few hundred microseconds for PLL to lock */ 5498 for (i = 0; i < timeout; ++i) { 5499 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) { 5500 break; 5501 } 5502 udelay(1); 5503 } 5504 if (i == timeout) { 5505 printk 5506 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n", 5507 __func__, source, period_ns); 5508 return -ETIMEDOUT; 5509 } 5510 return 3; 5511} 5512 5513static int ni_set_master_clock(struct comedi_device *dev, unsigned source, 5514 unsigned period_ns) 5515{ 5516 if (source == NI_MIO_INTERNAL_CLOCK) { 5517 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit; 5518 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, 5519 RTSI_Trig_Direction_Register); 5520 devpriv->clock_ns = TIMEBASE_1_NS; 5521 if (boardtype.reg_type & ni_reg_m_series_mask) { 5522 devpriv->clock_and_fout2 &= 5523 ~(MSeries_Timebase1_Select_Bit | 5524 MSeries_Timebase3_Select_Bit); 5525 ni_writew(devpriv->clock_and_fout2, 5526 M_Offset_Clock_and_Fout2); 5527 ni_writew(0, M_Offset_PLL_Control); 5528 } 5529 devpriv->clock_source = source; 5530 } else { 5531 if (boardtype.reg_type & ni_reg_m_series_mask) { 5532 return ni_mseries_set_pll_master_clock(dev, source, 5533 period_ns); 5534 } else { 5535 if (source == NI_MIO_RTSI_CLOCK) { 5536 devpriv->rtsi_trig_direction_reg |= 5537 Use_RTSI_Clock_Bit; 5538 devpriv->stc_writew(dev, 5539 devpriv->rtsi_trig_direction_reg, 5540 RTSI_Trig_Direction_Register); 5541 if (period_ns == 0) { 5542 printk 5543 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n", 5544 __func__); 5545 return -EINVAL; 5546 } else { 5547 devpriv->clock_ns = period_ns; 5548 } 5549 devpriv->clock_source = source; 5550 } else 5551 return -EINVAL; 5552 } 5553 } 5554 return 3; 5555} 5556 5557static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan, 5558 unsigned source) 5559{ 5560 if (chan >= num_configurable_rtsi_channels(dev)) { 5561 if (chan == old_RTSI_clock_channel) { 5562 if (source == NI_RTSI_OUTPUT_RTSI_OSC) 5563 return 1; 5564 else { 5565 printk 5566 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n", 5567 __func__, chan, 5568 old_RTSI_clock_channel); 5569 return 0; 5570 } 5571 } 5572 return 0; 5573 } 5574 switch (source) { 5575 case NI_RTSI_OUTPUT_ADR_START1: 5576 case NI_RTSI_OUTPUT_ADR_START2: 5577 case NI_RTSI_OUTPUT_SCLKG: 5578 case NI_RTSI_OUTPUT_DACUPDN: 5579 case NI_RTSI_OUTPUT_DA_START1: 5580 case NI_RTSI_OUTPUT_G_SRC0: 5581 case NI_RTSI_OUTPUT_G_GATE0: 5582 case NI_RTSI_OUTPUT_RGOUT0: 5583 case NI_RTSI_OUTPUT_RTSI_BRD_0: 5584 return 1; 5585 break; 5586 case NI_RTSI_OUTPUT_RTSI_OSC: 5587 if (boardtype.reg_type & ni_reg_m_series_mask) 5588 return 1; 5589 else 5590 return 0; 5591 break; 5592 default: 5593 return 0; 5594 break; 5595 } 5596} 5597 5598static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan, 5599 unsigned source) 5600{ 5601 if (ni_valid_rtsi_output_source(dev, chan, source) == 0) 5602 return -EINVAL; 5603 if (chan < 4) { 5604 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan); 5605 devpriv->rtsi_trig_a_output_reg |= 5606 RTSI_Trig_Output_Bits(chan, source); 5607 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg, 5608 RTSI_Trig_A_Output_Register); 5609 } else if (chan < 8) { 5610 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan); 5611 devpriv->rtsi_trig_b_output_reg |= 5612 RTSI_Trig_Output_Bits(chan, source); 5613 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg, 5614 RTSI_Trig_B_Output_Register); 5615 } 5616 return 2; 5617} 5618 5619static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan) 5620{ 5621 if (chan < 4) { 5622 return RTSI_Trig_Output_Source(chan, 5623 devpriv->rtsi_trig_a_output_reg); 5624 } else if (chan < num_configurable_rtsi_channels(dev)) { 5625 return RTSI_Trig_Output_Source(chan, 5626 devpriv->rtsi_trig_b_output_reg); 5627 } else { 5628 if (chan == old_RTSI_clock_channel) 5629 return NI_RTSI_OUTPUT_RTSI_OSC; 5630 printk("%s: bug! should never get here?\n", __func__); 5631 return 0; 5632 } 5633} 5634 5635static int ni_rtsi_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, 5636 struct comedi_insn *insn, unsigned int *data) 5637{ 5638 unsigned int chan = CR_CHAN(insn->chanspec); 5639 switch (data[0]) { 5640 case INSN_CONFIG_DIO_OUTPUT: 5641 if (chan < num_configurable_rtsi_channels(dev)) { 5642 devpriv->rtsi_trig_direction_reg |= 5643 RTSI_Output_Bit(chan, 5644 (boardtype.reg_type & ni_reg_m_series_mask) != 5645 0); 5646 } else if (chan == old_RTSI_clock_channel) { 5647 devpriv->rtsi_trig_direction_reg |= 5648 Drive_RTSI_Clock_Bit; 5649 } 5650 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, 5651 RTSI_Trig_Direction_Register); 5652 break; 5653 case INSN_CONFIG_DIO_INPUT: 5654 if (chan < num_configurable_rtsi_channels(dev)) { 5655 devpriv->rtsi_trig_direction_reg &= 5656 ~RTSI_Output_Bit(chan, 5657 (boardtype.reg_type & ni_reg_m_series_mask) != 5658 0); 5659 } else if (chan == old_RTSI_clock_channel) { 5660 devpriv->rtsi_trig_direction_reg &= 5661 ~Drive_RTSI_Clock_Bit; 5662 } 5663 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, 5664 RTSI_Trig_Direction_Register); 5665 break; 5666 case INSN_CONFIG_DIO_QUERY: 5667 if (chan < num_configurable_rtsi_channels(dev)) { 5668 data[1] = 5669 (devpriv-> 5670 rtsi_trig_direction_reg & RTSI_Output_Bit(chan, 5671 (boardtype. 5672 reg_type & ni_reg_m_series_mask) 5673 != 5674 0)) ? INSN_CONFIG_DIO_OUTPUT : 5675 INSN_CONFIG_DIO_INPUT; 5676 } else if (chan == old_RTSI_clock_channel) { 5677 data[1] = 5678 (devpriv-> 5679 rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit) 5680 ? INSN_CONFIG_DIO_OUTPUT : 5681 INSN_CONFIG_DIO_INPUT; 5682 } 5683 return 2; 5684 break; 5685 case INSN_CONFIG_SET_CLOCK_SRC: 5686 return ni_set_master_clock(dev, data[1], data[2]); 5687 break; 5688 case INSN_CONFIG_GET_CLOCK_SRC: 5689 data[1] = devpriv->clock_source; 5690 data[2] = devpriv->clock_ns; 5691 return 3; 5692 break; 5693 case INSN_CONFIG_SET_ROUTING: 5694 return ni_set_rtsi_routing(dev, chan, data[1]); 5695 break; 5696 case INSN_CONFIG_GET_ROUTING: 5697 data[1] = ni_get_rtsi_routing(dev, chan); 5698 return 2; 5699 break; 5700 default: 5701 return -EINVAL; 5702 break; 5703 } 5704 return 1; 5705} 5706 5707static int cs5529_wait_for_idle(struct comedi_device *dev) 5708{ 5709 unsigned short status; 5710 const int timeout = HZ; 5711 int i; 5712 5713 for (i = 0; i < timeout; i++) { 5714 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); 5715 if ((status & CSS_ADC_BUSY) == 0) { 5716 break; 5717 } 5718 set_current_state(TASK_INTERRUPTIBLE); 5719 if (schedule_timeout(1)) { 5720 return -EIO; 5721 } 5722 } 5723/* printk("looped %i times waiting for idle\n", i); */ 5724 if (i == timeout) { 5725 printk("%s: %s: timeout\n", __FILE__, __func__); 5726 return -ETIME; 5727 } 5728 return 0; 5729} 5730 5731static void cs5529_command(struct comedi_device *dev, unsigned short value) 5732{ 5733 static const int timeout = 100; 5734 int i; 5735 5736 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx); 5737 /* give time for command to start being serially clocked into cs5529. 5738 * this insures that the CSS_ADC_BUSY bit will get properly 5739 * set before we exit this function. 5740 */ 5741 for (i = 0; i < timeout; i++) { 5742 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY)) 5743 break; 5744 udelay(1); 5745 } 5746/* printk("looped %i times writing command to cs5529\n", i); */ 5747 if (i == timeout) { 5748 comedi_error(dev, "possible problem - never saw adc go busy?"); 5749 } 5750} 5751 5752/* write to cs5529 register */ 5753static void cs5529_config_write(struct comedi_device *dev, unsigned int value, 5754 unsigned int reg_select_bits) 5755{ 5756 ni_ao_win_outw(dev, ((value >> 16) & 0xff), 5757 CAL_ADC_Config_Data_High_Word_67xx); 5758 ni_ao_win_outw(dev, (value & 0xffff), 5759 CAL_ADC_Config_Data_Low_Word_67xx); 5760 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK; 5761 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits); 5762 if (cs5529_wait_for_idle(dev)) 5763 comedi_error(dev, "time or signal in cs5529_config_write()"); 5764} 5765 5766#ifdef NI_CS5529_DEBUG 5767/* read from cs5529 register */ 5768static unsigned int cs5529_config_read(struct comedi_device *dev, 5769 unsigned int reg_select_bits) 5770{ 5771 unsigned int value; 5772 5773 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK; 5774 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits); 5775 if (cs5529_wait_for_idle(dev)) 5776 comedi_error(dev, "timeout or signal in cs5529_config_read()"); 5777 value = (ni_ao_win_inw(dev, 5778 CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000; 5779 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff; 5780 return value; 5781} 5782#endif 5783 5784static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data) 5785{ 5786 int retval; 5787 unsigned short status; 5788 5789 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION); 5790 retval = cs5529_wait_for_idle(dev); 5791 if (retval) { 5792 comedi_error(dev, 5793 "timeout or signal in cs5529_do_conversion()"); 5794 return -ETIME; 5795 } 5796 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); 5797 if (status & CSS_OSC_DETECT) { 5798 printk 5799 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n"); 5800 return -EIO; 5801 } 5802 if (status & CSS_OVERRANGE) { 5803 printk 5804 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n"); 5805 } 5806 if (data) { 5807 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx); 5808 /* cs5529 returns 16 bit signed data in bipolar mode */ 5809 *data ^= (1 << 15); 5810 } 5811 return 0; 5812} 5813 5814static int cs5529_ai_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, 5815 struct comedi_insn *insn, unsigned int *data) 5816{ 5817 int n, retval; 5818 unsigned short sample; 5819 unsigned int channel_select; 5820 const unsigned int INTERNAL_REF = 0x1000; 5821 5822 /* Set calibration adc source. Docs lie, reference select bits 8 to 11 5823 * do nothing. bit 12 seems to chooses internal reference voltage, bit 5824 * 13 causes the adc input to go overrange (maybe reads external reference?) */ 5825 if (insn->chanspec & CR_ALT_SOURCE) 5826 channel_select = INTERNAL_REF; 5827 else 5828 channel_select = CR_CHAN(insn->chanspec); 5829 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx); 5830 5831 for (n = 0; n < insn->n; n++) { 5832 retval = cs5529_do_conversion(dev, &sample); 5833 if (retval < 0) 5834 return retval; 5835 data[n] = sample; 5836 } 5837 return insn->n; 5838} 5839 5840static int init_cs5529(struct comedi_device *dev) 5841{ 5842 unsigned int config_bits = 5843 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES; 5844 5845#if 1 5846 /* do self-calibration */ 5847 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, 5848 CSCMD_CONFIG_REGISTER); 5849 /* need to force a conversion for calibration to run */ 5850 cs5529_do_conversion(dev, NULL); 5851#else 5852 /* force gain calibration to 1 */ 5853 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER); 5854 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, 5855 CSCMD_CONFIG_REGISTER); 5856 if (cs5529_wait_for_idle(dev)) 5857 comedi_error(dev, "timeout or signal in init_cs5529()\n"); 5858#endif 5859#ifdef NI_CS5529_DEBUG 5860 printk("config: 0x%x\n", cs5529_config_read(dev, 5861 CSCMD_CONFIG_REGISTER)); 5862 printk("gain: 0x%x\n", cs5529_config_read(dev, 5863 CSCMD_GAIN_REGISTER)); 5864 printk("offset: 0x%x\n", cs5529_config_read(dev, 5865 CSCMD_OFFSET_REGISTER)); 5866#endif 5867 return 0; 5868} 5869