ni_pcidio.c revision 02f69d67684b77f7f04e281a026a790f0e08b3a3
1/* 2 comedi/drivers/ni_pcidio.c 3 driver for National Instruments PCI-DIO-96/PCI-6508 4 National Instruments PCI-DIO-32HS 5 National Instruments PCI-6503 6 7 COMEDI - Linux Control and Measurement Device Interface 8 Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org> 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 24*/ 25/* 26Driver: ni_pcidio 27Description: National Instruments PCI-DIO32HS, PCI-DIO96, PCI-6533, PCI-6503 28Author: ds 29Status: works 30Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio), PXI-6533, 31 PCI-DIO-96, PCI-DIO-96B, PXI-6508, PCI-6503, PCI-6503B, PCI-6503X, 32 PXI-6503, PCI-6533, PCI-6534 33Updated: Sun, 21 Apr 2002 21:03:38 -0700 34 35The DIO-96 appears as four 8255 subdevices. See the 8255 36driver notes for details. 37 38The DIO32HS board appears as one subdevice, with 32 channels. 39Each channel is individually I/O configurable. The channel order 40is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only 41supports simple digital I/O; no handshaking is supported. 42 43DMA mostly works for the PCI-DIO32HS, but only in timed input mode. 44 45This driver could be easily modified to support AT-MIO32HS and 46AT-MIO96. 47 48The PCI-6534 requires a firmware upload after power-up to work, the 49firmware data and instructions for loading it with comedi_config 50it are contained in the 51comedi_nonfree_firmware tarball available from http://www.comedi.org 52*/ 53 54/* 55 This driver is for both the NI PCI-DIO-32HS and the PCI-DIO-96, 56 which have very different architectures. But, since the '96 is 57 so simple, it is included here. 58 59 Manuals (available from ftp://ftp.natinst.com/support/manuals) 60 61 320938c.pdf PCI-DIO-96/PXI-6508/PCI-6503 User Manual 62 321464b.pdf AT/PCI-DIO-32HS User Manual 63 341329A.pdf PCI-6533 Register-Level Programmer Manual 64 341330A.pdf DAQ-DIO Technical Reference Manual 65 66 */ 67 68#define USE_DMA 69/* #define DEBUG 1 */ 70/* #define DEBUG_FLAGS */ 71 72#include <linux/interrupt.h> 73#include <linux/sched.h> 74#include "../comedidev.h" 75 76#include "mite.h" 77#include "8255.h" 78 79#undef DPRINTK 80#ifdef DEBUG 81#define DPRINTK(format, args...) printk(format, ## args) 82#else 83#define DPRINTK(format, args...) 84#endif 85 86#define PCI_DIO_SIZE 4096 87#define PCI_MITE_SIZE 4096 88 89/* defines for the PCI-DIO-96 */ 90 91#define NIDIO_8255_BASE(x) ((x)*4) 92#define NIDIO_A 0 93#define NIDIO_B 4 94#define NIDIO_C 8 95#define NIDIO_D 12 96 97/* defines for the PCI-DIO-32HS */ 98 99#define Window_Address 4 /* W */ 100#define Interrupt_And_Window_Status 4 /* R */ 101#define IntStatus1 (1<<0) 102#define IntStatus2 (1<<1) 103#define WindowAddressStatus_mask 0x7c 104 105#define Master_DMA_And_Interrupt_Control 5 /* W */ 106#define InterruptLine(x) ((x)&3) 107#define OpenInt (1<<2) 108#define Group_Status 5 /* R */ 109#define DataLeft (1<<0) 110#define Req (1<<2) 111#define StopTrig (1<<3) 112 113#define Group_1_Flags 6 /* R */ 114#define Group_2_Flags 7 /* R */ 115#define TransferReady (1<<0) 116#define CountExpired (1<<1) 117#define Waited (1<<5) 118#define PrimaryTC (1<<6) 119#define SecondaryTC (1<<7) 120 /* #define SerialRose */ 121 /* #define ReqRose */ 122 /* #define Paused */ 123 124#define Group_1_First_Clear 6 /* W */ 125#define Group_2_First_Clear 7 /* W */ 126#define ClearWaited (1<<3) 127#define ClearPrimaryTC (1<<4) 128#define ClearSecondaryTC (1<<5) 129#define DMAReset (1<<6) 130#define FIFOReset (1<<7) 131#define ClearAll 0xf8 132 133#define Group_1_FIFO 8 /* W */ 134#define Group_2_FIFO 12 /* W */ 135 136#define Transfer_Count 20 137#define Chip_ID_D 24 138#define Chip_ID_I 25 139#define Chip_ID_O 26 140#define Chip_Version 27 141#define Port_IO(x) (28+(x)) 142#define Port_Pin_Directions(x) (32+(x)) 143#define Port_Pin_Mask(x) (36+(x)) 144#define Port_Pin_Polarities(x) (40+(x)) 145 146#define Master_Clock_Routing 45 147#define RTSIClocking(x) (((x)&3)<<4) 148 149#define Group_1_Second_Clear 46 /* W */ 150#define Group_2_Second_Clear 47 /* W */ 151#define ClearExpired (1<<0) 152 153#define Port_Pattern(x) (48+(x)) 154 155#define Data_Path 64 156#define FIFOEnableA (1<<0) 157#define FIFOEnableB (1<<1) 158#define FIFOEnableC (1<<2) 159#define FIFOEnableD (1<<3) 160#define Funneling(x) (((x)&3)<<4) 161#define GroupDirection (1<<7) 162 163#define Protocol_Register_1 65 164#define OpMode Protocol_Register_1 165#define RunMode(x) ((x)&7) 166#define Numbered (1<<3) 167 168#define Protocol_Register_2 66 169#define ClockReg Protocol_Register_2 170#define ClockLine(x) (((x)&3)<<5) 171#define InvertStopTrig (1<<7) 172#define DataLatching(x) (((x)&3)<<5) 173 174#define Protocol_Register_3 67 175#define Sequence Protocol_Register_3 176 177#define Protocol_Register_14 68 /* 16 bit */ 178#define ClockSpeed Protocol_Register_14 179 180#define Protocol_Register_4 70 181#define ReqReg Protocol_Register_4 182#define ReqConditioning(x) (((x)&7)<<3) 183 184#define Protocol_Register_5 71 185#define BlockMode Protocol_Register_5 186 187#define FIFO_Control 72 188#define ReadyLevel(x) ((x)&7) 189 190#define Protocol_Register_6 73 191#define LinePolarities Protocol_Register_6 192#define InvertAck (1<<0) 193#define InvertReq (1<<1) 194#define InvertClock (1<<2) 195#define InvertSerial (1<<3) 196#define OpenAck (1<<4) 197#define OpenClock (1<<5) 198 199#define Protocol_Register_7 74 200#define AckSer Protocol_Register_7 201#define AckLine(x) (((x)&3)<<2) 202#define ExchangePins (1<<7) 203 204#define Interrupt_Control 75 205 /* bits same as flags */ 206 207#define DMA_Line_Control_Group1 76 208#define DMA_Line_Control_Group2 108 209/* channel zero is none */ 210static inline unsigned primary_DMAChannel_bits(unsigned channel) 211{ 212 return channel & 0x3; 213} 214 215static inline unsigned secondary_DMAChannel_bits(unsigned channel) 216{ 217 return (channel << 2) & 0xc; 218} 219 220#define Transfer_Size_Control 77 221#define TransferWidth(x) ((x)&3) 222#define TransferLength(x) (((x)&3)<<3) 223#define RequireRLevel (1<<5) 224 225#define Protocol_Register_15 79 226#define DAQOptions Protocol_Register_15 227#define StartSource(x) ((x)&0x3) 228#define InvertStart (1<<2) 229#define StopSource(x) (((x)&0x3)<<3) 230#define ReqStart (1<<6) 231#define PreStart (1<<7) 232 233#define Pattern_Detection 81 234#define DetectionMethod (1<<0) 235#define InvertMatch (1<<1) 236#define IE_Pattern_Detection (1<<2) 237 238#define Protocol_Register_9 82 239#define ReqDelay Protocol_Register_9 240 241#define Protocol_Register_10 83 242#define ReqNotDelay Protocol_Register_10 243 244#define Protocol_Register_11 84 245#define AckDelay Protocol_Register_11 246 247#define Protocol_Register_12 85 248#define AckNotDelay Protocol_Register_12 249 250#define Protocol_Register_13 86 251#define Data1Delay Protocol_Register_13 252 253#define Protocol_Register_8 88 /* 32 bit */ 254#define StartDelay Protocol_Register_8 255 256enum pci_6534_firmware_registers { /* 16 bit */ 257 Firmware_Control_Register = 0x100, 258 Firmware_Status_Register = 0x104, 259 Firmware_Data_Register = 0x108, 260 Firmware_Mask_Register = 0x10c, 261 Firmware_Debug_Register = 0x110, 262}; 263/* main fpga registers (32 bit)*/ 264enum pci_6534_fpga_registers { 265 FPGA_Control1_Register = 0x200, 266 FPGA_Control2_Register = 0x204, 267 FPGA_Irq_Mask_Register = 0x208, 268 FPGA_Status_Register = 0x20c, 269 FPGA_Signature_Register = 0x210, 270 FPGA_SCALS_Counter_Register = 0x280, /*write-clear */ 271 FPGA_SCAMS_Counter_Register = 0x284, /*write-clear */ 272 FPGA_SCBLS_Counter_Register = 0x288, /*write-clear */ 273 FPGA_SCBMS_Counter_Register = 0x28c, /*write-clear */ 274 FPGA_Temp_Control_Register = 0x2a0, 275 FPGA_DAR_Register = 0x2a8, 276 FPGA_ELC_Read_Register = 0x2b8, 277 FPGA_ELC_Write_Register = 0x2bc, 278}; 279enum FPGA_Control_Bits { 280 FPGA_Enable_Bit = 0x8000, 281}; 282 283#define TIMER_BASE 50 /* nanoseconds */ 284 285#ifdef USE_DMA 286#define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC) 287#else 288#define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC) 289#endif 290 291static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it); 292static int nidio_detach(struct comedi_device *dev); 293static int ni_pcidio_cancel(struct comedi_device *dev, 294 struct comedi_subdevice *s); 295 296static struct comedi_driver driver_pcidio = { 297 .driver_name = "ni_pcidio", 298 .module = THIS_MODULE, 299 .attach = nidio_attach, 300 .detach = nidio_detach, 301}; 302 303struct nidio_board { 304 305 int dev_id; 306 const char *name; 307 int n_8255; 308 unsigned int is_diodaq:1; 309 unsigned int uses_firmware:1; 310}; 311 312static const struct nidio_board nidio_boards[] = { 313 { 314 .dev_id = 0x1150, 315 .name = "pci-dio-32hs", 316 .n_8255 = 0, 317 .is_diodaq = 1, 318 }, 319 { 320 .dev_id = 0x1320, 321 .name = "pxi-6533", 322 .n_8255 = 0, 323 .is_diodaq = 1, 324 }, 325 { 326 .dev_id = 0x12b0, 327 .name = "pci-6534", 328 .n_8255 = 0, 329 .is_diodaq = 1, 330 .uses_firmware = 1, 331 }, 332 { 333 .dev_id = 0x0160, 334 .name = "pci-dio-96", 335 .n_8255 = 4, 336 .is_diodaq = 0, 337 }, 338 { 339 .dev_id = 0x1630, 340 .name = "pci-dio-96b", 341 .n_8255 = 4, 342 .is_diodaq = 0, 343 }, 344 { 345 .dev_id = 0x13c0, 346 .name = "pxi-6508", 347 .n_8255 = 4, 348 .is_diodaq = 0, 349 }, 350 { 351 .dev_id = 0x0400, 352 .name = "pci-6503", 353 .n_8255 = 1, 354 .is_diodaq = 0, 355 }, 356 { 357 .dev_id = 0x1250, 358 .name = "pci-6503b", 359 .n_8255 = 1, 360 .is_diodaq = 0, 361 }, 362 { 363 .dev_id = 0x17d0, 364 .name = "pci-6503x", 365 .n_8255 = 1, 366 .is_diodaq = 0, 367 }, 368 { 369 .dev_id = 0x1800, 370 .name = "pxi-6503", 371 .n_8255 = 1, 372 .is_diodaq = 0, 373 }, 374}; 375 376#define n_nidio_boards ARRAY_SIZE(nidio_boards) 377#define this_board ((const struct nidio_board *)dev->board_ptr) 378 379static DEFINE_PCI_DEVICE_TABLE(ni_pcidio_pci_table) = { 380 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1150)}, 381 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1320)}, 382 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x12b0)}, 383 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0160)}, 384 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1630)}, 385 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x13c0)}, 386 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0400)}, 387 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1250)}, 388 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x17d0)}, 389 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1800)}, 390 {0} 391}; 392 393MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table); 394 395struct nidio96_private { 396 struct mite_struct *mite; 397 int boardtype; 398 int dio; 399 unsigned short OpModeBits; 400 struct mite_channel *di_mite_chan; 401 struct mite_dma_descriptor_ring *di_mite_ring; 402 spinlock_t mite_channel_lock; 403}; 404#define devpriv ((struct nidio96_private *)dev->private) 405 406static int ni_pcidio_cmdtest(struct comedi_device *dev, 407 struct comedi_subdevice *s, 408 struct comedi_cmd *cmd); 409static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 410static int ni_pcidio_inttrig(struct comedi_device *dev, 411 struct comedi_subdevice *s, unsigned int trignum); 412static int nidio_find_device(struct comedi_device *dev, int bus, int slot); 413static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode); 414static int setup_mite_dma(struct comedi_device *dev, 415 struct comedi_subdevice *s); 416 417#ifdef DEBUG_FLAGS 418static void ni_pcidio_print_flags(unsigned int flags); 419static void ni_pcidio_print_status(unsigned int status); 420#else 421#define ni_pcidio_print_flags(x) 422#define ni_pcidio_print_status(x) 423#endif 424 425static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev) 426{ 427 unsigned long flags; 428 429 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 430 BUG_ON(devpriv->di_mite_chan); 431 devpriv->di_mite_chan = 432 mite_request_channel_in_range(devpriv->mite, 433 devpriv->di_mite_ring, 1, 2); 434 if (devpriv->di_mite_chan == NULL) { 435 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 436 comedi_error(dev, "failed to reserve mite dma channel."); 437 return -EBUSY; 438 } 439 devpriv->di_mite_chan->dir = COMEDI_INPUT; 440 writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) | 441 secondary_DMAChannel_bits(devpriv->di_mite_chan->channel), 442 devpriv->mite->daq_io_addr + DMA_Line_Control_Group1); 443 mmiowb(); 444 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 445 return 0; 446} 447 448static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev) 449{ 450 unsigned long flags; 451 452 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 453 if (devpriv->di_mite_chan) { 454 mite_dma_disarm(devpriv->di_mite_chan); 455 mite_dma_reset(devpriv->di_mite_chan); 456 mite_release_channel(devpriv->di_mite_chan); 457 devpriv->di_mite_chan = NULL; 458 writeb(primary_DMAChannel_bits(0) | 459 secondary_DMAChannel_bits(0), 460 devpriv->mite->daq_io_addr + DMA_Line_Control_Group1); 461 mmiowb(); 462 } 463 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 464} 465 466static int nidio96_8255_cb(int dir, int port, int data, unsigned long iobase) 467{ 468 if (dir) { 469 writeb(data, (void *)(iobase + port)); 470 return 0; 471 } else { 472 return readb((void *)(iobase + port)); 473 } 474} 475 476void ni_pcidio_event(struct comedi_device *dev, struct comedi_subdevice *s) 477{ 478 if (s-> 479 async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR | 480 COMEDI_CB_OVERFLOW)) { 481 ni_pcidio_cancel(dev, s); 482 } 483 comedi_event(dev, s); 484} 485 486static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s) 487{ 488 unsigned long irq_flags; 489 int count; 490 491 spin_lock_irqsave(&dev->spinlock, irq_flags); 492 spin_lock(&devpriv->mite_channel_lock); 493 if (devpriv->di_mite_chan) 494 mite_sync_input_dma(devpriv->di_mite_chan, s->async); 495 spin_unlock(&devpriv->mite_channel_lock); 496 count = s->async->buf_write_count - s->async->buf_read_count; 497 spin_unlock_irqrestore(&dev->spinlock, irq_flags); 498 return count; 499} 500 501static irqreturn_t nidio_interrupt(int irq, void *d) 502{ 503 struct comedi_device *dev = d; 504 struct comedi_subdevice *s = dev->subdevices; 505 struct comedi_async *async = s->async; 506 struct mite_struct *mite = devpriv->mite; 507 508 /* int i, j; */ 509 long int AuxData = 0; 510 short data1 = 0; 511 short data2 = 0; 512 int flags; 513 int status; 514 int work = 0; 515 unsigned int m_status = 0; 516 517 /* interrupcions parasites */ 518 if (dev->attached == 0) { 519 /* assume it's from another card */ 520 return IRQ_NONE; 521 } 522 523 /* Lock to avoid race with comedi_poll */ 524 spin_lock(&dev->spinlock); 525 526 status = readb(devpriv->mite->daq_io_addr + 527 Interrupt_And_Window_Status); 528 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 529 530 DPRINTK("ni_pcidio_interrupt: status=0x%02x,flags=0x%02x\n", 531 status, flags); 532 ni_pcidio_print_flags(flags); 533 ni_pcidio_print_status(status); 534 535 /* printk("buf[0]=%08x\n",*(unsigned int *)async->prealloc_buf); */ 536 /* printk("buf[4096]=%08x\n", 537 *(unsigned int *)(async->prealloc_buf+4096)); */ 538 539 spin_lock(&devpriv->mite_channel_lock); 540 if (devpriv->di_mite_chan) 541 m_status = mite_get_status(devpriv->di_mite_chan); 542#ifdef MITE_DEBUG 543 mite_print_chsr(m_status); 544#endif 545 /* printk("mite_bytes_transferred: %d\n", 546 mite_bytes_transferred(mite,DI_DMA_CHAN)); */ 547 548 /* mite_dump_regs(mite); */ 549 if (m_status & CHSR_INT) { 550 if (m_status & CHSR_LINKC) { 551 writel(CHOR_CLRLC, 552 mite->mite_io_addr + 553 MITE_CHOR(devpriv->di_mite_chan->channel)); 554 mite_sync_input_dma(devpriv->di_mite_chan, s->async); 555 /* XXX need to byteswap */ 556 } 557 if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY | 558 CHSR_DRQ1 | CHSR_MRDY)) { 559 DPRINTK("unknown mite interrupt, disabling IRQ\n"); 560 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 561 disable_irq(dev->irq); 562 } 563 } 564 spin_unlock(&devpriv->mite_channel_lock); 565 566 while (status & DataLeft) { 567 work++; 568 if (work > 20) { 569 DPRINTK("too much work in interrupt\n"); 570 writeb(0x00, 571 devpriv->mite->daq_io_addr + 572 Master_DMA_And_Interrupt_Control); 573 break; 574 } 575 576 flags &= IntEn; 577 578 if (flags & TransferReady) { 579 /* DPRINTK("TransferReady\n"); */ 580 while (flags & TransferReady) { 581 work++; 582 if (work > 100) { 583 DPRINTK("too much work in interrupt\n"); 584 writeb(0x00, 585 devpriv->mite->daq_io_addr + 586 Master_DMA_And_Interrupt_Control 587 ); 588 goto out; 589 } 590 AuxData = 591 readl(devpriv->mite->daq_io_addr + 592 Group_1_FIFO); 593 data1 = AuxData & 0xffff; 594 data2 = (AuxData & 0xffff0000) >> 16; 595 comedi_buf_put(async, data1); 596 comedi_buf_put(async, data2); 597 /* DPRINTK("read:%d, %d\n",data1,data2); */ 598 flags = readb(devpriv->mite->daq_io_addr + 599 Group_1_Flags); 600 } 601 /* DPRINTK("buf_int_count: %d\n", 602 async->buf_int_count); */ 603 /* DPRINTK("1) IntEn=%d,flags=%d,status=%d\n", 604 IntEn,flags,status); */ 605 /* ni_pcidio_print_flags(flags); */ 606 /* ni_pcidio_print_status(status); */ 607 async->events |= COMEDI_CB_BLOCK; 608 } 609 610 if (flags & CountExpired) { 611 DPRINTK("CountExpired\n"); 612 writeb(ClearExpired, 613 devpriv->mite->daq_io_addr + 614 Group_1_Second_Clear); 615 async->events |= COMEDI_CB_EOA; 616 617 writeb(0x00, devpriv->mite->daq_io_addr + OpMode); 618 break; 619 } else if (flags & Waited) { 620 DPRINTK("Waited\n"); 621 writeb(ClearWaited, 622 devpriv->mite->daq_io_addr + 623 Group_1_First_Clear); 624 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 625 break; 626 } else if (flags & PrimaryTC) { 627 DPRINTK("PrimaryTC\n"); 628 writeb(ClearPrimaryTC, 629 devpriv->mite->daq_io_addr + 630 Group_1_First_Clear); 631 async->events |= COMEDI_CB_EOA; 632 } else if (flags & SecondaryTC) { 633 DPRINTK("SecondaryTC\n"); 634 writeb(ClearSecondaryTC, 635 devpriv->mite->daq_io_addr + 636 Group_1_First_Clear); 637 async->events |= COMEDI_CB_EOA; 638 } 639#if 0 640 else { 641 printk("ni_pcidio: unknown interrupt\n"); 642 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 643 writeb(0x00, 644 devpriv->mite->daq_io_addr + 645 Master_DMA_And_Interrupt_Control); 646 } 647#endif 648 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 649 status = readb(devpriv->mite->daq_io_addr + 650 Interrupt_And_Window_Status); 651 /* DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x," 652 "status=0x%02x\n", IntEn, flags, status); */ 653 /* ni_pcidio_print_flags(flags); */ 654 /* ni_pcidio_print_status(status); */ 655 } 656 657out: 658 ni_pcidio_event(dev, s); 659#if 0 660 if (!tag) { 661 writeb(0x03, 662 devpriv->mite->daq_io_addr + 663 Master_DMA_And_Interrupt_Control); 664 } 665#endif 666 667 spin_unlock(&dev->spinlock); 668 return IRQ_HANDLED; 669} 670 671#ifdef DEBUG_FLAGS 672static const char *const flags_strings[] = { 673 "TransferReady", "CountExpired", "2", "3", 674 "4", "Waited", "PrimaryTC", "SecondaryTC", 675}; 676 677static void ni_pcidio_print_flags(unsigned int flags) 678{ 679 int i; 680 681 printk(KERN_INFO "group_1_flags:"); 682 for (i = 7; i >= 0; i--) { 683 if (flags & (1 << i)) 684 printk(" %s", flags_strings[i]); 685 } 686 printk("\n"); 687} 688 689static char *status_strings[] = { 690 "DataLeft1", "Reserved1", "Req1", "StopTrig1", 691 "DataLeft2", "Reserved2", "Req2", "StopTrig2", 692}; 693 694static void ni_pcidio_print_status(unsigned int flags) 695{ 696 int i; 697 698 printk(KERN_INFO "group_status:"); 699 for (i = 7; i >= 0; i--) { 700 if (flags & (1 << i)) 701 printk(" %s", status_strings[i]); 702 } 703 printk("\n"); 704} 705#endif 706 707#ifdef unused 708static void debug_int(struct comedi_device *dev) 709{ 710 int a, b; 711 static int n_int; 712 struct timeval tv; 713 714 do_gettimeofday(&tv); 715 a = readb(devpriv->mite->daq_io_addr + Group_Status); 716 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 717 718 if (n_int < 10) { 719 DPRINTK("status 0x%02x flags 0x%02x time %06d\n", a, b, 720 (int)tv.tv_usec); 721 } 722 723 while (b & 1) { 724 writew(0xff, devpriv->mite->daq_io_addr + Group_1_FIFO); 725 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 726 } 727 728 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 729 730 if (n_int < 10) { 731 DPRINTK("new status 0x%02x\n", b); 732 n_int++; 733 } 734} 735#endif 736 737static int ni_pcidio_insn_config(struct comedi_device *dev, 738 struct comedi_subdevice *s, 739 struct comedi_insn *insn, unsigned int *data) 740{ 741 if (insn->n != 1) 742 return -EINVAL; 743 switch (data[0]) { 744 case INSN_CONFIG_DIO_OUTPUT: 745 s->io_bits |= 1 << CR_CHAN(insn->chanspec); 746 break; 747 case INSN_CONFIG_DIO_INPUT: 748 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec)); 749 break; 750 case INSN_CONFIG_DIO_QUERY: 751 data[1] = 752 (s-> 753 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : 754 COMEDI_INPUT; 755 return insn->n; 756 break; 757 default: 758 return -EINVAL; 759 } 760 writel(s->io_bits, devpriv->mite->daq_io_addr + Port_Pin_Directions(0)); 761 762 return 1; 763} 764 765static int ni_pcidio_insn_bits(struct comedi_device *dev, 766 struct comedi_subdevice *s, 767 struct comedi_insn *insn, unsigned int *data) 768{ 769 if (insn->n != 2) 770 return -EINVAL; 771 if (data[0]) { 772 s->state &= ~data[0]; 773 s->state |= (data[0] & data[1]); 774 writel(s->state, devpriv->mite->daq_io_addr + Port_IO(0)); 775 } 776 data[1] = readl(devpriv->mite->daq_io_addr + Port_IO(0)); 777 778 return 2; 779} 780 781static int ni_pcidio_cmdtest(struct comedi_device *dev, 782 struct comedi_subdevice *s, struct comedi_cmd *cmd) 783{ 784 int err = 0; 785 int tmp; 786 787 /* step 1: make sure trigger sources are trivially valid */ 788 789 tmp = cmd->start_src; 790 cmd->start_src &= TRIG_NOW | TRIG_INT; 791 if (!cmd->start_src || tmp != cmd->start_src) 792 err++; 793 794 tmp = cmd->scan_begin_src; 795 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; 796 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 797 err++; 798 799 tmp = cmd->convert_src; 800 cmd->convert_src &= TRIG_NOW; 801 if (!cmd->convert_src || tmp != cmd->convert_src) 802 err++; 803 804 tmp = cmd->scan_end_src; 805 cmd->scan_end_src &= TRIG_COUNT; 806 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 807 err++; 808 809 tmp = cmd->stop_src; 810 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 811 if (!cmd->stop_src || tmp != cmd->stop_src) 812 err++; 813 814 if (err) 815 return 1; 816 817 /* step 2: make sure trigger sources are unique and mutually 818 compatible */ 819 820 /* note that mutual compatibility is not an issue here */ 821 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_INT) 822 err++; 823 if (cmd->scan_begin_src != TRIG_TIMER && 824 cmd->scan_begin_src != TRIG_EXT) 825 err++; 826 827 if (err) 828 return 2; 829 830 /* step 3: make sure arguments are trivially compatible */ 831 832 if (cmd->start_arg != 0) { 833 /* same for both TRIG_INT and TRIG_NOW */ 834 cmd->start_arg = 0; 835 err++; 836 } 837#define MAX_SPEED (TIMER_BASE) /* in nanoseconds */ 838 839 if (cmd->scan_begin_src == TRIG_TIMER) { 840 if (cmd->scan_begin_arg < MAX_SPEED) { 841 cmd->scan_begin_arg = MAX_SPEED; 842 err++; 843 } 844 /* no minimum speed */ 845 } else { 846 /* TRIG_EXT */ 847 /* should be level/edge, hi/lo specification here */ 848 if (cmd->scan_begin_arg != 0) { 849 cmd->scan_begin_arg = 0; 850 err++; 851 } 852 } 853 if (cmd->convert_arg != 0) { 854 cmd->convert_arg = 0; 855 err++; 856 } 857 858 if (cmd->scan_end_arg != cmd->chanlist_len) { 859 cmd->scan_end_arg = cmd->chanlist_len; 860 err++; 861 } 862 if (cmd->stop_src == TRIG_COUNT) { 863 /* no limit */ 864 } else { 865 /* TRIG_NONE */ 866 if (cmd->stop_arg != 0) { 867 cmd->stop_arg = 0; 868 err++; 869 } 870 } 871 872 if (err) 873 return 3; 874 875 /* step 4: fix up any arguments */ 876 877 if (cmd->scan_begin_src == TRIG_TIMER) { 878 tmp = cmd->scan_begin_arg; 879 ni_pcidio_ns_to_timer(&cmd->scan_begin_arg, 880 cmd->flags & TRIG_ROUND_MASK); 881 if (tmp != cmd->scan_begin_arg) 882 err++; 883 } 884 885 if (err) 886 return 4; 887 888 return 0; 889} 890 891static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode) 892{ 893 int divider, base; 894 895 base = TIMER_BASE; 896 897 switch (round_mode) { 898 case TRIG_ROUND_NEAREST: 899 default: 900 divider = (*nanosec + base / 2) / base; 901 break; 902 case TRIG_ROUND_DOWN: 903 divider = (*nanosec) / base; 904 break; 905 case TRIG_ROUND_UP: 906 divider = (*nanosec + base - 1) / base; 907 break; 908 } 909 910 *nanosec = base * divider; 911 return divider; 912} 913 914static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 915{ 916 struct comedi_cmd *cmd = &s->async->cmd; 917 918 /* XXX configure ports for input */ 919 writel(0x0000, devpriv->mite->daq_io_addr + Port_Pin_Directions(0)); 920 921 if (1) { 922 /* enable fifos A B C D */ 923 writeb(0x0f, devpriv->mite->daq_io_addr + Data_Path); 924 925 /* set transfer width a 32 bits */ 926 writeb(TransferWidth(0) | TransferLength(0), 927 devpriv->mite->daq_io_addr + Transfer_Size_Control); 928 } else { 929 writeb(0x03, devpriv->mite->daq_io_addr + Data_Path); 930 writeb(TransferWidth(3) | TransferLength(0), 931 devpriv->mite->daq_io_addr + Transfer_Size_Control); 932 } 933 934 /* protocol configuration */ 935 if (cmd->scan_begin_src == TRIG_TIMER) { 936 /* page 4-5, "input with internal REQs" */ 937 writeb(0, devpriv->mite->daq_io_addr + OpMode); 938 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg); 939 writeb(1, devpriv->mite->daq_io_addr + Sequence); 940 writeb(0x04, devpriv->mite->daq_io_addr + ReqReg); 941 writeb(4, devpriv->mite->daq_io_addr + BlockMode); 942 writeb(3, devpriv->mite->daq_io_addr + LinePolarities); 943 writeb(0xc0, devpriv->mite->daq_io_addr + AckSer); 944 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg, 945 TRIG_ROUND_NEAREST), 946 devpriv->mite->daq_io_addr + StartDelay); 947 writeb(1, devpriv->mite->daq_io_addr + ReqDelay); 948 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay); 949 writeb(1, devpriv->mite->daq_io_addr + AckDelay); 950 writeb(0x0b, devpriv->mite->daq_io_addr + AckNotDelay); 951 writeb(0x01, devpriv->mite->daq_io_addr + Data1Delay); 952 /* manual, page 4-5: ClockSpeed comment is incorrectly listed 953 * on DAQOptions */ 954 writew(0, devpriv->mite->daq_io_addr + ClockSpeed); 955 writeb(0, devpriv->mite->daq_io_addr + DAQOptions); 956 } else { 957 /* TRIG_EXT */ 958 /* page 4-5, "input with external REQs" */ 959 writeb(0, devpriv->mite->daq_io_addr + OpMode); 960 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg); 961 writeb(0, devpriv->mite->daq_io_addr + Sequence); 962 writeb(0x00, devpriv->mite->daq_io_addr + ReqReg); 963 writeb(4, devpriv->mite->daq_io_addr + BlockMode); 964 writeb(0, devpriv->mite->daq_io_addr + LinePolarities); 965 writeb(0x00, devpriv->mite->daq_io_addr + AckSer); 966 writel(1, devpriv->mite->daq_io_addr + StartDelay); 967 writeb(1, devpriv->mite->daq_io_addr + ReqDelay); 968 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay); 969 writeb(1, devpriv->mite->daq_io_addr + AckDelay); 970 writeb(0x0C, devpriv->mite->daq_io_addr + AckNotDelay); 971 writeb(0x10, devpriv->mite->daq_io_addr + Data1Delay); 972 writew(0, devpriv->mite->daq_io_addr + ClockSpeed); 973 writeb(0x60, devpriv->mite->daq_io_addr + DAQOptions); 974 } 975 976 if (cmd->stop_src == TRIG_COUNT) { 977 writel(cmd->stop_arg, 978 devpriv->mite->daq_io_addr + Transfer_Count); 979 } else { 980 /* XXX */ 981 } 982 983#ifdef USE_DMA 984 writeb(ClearPrimaryTC | ClearSecondaryTC, 985 devpriv->mite->daq_io_addr + Group_1_First_Clear); 986 987 { 988 int retval = setup_mite_dma(dev, s); 989 if (retval) 990 return retval; 991 } 992#else 993 writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group1); 994#endif 995 writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group2); 996 997 /* clear and enable interrupts */ 998 writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear); 999 /* writeb(ClearExpired, 1000 devpriv->mite->daq_io_addr+Group_1_Second_Clear); */ 1001 1002 writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control); 1003 writeb(0x03, 1004 devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control); 1005 1006 if (cmd->stop_src == TRIG_NONE) { 1007 devpriv->OpModeBits = DataLatching(0) | RunMode(7); 1008 } else { /* TRIG_TIMER */ 1009 devpriv->OpModeBits = Numbered | RunMode(7); 1010 } 1011 if (cmd->start_src == TRIG_NOW) { 1012 /* start */ 1013 writeb(devpriv->OpModeBits, 1014 devpriv->mite->daq_io_addr + OpMode); 1015 s->async->inttrig = NULL; 1016 } else { 1017 /* TRIG_INT */ 1018 s->async->inttrig = ni_pcidio_inttrig; 1019 } 1020 1021 DPRINTK("ni_pcidio: command started\n"); 1022 return 0; 1023} 1024 1025static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s) 1026{ 1027 int retval; 1028 unsigned long flags; 1029 1030 retval = ni_pcidio_request_di_mite_channel(dev); 1031 if (retval) 1032 return retval; 1033 1034 /* write alloc the entire buffer */ 1035 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz); 1036 1037 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1038 if (devpriv->di_mite_chan) { 1039 mite_prep_dma(devpriv->di_mite_chan, 32, 32); 1040 mite_dma_arm(devpriv->di_mite_chan); 1041 } else 1042 retval = -EIO; 1043 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1044 1045 return retval; 1046} 1047 1048static int ni_pcidio_inttrig(struct comedi_device *dev, 1049 struct comedi_subdevice *s, unsigned int trignum) 1050{ 1051 if (trignum != 0) 1052 return -EINVAL; 1053 1054 writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr + OpMode); 1055 s->async->inttrig = NULL; 1056 1057 return 1; 1058} 1059 1060static int ni_pcidio_cancel(struct comedi_device *dev, 1061 struct comedi_subdevice *s) 1062{ 1063 writeb(0x00, 1064 devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control); 1065 ni_pcidio_release_di_mite_channel(dev); 1066 1067 return 0; 1068} 1069 1070static int ni_pcidio_change(struct comedi_device *dev, 1071 struct comedi_subdevice *s, unsigned long new_size) 1072{ 1073 int ret; 1074 1075 ret = mite_buf_change(devpriv->di_mite_ring, s->async); 1076 if (ret < 0) 1077 return ret; 1078 1079 memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz); 1080 1081 return 0; 1082} 1083 1084static int pci_6534_load_fpga(struct comedi_device *dev, int fpga_index, 1085 u8 *data, int data_len) 1086{ 1087 static const int timeout = 1000; 1088 int i, j; 1089 writew(0x80 | fpga_index, 1090 devpriv->mite->daq_io_addr + Firmware_Control_Register); 1091 writew(0xc0 | fpga_index, 1092 devpriv->mite->daq_io_addr + Firmware_Control_Register); 1093 for (i = 0; 1094 (readw(devpriv->mite->daq_io_addr + 1095 Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i) { 1096 udelay(1); 1097 } 1098 if (i == timeout) { 1099 printk(KERN_WARNING "ni_pcidio: failed to load fpga %i, " 1100 "waiting for status 0x2\n", fpga_index); 1101 return -EIO; 1102 } 1103 writew(0x80 | fpga_index, 1104 devpriv->mite->daq_io_addr + Firmware_Control_Register); 1105 for (i = 0; 1106 readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) != 1107 0x3 && i < timeout; ++i) { 1108 udelay(1); 1109 } 1110 if (i == timeout) { 1111 printk(KERN_WARNING "ni_pcidio: failed to load fpga %i, " 1112 "waiting for status 0x3\n", fpga_index); 1113 return -EIO; 1114 } 1115 for (j = 0; j + 1 < data_len;) { 1116 unsigned int value = data[j++]; 1117 value |= data[j++] << 8; 1118 writew(value, 1119 devpriv->mite->daq_io_addr + Firmware_Data_Register); 1120 for (i = 0; 1121 (readw(devpriv->mite->daq_io_addr + 1122 Firmware_Status_Register) & 0x2) == 0 1123 && i < timeout; ++i) { 1124 udelay(1); 1125 } 1126 if (i == timeout) { 1127 printk("ni_pcidio: failed to load word into fpga %i\n", 1128 fpga_index); 1129 return -EIO; 1130 } 1131 if (need_resched()) 1132 schedule(); 1133 } 1134 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register); 1135 return 0; 1136} 1137 1138static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index) 1139{ 1140 return pci_6534_load_fpga(dev, fpga_index, NULL, 0); 1141} 1142 1143static int pci_6534_reset_fpgas(struct comedi_device *dev) 1144{ 1145 int ret; 1146 int i; 1147 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register); 1148 for (i = 0; i < 3; ++i) { 1149 ret = pci_6534_reset_fpga(dev, i); 1150 if (ret < 0) 1151 break; 1152 } 1153 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Mask_Register); 1154 return ret; 1155} 1156 1157static void pci_6534_init_main_fpga(struct comedi_device *dev) 1158{ 1159 writel(0, devpriv->mite->daq_io_addr + FPGA_Control1_Register); 1160 writel(0, devpriv->mite->daq_io_addr + FPGA_Control2_Register); 1161 writel(0, devpriv->mite->daq_io_addr + FPGA_SCALS_Counter_Register); 1162 writel(0, devpriv->mite->daq_io_addr + FPGA_SCAMS_Counter_Register); 1163 writel(0, devpriv->mite->daq_io_addr + FPGA_SCBLS_Counter_Register); 1164 writel(0, devpriv->mite->daq_io_addr + FPGA_SCBMS_Counter_Register); 1165} 1166 1167static int pci_6534_upload_firmware(struct comedi_device *dev, int options[]) 1168{ 1169 int ret; 1170 void *main_fpga_data, *scarab_a_data, *scarab_b_data; 1171 int main_fpga_data_len, scarab_a_data_len, scarab_b_data_len; 1172 1173 if (options[COMEDI_DEVCONF_AUX_DATA_LENGTH] == 0) 1174 return 0; 1175 ret = pci_6534_reset_fpgas(dev); 1176 if (ret < 0) 1177 return ret; 1178 main_fpga_data = comedi_aux_data(options, 0); 1179 main_fpga_data_len = options[COMEDI_DEVCONF_AUX_DATA0_LENGTH]; 1180 ret = pci_6534_load_fpga(dev, 2, main_fpga_data, main_fpga_data_len); 1181 if (ret < 0) 1182 return ret; 1183 pci_6534_init_main_fpga(dev); 1184 scarab_a_data = comedi_aux_data(options, 1); 1185 scarab_a_data_len = options[COMEDI_DEVCONF_AUX_DATA1_LENGTH]; 1186 ret = pci_6534_load_fpga(dev, 0, scarab_a_data, scarab_a_data_len); 1187 if (ret < 0) 1188 return ret; 1189 scarab_b_data = comedi_aux_data(options, 2); 1190 scarab_b_data_len = options[COMEDI_DEVCONF_AUX_DATA2_LENGTH]; 1191 ret = pci_6534_load_fpga(dev, 1, scarab_b_data, scarab_b_data_len); 1192 if (ret < 0) 1193 return ret; 1194 return 0; 1195} 1196 1197static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it) 1198{ 1199 struct comedi_subdevice *s; 1200 int i; 1201 int ret; 1202 int n_subdevices; 1203 unsigned int irq; 1204 1205 printk(KERN_INFO "comedi%d: nidio:", dev->minor); 1206 1207 ret = alloc_private(dev, sizeof(struct nidio96_private)); 1208 if (ret < 0) 1209 return ret; 1210 spin_lock_init(&devpriv->mite_channel_lock); 1211 1212 ret = nidio_find_device(dev, it->options[0], it->options[1]); 1213 if (ret < 0) 1214 return ret; 1215 1216 ret = mite_setup(devpriv->mite); 1217 if (ret < 0) { 1218 printk(KERN_WARNING "error setting up mite\n"); 1219 return ret; 1220 } 1221 comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev); 1222 devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite); 1223 if (devpriv->di_mite_ring == NULL) 1224 return -ENOMEM; 1225 1226 dev->board_name = this_board->name; 1227 irq = mite_irq(devpriv->mite); 1228 printk(KERN_INFO " %s", dev->board_name); 1229 if (this_board->uses_firmware) { 1230 ret = pci_6534_upload_firmware(dev, it->options); 1231 if (ret < 0) 1232 return ret; 1233 } 1234 if (!this_board->is_diodaq) 1235 n_subdevices = this_board->n_8255; 1236 else 1237 n_subdevices = 1; 1238 1239 ret = alloc_subdevices(dev, n_subdevices); 1240 if (ret < 0) 1241 return ret; 1242 1243 if (!this_board->is_diodaq) { 1244 for (i = 0; i < this_board->n_8255; i++) { 1245 subdev_8255_init(dev, dev->subdevices + i, 1246 nidio96_8255_cb, 1247 (unsigned long)(devpriv->mite-> 1248 daq_io_addr + 1249 NIDIO_8255_BASE(i))); 1250 } 1251 } else { 1252 1253 printk(KERN_INFO " rev=%d", 1254 readb(devpriv->mite->daq_io_addr + Chip_Version)); 1255 1256 s = dev->subdevices + 0; 1257 1258 dev->read_subdev = s; 1259 s->type = COMEDI_SUBD_DIO; 1260 s->subdev_flags = 1261 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED | 1262 SDF_CMD_READ; 1263 s->n_chan = 32; 1264 s->range_table = &range_digital; 1265 s->maxdata = 1; 1266 s->insn_config = &ni_pcidio_insn_config; 1267 s->insn_bits = &ni_pcidio_insn_bits; 1268 s->do_cmd = &ni_pcidio_cmd; 1269 s->do_cmdtest = &ni_pcidio_cmdtest; 1270 s->cancel = &ni_pcidio_cancel; 1271 s->len_chanlist = 32; /* XXX */ 1272 s->buf_change = &ni_pcidio_change; 1273 s->async_dma_dir = DMA_BIDIRECTIONAL; 1274 s->poll = &ni_pcidio_poll; 1275 1276 writel(0, devpriv->mite->daq_io_addr + Port_IO(0)); 1277 writel(0, devpriv->mite->daq_io_addr + Port_Pin_Directions(0)); 1278 writel(0, devpriv->mite->daq_io_addr + Port_Pin_Mask(0)); 1279 1280 /* disable interrupts on board */ 1281 writeb(0x00, 1282 devpriv->mite->daq_io_addr + 1283 Master_DMA_And_Interrupt_Control); 1284 1285 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED, 1286 "ni_pcidio", dev); 1287 if (ret < 0) 1288 printk(KERN_WARNING " irq not available"); 1289 1290 dev->irq = irq; 1291 } 1292 1293 printk("\n"); 1294 1295 return 0; 1296} 1297 1298static int nidio_detach(struct comedi_device *dev) 1299{ 1300 int i; 1301 1302 if (this_board && !this_board->is_diodaq) { 1303 for (i = 0; i < this_board->n_8255; i++) 1304 subdev_8255_cleanup(dev, dev->subdevices + i); 1305 } 1306 1307 if (dev->irq) 1308 free_irq(dev->irq, dev); 1309 1310 if (devpriv) { 1311 if (devpriv->di_mite_ring) { 1312 mite_free_ring(devpriv->di_mite_ring); 1313 devpriv->di_mite_ring = NULL; 1314 } 1315 if (devpriv->mite) 1316 mite_unsetup(devpriv->mite); 1317 } 1318 return 0; 1319} 1320 1321static int nidio_find_device(struct comedi_device *dev, int bus, int slot) 1322{ 1323 struct mite_struct *mite; 1324 int i; 1325 1326 for (mite = mite_devices; mite; mite = mite->next) { 1327 if (mite->used) 1328 continue; 1329 if (bus || slot) { 1330 if (bus != mite->pcidev->bus->number || 1331 slot != PCI_SLOT(mite->pcidev->devfn)) 1332 continue; 1333 } 1334 for (i = 0; i < n_nidio_boards; i++) { 1335 if (mite_device_id(mite) == nidio_boards[i].dev_id) { 1336 dev->board_ptr = nidio_boards + i; 1337 devpriv->mite = mite; 1338 1339 return 0; 1340 } 1341 } 1342 } 1343 printk(KERN_WARNING "no device found\n"); 1344 mite_list_devices(); 1345 return -EIO; 1346} 1347 1348static int __devinit driver_pcidio_pci_probe(struct pci_dev *dev, 1349 const struct pci_device_id *ent) 1350{ 1351 return comedi_pci_auto_config(dev, driver_pcidio.driver_name); 1352} 1353 1354static void __devexit driver_pcidio_pci_remove(struct pci_dev *dev) 1355{ 1356 comedi_pci_auto_unconfig(dev); 1357} 1358 1359static struct pci_driver driver_pcidio_pci_driver = { 1360 .id_table = ni_pcidio_pci_table, 1361 .probe = &driver_pcidio_pci_probe, 1362 .remove = __devexit_p(&driver_pcidio_pci_remove) 1363}; 1364 1365static int __init driver_pcidio_init_module(void) 1366{ 1367 int retval; 1368 1369 retval = comedi_driver_register(&driver_pcidio); 1370 if (retval < 0) 1371 return retval; 1372 1373 driver_pcidio_pci_driver.name = (char *)driver_pcidio.driver_name; 1374 return pci_register_driver(&driver_pcidio_pci_driver); 1375} 1376 1377static void __exit driver_pcidio_cleanup_module(void) 1378{ 1379 pci_unregister_driver(&driver_pcidio_pci_driver); 1380 comedi_driver_unregister(&driver_pcidio); 1381} 1382 1383module_init(driver_pcidio_init_module); 1384module_exit(driver_pcidio_cleanup_module); 1385 1386MODULE_AUTHOR("Comedi http://www.comedi.org"); 1387MODULE_DESCRIPTION("Comedi low-level driver"); 1388MODULE_LICENSE("GPL"); 1389