ni_pcidio.c revision 22494ed9b8e9404d6646f85c835bcd7b37d3f562
1/* 2 comedi/drivers/ni_pcidio.c 3 driver for National Instruments PCI-DIO-96/PCI-6508 4 National Instruments PCI-DIO-32HS 5 National Instruments PCI-6503 6 7 COMEDI - Linux Control and Measurement Device Interface 8 Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org> 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 24*/ 25/* 26Driver: ni_pcidio 27Description: National Instruments PCI-DIO32HS, PCI-DIO96, PCI-6533, PCI-6503 28Author: ds 29Status: works 30Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio), PXI-6533, 31 PCI-DIO-96, PCI-DIO-96B, PXI-6508, PCI-6503, PCI-6503B, PCI-6503X, 32 PXI-6503, PCI-6533, PCI-6534 33Updated: Mon, 09 Jan 2012 14:27:23 +0000 34 35The DIO-96 appears as four 8255 subdevices. See the 8255 36driver notes for details. 37 38The DIO32HS board appears as one subdevice, with 32 channels. 39Each channel is individually I/O configurable. The channel order 40is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only 41supports simple digital I/O; no handshaking is supported. 42 43DMA mostly works for the PCI-DIO32HS, but only in timed input mode. 44 45The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting 46scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting 47scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the 48trailing edge. 49 50This driver could be easily modified to support AT-MIO32HS and 51AT-MIO96. 52 53The PCI-6534 requires a firmware upload after power-up to work, the 54firmware data and instructions for loading it with comedi_config 55it are contained in the 56comedi_nonfree_firmware tarball available from http://www.comedi.org 57*/ 58 59/* 60 This driver is for both the NI PCI-DIO-32HS and the PCI-DIO-96, 61 which have very different architectures. But, since the '96 is 62 so simple, it is included here. 63 64 Manuals (available from ftp://ftp.natinst.com/support/manuals) 65 66 320938c.pdf PCI-DIO-96/PXI-6508/PCI-6503 User Manual 67 321464b.pdf AT/PCI-DIO-32HS User Manual 68 341329A.pdf PCI-6533 Register-Level Programmer Manual 69 341330A.pdf DAQ-DIO Technical Reference Manual 70 71 */ 72 73#define USE_DMA 74/* #define DEBUG 1 */ 75/* #define DEBUG_FLAGS */ 76 77#include <linux/interrupt.h> 78#include <linux/sched.h> 79#include "../comedidev.h" 80 81#include "mite.h" 82#include "8255.h" 83 84#undef DPRINTK 85#ifdef DEBUG 86#define DPRINTK(format, args...) printk(format, ## args) 87#else 88#define DPRINTK(format, args...) 89#endif 90 91#define PCI_DIO_SIZE 4096 92#define PCI_MITE_SIZE 4096 93 94/* defines for the PCI-DIO-96 */ 95 96#define NIDIO_8255_BASE(x) ((x)*4) 97#define NIDIO_A 0 98#define NIDIO_B 4 99#define NIDIO_C 8 100#define NIDIO_D 12 101 102/* defines for the PCI-DIO-32HS */ 103 104#define Window_Address 4 /* W */ 105#define Interrupt_And_Window_Status 4 /* R */ 106#define IntStatus1 (1<<0) 107#define IntStatus2 (1<<1) 108#define WindowAddressStatus_mask 0x7c 109 110#define Master_DMA_And_Interrupt_Control 5 /* W */ 111#define InterruptLine(x) ((x)&3) 112#define OpenInt (1<<2) 113#define Group_Status 5 /* R */ 114#define DataLeft (1<<0) 115#define Req (1<<2) 116#define StopTrig (1<<3) 117 118#define Group_1_Flags 6 /* R */ 119#define Group_2_Flags 7 /* R */ 120#define TransferReady (1<<0) 121#define CountExpired (1<<1) 122#define Waited (1<<5) 123#define PrimaryTC (1<<6) 124#define SecondaryTC (1<<7) 125 /* #define SerialRose */ 126 /* #define ReqRose */ 127 /* #define Paused */ 128 129#define Group_1_First_Clear 6 /* W */ 130#define Group_2_First_Clear 7 /* W */ 131#define ClearWaited (1<<3) 132#define ClearPrimaryTC (1<<4) 133#define ClearSecondaryTC (1<<5) 134#define DMAReset (1<<6) 135#define FIFOReset (1<<7) 136#define ClearAll 0xf8 137 138#define Group_1_FIFO 8 /* W */ 139#define Group_2_FIFO 12 /* W */ 140 141#define Transfer_Count 20 142#define Chip_ID_D 24 143#define Chip_ID_I 25 144#define Chip_ID_O 26 145#define Chip_Version 27 146#define Port_IO(x) (28+(x)) 147#define Port_Pin_Directions(x) (32+(x)) 148#define Port_Pin_Mask(x) (36+(x)) 149#define Port_Pin_Polarities(x) (40+(x)) 150 151#define Master_Clock_Routing 45 152#define RTSIClocking(x) (((x)&3)<<4) 153 154#define Group_1_Second_Clear 46 /* W */ 155#define Group_2_Second_Clear 47 /* W */ 156#define ClearExpired (1<<0) 157 158#define Port_Pattern(x) (48+(x)) 159 160#define Data_Path 64 161#define FIFOEnableA (1<<0) 162#define FIFOEnableB (1<<1) 163#define FIFOEnableC (1<<2) 164#define FIFOEnableD (1<<3) 165#define Funneling(x) (((x)&3)<<4) 166#define GroupDirection (1<<7) 167 168#define Protocol_Register_1 65 169#define OpMode Protocol_Register_1 170#define RunMode(x) ((x)&7) 171#define Numbered (1<<3) 172 173#define Protocol_Register_2 66 174#define ClockReg Protocol_Register_2 175#define ClockLine(x) (((x)&3)<<5) 176#define InvertStopTrig (1<<7) 177#define DataLatching(x) (((x)&3)<<5) 178 179#define Protocol_Register_3 67 180#define Sequence Protocol_Register_3 181 182#define Protocol_Register_14 68 /* 16 bit */ 183#define ClockSpeed Protocol_Register_14 184 185#define Protocol_Register_4 70 186#define ReqReg Protocol_Register_4 187#define ReqConditioning(x) (((x)&7)<<3) 188 189#define Protocol_Register_5 71 190#define BlockMode Protocol_Register_5 191 192#define FIFO_Control 72 193#define ReadyLevel(x) ((x)&7) 194 195#define Protocol_Register_6 73 196#define LinePolarities Protocol_Register_6 197#define InvertAck (1<<0) 198#define InvertReq (1<<1) 199#define InvertClock (1<<2) 200#define InvertSerial (1<<3) 201#define OpenAck (1<<4) 202#define OpenClock (1<<5) 203 204#define Protocol_Register_7 74 205#define AckSer Protocol_Register_7 206#define AckLine(x) (((x)&3)<<2) 207#define ExchangePins (1<<7) 208 209#define Interrupt_Control 75 210 /* bits same as flags */ 211 212#define DMA_Line_Control_Group1 76 213#define DMA_Line_Control_Group2 108 214/* channel zero is none */ 215static inline unsigned primary_DMAChannel_bits(unsigned channel) 216{ 217 return channel & 0x3; 218} 219 220static inline unsigned secondary_DMAChannel_bits(unsigned channel) 221{ 222 return (channel << 2) & 0xc; 223} 224 225#define Transfer_Size_Control 77 226#define TransferWidth(x) ((x)&3) 227#define TransferLength(x) (((x)&3)<<3) 228#define RequireRLevel (1<<5) 229 230#define Protocol_Register_15 79 231#define DAQOptions Protocol_Register_15 232#define StartSource(x) ((x)&0x3) 233#define InvertStart (1<<2) 234#define StopSource(x) (((x)&0x3)<<3) 235#define ReqStart (1<<6) 236#define PreStart (1<<7) 237 238#define Pattern_Detection 81 239#define DetectionMethod (1<<0) 240#define InvertMatch (1<<1) 241#define IE_Pattern_Detection (1<<2) 242 243#define Protocol_Register_9 82 244#define ReqDelay Protocol_Register_9 245 246#define Protocol_Register_10 83 247#define ReqNotDelay Protocol_Register_10 248 249#define Protocol_Register_11 84 250#define AckDelay Protocol_Register_11 251 252#define Protocol_Register_12 85 253#define AckNotDelay Protocol_Register_12 254 255#define Protocol_Register_13 86 256#define Data1Delay Protocol_Register_13 257 258#define Protocol_Register_8 88 /* 32 bit */ 259#define StartDelay Protocol_Register_8 260 261enum pci_6534_firmware_registers { /* 16 bit */ 262 Firmware_Control_Register = 0x100, 263 Firmware_Status_Register = 0x104, 264 Firmware_Data_Register = 0x108, 265 Firmware_Mask_Register = 0x10c, 266 Firmware_Debug_Register = 0x110, 267}; 268/* main fpga registers (32 bit)*/ 269enum pci_6534_fpga_registers { 270 FPGA_Control1_Register = 0x200, 271 FPGA_Control2_Register = 0x204, 272 FPGA_Irq_Mask_Register = 0x208, 273 FPGA_Status_Register = 0x20c, 274 FPGA_Signature_Register = 0x210, 275 FPGA_SCALS_Counter_Register = 0x280, /*write-clear */ 276 FPGA_SCAMS_Counter_Register = 0x284, /*write-clear */ 277 FPGA_SCBLS_Counter_Register = 0x288, /*write-clear */ 278 FPGA_SCBMS_Counter_Register = 0x28c, /*write-clear */ 279 FPGA_Temp_Control_Register = 0x2a0, 280 FPGA_DAR_Register = 0x2a8, 281 FPGA_ELC_Read_Register = 0x2b8, 282 FPGA_ELC_Write_Register = 0x2bc, 283}; 284enum FPGA_Control_Bits { 285 FPGA_Enable_Bit = 0x8000, 286}; 287 288#define TIMER_BASE 50 /* nanoseconds */ 289 290#ifdef USE_DMA 291#define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC) 292#else 293#define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC) 294#endif 295 296static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it); 297static int nidio_detach(struct comedi_device *dev); 298static int ni_pcidio_cancel(struct comedi_device *dev, 299 struct comedi_subdevice *s); 300 301static struct comedi_driver driver_pcidio = { 302 .driver_name = "ni_pcidio", 303 .module = THIS_MODULE, 304 .attach = nidio_attach, 305 .detach = nidio_detach, 306}; 307 308struct nidio_board { 309 310 int dev_id; 311 const char *name; 312 int n_8255; 313 unsigned int is_diodaq:1; 314 unsigned int uses_firmware:1; 315}; 316 317static const struct nidio_board nidio_boards[] = { 318 { 319 .dev_id = 0x1150, 320 .name = "pci-dio-32hs", 321 .n_8255 = 0, 322 .is_diodaq = 1, 323 }, 324 { 325 .dev_id = 0x1320, 326 .name = "pxi-6533", 327 .n_8255 = 0, 328 .is_diodaq = 1, 329 }, 330 { 331 .dev_id = 0x12b0, 332 .name = "pci-6534", 333 .n_8255 = 0, 334 .is_diodaq = 1, 335 .uses_firmware = 1, 336 }, 337 { 338 .dev_id = 0x0160, 339 .name = "pci-dio-96", 340 .n_8255 = 4, 341 .is_diodaq = 0, 342 }, 343 { 344 .dev_id = 0x1630, 345 .name = "pci-dio-96b", 346 .n_8255 = 4, 347 .is_diodaq = 0, 348 }, 349 { 350 .dev_id = 0x13c0, 351 .name = "pxi-6508", 352 .n_8255 = 4, 353 .is_diodaq = 0, 354 }, 355 { 356 .dev_id = 0x0400, 357 .name = "pci-6503", 358 .n_8255 = 1, 359 .is_diodaq = 0, 360 }, 361 { 362 .dev_id = 0x1250, 363 .name = "pci-6503b", 364 .n_8255 = 1, 365 .is_diodaq = 0, 366 }, 367 { 368 .dev_id = 0x17d0, 369 .name = "pci-6503x", 370 .n_8255 = 1, 371 .is_diodaq = 0, 372 }, 373 { 374 .dev_id = 0x1800, 375 .name = "pxi-6503", 376 .n_8255 = 1, 377 .is_diodaq = 0, 378 }, 379}; 380 381#define n_nidio_boards ARRAY_SIZE(nidio_boards) 382#define this_board ((const struct nidio_board *)dev->board_ptr) 383 384static DEFINE_PCI_DEVICE_TABLE(ni_pcidio_pci_table) = { 385 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1150)}, 386 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1320)}, 387 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x12b0)}, 388 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0160)}, 389 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1630)}, 390 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x13c0)}, 391 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0400)}, 392 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1250)}, 393 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x17d0)}, 394 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1800)}, 395 {0} 396}; 397 398MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table); 399 400struct nidio96_private { 401 struct mite_struct *mite; 402 int boardtype; 403 int dio; 404 unsigned short OpModeBits; 405 struct mite_channel *di_mite_chan; 406 struct mite_dma_descriptor_ring *di_mite_ring; 407 spinlock_t mite_channel_lock; 408}; 409#define devpriv ((struct nidio96_private *)dev->private) 410 411static int ni_pcidio_cmdtest(struct comedi_device *dev, 412 struct comedi_subdevice *s, 413 struct comedi_cmd *cmd); 414static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 415static int ni_pcidio_inttrig(struct comedi_device *dev, 416 struct comedi_subdevice *s, unsigned int trignum); 417static int nidio_find_device(struct comedi_device *dev, int bus, int slot); 418static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode); 419static int setup_mite_dma(struct comedi_device *dev, 420 struct comedi_subdevice *s); 421 422#ifdef DEBUG_FLAGS 423static void ni_pcidio_print_flags(unsigned int flags); 424static void ni_pcidio_print_status(unsigned int status); 425#else 426#define ni_pcidio_print_flags(x) 427#define ni_pcidio_print_status(x) 428#endif 429 430static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev) 431{ 432 unsigned long flags; 433 434 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 435 BUG_ON(devpriv->di_mite_chan); 436 devpriv->di_mite_chan = 437 mite_request_channel_in_range(devpriv->mite, 438 devpriv->di_mite_ring, 1, 2); 439 if (devpriv->di_mite_chan == NULL) { 440 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 441 comedi_error(dev, "failed to reserve mite dma channel."); 442 return -EBUSY; 443 } 444 devpriv->di_mite_chan->dir = COMEDI_INPUT; 445 writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) | 446 secondary_DMAChannel_bits(devpriv->di_mite_chan->channel), 447 devpriv->mite->daq_io_addr + DMA_Line_Control_Group1); 448 mmiowb(); 449 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 450 return 0; 451} 452 453static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev) 454{ 455 unsigned long flags; 456 457 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 458 if (devpriv->di_mite_chan) { 459 mite_dma_disarm(devpriv->di_mite_chan); 460 mite_dma_reset(devpriv->di_mite_chan); 461 mite_release_channel(devpriv->di_mite_chan); 462 devpriv->di_mite_chan = NULL; 463 writeb(primary_DMAChannel_bits(0) | 464 secondary_DMAChannel_bits(0), 465 devpriv->mite->daq_io_addr + DMA_Line_Control_Group1); 466 mmiowb(); 467 } 468 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 469} 470 471static int nidio96_8255_cb(int dir, int port, int data, unsigned long iobase) 472{ 473 if (dir) { 474 writeb(data, (void *)(iobase + port)); 475 return 0; 476 } else { 477 return readb((void *)(iobase + port)); 478 } 479} 480 481void ni_pcidio_event(struct comedi_device *dev, struct comedi_subdevice *s) 482{ 483 if (s-> 484 async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR | 485 COMEDI_CB_OVERFLOW)) { 486 ni_pcidio_cancel(dev, s); 487 } 488 comedi_event(dev, s); 489} 490 491static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s) 492{ 493 unsigned long irq_flags; 494 int count; 495 496 spin_lock_irqsave(&dev->spinlock, irq_flags); 497 spin_lock(&devpriv->mite_channel_lock); 498 if (devpriv->di_mite_chan) 499 mite_sync_input_dma(devpriv->di_mite_chan, s->async); 500 spin_unlock(&devpriv->mite_channel_lock); 501 count = s->async->buf_write_count - s->async->buf_read_count; 502 spin_unlock_irqrestore(&dev->spinlock, irq_flags); 503 return count; 504} 505 506static irqreturn_t nidio_interrupt(int irq, void *d) 507{ 508 struct comedi_device *dev = d; 509 struct comedi_subdevice *s = dev->subdevices; 510 struct comedi_async *async = s->async; 511 struct mite_struct *mite = devpriv->mite; 512 513 /* int i, j; */ 514 long int AuxData = 0; 515 short data1 = 0; 516 short data2 = 0; 517 int flags; 518 int status; 519 int work = 0; 520 unsigned int m_status = 0; 521 522 /* interrupcions parasites */ 523 if (dev->attached == 0) { 524 /* assume it's from another card */ 525 return IRQ_NONE; 526 } 527 528 /* Lock to avoid race with comedi_poll */ 529 spin_lock(&dev->spinlock); 530 531 status = readb(devpriv->mite->daq_io_addr + 532 Interrupt_And_Window_Status); 533 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 534 535 DPRINTK("ni_pcidio_interrupt: status=0x%02x,flags=0x%02x\n", 536 status, flags); 537 ni_pcidio_print_flags(flags); 538 ni_pcidio_print_status(status); 539 540 /* printk("buf[0]=%08x\n",*(unsigned int *)async->prealloc_buf); */ 541 /* printk("buf[4096]=%08x\n", 542 *(unsigned int *)(async->prealloc_buf+4096)); */ 543 544 spin_lock(&devpriv->mite_channel_lock); 545 if (devpriv->di_mite_chan) 546 m_status = mite_get_status(devpriv->di_mite_chan); 547#ifdef MITE_DEBUG 548 mite_print_chsr(m_status); 549#endif 550 /* printk("mite_bytes_transferred: %d\n", 551 mite_bytes_transferred(mite,DI_DMA_CHAN)); */ 552 553 /* mite_dump_regs(mite); */ 554 if (m_status & CHSR_INT) { 555 if (m_status & CHSR_LINKC) { 556 writel(CHOR_CLRLC, 557 mite->mite_io_addr + 558 MITE_CHOR(devpriv->di_mite_chan->channel)); 559 mite_sync_input_dma(devpriv->di_mite_chan, s->async); 560 /* XXX need to byteswap */ 561 } 562 if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY | 563 CHSR_DRQ1 | CHSR_MRDY)) { 564 DPRINTK("unknown mite interrupt, disabling IRQ\n"); 565 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 566 disable_irq(dev->irq); 567 } 568 } 569 spin_unlock(&devpriv->mite_channel_lock); 570 571 while (status & DataLeft) { 572 work++; 573 if (work > 20) { 574 DPRINTK("too much work in interrupt\n"); 575 writeb(0x00, 576 devpriv->mite->daq_io_addr + 577 Master_DMA_And_Interrupt_Control); 578 break; 579 } 580 581 flags &= IntEn; 582 583 if (flags & TransferReady) { 584 /* DPRINTK("TransferReady\n"); */ 585 while (flags & TransferReady) { 586 work++; 587 if (work > 100) { 588 DPRINTK("too much work in interrupt\n"); 589 writeb(0x00, 590 devpriv->mite->daq_io_addr + 591 Master_DMA_And_Interrupt_Control 592 ); 593 goto out; 594 } 595 AuxData = 596 readl(devpriv->mite->daq_io_addr + 597 Group_1_FIFO); 598 data1 = AuxData & 0xffff; 599 data2 = (AuxData & 0xffff0000) >> 16; 600 comedi_buf_put(async, data1); 601 comedi_buf_put(async, data2); 602 /* DPRINTK("read:%d, %d\n",data1,data2); */ 603 flags = readb(devpriv->mite->daq_io_addr + 604 Group_1_Flags); 605 } 606 /* DPRINTK("buf_int_count: %d\n", 607 async->buf_int_count); */ 608 /* DPRINTK("1) IntEn=%d,flags=%d,status=%d\n", 609 IntEn,flags,status); */ 610 /* ni_pcidio_print_flags(flags); */ 611 /* ni_pcidio_print_status(status); */ 612 async->events |= COMEDI_CB_BLOCK; 613 } 614 615 if (flags & CountExpired) { 616 DPRINTK("CountExpired\n"); 617 writeb(ClearExpired, 618 devpriv->mite->daq_io_addr + 619 Group_1_Second_Clear); 620 async->events |= COMEDI_CB_EOA; 621 622 writeb(0x00, devpriv->mite->daq_io_addr + OpMode); 623 break; 624 } else if (flags & Waited) { 625 DPRINTK("Waited\n"); 626 writeb(ClearWaited, 627 devpriv->mite->daq_io_addr + 628 Group_1_First_Clear); 629 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 630 break; 631 } else if (flags & PrimaryTC) { 632 DPRINTK("PrimaryTC\n"); 633 writeb(ClearPrimaryTC, 634 devpriv->mite->daq_io_addr + 635 Group_1_First_Clear); 636 async->events |= COMEDI_CB_EOA; 637 } else if (flags & SecondaryTC) { 638 DPRINTK("SecondaryTC\n"); 639 writeb(ClearSecondaryTC, 640 devpriv->mite->daq_io_addr + 641 Group_1_First_Clear); 642 async->events |= COMEDI_CB_EOA; 643 } 644#if 0 645 else { 646 printk("ni_pcidio: unknown interrupt\n"); 647 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 648 writeb(0x00, 649 devpriv->mite->daq_io_addr + 650 Master_DMA_And_Interrupt_Control); 651 } 652#endif 653 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 654 status = readb(devpriv->mite->daq_io_addr + 655 Interrupt_And_Window_Status); 656 /* DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x," 657 "status=0x%02x\n", IntEn, flags, status); */ 658 /* ni_pcidio_print_flags(flags); */ 659 /* ni_pcidio_print_status(status); */ 660 } 661 662out: 663 ni_pcidio_event(dev, s); 664#if 0 665 if (!tag) { 666 writeb(0x03, 667 devpriv->mite->daq_io_addr + 668 Master_DMA_And_Interrupt_Control); 669 } 670#endif 671 672 spin_unlock(&dev->spinlock); 673 return IRQ_HANDLED; 674} 675 676#ifdef DEBUG_FLAGS 677static const char *const flags_strings[] = { 678 "TransferReady", "CountExpired", "2", "3", 679 "4", "Waited", "PrimaryTC", "SecondaryTC", 680}; 681 682static void ni_pcidio_print_flags(unsigned int flags) 683{ 684 int i; 685 686 printk(KERN_INFO "group_1_flags:"); 687 for (i = 7; i >= 0; i--) { 688 if (flags & (1 << i)) 689 printk(" %s", flags_strings[i]); 690 } 691 printk("\n"); 692} 693 694static char *status_strings[] = { 695 "DataLeft1", "Reserved1", "Req1", "StopTrig1", 696 "DataLeft2", "Reserved2", "Req2", "StopTrig2", 697}; 698 699static void ni_pcidio_print_status(unsigned int flags) 700{ 701 int i; 702 703 printk(KERN_INFO "group_status:"); 704 for (i = 7; i >= 0; i--) { 705 if (flags & (1 << i)) 706 printk(" %s", status_strings[i]); 707 } 708 printk("\n"); 709} 710#endif 711 712#ifdef unused 713static void debug_int(struct comedi_device *dev) 714{ 715 int a, b; 716 static int n_int; 717 struct timeval tv; 718 719 do_gettimeofday(&tv); 720 a = readb(devpriv->mite->daq_io_addr + Group_Status); 721 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 722 723 if (n_int < 10) { 724 DPRINTK("status 0x%02x flags 0x%02x time %06d\n", a, b, 725 (int)tv.tv_usec); 726 } 727 728 while (b & 1) { 729 writew(0xff, devpriv->mite->daq_io_addr + Group_1_FIFO); 730 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 731 } 732 733 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 734 735 if (n_int < 10) { 736 DPRINTK("new status 0x%02x\n", b); 737 n_int++; 738 } 739} 740#endif 741 742static int ni_pcidio_insn_config(struct comedi_device *dev, 743 struct comedi_subdevice *s, 744 struct comedi_insn *insn, unsigned int *data) 745{ 746 if (insn->n != 1) 747 return -EINVAL; 748 switch (data[0]) { 749 case INSN_CONFIG_DIO_OUTPUT: 750 s->io_bits |= 1 << CR_CHAN(insn->chanspec); 751 break; 752 case INSN_CONFIG_DIO_INPUT: 753 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec)); 754 break; 755 case INSN_CONFIG_DIO_QUERY: 756 data[1] = 757 (s-> 758 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : 759 COMEDI_INPUT; 760 return insn->n; 761 break; 762 default: 763 return -EINVAL; 764 } 765 writel(s->io_bits, devpriv->mite->daq_io_addr + Port_Pin_Directions(0)); 766 767 return 1; 768} 769 770static int ni_pcidio_insn_bits(struct comedi_device *dev, 771 struct comedi_subdevice *s, 772 struct comedi_insn *insn, unsigned int *data) 773{ 774 if (insn->n != 2) 775 return -EINVAL; 776 if (data[0]) { 777 s->state &= ~data[0]; 778 s->state |= (data[0] & data[1]); 779 writel(s->state, devpriv->mite->daq_io_addr + Port_IO(0)); 780 } 781 data[1] = readl(devpriv->mite->daq_io_addr + Port_IO(0)); 782 783 return 2; 784} 785 786static int ni_pcidio_cmdtest(struct comedi_device *dev, 787 struct comedi_subdevice *s, struct comedi_cmd *cmd) 788{ 789 int err = 0; 790 int tmp; 791 792 /* step 1: make sure trigger sources are trivially valid */ 793 794 tmp = cmd->start_src; 795 cmd->start_src &= TRIG_NOW | TRIG_INT; 796 if (!cmd->start_src || tmp != cmd->start_src) 797 err++; 798 799 tmp = cmd->scan_begin_src; 800 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; 801 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 802 err++; 803 804 tmp = cmd->convert_src; 805 cmd->convert_src &= TRIG_NOW; 806 if (!cmd->convert_src || tmp != cmd->convert_src) 807 err++; 808 809 tmp = cmd->scan_end_src; 810 cmd->scan_end_src &= TRIG_COUNT; 811 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 812 err++; 813 814 tmp = cmd->stop_src; 815 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 816 if (!cmd->stop_src || tmp != cmd->stop_src) 817 err++; 818 819 if (err) 820 return 1; 821 822 /* step 2: make sure trigger sources are unique and mutually 823 compatible */ 824 825 /* note that mutual compatibility is not an issue here */ 826 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_INT) 827 err++; 828 if (cmd->scan_begin_src != TRIG_TIMER && 829 cmd->scan_begin_src != TRIG_EXT) 830 err++; 831 832 if (err) 833 return 2; 834 835 /* step 3: make sure arguments are trivially compatible */ 836 837 if (cmd->start_arg != 0) { 838 /* same for both TRIG_INT and TRIG_NOW */ 839 cmd->start_arg = 0; 840 err++; 841 } 842#define MAX_SPEED (TIMER_BASE) /* in nanoseconds */ 843 844 if (cmd->scan_begin_src == TRIG_TIMER) { 845 if (cmd->scan_begin_arg < MAX_SPEED) { 846 cmd->scan_begin_arg = MAX_SPEED; 847 err++; 848 } 849 /* no minimum speed */ 850 } else { 851 /* TRIG_EXT */ 852 /* should be level/edge, hi/lo specification here */ 853 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) { 854 cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT); 855 err++; 856 } 857 } 858 if (cmd->convert_arg != 0) { 859 cmd->convert_arg = 0; 860 err++; 861 } 862 863 if (cmd->scan_end_arg != cmd->chanlist_len) { 864 cmd->scan_end_arg = cmd->chanlist_len; 865 err++; 866 } 867 if (cmd->stop_src == TRIG_COUNT) { 868 /* no limit */ 869 } else { 870 /* TRIG_NONE */ 871 if (cmd->stop_arg != 0) { 872 cmd->stop_arg = 0; 873 err++; 874 } 875 } 876 877 if (err) 878 return 3; 879 880 /* step 4: fix up any arguments */ 881 882 if (cmd->scan_begin_src == TRIG_TIMER) { 883 tmp = cmd->scan_begin_arg; 884 ni_pcidio_ns_to_timer(&cmd->scan_begin_arg, 885 cmd->flags & TRIG_ROUND_MASK); 886 if (tmp != cmd->scan_begin_arg) 887 err++; 888 } 889 890 if (err) 891 return 4; 892 893 return 0; 894} 895 896static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode) 897{ 898 int divider, base; 899 900 base = TIMER_BASE; 901 902 switch (round_mode) { 903 case TRIG_ROUND_NEAREST: 904 default: 905 divider = (*nanosec + base / 2) / base; 906 break; 907 case TRIG_ROUND_DOWN: 908 divider = (*nanosec) / base; 909 break; 910 case TRIG_ROUND_UP: 911 divider = (*nanosec + base - 1) / base; 912 break; 913 } 914 915 *nanosec = base * divider; 916 return divider; 917} 918 919static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 920{ 921 struct comedi_cmd *cmd = &s->async->cmd; 922 923 /* XXX configure ports for input */ 924 writel(0x0000, devpriv->mite->daq_io_addr + Port_Pin_Directions(0)); 925 926 if (1) { 927 /* enable fifos A B C D */ 928 writeb(0x0f, devpriv->mite->daq_io_addr + Data_Path); 929 930 /* set transfer width a 32 bits */ 931 writeb(TransferWidth(0) | TransferLength(0), 932 devpriv->mite->daq_io_addr + Transfer_Size_Control); 933 } else { 934 writeb(0x03, devpriv->mite->daq_io_addr + Data_Path); 935 writeb(TransferWidth(3) | TransferLength(0), 936 devpriv->mite->daq_io_addr + Transfer_Size_Control); 937 } 938 939 /* protocol configuration */ 940 if (cmd->scan_begin_src == TRIG_TIMER) { 941 /* page 4-5, "input with internal REQs" */ 942 writeb(0, devpriv->mite->daq_io_addr + OpMode); 943 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg); 944 writeb(1, devpriv->mite->daq_io_addr + Sequence); 945 writeb(0x04, devpriv->mite->daq_io_addr + ReqReg); 946 writeb(4, devpriv->mite->daq_io_addr + BlockMode); 947 writeb(3, devpriv->mite->daq_io_addr + LinePolarities); 948 writeb(0xc0, devpriv->mite->daq_io_addr + AckSer); 949 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg, 950 TRIG_ROUND_NEAREST), 951 devpriv->mite->daq_io_addr + StartDelay); 952 writeb(1, devpriv->mite->daq_io_addr + ReqDelay); 953 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay); 954 writeb(1, devpriv->mite->daq_io_addr + AckDelay); 955 writeb(0x0b, devpriv->mite->daq_io_addr + AckNotDelay); 956 writeb(0x01, devpriv->mite->daq_io_addr + Data1Delay); 957 /* manual, page 4-5: ClockSpeed comment is incorrectly listed 958 * on DAQOptions */ 959 writew(0, devpriv->mite->daq_io_addr + ClockSpeed); 960 writeb(0, devpriv->mite->daq_io_addr + DAQOptions); 961 } else { 962 /* TRIG_EXT */ 963 /* page 4-5, "input with external REQs" */ 964 writeb(0, devpriv->mite->daq_io_addr + OpMode); 965 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg); 966 writeb(0, devpriv->mite->daq_io_addr + Sequence); 967 writeb(0x00, devpriv->mite->daq_io_addr + ReqReg); 968 writeb(4, devpriv->mite->daq_io_addr + BlockMode); 969 if (!(cmd->scan_begin_arg & CR_INVERT)) { 970 /* Leading Edge pulse mode */ 971 writeb(0, devpriv->mite->daq_io_addr + LinePolarities); 972 } else { 973 /* Trailing Edge pulse mode */ 974 writeb(2, devpriv->mite->daq_io_addr + LinePolarities); 975 } 976 writeb(0x00, devpriv->mite->daq_io_addr + AckSer); 977 writel(1, devpriv->mite->daq_io_addr + StartDelay); 978 writeb(1, devpriv->mite->daq_io_addr + ReqDelay); 979 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay); 980 writeb(1, devpriv->mite->daq_io_addr + AckDelay); 981 writeb(0x0C, devpriv->mite->daq_io_addr + AckNotDelay); 982 writeb(0x10, devpriv->mite->daq_io_addr + Data1Delay); 983 writew(0, devpriv->mite->daq_io_addr + ClockSpeed); 984 writeb(0x60, devpriv->mite->daq_io_addr + DAQOptions); 985 } 986 987 if (cmd->stop_src == TRIG_COUNT) { 988 writel(cmd->stop_arg, 989 devpriv->mite->daq_io_addr + Transfer_Count); 990 } else { 991 /* XXX */ 992 } 993 994#ifdef USE_DMA 995 writeb(ClearPrimaryTC | ClearSecondaryTC, 996 devpriv->mite->daq_io_addr + Group_1_First_Clear); 997 998 { 999 int retval = setup_mite_dma(dev, s); 1000 if (retval) 1001 return retval; 1002 } 1003#else 1004 writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group1); 1005#endif 1006 writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group2); 1007 1008 /* clear and enable interrupts */ 1009 writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear); 1010 /* writeb(ClearExpired, 1011 devpriv->mite->daq_io_addr+Group_1_Second_Clear); */ 1012 1013 writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control); 1014 writeb(0x03, 1015 devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control); 1016 1017 if (cmd->stop_src == TRIG_NONE) { 1018 devpriv->OpModeBits = DataLatching(0) | RunMode(7); 1019 } else { /* TRIG_TIMER */ 1020 devpriv->OpModeBits = Numbered | RunMode(7); 1021 } 1022 if (cmd->start_src == TRIG_NOW) { 1023 /* start */ 1024 writeb(devpriv->OpModeBits, 1025 devpriv->mite->daq_io_addr + OpMode); 1026 s->async->inttrig = NULL; 1027 } else { 1028 /* TRIG_INT */ 1029 s->async->inttrig = ni_pcidio_inttrig; 1030 } 1031 1032 DPRINTK("ni_pcidio: command started\n"); 1033 return 0; 1034} 1035 1036static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s) 1037{ 1038 int retval; 1039 unsigned long flags; 1040 1041 retval = ni_pcidio_request_di_mite_channel(dev); 1042 if (retval) 1043 return retval; 1044 1045 /* write alloc the entire buffer */ 1046 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz); 1047 1048 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1049 if (devpriv->di_mite_chan) { 1050 mite_prep_dma(devpriv->di_mite_chan, 32, 32); 1051 mite_dma_arm(devpriv->di_mite_chan); 1052 } else 1053 retval = -EIO; 1054 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1055 1056 return retval; 1057} 1058 1059static int ni_pcidio_inttrig(struct comedi_device *dev, 1060 struct comedi_subdevice *s, unsigned int trignum) 1061{ 1062 if (trignum != 0) 1063 return -EINVAL; 1064 1065 writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr + OpMode); 1066 s->async->inttrig = NULL; 1067 1068 return 1; 1069} 1070 1071static int ni_pcidio_cancel(struct comedi_device *dev, 1072 struct comedi_subdevice *s) 1073{ 1074 writeb(0x00, 1075 devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control); 1076 ni_pcidio_release_di_mite_channel(dev); 1077 1078 return 0; 1079} 1080 1081static int ni_pcidio_change(struct comedi_device *dev, 1082 struct comedi_subdevice *s, unsigned long new_size) 1083{ 1084 int ret; 1085 1086 ret = mite_buf_change(devpriv->di_mite_ring, s->async); 1087 if (ret < 0) 1088 return ret; 1089 1090 memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz); 1091 1092 return 0; 1093} 1094 1095static int pci_6534_load_fpga(struct comedi_device *dev, int fpga_index, 1096 u8 *data, int data_len) 1097{ 1098 static const int timeout = 1000; 1099 int i, j; 1100 writew(0x80 | fpga_index, 1101 devpriv->mite->daq_io_addr + Firmware_Control_Register); 1102 writew(0xc0 | fpga_index, 1103 devpriv->mite->daq_io_addr + Firmware_Control_Register); 1104 for (i = 0; 1105 (readw(devpriv->mite->daq_io_addr + 1106 Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i) { 1107 udelay(1); 1108 } 1109 if (i == timeout) { 1110 printk(KERN_WARNING "ni_pcidio: failed to load fpga %i, " 1111 "waiting for status 0x2\n", fpga_index); 1112 return -EIO; 1113 } 1114 writew(0x80 | fpga_index, 1115 devpriv->mite->daq_io_addr + Firmware_Control_Register); 1116 for (i = 0; 1117 readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) != 1118 0x3 && i < timeout; ++i) { 1119 udelay(1); 1120 } 1121 if (i == timeout) { 1122 printk(KERN_WARNING "ni_pcidio: failed to load fpga %i, " 1123 "waiting for status 0x3\n", fpga_index); 1124 return -EIO; 1125 } 1126 for (j = 0; j + 1 < data_len;) { 1127 unsigned int value = data[j++]; 1128 value |= data[j++] << 8; 1129 writew(value, 1130 devpriv->mite->daq_io_addr + Firmware_Data_Register); 1131 for (i = 0; 1132 (readw(devpriv->mite->daq_io_addr + 1133 Firmware_Status_Register) & 0x2) == 0 1134 && i < timeout; ++i) { 1135 udelay(1); 1136 } 1137 if (i == timeout) { 1138 printk("ni_pcidio: failed to load word into fpga %i\n", 1139 fpga_index); 1140 return -EIO; 1141 } 1142 if (need_resched()) 1143 schedule(); 1144 } 1145 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register); 1146 return 0; 1147} 1148 1149static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index) 1150{ 1151 return pci_6534_load_fpga(dev, fpga_index, NULL, 0); 1152} 1153 1154static int pci_6534_reset_fpgas(struct comedi_device *dev) 1155{ 1156 int ret; 1157 int i; 1158 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register); 1159 for (i = 0; i < 3; ++i) { 1160 ret = pci_6534_reset_fpga(dev, i); 1161 if (ret < 0) 1162 break; 1163 } 1164 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Mask_Register); 1165 return ret; 1166} 1167 1168static void pci_6534_init_main_fpga(struct comedi_device *dev) 1169{ 1170 writel(0, devpriv->mite->daq_io_addr + FPGA_Control1_Register); 1171 writel(0, devpriv->mite->daq_io_addr + FPGA_Control2_Register); 1172 writel(0, devpriv->mite->daq_io_addr + FPGA_SCALS_Counter_Register); 1173 writel(0, devpriv->mite->daq_io_addr + FPGA_SCAMS_Counter_Register); 1174 writel(0, devpriv->mite->daq_io_addr + FPGA_SCBLS_Counter_Register); 1175 writel(0, devpriv->mite->daq_io_addr + FPGA_SCBMS_Counter_Register); 1176} 1177 1178static int pci_6534_upload_firmware(struct comedi_device *dev, int options[]) 1179{ 1180 int ret; 1181 void *main_fpga_data, *scarab_a_data, *scarab_b_data; 1182 int main_fpga_data_len, scarab_a_data_len, scarab_b_data_len; 1183 1184 if (options[COMEDI_DEVCONF_AUX_DATA_LENGTH] == 0) 1185 return 0; 1186 ret = pci_6534_reset_fpgas(dev); 1187 if (ret < 0) 1188 return ret; 1189 main_fpga_data = comedi_aux_data(options, 0); 1190 main_fpga_data_len = options[COMEDI_DEVCONF_AUX_DATA0_LENGTH]; 1191 ret = pci_6534_load_fpga(dev, 2, main_fpga_data, main_fpga_data_len); 1192 if (ret < 0) 1193 return ret; 1194 pci_6534_init_main_fpga(dev); 1195 scarab_a_data = comedi_aux_data(options, 1); 1196 scarab_a_data_len = options[COMEDI_DEVCONF_AUX_DATA1_LENGTH]; 1197 ret = pci_6534_load_fpga(dev, 0, scarab_a_data, scarab_a_data_len); 1198 if (ret < 0) 1199 return ret; 1200 scarab_b_data = comedi_aux_data(options, 2); 1201 scarab_b_data_len = options[COMEDI_DEVCONF_AUX_DATA2_LENGTH]; 1202 ret = pci_6534_load_fpga(dev, 1, scarab_b_data, scarab_b_data_len); 1203 if (ret < 0) 1204 return ret; 1205 return 0; 1206} 1207 1208static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it) 1209{ 1210 struct comedi_subdevice *s; 1211 int i; 1212 int ret; 1213 int n_subdevices; 1214 unsigned int irq; 1215 1216 printk(KERN_INFO "comedi%d: nidio:", dev->minor); 1217 1218 ret = alloc_private(dev, sizeof(struct nidio96_private)); 1219 if (ret < 0) 1220 return ret; 1221 spin_lock_init(&devpriv->mite_channel_lock); 1222 1223 ret = nidio_find_device(dev, it->options[0], it->options[1]); 1224 if (ret < 0) 1225 return ret; 1226 1227 ret = mite_setup(devpriv->mite); 1228 if (ret < 0) { 1229 printk(KERN_WARNING "error setting up mite\n"); 1230 return ret; 1231 } 1232 comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev); 1233 devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite); 1234 if (devpriv->di_mite_ring == NULL) 1235 return -ENOMEM; 1236 1237 dev->board_name = this_board->name; 1238 irq = mite_irq(devpriv->mite); 1239 printk(KERN_INFO " %s", dev->board_name); 1240 if (this_board->uses_firmware) { 1241 ret = pci_6534_upload_firmware(dev, it->options); 1242 if (ret < 0) 1243 return ret; 1244 } 1245 if (!this_board->is_diodaq) 1246 n_subdevices = this_board->n_8255; 1247 else 1248 n_subdevices = 1; 1249 1250 ret = alloc_subdevices(dev, n_subdevices); 1251 if (ret < 0) 1252 return ret; 1253 1254 if (!this_board->is_diodaq) { 1255 for (i = 0; i < this_board->n_8255; i++) { 1256 subdev_8255_init(dev, dev->subdevices + i, 1257 nidio96_8255_cb, 1258 (unsigned long)(devpriv->mite-> 1259 daq_io_addr + 1260 NIDIO_8255_BASE(i))); 1261 } 1262 } else { 1263 1264 printk(KERN_INFO " rev=%d", 1265 readb(devpriv->mite->daq_io_addr + Chip_Version)); 1266 1267 s = dev->subdevices + 0; 1268 1269 dev->read_subdev = s; 1270 s->type = COMEDI_SUBD_DIO; 1271 s->subdev_flags = 1272 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED | 1273 SDF_CMD_READ; 1274 s->n_chan = 32; 1275 s->range_table = &range_digital; 1276 s->maxdata = 1; 1277 s->insn_config = &ni_pcidio_insn_config; 1278 s->insn_bits = &ni_pcidio_insn_bits; 1279 s->do_cmd = &ni_pcidio_cmd; 1280 s->do_cmdtest = &ni_pcidio_cmdtest; 1281 s->cancel = &ni_pcidio_cancel; 1282 s->len_chanlist = 32; /* XXX */ 1283 s->buf_change = &ni_pcidio_change; 1284 s->async_dma_dir = DMA_BIDIRECTIONAL; 1285 s->poll = &ni_pcidio_poll; 1286 1287 writel(0, devpriv->mite->daq_io_addr + Port_IO(0)); 1288 writel(0, devpriv->mite->daq_io_addr + Port_Pin_Directions(0)); 1289 writel(0, devpriv->mite->daq_io_addr + Port_Pin_Mask(0)); 1290 1291 /* disable interrupts on board */ 1292 writeb(0x00, 1293 devpriv->mite->daq_io_addr + 1294 Master_DMA_And_Interrupt_Control); 1295 1296 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED, 1297 "ni_pcidio", dev); 1298 if (ret < 0) 1299 printk(KERN_WARNING " irq not available"); 1300 1301 dev->irq = irq; 1302 } 1303 1304 printk("\n"); 1305 1306 return 0; 1307} 1308 1309static int nidio_detach(struct comedi_device *dev) 1310{ 1311 int i; 1312 1313 if (this_board && !this_board->is_diodaq) { 1314 for (i = 0; i < this_board->n_8255; i++) 1315 subdev_8255_cleanup(dev, dev->subdevices + i); 1316 } 1317 1318 if (dev->irq) 1319 free_irq(dev->irq, dev); 1320 1321 if (devpriv) { 1322 if (devpriv->di_mite_ring) { 1323 mite_free_ring(devpriv->di_mite_ring); 1324 devpriv->di_mite_ring = NULL; 1325 } 1326 if (devpriv->mite) 1327 mite_unsetup(devpriv->mite); 1328 } 1329 return 0; 1330} 1331 1332static int nidio_find_device(struct comedi_device *dev, int bus, int slot) 1333{ 1334 struct mite_struct *mite; 1335 int i; 1336 1337 for (mite = mite_devices; mite; mite = mite->next) { 1338 if (mite->used) 1339 continue; 1340 if (bus || slot) { 1341 if (bus != mite->pcidev->bus->number || 1342 slot != PCI_SLOT(mite->pcidev->devfn)) 1343 continue; 1344 } 1345 for (i = 0; i < n_nidio_boards; i++) { 1346 if (mite_device_id(mite) == nidio_boards[i].dev_id) { 1347 dev->board_ptr = nidio_boards + i; 1348 devpriv->mite = mite; 1349 1350 return 0; 1351 } 1352 } 1353 } 1354 printk(KERN_WARNING "no device found\n"); 1355 mite_list_devices(); 1356 return -EIO; 1357} 1358 1359static int __devinit driver_pcidio_pci_probe(struct pci_dev *dev, 1360 const struct pci_device_id *ent) 1361{ 1362 return comedi_pci_auto_config(dev, driver_pcidio.driver_name); 1363} 1364 1365static void __devexit driver_pcidio_pci_remove(struct pci_dev *dev) 1366{ 1367 comedi_pci_auto_unconfig(dev); 1368} 1369 1370static struct pci_driver driver_pcidio_pci_driver = { 1371 .id_table = ni_pcidio_pci_table, 1372 .probe = &driver_pcidio_pci_probe, 1373 .remove = __devexit_p(&driver_pcidio_pci_remove) 1374}; 1375 1376static int __init driver_pcidio_init_module(void) 1377{ 1378 int retval; 1379 1380 retval = comedi_driver_register(&driver_pcidio); 1381 if (retval < 0) 1382 return retval; 1383 1384 driver_pcidio_pci_driver.name = (char *)driver_pcidio.driver_name; 1385 return pci_register_driver(&driver_pcidio_pci_driver); 1386} 1387 1388static void __exit driver_pcidio_cleanup_module(void) 1389{ 1390 pci_unregister_driver(&driver_pcidio_pci_driver); 1391 comedi_driver_unregister(&driver_pcidio); 1392} 1393 1394module_init(driver_pcidio_init_module); 1395module_exit(driver_pcidio_cleanup_module); 1396 1397MODULE_AUTHOR("Comedi http://www.comedi.org"); 1398MODULE_DESCRIPTION("Comedi low-level driver"); 1399MODULE_LICENSE("GPL"); 1400