ni_pcidio.c revision 5f74ea14c07fee91d3bdbaad88bff6264c6200e6
1/* 2 comedi/drivers/ni_pcidio.c 3 driver for National Instruments PCI-DIO-96/PCI-6508 4 National Instruments PCI-DIO-32HS 5 National Instruments PCI-6503 6 7 COMEDI - Linux Control and Measurement Device Interface 8 Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org> 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 24*/ 25/* 26Driver: ni_pcidio 27Description: National Instruments PCI-DIO32HS, PCI-DIO96, PCI-6533, PCI-6503 28Author: ds 29Status: works 30Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio), PXI-6533, 31 PCI-DIO-96, PCI-DIO-96B, PXI-6508, PCI-6503, PCI-6503B, PCI-6503X, 32 PXI-6503, PCI-6533, PCI-6534 33Updated: Sun, 21 Apr 2002 21:03:38 -0700 34 35The DIO-96 appears as four 8255 subdevices. See the 8255 36driver notes for details. 37 38The DIO32HS board appears as one subdevice, with 32 channels. 39Each channel is individually I/O configurable. The channel order 40is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only 41supports simple digital I/O; no handshaking is supported. 42 43DMA mostly works for the PCI-DIO32HS, but only in timed input mode. 44 45This driver could be easily modified to support AT-MIO32HS and 46AT-MIO96. 47 48The PCI-6534 requires a firmware upload after power-up to work, the 49firmware data and instructions for loading it with comedi_config 50it are contained in the 51comedi_nonfree_firmware tarball available from http://www.comedi.org 52*/ 53 54/* 55 This driver is for both the NI PCI-DIO-32HS and the PCI-DIO-96, 56 which have very different architectures. But, since the '96 is 57 so simple, it is included here. 58 59 Manuals (available from ftp://ftp.natinst.com/support/manuals) 60 61 320938c.pdf PCI-DIO-96/PXI-6508/PCI-6503 User Manual 62 321464b.pdf AT/PCI-DIO-32HS User Manual 63 341329A.pdf PCI-6533 Register-Level Programmer Manual 64 341330A.pdf DAQ-DIO Technical Reference Manual 65 66 */ 67 68#define USE_DMA 69/* #define DEBUG 1 */ 70/* #define DEBUG_FLAGS */ 71 72#include "../comedidev.h" 73 74#include "mite.h" 75#include "8255.h" 76 77#undef DPRINTK 78#ifdef DEBUG 79#define DPRINTK(format, args...) printk(format, ## args) 80#else 81#define DPRINTK(format, args...) 82#endif 83 84#define PCI_VENDOR_ID_NATINST 0x1093 85 86#define PCI_DIO_SIZE 4096 87#define PCI_MITE_SIZE 4096 88 89/* defines for the PCI-DIO-96 */ 90 91#define NIDIO_8255_BASE(x) ((x)*4) 92#define NIDIO_A 0 93#define NIDIO_B 4 94#define NIDIO_C 8 95#define NIDIO_D 12 96 97/* defines for the PCI-DIO-32HS */ 98 99#define Window_Address 4 /* W */ 100#define Interrupt_And_Window_Status 4 /* R */ 101#define IntStatus1 (1<<0) 102#define IntStatus2 (1<<1) 103#define WindowAddressStatus_mask 0x7c 104 105#define Master_DMA_And_Interrupt_Control 5 /* W */ 106#define InterruptLine(x) ((x)&3) 107#define OpenInt (1<<2) 108#define Group_Status 5 /* R */ 109#define DataLeft (1<<0) 110#define Req (1<<2) 111#define StopTrig (1<<3) 112 113#define Group_1_Flags 6 /* R */ 114#define Group_2_Flags 7 /* R */ 115#define TransferReady (1<<0) 116#define CountExpired (1<<1) 117#define Waited (1<<5) 118#define PrimaryTC (1<<6) 119#define SecondaryTC (1<<7) 120 /* #define SerialRose */ 121 /* #define ReqRose */ 122 /* #define Paused */ 123 124#define Group_1_First_Clear 6 /* W */ 125#define Group_2_First_Clear 7 /* W */ 126#define ClearWaited (1<<3) 127#define ClearPrimaryTC (1<<4) 128#define ClearSecondaryTC (1<<5) 129#define DMAReset (1<<6) 130#define FIFOReset (1<<7) 131#define ClearAll 0xf8 132 133#define Group_1_FIFO 8 /* W */ 134#define Group_2_FIFO 12 /* W */ 135 136#define Transfer_Count 20 137#define Chip_ID_D 24 138#define Chip_ID_I 25 139#define Chip_ID_O 26 140#define Chip_Version 27 141#define Port_IO(x) (28+(x)) 142#define Port_Pin_Directions(x) (32+(x)) 143#define Port_Pin_Mask(x) (36+(x)) 144#define Port_Pin_Polarities(x) (40+(x)) 145 146#define Master_Clock_Routing 45 147#define RTSIClocking(x) (((x)&3)<<4) 148 149#define Group_1_Second_Clear 46 /* W */ 150#define Group_2_Second_Clear 47 /* W */ 151#define ClearExpired (1<<0) 152 153#define Port_Pattern(x) (48+(x)) 154 155#define Data_Path 64 156#define FIFOEnableA (1<<0) 157#define FIFOEnableB (1<<1) 158#define FIFOEnableC (1<<2) 159#define FIFOEnableD (1<<3) 160#define Funneling(x) (((x)&3)<<4) 161#define GroupDirection (1<<7) 162 163#define Protocol_Register_1 65 164#define OpMode Protocol_Register_1 165#define RunMode(x) ((x)&7) 166#define Numbered (1<<3) 167 168#define Protocol_Register_2 66 169#define ClockReg Protocol_Register_2 170#define ClockLine(x) (((x)&3)<<5) 171#define InvertStopTrig (1<<7) 172#define DataLatching(x) (((x)&3)<<5) 173 174#define Protocol_Register_3 67 175#define Sequence Protocol_Register_3 176 177#define Protocol_Register_14 68 /* 16 bit */ 178#define ClockSpeed Protocol_Register_14 179 180#define Protocol_Register_4 70 181#define ReqReg Protocol_Register_4 182#define ReqConditioning(x) (((x)&7)<<3) 183 184#define Protocol_Register_5 71 185#define BlockMode Protocol_Register_5 186 187#define FIFO_Control 72 188#define ReadyLevel(x) ((x)&7) 189 190#define Protocol_Register_6 73 191#define LinePolarities Protocol_Register_6 192#define InvertAck (1<<0) 193#define InvertReq (1<<1) 194#define InvertClock (1<<2) 195#define InvertSerial (1<<3) 196#define OpenAck (1<<4) 197#define OpenClock (1<<5) 198 199#define Protocol_Register_7 74 200#define AckSer Protocol_Register_7 201#define AckLine(x) (((x)&3)<<2) 202#define ExchangePins (1<<7) 203 204#define Interrupt_Control 75 205 /* bits same as flags */ 206 207#define DMA_Line_Control_Group1 76 208#define DMA_Line_Control_Group2 108 209/* channel zero is none */ 210static inline unsigned primary_DMAChannel_bits(unsigned channel) 211{ 212 return channel & 0x3; 213} 214static inline unsigned secondary_DMAChannel_bits(unsigned channel) 215{ 216 return (channel << 2) & 0xc; 217} 218 219#define Transfer_Size_Control 77 220#define TransferWidth(x) ((x)&3) 221#define TransferLength(x) (((x)&3)<<3) 222#define RequireRLevel (1<<5) 223 224#define Protocol_Register_15 79 225#define DAQOptions Protocol_Register_15 226#define StartSource(x) ((x)&0x3) 227#define InvertStart (1<<2) 228#define StopSource(x) (((x)&0x3)<<3) 229#define ReqStart (1<<6) 230#define PreStart (1<<7) 231 232#define Pattern_Detection 81 233#define DetectionMethod (1<<0) 234#define InvertMatch (1<<1) 235#define IE_Pattern_Detection (1<<2) 236 237#define Protocol_Register_9 82 238#define ReqDelay Protocol_Register_9 239 240#define Protocol_Register_10 83 241#define ReqNotDelay Protocol_Register_10 242 243#define Protocol_Register_11 84 244#define AckDelay Protocol_Register_11 245 246#define Protocol_Register_12 85 247#define AckNotDelay Protocol_Register_12 248 249#define Protocol_Register_13 86 250#define Data1Delay Protocol_Register_13 251 252#define Protocol_Register_8 88 /* 32 bit */ 253#define StartDelay Protocol_Register_8 254 255enum pci_6534_firmware_registers { /* 16 bit */ 256 Firmware_Control_Register = 0x100, 257 Firmware_Status_Register = 0x104, 258 Firmware_Data_Register = 0x108, 259 Firmware_Mask_Register = 0x10c, 260 Firmware_Debug_Register = 0x110, 261}; 262/* main fpga registers (32 bit)*/ 263enum pci_6534_fpga_registers { 264 FPGA_Control1_Register = 0x200, 265 FPGA_Control2_Register = 0x204, 266 FPGA_Irq_Mask_Register = 0x208, 267 FPGA_Status_Register = 0x20c, 268 FPGA_Signature_Register = 0x210, 269 FPGA_SCALS_Counter_Register = 0x280, /*write-clear */ 270 FPGA_SCAMS_Counter_Register = 0x284, /*write-clear */ 271 FPGA_SCBLS_Counter_Register = 0x288, /*write-clear */ 272 FPGA_SCBMS_Counter_Register = 0x28c, /*write-clear */ 273 FPGA_Temp_Control_Register = 0x2a0, 274 FPGA_DAR_Register = 0x2a8, 275 FPGA_ELC_Read_Register = 0x2b8, 276 FPGA_ELC_Write_Register = 0x2bc, 277}; 278enum FPGA_Control_Bits { 279 FPGA_Enable_Bit = 0x8000, 280}; 281 282#define TIMER_BASE 50 /* nanoseconds */ 283 284#ifdef USE_DMA 285#define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC) 286#else 287#define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC) 288#endif 289 290static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it); 291static int nidio_detach(struct comedi_device *dev); 292static int ni_pcidio_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 293 294static struct comedi_driver driver_pcidio = { 295 .driver_name = "ni_pcidio", 296 .module = THIS_MODULE, 297 .attach = nidio_attach, 298 .detach = nidio_detach, 299}; 300 301struct nidio_board { 302 303 int dev_id; 304 const char *name; 305 int n_8255; 306 unsigned int is_diodaq:1; 307 unsigned int uses_firmware:1; 308}; 309 310static const struct nidio_board nidio_boards[] = { 311 { 312 .dev_id = 0x1150, 313 .name = "pci-dio-32hs", 314 .n_8255 = 0, 315 .is_diodaq = 1, 316 }, 317 { 318 .dev_id = 0x1320, 319 .name = "pxi-6533", 320 .n_8255 = 0, 321 .is_diodaq = 1, 322 }, 323 { 324 .dev_id = 0x12b0, 325 .name = "pci-6534", 326 .n_8255 = 0, 327 .is_diodaq = 1, 328 .uses_firmware = 1, 329 }, 330 { 331 .dev_id = 0x0160, 332 .name = "pci-dio-96", 333 .n_8255 = 4, 334 .is_diodaq = 0, 335 }, 336 { 337 .dev_id = 0x1630, 338 .name = "pci-dio-96b", 339 .n_8255 = 4, 340 .is_diodaq = 0, 341 }, 342 { 343 .dev_id = 0x13c0, 344 .name = "pxi-6508", 345 .n_8255 = 4, 346 .is_diodaq = 0, 347 }, 348 { 349 .dev_id = 0x0400, 350 .name = "pci-6503", 351 .n_8255 = 1, 352 .is_diodaq = 0, 353 }, 354 { 355 .dev_id = 0x1250, 356 .name = "pci-6503b", 357 .n_8255 = 1, 358 .is_diodaq = 0, 359 }, 360 { 361 .dev_id = 0x17d0, 362 .name = "pci-6503x", 363 .n_8255 = 1, 364 .is_diodaq = 0, 365 }, 366 { 367 .dev_id = 0x1800, 368 .name = "pxi-6503", 369 .n_8255 = 1, 370 .is_diodaq = 0, 371 }, 372}; 373 374#define n_nidio_boards (sizeof(nidio_boards)/sizeof(nidio_boards[0])) 375#define this_board ((const struct nidio_board *)dev->board_ptr) 376 377static DEFINE_PCI_DEVICE_TABLE(ni_pcidio_pci_table) = { 378 {PCI_VENDOR_ID_NATINST, 0x1150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 379 {PCI_VENDOR_ID_NATINST, 0x1320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 380 {PCI_VENDOR_ID_NATINST, 0x12b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 381 {PCI_VENDOR_ID_NATINST, 0x0160, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 382 {PCI_VENDOR_ID_NATINST, 0x1630, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 383 {PCI_VENDOR_ID_NATINST, 0x13c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 384 {PCI_VENDOR_ID_NATINST, 0x0400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 385 {PCI_VENDOR_ID_NATINST, 0x1250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 386 {PCI_VENDOR_ID_NATINST, 0x17d0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 387 {PCI_VENDOR_ID_NATINST, 0x1800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 388 {0} 389}; 390 391MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table); 392 393struct nidio96_private { 394 struct mite_struct *mite; 395 int boardtype; 396 int dio; 397 unsigned short OpModeBits; 398 struct mite_channel *di_mite_chan; 399 struct mite_dma_descriptor_ring *di_mite_ring; 400 spinlock_t mite_channel_lock; 401}; 402#define devpriv ((struct nidio96_private *)dev->private) 403 404static int ni_pcidio_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 405 struct comedi_cmd *cmd); 406static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 407static int ni_pcidio_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 408 unsigned int trignum); 409static int nidio_find_device(struct comedi_device *dev, int bus, int slot); 410static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode); 411static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s); 412 413#ifdef DEBUG_FLAGS 414static void ni_pcidio_print_flags(unsigned int flags); 415static void ni_pcidio_print_status(unsigned int status); 416#else 417#define ni_pcidio_print_flags(x) 418#define ni_pcidio_print_status(x) 419#endif 420 421static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev) 422{ 423 unsigned long flags; 424 425 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 426 BUG_ON(devpriv->di_mite_chan); 427 devpriv->di_mite_chan = 428 mite_request_channel_in_range(devpriv->mite, 429 devpriv->di_mite_ring, 1, 2); 430 if (devpriv->di_mite_chan == NULL) { 431 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 432 comedi_error(dev, "failed to reserve mite dma channel."); 433 return -EBUSY; 434 } 435 writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) | 436 secondary_DMAChannel_bits(devpriv->di_mite_chan->channel), 437 devpriv->mite->daq_io_addr + DMA_Line_Control_Group1); 438 mmiowb(); 439 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 440 return 0; 441} 442 443static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev) 444{ 445 unsigned long flags; 446 447 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 448 if (devpriv->di_mite_chan) { 449 mite_dma_disarm(devpriv->di_mite_chan); 450 mite_dma_reset(devpriv->di_mite_chan); 451 mite_release_channel(devpriv->di_mite_chan); 452 devpriv->di_mite_chan = NULL; 453 writeb(primary_DMAChannel_bits(0) | 454 secondary_DMAChannel_bits(0), 455 devpriv->mite->daq_io_addr + DMA_Line_Control_Group1); 456 mmiowb(); 457 } 458 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 459} 460 461static int nidio96_8255_cb(int dir, int port, int data, unsigned long iobase) 462{ 463 if (dir) { 464 writeb(data, (void *)(iobase + port)); 465 return 0; 466 } else { 467 return readb((void *)(iobase + port)); 468 } 469} 470 471void ni_pcidio_event(struct comedi_device *dev, struct comedi_subdevice *s) 472{ 473 if (s->async-> 474 events & (COMEDI_CB_EOA | COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW)) 475 { 476 ni_pcidio_cancel(dev, s); 477 } 478 comedi_event(dev, s); 479} 480 481static irqreturn_t nidio_interrupt(int irq, void *d) 482{ 483 struct comedi_device *dev = d; 484 struct comedi_subdevice *s = dev->subdevices; 485 struct comedi_async *async = s->async; 486 struct mite_struct *mite = devpriv->mite; 487 488 /* int i, j; */ 489 long int AuxData = 0; 490 short data1 = 0; 491 short data2 = 0; 492 int flags; 493 int status; 494 int work = 0; 495 unsigned int m_status = 0; 496 unsigned long irq_flags; 497 498 /* interrupcions parasites */ 499 if (dev->attached == 0) { 500 /* assume it's from another card */ 501 return IRQ_NONE; 502 } 503 504 status = readb(devpriv->mite->daq_io_addr + 505 Interrupt_And_Window_Status); 506 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 507 508 DPRINTK("ni_pcidio_interrupt: status=0x%02x,flags=0x%02x\n", 509 status, flags); 510 ni_pcidio_print_flags(flags); 511 ni_pcidio_print_status(status); 512 513 /* printk("buf[0]=%08x\n",*(unsigned int *)async->prealloc_buf); */ 514 /* printk("buf[4096]=%08x\n",*(unsigned int *)(async->prealloc_buf+4096)); */ 515 516 spin_lock_irqsave(&devpriv->mite_channel_lock, irq_flags); 517 if (devpriv->di_mite_chan) 518 m_status = mite_get_status(devpriv->di_mite_chan); 519#ifdef MITE_DEBUG 520 mite_print_chsr(m_status); 521#endif 522 /* printk("mite_bytes_transferred: %d\n",mite_bytes_transferred(mite,DI_DMA_CHAN)); */ 523 /* mite_dump_regs(mite); */ 524 if (m_status & CHSR_INT) { 525 if (m_status & CHSR_LINKC) { 526 writel(CHOR_CLRLC, 527 mite->mite_io_addr + 528 MITE_CHOR(devpriv->di_mite_chan->channel)); 529 mite_sync_input_dma(devpriv->di_mite_chan, s->async); 530 /* XXX need to byteswap */ 531 } 532 if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY | 533 CHSR_DRQ1 | CHSR_MRDY)) { 534 DPRINTK("unknown mite interrupt, disabling IRQ\n"); 535 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 536 disable_irq(dev->irq); 537 } 538 } 539 spin_unlock_irqrestore(&devpriv->mite_channel_lock, irq_flags); 540 541 while (status & DataLeft) { 542 work++; 543 if (work > 20) { 544 DPRINTK("too much work in interrupt\n"); 545 writeb(0x00, 546 devpriv->mite->daq_io_addr + 547 Master_DMA_And_Interrupt_Control); 548 break; 549 } 550 551 flags &= IntEn; 552 553 if (flags & TransferReady) { 554 /* DPRINTK("TransferReady\n"); */ 555 while (flags & TransferReady) { 556 work++; 557 if (work > 100) { 558 DPRINTK("too much work in interrupt\n"); 559 writeb(0x00, 560 devpriv->mite->daq_io_addr + 561 Master_DMA_And_Interrupt_Control); 562 goto out; 563 } 564 AuxData = 565 readl(devpriv->mite->daq_io_addr + 566 Group_1_FIFO); 567 data1 = AuxData & 0xffff; 568 data2 = (AuxData & 0xffff0000) >> 16; 569 comedi_buf_put(async, data1); 570 comedi_buf_put(async, data2); 571 /* DPRINTK("read:%d, %d\n",data1,data2); */ 572 flags = readb(devpriv->mite->daq_io_addr + 573 Group_1_Flags); 574 } 575 /* DPRINTK("buf_int_count: %d\n",async->buf_int_count); */ 576 /* DPRINTK("1) IntEn=%d,flags=%d,status=%d\n",IntEn,flags,status); */ 577 /* ni_pcidio_print_flags(flags); */ 578 /* ni_pcidio_print_status(status); */ 579 async->events |= COMEDI_CB_BLOCK; 580 } 581 582 if (flags & CountExpired) { 583 DPRINTK("CountExpired\n"); 584 writeb(ClearExpired, 585 devpriv->mite->daq_io_addr + 586 Group_1_Second_Clear); 587 async->events |= COMEDI_CB_EOA; 588 589 writeb(0x00, devpriv->mite->daq_io_addr + OpMode); 590 break; 591 } else if (flags & Waited) { 592 DPRINTK("Waited\n"); 593 writeb(ClearWaited, 594 devpriv->mite->daq_io_addr + 595 Group_1_First_Clear); 596 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 597 break; 598 } else if (flags & PrimaryTC) { 599 DPRINTK("PrimaryTC\n"); 600 writeb(ClearPrimaryTC, 601 devpriv->mite->daq_io_addr + 602 Group_1_First_Clear); 603 async->events |= COMEDI_CB_EOA; 604 } else if (flags & SecondaryTC) { 605 DPRINTK("SecondaryTC\n"); 606 writeb(ClearSecondaryTC, 607 devpriv->mite->daq_io_addr + 608 Group_1_First_Clear); 609 async->events |= COMEDI_CB_EOA; 610 } 611#if 0 612 else { 613 printk("ni_pcidio: unknown interrupt\n"); 614 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 615 writeb(0x00, 616 devpriv->mite->daq_io_addr + 617 Master_DMA_And_Interrupt_Control); 618 } 619#endif 620 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 621 status = readb(devpriv->mite->daq_io_addr + 622 Interrupt_And_Window_Status); 623 /* DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x,status=0x%02x\n", */ 624 /* IntEn,flags,status); */ 625 /* ni_pcidio_print_flags(flags); */ 626 /* ni_pcidio_print_status(status); */ 627 } 628 629 out: 630 ni_pcidio_event(dev, s); 631#if 0 632 if (!tag) { 633 writeb(0x03, 634 devpriv->mite->daq_io_addr + 635 Master_DMA_And_Interrupt_Control); 636 } 637#endif 638 return IRQ_HANDLED; 639} 640 641#ifdef DEBUG_FLAGS 642static const char *const flags_strings[] = { 643 "TransferReady", "CountExpired", "2", "3", 644 "4", "Waited", "PrimaryTC", "SecondaryTC", 645}; 646static void ni_pcidio_print_flags(unsigned int flags) 647{ 648 int i; 649 650 printk("group_1_flags:"); 651 for (i = 7; i >= 0; i--) { 652 if (flags & (1 << i)) { 653 printk(" %s", flags_strings[i]); 654 } 655 } 656 printk("\n"); 657} 658static char *status_strings[] = { 659 "DataLeft1", "Reserved1", "Req1", "StopTrig1", 660 "DataLeft2", "Reserved2", "Req2", "StopTrig2", 661}; 662static void ni_pcidio_print_status(unsigned int flags) 663{ 664 int i; 665 666 printk("group_status:"); 667 for (i = 7; i >= 0; i--) { 668 if (flags & (1 << i)) { 669 printk(" %s", status_strings[i]); 670 } 671 } 672 printk("\n"); 673} 674#endif 675 676#ifdef unused 677static void debug_int(struct comedi_device * dev) 678{ 679 int a, b; 680 static int n_int = 0; 681 struct timeval tv; 682 683 do_gettimeofday(&tv); 684 a = readb(devpriv->mite->daq_io_addr + Group_Status); 685 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 686 687 if (n_int < 10) { 688 DPRINTK("status 0x%02x flags 0x%02x time %06d\n", a, b, 689 (int)tv.tv_usec); 690 } 691 692 while (b & 1) { 693 writew(0xff, devpriv->mite->daq_io_addr + Group_1_FIFO); 694 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 695 } 696 697 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags); 698 699 if (n_int < 10) { 700 DPRINTK("new status 0x%02x\n", b); 701 n_int++; 702 } 703} 704#endif 705 706static int ni_pcidio_insn_config(struct comedi_device * dev, struct comedi_subdevice * s, 707 struct comedi_insn * insn, unsigned int * data) 708{ 709 if (insn->n != 1) 710 return -EINVAL; 711 switch (data[0]) { 712 case INSN_CONFIG_DIO_OUTPUT: 713 s->io_bits |= 1 << CR_CHAN(insn->chanspec); 714 break; 715 case INSN_CONFIG_DIO_INPUT: 716 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec)); 717 break; 718 case INSN_CONFIG_DIO_QUERY: 719 data[1] = 720 (s->io_bits & (1 << CR_CHAN(insn-> 721 chanspec))) ? COMEDI_OUTPUT : 722 COMEDI_INPUT; 723 return insn->n; 724 break; 725 default: 726 return -EINVAL; 727 } 728 writel(s->io_bits, devpriv->mite->daq_io_addr + Port_Pin_Directions(0)); 729 730 return 1; 731} 732 733static int ni_pcidio_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s, 734 struct comedi_insn * insn, unsigned int * data) 735{ 736 if (insn->n != 2) 737 return -EINVAL; 738 if (data[0]) { 739 s->state &= ~data[0]; 740 s->state |= (data[0] & data[1]); 741 writel(s->state, devpriv->mite->daq_io_addr + Port_IO(0)); 742 } 743 data[1] = readl(devpriv->mite->daq_io_addr + Port_IO(0)); 744 745 return 2; 746} 747 748static int ni_pcidio_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s, 749 struct comedi_cmd * cmd) 750{ 751 int err = 0; 752 int tmp; 753 754 /* step 1: make sure trigger sources are trivially valid */ 755 756 tmp = cmd->start_src; 757 cmd->start_src &= TRIG_NOW | TRIG_INT; 758 if (!cmd->start_src || tmp != cmd->start_src) 759 err++; 760 761 tmp = cmd->scan_begin_src; 762 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; 763 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 764 err++; 765 766 tmp = cmd->convert_src; 767 cmd->convert_src &= TRIG_NOW; 768 if (!cmd->convert_src || tmp != cmd->convert_src) 769 err++; 770 771 tmp = cmd->scan_end_src; 772 cmd->scan_end_src &= TRIG_COUNT; 773 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 774 err++; 775 776 tmp = cmd->stop_src; 777 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 778 if (!cmd->stop_src || tmp != cmd->stop_src) 779 err++; 780 781 if (err) 782 return 1; 783 784 /* step 2: make sure trigger sources are unique and mutually compatible */ 785 786 /* note that mutual compatiblity is not an issue here */ 787 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_INT) 788 err++; 789 if (cmd->scan_begin_src != TRIG_TIMER && 790 cmd->scan_begin_src != TRIG_EXT) 791 err++; 792 793 if (err) 794 return 2; 795 796 /* step 3: make sure arguments are trivially compatible */ 797 798 if (cmd->start_arg != 0) { 799 /* same for both TRIG_INT and TRIG_NOW */ 800 cmd->start_arg = 0; 801 err++; 802 } 803#define MAX_SPEED (TIMER_BASE) /* in nanoseconds */ 804 805 if (cmd->scan_begin_src == TRIG_TIMER) { 806 if (cmd->scan_begin_arg < MAX_SPEED) { 807 cmd->scan_begin_arg = MAX_SPEED; 808 err++; 809 } 810 /* no minumum speed */ 811 } else { 812 /* TRIG_EXT */ 813 /* should be level/edge, hi/lo specification here */ 814 if (cmd->scan_begin_arg != 0) { 815 cmd->scan_begin_arg = 0; 816 err++; 817 } 818 } 819 if (cmd->convert_arg != 0) { 820 cmd->convert_arg = 0; 821 err++; 822 } 823 824 if (cmd->scan_end_arg != cmd->chanlist_len) { 825 cmd->scan_end_arg = cmd->chanlist_len; 826 err++; 827 } 828 if (cmd->stop_src == TRIG_COUNT) { 829 /* no limit */ 830 } else { 831 /* TRIG_NONE */ 832 if (cmd->stop_arg != 0) { 833 cmd->stop_arg = 0; 834 err++; 835 } 836 } 837 838 if (err) 839 return 3; 840 841 /* step 4: fix up any arguments */ 842 843 if (cmd->scan_begin_src == TRIG_TIMER) { 844 tmp = cmd->scan_begin_arg; 845 ni_pcidio_ns_to_timer(&cmd->scan_begin_arg, 846 cmd->flags & TRIG_ROUND_MASK); 847 if (tmp != cmd->scan_begin_arg) 848 err++; 849 } 850 851 if (err) 852 return 4; 853 854 return 0; 855} 856 857static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode) 858{ 859 int divider, base; 860 861 base = TIMER_BASE; 862 863 switch (round_mode) { 864 case TRIG_ROUND_NEAREST: 865 default: 866 divider = (*nanosec + base / 2) / base; 867 break; 868 case TRIG_ROUND_DOWN: 869 divider = (*nanosec) / base; 870 break; 871 case TRIG_ROUND_UP: 872 divider = (*nanosec + base - 1) / base; 873 break; 874 } 875 876 *nanosec = base * divider; 877 return divider; 878} 879 880static int ni_pcidio_cmd(struct comedi_device * dev, struct comedi_subdevice * s) 881{ 882 struct comedi_cmd *cmd = &s->async->cmd; 883 884 /* XXX configure ports for input */ 885 writel(0x0000, devpriv->mite->daq_io_addr + Port_Pin_Directions(0)); 886 887 if (1) { 888 /* enable fifos A B C D */ 889 writeb(0x0f, devpriv->mite->daq_io_addr + Data_Path); 890 891 /* set transfer width a 32 bits */ 892 writeb(TransferWidth(0) | TransferLength(0), 893 devpriv->mite->daq_io_addr + Transfer_Size_Control); 894 } else { 895 writeb(0x03, devpriv->mite->daq_io_addr + Data_Path); 896 writeb(TransferWidth(3) | TransferLength(0), 897 devpriv->mite->daq_io_addr + Transfer_Size_Control); 898 } 899 900 /* protocol configuration */ 901 if (cmd->scan_begin_src == TRIG_TIMER) { 902 /* page 4-5, "input with internal REQs" */ 903 writeb(0, devpriv->mite->daq_io_addr + OpMode); 904 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg); 905 writeb(1, devpriv->mite->daq_io_addr + Sequence); 906 writeb(0x04, devpriv->mite->daq_io_addr + ReqReg); 907 writeb(4, devpriv->mite->daq_io_addr + BlockMode); 908 writeb(3, devpriv->mite->daq_io_addr + LinePolarities); 909 writeb(0xc0, devpriv->mite->daq_io_addr + AckSer); 910 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg, 911 TRIG_ROUND_NEAREST), 912 devpriv->mite->daq_io_addr + StartDelay); 913 writeb(1, devpriv->mite->daq_io_addr + ReqDelay); 914 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay); 915 writeb(1, devpriv->mite->daq_io_addr + AckDelay); 916 writeb(0x0b, devpriv->mite->daq_io_addr + AckNotDelay); 917 writeb(0x01, devpriv->mite->daq_io_addr + Data1Delay); 918 /* manual, page 4-5: ClockSpeed comment is incorrectly listed 919 * on DAQOptions */ 920 writew(0, devpriv->mite->daq_io_addr + ClockSpeed); 921 writeb(0, devpriv->mite->daq_io_addr + DAQOptions); 922 } else { 923 /* TRIG_EXT */ 924 /* page 4-5, "input with external REQs" */ 925 writeb(0, devpriv->mite->daq_io_addr + OpMode); 926 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg); 927 writeb(0, devpriv->mite->daq_io_addr + Sequence); 928 writeb(0x00, devpriv->mite->daq_io_addr + ReqReg); 929 writeb(4, devpriv->mite->daq_io_addr + BlockMode); 930 writeb(0, devpriv->mite->daq_io_addr + LinePolarities); 931 writeb(0x00, devpriv->mite->daq_io_addr + AckSer); 932 writel(1, devpriv->mite->daq_io_addr + StartDelay); 933 writeb(1, devpriv->mite->daq_io_addr + ReqDelay); 934 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay); 935 writeb(1, devpriv->mite->daq_io_addr + AckDelay); 936 writeb(0x0C, devpriv->mite->daq_io_addr + AckNotDelay); 937 writeb(0x10, devpriv->mite->daq_io_addr + Data1Delay); 938 writew(0, devpriv->mite->daq_io_addr + ClockSpeed); 939 writeb(0x60, devpriv->mite->daq_io_addr + DAQOptions); 940 } 941 942 if (cmd->stop_src == TRIG_COUNT) { 943 writel(cmd->stop_arg, 944 devpriv->mite->daq_io_addr + Transfer_Count); 945 } else { 946 /* XXX */ 947 } 948 949#ifdef USE_DMA 950 writeb(ClearPrimaryTC | ClearSecondaryTC, 951 devpriv->mite->daq_io_addr + Group_1_First_Clear); 952 953 { 954 int retval = setup_mite_dma(dev, s); 955 if (retval) 956 return retval; 957 } 958#else 959 writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group1); 960#endif 961 writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group2); 962 963 /* clear and enable interrupts */ 964 writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear); 965 /* writeb(ClearExpired,devpriv->mite->daq_io_addr+Group_1_Second_Clear); */ 966 967 writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control); 968 writeb(0x03, 969 devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control); 970 971 if (cmd->stop_src == TRIG_NONE) { 972 devpriv->OpModeBits = DataLatching(0) | RunMode(7); 973 } else { /* TRIG_TIMER */ 974 devpriv->OpModeBits = Numbered | RunMode(7); 975 } 976 if (cmd->start_src == TRIG_NOW) { 977 /* start */ 978 writeb(devpriv->OpModeBits, 979 devpriv->mite->daq_io_addr + OpMode); 980 s->async->inttrig = NULL; 981 } else { 982 /* TRIG_INT */ 983 s->async->inttrig = ni_pcidio_inttrig; 984 } 985 986 DPRINTK("ni_pcidio: command started\n"); 987 return 0; 988} 989 990static int setup_mite_dma(struct comedi_device * dev, struct comedi_subdevice * s) 991{ 992 int retval; 993 994 retval = ni_pcidio_request_di_mite_channel(dev); 995 if (retval) 996 return retval; 997 998 devpriv->di_mite_chan->dir = COMEDI_INPUT; 999 1000 mite_prep_dma(devpriv->di_mite_chan, 32, 32); 1001 1002 mite_dma_arm(devpriv->di_mite_chan); 1003 return 0; 1004} 1005 1006static int ni_pcidio_inttrig(struct comedi_device * dev, struct comedi_subdevice * s, 1007 unsigned int trignum) 1008{ 1009 if (trignum != 0) 1010 return -EINVAL; 1011 1012 writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr + OpMode); 1013 s->async->inttrig = NULL; 1014 1015 return 1; 1016} 1017 1018static int ni_pcidio_cancel(struct comedi_device * dev, struct comedi_subdevice * s) 1019{ 1020 writeb(0x00, 1021 devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control); 1022 ni_pcidio_release_di_mite_channel(dev); 1023 1024 return 0; 1025} 1026 1027static int ni_pcidio_change(struct comedi_device * dev, struct comedi_subdevice * s, 1028 unsigned long new_size) 1029{ 1030 int ret; 1031 1032 ret = mite_buf_change(devpriv->di_mite_ring, s->async); 1033 if (ret < 0) 1034 return ret; 1035 1036 memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz); 1037 1038 return 0; 1039} 1040 1041static int pci_6534_load_fpga(struct comedi_device * dev, int fpga_index, u8 * data, 1042 int data_len) 1043{ 1044 static const int timeout = 1000; 1045 int i, j; 1046 writew(0x80 | fpga_index, 1047 devpriv->mite->daq_io_addr + Firmware_Control_Register); 1048 writew(0xc0 | fpga_index, 1049 devpriv->mite->daq_io_addr + Firmware_Control_Register); 1050 for (i = 0; 1051 (readw(devpriv->mite->daq_io_addr + 1052 Firmware_Status_Register) & 0x2) == 0 1053 && i < timeout; ++i) { 1054 udelay(1); 1055 } 1056 if (i == timeout) { 1057 printk("ni_pcidio: failed to load fpga %i, waiting for status 0x2\n", fpga_index); 1058 return -EIO; 1059 } 1060 writew(0x80 | fpga_index, 1061 devpriv->mite->daq_io_addr + Firmware_Control_Register); 1062 for (i = 0; 1063 readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) != 1064 0x3 && i < timeout; ++i) { 1065 udelay(1); 1066 } 1067 if (i == timeout) { 1068 printk("ni_pcidio: failed to load fpga %i, waiting for status 0x3\n", fpga_index); 1069 return -EIO; 1070 } 1071 for (j = 0; j + 1 < data_len;) { 1072 unsigned int value = data[j++]; 1073 value |= data[j++] << 8; 1074 writew(value, 1075 devpriv->mite->daq_io_addr + Firmware_Data_Register); 1076 for (i = 0; 1077 (readw(devpriv->mite->daq_io_addr + 1078 Firmware_Status_Register) & 0x2) == 0 1079 && i < timeout; ++i) { 1080 udelay(1); 1081 } 1082 if (i == timeout) { 1083 printk("ni_pcidio: failed to load word into fpga %i\n", 1084 fpga_index); 1085 return -EIO; 1086 } 1087 if (need_resched()) 1088 schedule(); 1089 } 1090 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register); 1091 return 0; 1092} 1093 1094static int pci_6534_reset_fpga(struct comedi_device * dev, int fpga_index) 1095{ 1096 return pci_6534_load_fpga(dev, fpga_index, NULL, 0); 1097} 1098 1099static int pci_6534_reset_fpgas(struct comedi_device * dev) 1100{ 1101 int ret; 1102 int i; 1103 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register); 1104 for (i = 0; i < 3; ++i) { 1105 ret = pci_6534_reset_fpga(dev, i); 1106 if (ret < 0) 1107 break; 1108 } 1109 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Mask_Register); 1110 return ret; 1111} 1112 1113static void pci_6534_init_main_fpga(struct comedi_device * dev) 1114{ 1115 writel(0, devpriv->mite->daq_io_addr + FPGA_Control1_Register); 1116 writel(0, devpriv->mite->daq_io_addr + FPGA_Control2_Register); 1117 writel(0, devpriv->mite->daq_io_addr + FPGA_SCALS_Counter_Register); 1118 writel(0, devpriv->mite->daq_io_addr + FPGA_SCAMS_Counter_Register); 1119 writel(0, devpriv->mite->daq_io_addr + FPGA_SCBLS_Counter_Register); 1120 writel(0, devpriv->mite->daq_io_addr + FPGA_SCBMS_Counter_Register); 1121} 1122 1123static int pci_6534_upload_firmware(struct comedi_device * dev, int options[]) 1124{ 1125 int ret; 1126 void *main_fpga_data, *scarab_a_data, *scarab_b_data; 1127 int main_fpga_data_len, scarab_a_data_len, scarab_b_data_len; 1128 1129 if (options[COMEDI_DEVCONF_AUX_DATA_LENGTH] == 0) 1130 return 0; 1131 ret = pci_6534_reset_fpgas(dev); 1132 if (ret < 0) 1133 return ret; 1134 main_fpga_data = comedi_aux_data(options, 0); 1135 main_fpga_data_len = options[COMEDI_DEVCONF_AUX_DATA0_LENGTH]; 1136 ret = pci_6534_load_fpga(dev, 2, main_fpga_data, main_fpga_data_len); 1137 if (ret < 0) 1138 return ret; 1139 pci_6534_init_main_fpga(dev); 1140 scarab_a_data = comedi_aux_data(options, 1); 1141 scarab_a_data_len = options[COMEDI_DEVCONF_AUX_DATA1_LENGTH]; 1142 ret = pci_6534_load_fpga(dev, 0, scarab_a_data, scarab_a_data_len); 1143 if (ret < 0) 1144 return ret; 1145 scarab_b_data = comedi_aux_data(options, 2); 1146 scarab_b_data_len = options[COMEDI_DEVCONF_AUX_DATA2_LENGTH]; 1147 ret = pci_6534_load_fpga(dev, 1, scarab_b_data, scarab_b_data_len); 1148 if (ret < 0) 1149 return ret; 1150 return 0; 1151} 1152 1153static int nidio_attach(struct comedi_device * dev, struct comedi_devconfig * it) 1154{ 1155 struct comedi_subdevice *s; 1156 int i; 1157 int ret; 1158 int n_subdevices; 1159 unsigned int irq; 1160 1161 printk("comedi%d: nidio:", dev->minor); 1162 1163 if ((ret = alloc_private(dev, sizeof(struct nidio96_private))) < 0) 1164 return ret; 1165 spin_lock_init(&devpriv->mite_channel_lock); 1166 1167 ret = nidio_find_device(dev, it->options[0], it->options[1]); 1168 if (ret < 0) 1169 return ret; 1170 1171 ret = mite_setup(devpriv->mite); 1172 if (ret < 0) { 1173 printk("error setting up mite\n"); 1174 return ret; 1175 } 1176 comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev); 1177 devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite); 1178 if (devpriv->di_mite_ring == NULL) 1179 return -ENOMEM; 1180 1181 dev->board_name = this_board->name; 1182 irq = mite_irq(devpriv->mite); 1183 printk(" %s", dev->board_name); 1184 if (this_board->uses_firmware) { 1185 ret = pci_6534_upload_firmware(dev, it->options); 1186 if (ret < 0) 1187 return ret; 1188 } 1189 if (!this_board->is_diodaq) { 1190 n_subdevices = this_board->n_8255; 1191 } else { 1192 n_subdevices = 1; 1193 } 1194 if ((ret = alloc_subdevices(dev, n_subdevices)) < 0) 1195 return ret; 1196 1197 if (!this_board->is_diodaq) { 1198 for (i = 0; i < this_board->n_8255; i++) { 1199 subdev_8255_init(dev, dev->subdevices + i, 1200 nidio96_8255_cb, 1201 (unsigned long)(devpriv->mite->daq_io_addr + 1202 NIDIO_8255_BASE(i))); 1203 } 1204 } else { 1205 1206 printk(" rev=%d", 1207 readb(devpriv->mite->daq_io_addr + Chip_Version)); 1208 1209 s = dev->subdevices + 0; 1210 1211 dev->read_subdev = s; 1212 s->type = COMEDI_SUBD_DIO; 1213 s->subdev_flags = 1214 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED | 1215 SDF_CMD_READ; 1216 s->n_chan = 32; 1217 s->range_table = &range_digital; 1218 s->maxdata = 1; 1219 s->insn_config = &ni_pcidio_insn_config; 1220 s->insn_bits = &ni_pcidio_insn_bits; 1221 s->do_cmd = &ni_pcidio_cmd; 1222 s->do_cmdtest = &ni_pcidio_cmdtest; 1223 s->cancel = &ni_pcidio_cancel; 1224 s->len_chanlist = 32; /* XXX */ 1225 s->buf_change = &ni_pcidio_change; 1226 s->async_dma_dir = DMA_BIDIRECTIONAL; 1227 1228 writel(0, devpriv->mite->daq_io_addr + Port_IO(0)); 1229 writel(0, devpriv->mite->daq_io_addr + Port_Pin_Directions(0)); 1230 writel(0, devpriv->mite->daq_io_addr + Port_Pin_Mask(0)); 1231 1232 /* disable interrupts on board */ 1233 writeb(0x00, 1234 devpriv->mite->daq_io_addr + 1235 Master_DMA_And_Interrupt_Control); 1236 1237 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED, 1238 "ni_pcidio", dev); 1239 if (ret < 0) { 1240 printk(" irq not available"); 1241 } 1242 dev->irq = irq; 1243 } 1244 1245 printk("\n"); 1246 1247 return 0; 1248} 1249 1250static int nidio_detach(struct comedi_device * dev) 1251{ 1252 int i; 1253 1254 if (this_board && !this_board->is_diodaq) { 1255 for (i = 0; i < this_board->n_8255; i++) { 1256 subdev_8255_cleanup(dev, dev->subdevices + i); 1257 } 1258 } 1259 1260 if (dev->irq) 1261 free_irq(dev->irq, dev); 1262 1263 if (devpriv) { 1264 if (devpriv->di_mite_ring) { 1265 mite_free_ring(devpriv->di_mite_ring); 1266 devpriv->di_mite_ring = NULL; 1267 } 1268 if (devpriv->mite) 1269 mite_unsetup(devpriv->mite); 1270 } 1271 return 0; 1272} 1273 1274static int nidio_find_device(struct comedi_device * dev, int bus, int slot) 1275{ 1276 struct mite_struct *mite; 1277 int i; 1278 1279 for (mite = mite_devices; mite; mite = mite->next) { 1280 if (mite->used) 1281 continue; 1282 if (bus || slot) { 1283 if (bus != mite->pcidev->bus->number || 1284 slot != PCI_SLOT(mite->pcidev->devfn)) 1285 continue; 1286 } 1287 for (i = 0; i < n_nidio_boards; i++) { 1288 if (mite_device_id(mite) == nidio_boards[i].dev_id) { 1289 dev->board_ptr = nidio_boards + i; 1290 devpriv->mite = mite; 1291 1292 return 0; 1293 } 1294 } 1295 } 1296 printk("no device found\n"); 1297 mite_list_devices(); 1298 return -EIO; 1299} 1300 1301COMEDI_PCI_INITCLEANUP(driver_pcidio, ni_pcidio_pci_table); 1302