ni_pcimio.c revision da91b2692e0939b307f9047192d2b9fe07793e7a
1/* 2 comedi/drivers/ni_pcimio.c 3 Hardware driver for NI PCI-MIO E series cards 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21*/ 22/* 23Driver: ni_pcimio 24Description: National Instruments PCI-MIO-E series and M series (all boards) 25Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans, 26 Herman Bruyninckx, Terry Barnaby 27Status: works 28Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio), 29 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E, 30 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E, 31 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E, 32 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, PCI-6225, 33 PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PCI-6254, PCI-6259, PCIe-6259, 34 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289, 35 PCI-6711, PXI-6711, PCI-6713, PXI-6713, 36 PXI-6071E, PCI-6070E, PXI-6070E, 37 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733, 38 PCI-6143, PXI-6143 39Updated: Wed, 03 Dec 2008 10:51:47 +0000 40 41These boards are almost identical to the AT-MIO E series, except that 42they use the PCI bus instead of ISA (i.e., AT). See the notes for 43the ni_atmio.o driver for additional information about these boards. 44 45Autocalibration is supported on many of the devices, using the 46comedi_calibrate (or comedi_soft_calibrate for m-series) utility. 47M-Series boards do analog input and analog output calibration entirely 48in software. The software calibration corrects 49the analog input for offset, gain and 50nonlinearity. The analog outputs are corrected for offset and gain. 51See the comedilib documentation on comedi_get_softcal_converter() for 52more information. 53 54By default, the driver uses DMA to transfer analog input data to 55memory. When DMA is enabled, not all triggering features are 56supported. 57 58Digital I/O may not work on 673x. 59 60Note that the PCI-6143 is a simultaineous sampling device with 8 convertors. 61With this board all of the convertors perform one simultaineous sample during 62a scan interval. The period for a scan is used for the convert time in a 63Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default. 64 65The RTSI trigger bus is supported on these cards on 66subdevice 10. See the comedilib documentation for details. 67 68Information (number of channels, bits, etc.) for some devices may be 69incorrect. Please check this and submit a bug if there are problems 70for your device. 71 72SCXI is probably broken for m-series boards. 73 74Bugs: 75 - When DMA is enabled, COMEDI_EV_CONVERT does 76 not work correctly. 77 78*/ 79/* 80 The PCI-MIO E series driver was originally written by 81 Tomasz Motylewski <...>, and ported to comedi by ds. 82 83 References: 84 85 341079b.pdf PCI E Series Register-Level Programmer Manual 86 340934b.pdf DAQ-STC reference manual 87 88 322080b.pdf 6711/6713/6715 User Manual 89 90 320945c.pdf PCI E Series User Manual 91 322138a.pdf PCI-6052E and DAQPad-6052E User Manual 92 93 ISSUES: 94 95 need to deal with external reference for DAC, and other DAC 96 properties in board properties 97 98 deal with at-mio-16de-10 revision D to N changes, etc. 99 100 need to add other CALDAC type 101 102 need to slow down DAC loading. I don't trust NI's claim that 103 two writes to the PCI bus slows IO enough. I would prefer to 104 use comedi_udelay(). Timing specs: (clock) 105 AD8522 30ns 106 DAC8043 120ns 107 DAC8800 60ns 108 MB88341 ? 109 110*/ 111 112#include "../comedidev.h" 113 114#include <asm/byteorder.h> 115#include <linux/delay.h> 116 117#include "ni_stc.h" 118#include "mite.h" 119 120/* #define PCI_DEBUG */ 121 122#define PCIDMA 123 124#define PCIMIO 1 125#undef ATMIO 126 127#define MAX_N_CALDACS (16+16+2) 128 129#define DRV_NAME "ni_pcimio" 130 131/* The following two tables must be in the same order */ 132static DEFINE_PCI_DEVICE_TABLE(ni_pci_table) = { 133 {PCI_VENDOR_ID_NATINST, 0x0162, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 134 {PCI_VENDOR_ID_NATINST, 0x1170, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 135 {PCI_VENDOR_ID_NATINST, 0x1180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 136 {PCI_VENDOR_ID_NATINST, 0x1190, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 137 {PCI_VENDOR_ID_NATINST, 0x11b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 138 {PCI_VENDOR_ID_NATINST, 0x11c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 139 {PCI_VENDOR_ID_NATINST, 0x11d0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 140 {PCI_VENDOR_ID_NATINST, 0x1270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 141 {PCI_VENDOR_ID_NATINST, 0x1330, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 142 {PCI_VENDOR_ID_NATINST, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 143 {PCI_VENDOR_ID_NATINST, 0x1350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 144 {PCI_VENDOR_ID_NATINST, 0x14e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 145 {PCI_VENDOR_ID_NATINST, 0x14f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 146 {PCI_VENDOR_ID_NATINST, 0x1580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 147 {PCI_VENDOR_ID_NATINST, 0x15b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 148 {PCI_VENDOR_ID_NATINST, 0x1880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 149 {PCI_VENDOR_ID_NATINST, 0x1870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 150 {PCI_VENDOR_ID_NATINST, 0x18b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 151 {PCI_VENDOR_ID_NATINST, 0x18c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 152 {PCI_VENDOR_ID_NATINST, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 153 {PCI_VENDOR_ID_NATINST, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 154 {PCI_VENDOR_ID_NATINST, 0x2430, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 155 {PCI_VENDOR_ID_NATINST, 0x2890, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 156 {PCI_VENDOR_ID_NATINST, 0x28c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 157 {PCI_VENDOR_ID_NATINST, 0x2a60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 158 {PCI_VENDOR_ID_NATINST, 0x2a70, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 159 {PCI_VENDOR_ID_NATINST, 0x2a80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 160 {PCI_VENDOR_ID_NATINST, 0x2ab0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 161 {PCI_VENDOR_ID_NATINST, 0x2b80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 162 {PCI_VENDOR_ID_NATINST, 0x2b90, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 163 {PCI_VENDOR_ID_NATINST, 0x2c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 164 {PCI_VENDOR_ID_NATINST, 0x2ca0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 165 {PCI_VENDOR_ID_NATINST, 0x70aa, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 166 {PCI_VENDOR_ID_NATINST, 0x70ab, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 167 {PCI_VENDOR_ID_NATINST, 0x70ac, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 168 {PCI_VENDOR_ID_NATINST, 0x70af, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 169 {PCI_VENDOR_ID_NATINST, 0x70b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 170 {PCI_VENDOR_ID_NATINST, 0x70b4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 171 {PCI_VENDOR_ID_NATINST, 0x70b6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 172 {PCI_VENDOR_ID_NATINST, 0x70b7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 173 {PCI_VENDOR_ID_NATINST, 0x70b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 174 {PCI_VENDOR_ID_NATINST, 0x70bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 175 {PCI_VENDOR_ID_NATINST, 0x70bd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 176 {PCI_VENDOR_ID_NATINST, 0x70bf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 177 {PCI_VENDOR_ID_NATINST, 0x70c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 178 {PCI_VENDOR_ID_NATINST, 0x70f2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 179 {PCI_VENDOR_ID_NATINST, 0x710d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 180 {PCI_VENDOR_ID_NATINST, 0x716c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 181 {PCI_VENDOR_ID_NATINST, 0x717f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 182 {PCI_VENDOR_ID_NATINST, 0x71bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 183 {PCI_VENDOR_ID_NATINST, 0x717d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 184 {0} 185}; 186 187MODULE_DEVICE_TABLE(pci, ni_pci_table); 188 189/* These are not all the possible ao ranges for 628x boards. 190 They can do OFFSET +- REFERENCE where OFFSET can be 191 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can 192 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's 193 63 different possibilities. An AO channel 194 can not act as it's own OFFSET or REFERENCE. 195*/ 196static const struct comedi_lrange range_ni_M_628x_ao = { 8, { 197 RANGE(-10, 10), 198 RANGE(-5, 5), 199 RANGE(-2, 2), 200 RANGE(-1, 1), 201 RANGE(-5, 15), 202 RANGE(0, 10), 203 RANGE(3, 7), 204 RANGE(4, 6), 205 RANGE_ext(-1, 1) 206 } 207}; 208static const struct comedi_lrange range_ni_M_625x_ao = { 3, { 209 RANGE(-10, 10), 210 RANGE(-5, 5), 211 RANGE_ext(-1, 1) 212 } 213}; 214static const struct comedi_lrange range_ni_M_622x_ao = { 1, { 215 RANGE(-10, 10), 216 } 217}; 218 219static const struct ni_board_struct ni_boards[] = { 220 { 221 .device_id = 0x0162, /* NI also says 0x1620. typo? */ 222 .name = "pci-mio-16xe-50", 223 .n_adchan = 16, 224 .adbits = 16, 225 .ai_fifo_depth = 2048, 226 .alwaysdither = 1, 227 .gainlkup = ai_gain_8, 228 .ai_speed = 50000, 229 .n_aochan = 2, 230 .aobits = 12, 231 .ao_fifo_depth = 0, 232 .ao_range_table = &range_bipolar10, 233 .ao_unipolar = 0, 234 .ao_speed = 50000, 235 .num_p0_dio_channels = 8, 236 .caldac = {dac8800, dac8043}, 237 .has_8255 = 0, 238 }, 239 { 240 .device_id = 0x1170, 241 .name = "pci-mio-16xe-10", /* aka pci-6030E */ 242 .n_adchan = 16, 243 .adbits = 16, 244 .ai_fifo_depth = 512, 245 .alwaysdither = 1, 246 .gainlkup = ai_gain_14, 247 .ai_speed = 10000, 248 .n_aochan = 2, 249 .aobits = 16, 250 .ao_fifo_depth = 2048, 251 .ao_range_table = &range_ni_E_ao_ext, 252 .ao_unipolar = 1, 253 .ao_speed = 10000, 254 .num_p0_dio_channels = 8, 255 .caldac = {dac8800, dac8043, ad8522}, 256 .has_8255 = 0, 257 }, 258 { 259 .device_id = 0x28c0, 260 .name = "pci-6014", 261 .n_adchan = 16, 262 .adbits = 16, 263 .ai_fifo_depth = 512, 264 .alwaysdither = 1, 265 .gainlkup = ai_gain_4, 266 .ai_speed = 5000, 267 .n_aochan = 2, 268 .aobits = 16, 269 .ao_fifo_depth = 0, 270 .ao_range_table = &range_bipolar10, 271 .ao_unipolar = 0, 272 .ao_speed = 100000, 273 .num_p0_dio_channels = 8, 274 .caldac = {ad8804_debug}, 275 .has_8255 = 0, 276 }, 277 { 278 .device_id = 0x11d0, 279 .name = "pxi-6030e", 280 .n_adchan = 16, 281 .adbits = 16, 282 .ai_fifo_depth = 512, 283 .alwaysdither = 1, 284 .gainlkup = ai_gain_14, 285 .ai_speed = 10000, 286 .n_aochan = 2, 287 .aobits = 16, 288 .ao_fifo_depth = 2048, 289 .ao_range_table = &range_ni_E_ao_ext, 290 .ao_unipolar = 1, 291 .ao_speed = 10000, 292 .num_p0_dio_channels = 8, 293 .caldac = {dac8800, dac8043, ad8522}, 294 .has_8255 = 0, 295 }, 296 { 297 .device_id = 0x1180, 298 .name = "pci-mio-16e-1", /* aka pci-6070e */ 299 .n_adchan = 16, 300 .adbits = 12, 301 .ai_fifo_depth = 512, 302 .alwaysdither = 0, 303 .gainlkup = ai_gain_16, 304 .ai_speed = 800, 305 .n_aochan = 2, 306 .aobits = 12, 307 .ao_fifo_depth = 2048, 308 .ao_range_table = &range_ni_E_ao_ext, 309 .ao_unipolar = 1, 310 .ao_speed = 1000, 311 .num_p0_dio_channels = 8, 312 .caldac = {mb88341}, 313 .has_8255 = 0, 314 }, 315 { 316 .device_id = 0x1190, 317 .name = "pci-mio-16e-4", /* aka pci-6040e */ 318 .n_adchan = 16, 319 .adbits = 12, 320 .ai_fifo_depth = 512, 321 .alwaysdither = 0, 322 .gainlkup = ai_gain_16, 323 /* Note: there have been reported problems with full speed 324 * on this board */ 325 .ai_speed = 2000, 326 .n_aochan = 2, 327 .aobits = 12, 328 .ao_fifo_depth = 512, 329 .ao_range_table = &range_ni_E_ao_ext, 330 .ao_unipolar = 1, 331 .ao_speed = 1000, 332 .num_p0_dio_channels = 8, 333 .caldac = {ad8804_debug}, /* doc says mb88341 */ 334 .has_8255 = 0, 335 }, 336 { 337 .device_id = 0x11c0, 338 .name = "pxi-6040e", 339 .n_adchan = 16, 340 .adbits = 12, 341 .ai_fifo_depth = 512, 342 .alwaysdither = 0, 343 .gainlkup = ai_gain_16, 344 .ai_speed = 2000, 345 .n_aochan = 2, 346 .aobits = 12, 347 .ao_fifo_depth = 512, 348 .ao_range_table = &range_ni_E_ao_ext, 349 .ao_unipolar = 1, 350 .ao_speed = 1000, 351 .num_p0_dio_channels = 8, 352 .caldac = {mb88341}, 353 .has_8255 = 0, 354 }, 355 356 { 357 .device_id = 0x1330, 358 .name = "pci-6031e", 359 .n_adchan = 64, 360 .adbits = 16, 361 .ai_fifo_depth = 512, 362 .alwaysdither = 1, 363 .gainlkup = ai_gain_14, 364 .ai_speed = 10000, 365 .n_aochan = 2, 366 .aobits = 16, 367 .ao_fifo_depth = 2048, 368 .ao_range_table = &range_ni_E_ao_ext, 369 .ao_unipolar = 1, 370 .ao_speed = 10000, 371 .num_p0_dio_channels = 8, 372 .caldac = {dac8800, dac8043, ad8522}, 373 .has_8255 = 0, 374 }, 375 { 376 .device_id = 0x1270, 377 .name = "pci-6032e", 378 .n_adchan = 16, 379 .adbits = 16, 380 .ai_fifo_depth = 512, 381 .alwaysdither = 1, 382 .gainlkup = ai_gain_14, 383 .ai_speed = 10000, 384 .n_aochan = 0, 385 .aobits = 0, 386 .ao_fifo_depth = 0, 387 .ao_unipolar = 0, 388 .num_p0_dio_channels = 8, 389 .caldac = {dac8800, dac8043, ad8522}, 390 .has_8255 = 0, 391 }, 392 { 393 .device_id = 0x1340, 394 .name = "pci-6033e", 395 .n_adchan = 64, 396 .adbits = 16, 397 .ai_fifo_depth = 512, 398 .alwaysdither = 1, 399 .gainlkup = ai_gain_14, 400 .ai_speed = 10000, 401 .n_aochan = 0, 402 .aobits = 0, 403 .ao_fifo_depth = 0, 404 .ao_unipolar = 0, 405 .num_p0_dio_channels = 8, 406 .caldac = {dac8800, dac8043, ad8522}, 407 .has_8255 = 0, 408 }, 409 { 410 .device_id = 0x1350, 411 .name = "pci-6071e", 412 .n_adchan = 64, 413 .adbits = 12, 414 .ai_fifo_depth = 512, 415 .alwaysdither = 1, 416 .gainlkup = ai_gain_16, 417 .ai_speed = 800, 418 .n_aochan = 2, 419 .aobits = 12, 420 .ao_fifo_depth = 2048, 421 .ao_range_table = &range_ni_E_ao_ext, 422 .ao_unipolar = 1, 423 .ao_speed = 1000, 424 .num_p0_dio_channels = 8, 425 .caldac = {ad8804_debug}, 426 .has_8255 = 0, 427 }, 428 { 429 .device_id = 0x2a60, 430 .name = "pci-6023e", 431 .n_adchan = 16, 432 .adbits = 12, 433 .ai_fifo_depth = 512, 434 .alwaysdither = 0, 435 .gainlkup = ai_gain_4, 436 .ai_speed = 5000, 437 .n_aochan = 0, 438 .aobits = 0, 439 .ao_unipolar = 0, 440 .num_p0_dio_channels = 8, 441 .caldac = {ad8804_debug}, /* manual is wrong */ 442 .has_8255 = 0, 443 }, 444 { 445 .device_id = 0x2a70, 446 .name = "pci-6024e", 447 .n_adchan = 16, 448 .adbits = 12, 449 .ai_fifo_depth = 512, 450 .alwaysdither = 0, 451 .gainlkup = ai_gain_4, 452 .ai_speed = 5000, 453 .n_aochan = 2, 454 .aobits = 12, 455 .ao_fifo_depth = 0, 456 .ao_range_table = &range_bipolar10, 457 .ao_unipolar = 0, 458 .ao_speed = 100000, 459 .num_p0_dio_channels = 8, 460 .caldac = {ad8804_debug}, /* manual is wrong */ 461 .has_8255 = 0, 462 }, 463 { 464 .device_id = 0x2a80, 465 .name = "pci-6025e", 466 .n_adchan = 16, 467 .adbits = 12, 468 .ai_fifo_depth = 512, 469 .alwaysdither = 0, 470 .gainlkup = ai_gain_4, 471 .ai_speed = 5000, 472 .n_aochan = 2, 473 .aobits = 12, 474 .ao_fifo_depth = 0, 475 .ao_range_table = &range_bipolar10, 476 .ao_unipolar = 0, 477 .ao_speed = 100000, 478 .num_p0_dio_channels = 8, 479 .caldac = {ad8804_debug}, /* manual is wrong */ 480 .has_8255 = 1, 481 }, 482 { 483 .device_id = 0x2ab0, 484 .name = "pxi-6025e", 485 .n_adchan = 16, 486 .adbits = 12, 487 .ai_fifo_depth = 512, 488 .alwaysdither = 0, 489 .gainlkup = ai_gain_4, 490 .ai_speed = 5000, 491 .n_aochan = 2, 492 .aobits = 12, 493 .ao_fifo_depth = 0, 494 .ao_range_table = &range_ni_E_ao_ext, 495 .ao_unipolar = 1, 496 .ao_speed = 100000, 497 .num_p0_dio_channels = 8, 498 .caldac = {ad8804_debug}, /* manual is wrong */ 499 .has_8255 = 1, 500 }, 501 502 { 503 .device_id = 0x2ca0, 504 .name = "pci-6034e", 505 .n_adchan = 16, 506 .adbits = 16, 507 .ai_fifo_depth = 512, 508 .alwaysdither = 1, 509 .gainlkup = ai_gain_4, 510 .ai_speed = 5000, 511 .n_aochan = 0, 512 .aobits = 0, 513 .ao_fifo_depth = 0, 514 .ao_unipolar = 0, 515 .num_p0_dio_channels = 8, 516 .caldac = {ad8804_debug}, 517 .has_8255 = 0, 518 }, 519 { 520 .device_id = 0x2c80, 521 .name = "pci-6035e", 522 .n_adchan = 16, 523 .adbits = 16, 524 .ai_fifo_depth = 512, 525 .alwaysdither = 1, 526 .gainlkup = ai_gain_4, 527 .ai_speed = 5000, 528 .n_aochan = 2, 529 .aobits = 12, 530 .ao_fifo_depth = 0, 531 .ao_range_table = &range_bipolar10, 532 .ao_unipolar = 0, 533 .ao_speed = 100000, 534 .num_p0_dio_channels = 8, 535 .caldac = {ad8804_debug}, 536 .has_8255 = 0, 537 }, 538 { 539 .device_id = 0x18b0, 540 .name = "pci-6052e", 541 .n_adchan = 16, 542 .adbits = 16, 543 .ai_fifo_depth = 512, 544 .alwaysdither = 1, 545 .gainlkup = ai_gain_16, 546 .ai_speed = 3000, 547 .n_aochan = 2, 548 .aobits = 16, 549 .ao_unipolar = 1, 550 .ao_fifo_depth = 2048, 551 .ao_range_table = &range_ni_E_ao_ext, 552 .ao_speed = 3000, 553 .num_p0_dio_channels = 8, 554 .caldac = {ad8804_debug, ad8804_debug, ad8522}, /* manual is wrong */ 555 }, 556 {.device_id = 0x14e0, 557 .name = "pci-6110", 558 .n_adchan = 4, 559 .adbits = 12, 560 .ai_fifo_depth = 8192, 561 .alwaysdither = 0, 562 .gainlkup = ai_gain_611x, 563 .ai_speed = 200, 564 .n_aochan = 2, 565 .aobits = 16, 566 .reg_type = ni_reg_611x, 567 .ao_range_table = &range_bipolar10, 568 .ao_unipolar = 0, 569 .ao_fifo_depth = 2048, 570 .ao_speed = 250, 571 .num_p0_dio_channels = 8, 572 .caldac = {ad8804, ad8804}, 573 }, 574 { 575 .device_id = 0x14f0, 576 .name = "pci-6111", 577 .n_adchan = 2, 578 .adbits = 12, 579 .ai_fifo_depth = 8192, 580 .alwaysdither = 0, 581 .gainlkup = ai_gain_611x, 582 .ai_speed = 200, 583 .n_aochan = 2, 584 .aobits = 16, 585 .reg_type = ni_reg_611x, 586 .ao_range_table = &range_bipolar10, 587 .ao_unipolar = 0, 588 .ao_fifo_depth = 2048, 589 .ao_speed = 250, 590 .num_p0_dio_channels = 8, 591 .caldac = {ad8804, ad8804}, 592 }, 593#if 0 594 /* The 6115 boards probably need their own driver */ 595 { 596 .device_id = 0x2ed0, 597 .name = "pci-6115", 598 .n_adchan = 4, 599 .adbits = 12, 600 .ai_fifo_depth = 8192, 601 .alwaysdither = 0, 602 .gainlkup = ai_gain_611x, 603 .ai_speed = 100, 604 .n_aochan = 2, 605 .aobits = 16, 606 .ao_671x = 1, 607 .ao_unipolar = 0, 608 .ao_fifo_depth = 2048, 609 .ao_speed = 250, 610 .num_p0_dio_channels = 8, 611 .reg_611x = 1, 612 .caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */ 613 }, 614#endif 615#if 0 616 { 617 .device_id = 0x0000, 618 .name = "pxi-6115", 619 .n_adchan = 4, 620 .adbits = 12, 621 .ai_fifo_depth = 8192, 622 .alwaysdither = 0, 623 .gainlkup = ai_gain_611x, 624 .ai_speed = 100, 625 .n_aochan = 2, 626 .aobits = 16, 627 .ao_671x = 1, 628 .ao_unipolar = 0, 629 .ao_fifo_depth = 2048, 630 .ao_speed = 250, 631 .reg_611x = 1, 632 .num_p0_dio_channels = 8, 633 caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */ 634 }, 635#endif 636 { 637 .device_id = 0x1880, 638 .name = "pci-6711", 639 .n_adchan = 0, /* no analog input */ 640 .n_aochan = 4, 641 .aobits = 12, 642 .ao_unipolar = 0, 643 .ao_fifo_depth = 16384, 644 /* data sheet says 8192, but fifo really holds 16384 samples */ 645 .ao_range_table = &range_bipolar10, 646 .ao_speed = 1000, 647 .num_p0_dio_channels = 8, 648 .reg_type = ni_reg_6711, 649 .caldac = {ad8804_debug}, 650 }, 651 { 652 .device_id = 0x2b90, 653 .name = "pxi-6711", 654 .n_adchan = 0, /* no analog input */ 655 .n_aochan = 4, 656 .aobits = 12, 657 .ao_unipolar = 0, 658 .ao_fifo_depth = 16384, 659 .ao_range_table = &range_bipolar10, 660 .ao_speed = 1000, 661 .num_p0_dio_channels = 8, 662 .reg_type = ni_reg_6711, 663 .caldac = {ad8804_debug}, 664 }, 665 { 666 .device_id = 0x1870, 667 .name = "pci-6713", 668 .n_adchan = 0, /* no analog input */ 669 .n_aochan = 8, 670 .aobits = 12, 671 .ao_unipolar = 0, 672 .ao_fifo_depth = 16384, 673 .ao_range_table = &range_bipolar10, 674 .ao_speed = 1000, 675 .num_p0_dio_channels = 8, 676 .reg_type = ni_reg_6713, 677 .caldac = {ad8804_debug, ad8804_debug}, 678 }, 679 { 680 .device_id = 0x2b80, 681 .name = "pxi-6713", 682 .n_adchan = 0, /* no analog input */ 683 .n_aochan = 8, 684 .aobits = 12, 685 .ao_unipolar = 0, 686 .ao_fifo_depth = 16384, 687 .ao_range_table = &range_bipolar10, 688 .ao_speed = 1000, 689 .num_p0_dio_channels = 8, 690 .reg_type = ni_reg_6713, 691 .caldac = {ad8804_debug, ad8804_debug}, 692 }, 693 { 694 .device_id = 0x2430, 695 .name = "pci-6731", 696 .n_adchan = 0, /* no analog input */ 697 .n_aochan = 4, 698 .aobits = 16, 699 .ao_unipolar = 0, 700 .ao_fifo_depth = 8192, 701 .ao_range_table = &range_bipolar10, 702 .ao_speed = 1000, 703 .num_p0_dio_channels = 8, 704 .reg_type = ni_reg_6711, 705 .caldac = {ad8804_debug}, 706 }, 707#if 0 /* need device ids */ 708 { 709 .device_id = 0x0, 710 .name = "pxi-6731", 711 .n_adchan = 0, /* no analog input */ 712 .n_aochan = 4, 713 .aobits = 16, 714 .ao_unipolar = 0, 715 .ao_fifo_depth = 8192, 716 .ao_range_table = &range_bipolar10, 717 .num_p0_dio_channels = 8, 718 .reg_type = ni_reg_6711, 719 .caldac = {ad8804_debug}, 720 }, 721#endif 722 { 723 .device_id = 0x2410, 724 .name = "pci-6733", 725 .n_adchan = 0, /* no analog input */ 726 .n_aochan = 8, 727 .aobits = 16, 728 .ao_unipolar = 0, 729 .ao_fifo_depth = 16384, 730 .ao_range_table = &range_bipolar10, 731 .ao_speed = 1000, 732 .num_p0_dio_channels = 8, 733 .reg_type = ni_reg_6713, 734 .caldac = {ad8804_debug, ad8804_debug}, 735 }, 736 { 737 .device_id = 0x2420, 738 .name = "pxi-6733", 739 .n_adchan = 0, /* no analog input */ 740 .n_aochan = 8, 741 .aobits = 16, 742 .ao_unipolar = 0, 743 .ao_fifo_depth = 16384, 744 .ao_range_table = &range_bipolar10, 745 .ao_speed = 1000, 746 .num_p0_dio_channels = 8, 747 .reg_type = ni_reg_6713, 748 .caldac = {ad8804_debug, ad8804_debug}, 749 }, 750 { 751 .device_id = 0x15b0, 752 .name = "pxi-6071e", 753 .n_adchan = 64, 754 .adbits = 12, 755 .ai_fifo_depth = 512, 756 .alwaysdither = 1, 757 .gainlkup = ai_gain_16, 758 .ai_speed = 800, 759 .n_aochan = 2, 760 .aobits = 12, 761 .ao_fifo_depth = 2048, 762 .ao_range_table = &range_ni_E_ao_ext, 763 .ao_unipolar = 1, 764 .ao_speed = 1000, 765 .num_p0_dio_channels = 8, 766 .caldac = {ad8804_debug}, 767 .has_8255 = 0, 768 }, 769 { 770 .device_id = 0x11b0, 771 .name = "pxi-6070e", 772 .n_adchan = 16, 773 .adbits = 12, 774 .ai_fifo_depth = 512, 775 .alwaysdither = 1, 776 .gainlkup = ai_gain_16, 777 .ai_speed = 800, 778 .n_aochan = 2, 779 .aobits = 12, 780 .ao_fifo_depth = 2048, 781 .ao_range_table = &range_ni_E_ao_ext, 782 .ao_unipolar = 1, 783 .ao_speed = 1000, 784 .num_p0_dio_channels = 8, 785 .caldac = {ad8804_debug}, 786 .has_8255 = 0, 787 }, 788 { 789 .device_id = 0x18c0, 790 .name = "pxi-6052e", 791 .n_adchan = 16, 792 .adbits = 16, 793 .ai_fifo_depth = 512, 794 .alwaysdither = 1, 795 .gainlkup = ai_gain_16, 796 .ai_speed = 3000, 797 .n_aochan = 2, 798 .aobits = 16, 799 .ao_unipolar = 1, 800 .ao_fifo_depth = 2048, 801 .ao_range_table = &range_ni_E_ao_ext, 802 .ao_speed = 3000, 803 .num_p0_dio_channels = 8, 804 .caldac = {mb88341, mb88341, ad8522}, 805 }, 806 { 807 .device_id = 0x1580, 808 .name = "pxi-6031e", 809 .n_adchan = 64, 810 .adbits = 16, 811 .ai_fifo_depth = 512, 812 .alwaysdither = 1, 813 .gainlkup = ai_gain_14, 814 .ai_speed = 10000, 815 .n_aochan = 2, 816 .aobits = 16, 817 .ao_fifo_depth = 2048, 818 .ao_range_table = &range_ni_E_ao_ext, 819 .ao_unipolar = 1, 820 .ao_speed = 10000, 821 .num_p0_dio_channels = 8, 822 .caldac = {dac8800, dac8043, ad8522}, 823 }, 824 { 825 .device_id = 0x2890, 826 .name = "pci-6036e", 827 .n_adchan = 16, 828 .adbits = 16, 829 .ai_fifo_depth = 512, 830 .alwaysdither = 1, 831 .gainlkup = ai_gain_4, 832 .ai_speed = 5000, 833 .n_aochan = 2, 834 .aobits = 16, 835 .ao_fifo_depth = 0, 836 .ao_range_table = &range_bipolar10, 837 .ao_unipolar = 0, 838 .ao_speed = 100000, 839 .num_p0_dio_channels = 8, 840 .caldac = {ad8804_debug}, 841 .has_8255 = 0, 842 }, 843 { 844 .device_id = 0x70b0, 845 .name = "pci-6220", 846 .n_adchan = 16, 847 .adbits = 16, 848 .ai_fifo_depth = 512, 849 /* FIXME: guess */ 850 .gainlkup = ai_gain_622x, 851 .ai_speed = 4000, 852 .n_aochan = 0, 853 .aobits = 0, 854 .ao_fifo_depth = 0, 855 .num_p0_dio_channels = 8, 856 .reg_type = ni_reg_622x, 857 .ao_unipolar = 0, 858 .caldac = {caldac_none}, 859 .has_8255 = 0, 860 }, 861 { 862 .device_id = 0x70af, 863 .name = "pci-6221", 864 .n_adchan = 16, 865 .adbits = 16, 866 .ai_fifo_depth = 4095, 867 .gainlkup = ai_gain_622x, 868 .ai_speed = 4000, 869 .n_aochan = 2, 870 .aobits = 16, 871 .ao_fifo_depth = 8191, 872 .ao_range_table = &range_ni_M_622x_ao, 873 .reg_type = ni_reg_622x, 874 .ao_unipolar = 0, 875 .ao_speed = 1200, 876 .num_p0_dio_channels = 8, 877 .caldac = {caldac_none}, 878 .has_8255 = 0, 879 }, 880 { 881 .device_id = 0x71bc, 882 .name = "pci-6221_37pin", 883 .n_adchan = 16, 884 .adbits = 16, 885 .ai_fifo_depth = 4095, 886 .gainlkup = ai_gain_622x, 887 .ai_speed = 4000, 888 .n_aochan = 2, 889 .aobits = 16, 890 .ao_fifo_depth = 8191, 891 .ao_range_table = &range_ni_M_622x_ao, 892 .reg_type = ni_reg_622x, 893 .ao_unipolar = 0, 894 .ao_speed = 1200, 895 .num_p0_dio_channels = 8, 896 .caldac = {caldac_none}, 897 .has_8255 = 0, 898 }, 899 { 900 .device_id = 0x70f2, 901 .name = "pci-6224", 902 .n_adchan = 32, 903 .adbits = 16, 904 .ai_fifo_depth = 4095, 905 .gainlkup = ai_gain_622x, 906 .ai_speed = 4000, 907 .n_aochan = 0, 908 .aobits = 0, 909 .ao_fifo_depth = 0, 910 .reg_type = ni_reg_622x, 911 .ao_unipolar = 0, 912 .num_p0_dio_channels = 32, 913 .caldac = {caldac_none}, 914 .has_8255 = 0, 915 }, 916 { 917 .device_id = 0x70f3, 918 .name = "pxi-6224", 919 .n_adchan = 32, 920 .adbits = 16, 921 .ai_fifo_depth = 4095, 922 .gainlkup = ai_gain_622x, 923 .ai_speed = 4000, 924 .n_aochan = 0, 925 .aobits = 0, 926 .ao_fifo_depth = 0, 927 .reg_type = ni_reg_622x, 928 .ao_unipolar = 0, 929 .num_p0_dio_channels = 32, 930 .caldac = {caldac_none}, 931 .has_8255 = 0, 932 }, 933 { 934 .device_id = 0x716c, 935 .name = "pci-6225", 936 .n_adchan = 80, 937 .adbits = 16, 938 .ai_fifo_depth = 4095, 939 .gainlkup = ai_gain_622x, 940 .ai_speed = 4000, 941 .n_aochan = 2, 942 .aobits = 16, 943 .ao_fifo_depth = 8191, 944 .ao_range_table = &range_ni_M_622x_ao, 945 .reg_type = ni_reg_622x, 946 .ao_unipolar = 0, 947 .ao_speed = 1200, 948 .num_p0_dio_channels = 32, 949 .caldac = {caldac_none}, 950 .has_8255 = 0, 951 }, 952 { 953 .device_id = 0x70aa, 954 .name = "pci-6229", 955 .n_adchan = 32, 956 .adbits = 16, 957 .ai_fifo_depth = 4095, 958 .gainlkup = ai_gain_622x, 959 .ai_speed = 4000, 960 .n_aochan = 4, 961 .aobits = 16, 962 .ao_fifo_depth = 8191, 963 .ao_range_table = &range_ni_M_622x_ao, 964 .reg_type = ni_reg_622x, 965 .ao_unipolar = 0, 966 .ao_speed = 1200, 967 .num_p0_dio_channels = 32, 968 .caldac = {caldac_none}, 969 .has_8255 = 0, 970 }, 971 { 972 .device_id = 0x70b4, 973 .name = "pci-6250", 974 .n_adchan = 16, 975 .adbits = 16, 976 .ai_fifo_depth = 4095, 977 .gainlkup = ai_gain_628x, 978 .ai_speed = 800, 979 .n_aochan = 0, 980 .aobits = 0, 981 .ao_fifo_depth = 0, 982 .reg_type = ni_reg_625x, 983 .ao_unipolar = 0, 984 .num_p0_dio_channels = 8, 985 .caldac = {caldac_none}, 986 .has_8255 = 0, 987 }, 988 { 989 .device_id = 0x70b8, 990 .name = "pci-6251", 991 .n_adchan = 16, 992 .adbits = 16, 993 .ai_fifo_depth = 4095, 994 .gainlkup = ai_gain_628x, 995 .ai_speed = 800, 996 .n_aochan = 2, 997 .aobits = 16, 998 .ao_fifo_depth = 8191, 999 .ao_range_table = &range_ni_M_625x_ao, 1000 .reg_type = ni_reg_625x, 1001 .ao_unipolar = 0, 1002 .ao_speed = 357, 1003 .num_p0_dio_channels = 8, 1004 .caldac = {caldac_none}, 1005 .has_8255 = 0, 1006 }, 1007 { 1008 .device_id = 0x717d, 1009 .name = "pcie-6251", 1010 .n_adchan = 16, 1011 .adbits = 16, 1012 .ai_fifo_depth = 4095, 1013 .gainlkup = ai_gain_628x, 1014 .ai_speed = 800, 1015 .n_aochan = 2, 1016 .aobits = 16, 1017 .ao_fifo_depth = 8191, 1018 .ao_range_table = &range_ni_M_625x_ao, 1019 .reg_type = ni_reg_625x, 1020 .ao_unipolar = 0, 1021 .ao_speed = 357, 1022 .num_p0_dio_channels = 8, 1023 .caldac = {caldac_none}, 1024 .has_8255 = 0, 1025 }, 1026 { 1027 .device_id = 0x70b7, 1028 .name = "pci-6254", 1029 .n_adchan = 32, 1030 .adbits = 16, 1031 .ai_fifo_depth = 4095, 1032 .gainlkup = ai_gain_628x, 1033 .ai_speed = 800, 1034 .n_aochan = 0, 1035 .aobits = 0, 1036 .ao_fifo_depth = 0, 1037 .reg_type = ni_reg_625x, 1038 .ao_unipolar = 0, 1039 .num_p0_dio_channels = 32, 1040 .caldac = {caldac_none}, 1041 .has_8255 = 0, 1042 }, 1043 { 1044 .device_id = 0x70ab, 1045 .name = "pci-6259", 1046 .n_adchan = 32, 1047 .adbits = 16, 1048 .ai_fifo_depth = 4095, 1049 .gainlkup = ai_gain_628x, 1050 .ai_speed = 800, 1051 .n_aochan = 4, 1052 .aobits = 16, 1053 .ao_fifo_depth = 8191, 1054 .ao_range_table = &range_ni_M_625x_ao, 1055 .reg_type = ni_reg_625x, 1056 .ao_unipolar = 0, 1057 .ao_speed = 357, 1058 .num_p0_dio_channels = 32, 1059 .caldac = {caldac_none}, 1060 .has_8255 = 0, 1061 }, 1062 { 1063 .device_id = 0x717f, 1064 .name = "pcie-6259", 1065 .n_adchan = 32, 1066 .adbits = 16, 1067 .ai_fifo_depth = 4095, 1068 .gainlkup = ai_gain_628x, 1069 .ai_speed = 800, 1070 .n_aochan = 4, 1071 .aobits = 16, 1072 .ao_fifo_depth = 8191, 1073 .ao_range_table = &range_ni_M_625x_ao, 1074 .reg_type = ni_reg_625x, 1075 .ao_unipolar = 0, 1076 .ao_speed = 357, 1077 .num_p0_dio_channels = 32, 1078 .caldac = {caldac_none}, 1079 .has_8255 = 0, 1080 }, 1081 { 1082 .device_id = 0x70b6, 1083 .name = "pci-6280", 1084 .n_adchan = 16, 1085 .adbits = 18, 1086 .ai_fifo_depth = 2047, 1087 .gainlkup = ai_gain_628x, 1088 .ai_speed = 1600, 1089 .n_aochan = 0, 1090 .aobits = 0, 1091 .ao_fifo_depth = 8191, 1092 .reg_type = ni_reg_628x, 1093 .ao_unipolar = 0, 1094 .num_p0_dio_channels = 8, 1095 .caldac = {caldac_none}, 1096 .has_8255 = 0, 1097 }, 1098 { 1099 .device_id = 0x70bd, 1100 .name = "pci-6281", 1101 .n_adchan = 16, 1102 .adbits = 18, 1103 .ai_fifo_depth = 2047, 1104 .gainlkup = ai_gain_628x, 1105 .ai_speed = 1600, 1106 .n_aochan = 2, 1107 .aobits = 16, 1108 .ao_fifo_depth = 8191, 1109 .ao_range_table = &range_ni_M_628x_ao, 1110 .reg_type = ni_reg_628x, 1111 .ao_unipolar = 1, 1112 .ao_speed = 357, 1113 .num_p0_dio_channels = 8, 1114 .caldac = {caldac_none}, 1115 .has_8255 = 0, 1116 }, 1117 { 1118 .device_id = 0x70bf, 1119 .name = "pxi-6281", 1120 .n_adchan = 16, 1121 .adbits = 18, 1122 .ai_fifo_depth = 2047, 1123 .gainlkup = ai_gain_628x, 1124 .ai_speed = 1600, 1125 .n_aochan = 2, 1126 .aobits = 16, 1127 .ao_fifo_depth = 8191, 1128 .ao_range_table = &range_ni_M_628x_ao, 1129 .reg_type = ni_reg_628x, 1130 .ao_unipolar = 1, 1131 .ao_speed = 357, 1132 .num_p0_dio_channels = 8, 1133 .caldac = {caldac_none}, 1134 .has_8255 = 0, 1135 }, 1136 { 1137 .device_id = 0x70bc, 1138 .name = "pci-6284", 1139 .n_adchan = 32, 1140 .adbits = 18, 1141 .ai_fifo_depth = 2047, 1142 .gainlkup = ai_gain_628x, 1143 .ai_speed = 1600, 1144 .n_aochan = 0, 1145 .aobits = 0, 1146 .ao_fifo_depth = 0, 1147 .reg_type = ni_reg_628x, 1148 .ao_unipolar = 0, 1149 .num_p0_dio_channels = 32, 1150 .caldac = {caldac_none}, 1151 .has_8255 = 0, 1152 }, 1153 { 1154 .device_id = 0x70ac, 1155 .name = "pci-6289", 1156 .n_adchan = 32, 1157 .adbits = 18, 1158 .ai_fifo_depth = 2047, 1159 .gainlkup = ai_gain_628x, 1160 .ai_speed = 1600, 1161 .n_aochan = 4, 1162 .aobits = 16, 1163 .ao_fifo_depth = 8191, 1164 .ao_range_table = &range_ni_M_628x_ao, 1165 .reg_type = ni_reg_628x, 1166 .ao_unipolar = 1, 1167 .ao_speed = 357, 1168 .num_p0_dio_channels = 32, 1169 .caldac = {caldac_none}, 1170 .has_8255 = 0, 1171 }, 1172 { 1173 .device_id = 0x70C0, 1174 .name = "pci-6143", 1175 .n_adchan = 8, 1176 .adbits = 16, 1177 .ai_fifo_depth = 1024, 1178 .alwaysdither = 0, 1179 .gainlkup = ai_gain_6143, 1180 .ai_speed = 4000, 1181 .n_aochan = 0, 1182 .aobits = 0, 1183 .reg_type = ni_reg_6143, 1184 .ao_unipolar = 0, 1185 .ao_fifo_depth = 0, 1186 .num_p0_dio_channels = 8, 1187 .caldac = {ad8804_debug, ad8804_debug}, 1188 }, 1189 { 1190 .device_id = 0x710D, 1191 .name = "pxi-6143", 1192 .n_adchan = 8, 1193 .adbits = 16, 1194 .ai_fifo_depth = 1024, 1195 .alwaysdither = 0, 1196 .gainlkup = ai_gain_6143, 1197 .ai_speed = 4000, 1198 .n_aochan = 0, 1199 .aobits = 0, 1200 .reg_type = ni_reg_6143, 1201 .ao_unipolar = 0, 1202 .ao_fifo_depth = 0, 1203 .num_p0_dio_channels = 8, 1204 .caldac = {ad8804_debug, ad8804_debug}, 1205 }, 1206}; 1207 1208#define n_pcimio_boards ((sizeof(ni_boards)/sizeof(ni_boards[0]))) 1209 1210static int pcimio_attach(struct comedi_device *dev, struct comedi_devconfig *it); 1211static int pcimio_detach(struct comedi_device *dev); 1212static struct comedi_driver driver_pcimio = { 1213 driver_name: DRV_NAME, 1214 module:THIS_MODULE, 1215 attach:pcimio_attach, 1216 detach:pcimio_detach, 1217}; 1218 1219COMEDI_PCI_INITCLEANUP(driver_pcimio, ni_pci_table) 1220 1221struct ni_private { 1222 NI_PRIVATE_COMMON 1223}; 1224#define devpriv ((struct ni_private *)dev->private) 1225 1226/* How we access registers */ 1227 1228#define ni_writel(a,b) (writel((a), devpriv->mite->daq_io_addr + (b))) 1229#define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a))) 1230#define ni_writew(a,b) (writew((a), devpriv->mite->daq_io_addr + (b))) 1231#define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a))) 1232#define ni_writeb(a,b) (writeb((a), devpriv->mite->daq_io_addr + (b))) 1233#define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a))) 1234 1235/* How we access STC registers */ 1236 1237/* We automatically take advantage of STC registers that can be 1238 * read/written directly in the I/O space of the board. Most 1239 * PCIMIO devices map the low 8 STC registers to iobase+addr*2. 1240 * The 611x devices map the write registers to iobase+addr*2, and 1241 * the read registers to iobase+(addr-1)*2. */ 1242/* However, the 611x boards still aren't working, so I'm disabling 1243 * non-windowed STC access temporarily */ 1244 1245static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg) 1246{ 1247 unsigned long flags; 1248 1249 comedi_spin_lock_irqsave(&devpriv->window_lock, flags); 1250 ni_writew(reg, Window_Address); 1251 ni_writew(data, Window_Data); 1252 comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags); 1253} 1254 1255static uint16_t e_series_win_in(struct comedi_device *dev, int reg) 1256{ 1257 unsigned long flags; 1258 uint16_t ret; 1259 1260 comedi_spin_lock_irqsave(&devpriv->window_lock, flags); 1261 ni_writew(reg, Window_Address); 1262 ret = ni_readw(Window_Data); 1263 comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags); 1264 1265 return ret; 1266} 1267 1268static void m_series_stc_writew(struct comedi_device *dev, uint16_t data, int reg) 1269{ 1270 unsigned offset; 1271 switch (reg) { 1272 case ADC_FIFO_Clear: 1273 offset = M_Offset_AI_FIFO_Clear; 1274 break; 1275 case AI_Command_1_Register: 1276 offset = M_Offset_AI_Command_1; 1277 break; 1278 case AI_Command_2_Register: 1279 offset = M_Offset_AI_Command_2; 1280 break; 1281 case AI_Mode_1_Register: 1282 offset = M_Offset_AI_Mode_1; 1283 break; 1284 case AI_Mode_2_Register: 1285 offset = M_Offset_AI_Mode_2; 1286 break; 1287 case AI_Mode_3_Register: 1288 offset = M_Offset_AI_Mode_3; 1289 break; 1290 case AI_Output_Control_Register: 1291 offset = M_Offset_AI_Output_Control; 1292 break; 1293 case AI_Personal_Register: 1294 offset = M_Offset_AI_Personal; 1295 break; 1296 case AI_SI2_Load_A_Register: 1297 /* this is actually a 32 bit register on m series boards */ 1298 ni_writel(data, M_Offset_AI_SI2_Load_A); 1299 return; 1300 break; 1301 case AI_SI2_Load_B_Register: 1302 /* this is actually a 32 bit register on m series boards */ 1303 ni_writel(data, M_Offset_AI_SI2_Load_B); 1304 return; 1305 break; 1306 case AI_START_STOP_Select_Register: 1307 offset = M_Offset_AI_START_STOP_Select; 1308 break; 1309 case AI_Trigger_Select_Register: 1310 offset = M_Offset_AI_Trigger_Select; 1311 break; 1312 case Analog_Trigger_Etc_Register: 1313 offset = M_Offset_Analog_Trigger_Etc; 1314 break; 1315 case AO_Command_1_Register: 1316 offset = M_Offset_AO_Command_1; 1317 break; 1318 case AO_Command_2_Register: 1319 offset = M_Offset_AO_Command_2; 1320 break; 1321 case AO_Mode_1_Register: 1322 offset = M_Offset_AO_Mode_1; 1323 break; 1324 case AO_Mode_2_Register: 1325 offset = M_Offset_AO_Mode_2; 1326 break; 1327 case AO_Mode_3_Register: 1328 offset = M_Offset_AO_Mode_3; 1329 break; 1330 case AO_Output_Control_Register: 1331 offset = M_Offset_AO_Output_Control; 1332 break; 1333 case AO_Personal_Register: 1334 offset = M_Offset_AO_Personal; 1335 break; 1336 case AO_Start_Select_Register: 1337 offset = M_Offset_AO_Start_Select; 1338 break; 1339 case AO_Trigger_Select_Register: 1340 offset = M_Offset_AO_Trigger_Select; 1341 break; 1342 case Clock_and_FOUT_Register: 1343 offset = M_Offset_Clock_and_FOUT; 1344 break; 1345 case Configuration_Memory_Clear: 1346 offset = M_Offset_Configuration_Memory_Clear; 1347 break; 1348 case DAC_FIFO_Clear: 1349 offset = M_Offset_AO_FIFO_Clear; 1350 break; 1351 case DIO_Control_Register: 1352 rt_printk 1353 ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n", 1354 __func__, reg); 1355 return; 1356 break; 1357 case G_Autoincrement_Register(0): 1358 offset = M_Offset_G0_Autoincrement; 1359 break; 1360 case G_Autoincrement_Register(1): 1361 offset = M_Offset_G1_Autoincrement; 1362 break; 1363 case G_Command_Register(0): 1364 offset = M_Offset_G0_Command; 1365 break; 1366 case G_Command_Register(1): 1367 offset = M_Offset_G1_Command; 1368 break; 1369 case G_Input_Select_Register(0): 1370 offset = M_Offset_G0_Input_Select; 1371 break; 1372 case G_Input_Select_Register(1): 1373 offset = M_Offset_G1_Input_Select; 1374 break; 1375 case G_Mode_Register(0): 1376 offset = M_Offset_G0_Mode; 1377 break; 1378 case G_Mode_Register(1): 1379 offset = M_Offset_G1_Mode; 1380 break; 1381 case Interrupt_A_Ack_Register: 1382 offset = M_Offset_Interrupt_A_Ack; 1383 break; 1384 case Interrupt_A_Enable_Register: 1385 offset = M_Offset_Interrupt_A_Enable; 1386 break; 1387 case Interrupt_B_Ack_Register: 1388 offset = M_Offset_Interrupt_B_Ack; 1389 break; 1390 case Interrupt_B_Enable_Register: 1391 offset = M_Offset_Interrupt_B_Enable; 1392 break; 1393 case Interrupt_Control_Register: 1394 offset = M_Offset_Interrupt_Control; 1395 break; 1396 case IO_Bidirection_Pin_Register: 1397 offset = M_Offset_IO_Bidirection_Pin; 1398 break; 1399 case Joint_Reset_Register: 1400 offset = M_Offset_Joint_Reset; 1401 break; 1402 case RTSI_Trig_A_Output_Register: 1403 offset = M_Offset_RTSI_Trig_A_Output; 1404 break; 1405 case RTSI_Trig_B_Output_Register: 1406 offset = M_Offset_RTSI_Trig_B_Output; 1407 break; 1408 case RTSI_Trig_Direction_Register: 1409 offset = M_Offset_RTSI_Trig_Direction; 1410 break; 1411 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit) 1412 and M_Offset_SCXI_Serial_Data_Out (8 bit) */ 1413 default: 1414 rt_printk("%s: bug! unhandled register=0x%x in switch.\n", 1415 __func__, reg); 1416 BUG(); 1417 return; 1418 break; 1419 } 1420 ni_writew(data, offset); 1421} 1422 1423static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg) 1424{ 1425 unsigned offset; 1426 switch (reg) { 1427 case AI_Status_1_Register: 1428 offset = M_Offset_AI_Status_1; 1429 break; 1430 case AO_Status_1_Register: 1431 offset = M_Offset_AO_Status_1; 1432 break; 1433 case AO_Status_2_Register: 1434 offset = M_Offset_AO_Status_2; 1435 break; 1436 case DIO_Serial_Input_Register: 1437 return ni_readb(M_Offset_SCXI_Serial_Data_In); 1438 break; 1439 case Joint_Status_1_Register: 1440 offset = M_Offset_Joint_Status_1; 1441 break; 1442 case Joint_Status_2_Register: 1443 offset = M_Offset_Joint_Status_2; 1444 break; 1445 case G_Status_Register: 1446 offset = M_Offset_G01_Status; 1447 break; 1448 default: 1449 rt_printk("%s: bug! unhandled register=0x%x in switch.\n", 1450 __func__, reg); 1451 BUG(); 1452 return 0; 1453 break; 1454 } 1455 return ni_readw(offset); 1456} 1457 1458static void m_series_stc_writel(struct comedi_device *dev, uint32_t data, int reg) 1459{ 1460 unsigned offset; 1461 switch (reg) { 1462 case AI_SC_Load_A_Registers: 1463 offset = M_Offset_AI_SC_Load_A; 1464 break; 1465 case AI_SI_Load_A_Registers: 1466 offset = M_Offset_AI_SI_Load_A; 1467 break; 1468 case AO_BC_Load_A_Register: 1469 offset = M_Offset_AO_BC_Load_A; 1470 break; 1471 case AO_UC_Load_A_Register: 1472 offset = M_Offset_AO_UC_Load_A; 1473 break; 1474 case AO_UI_Load_A_Register: 1475 offset = M_Offset_AO_UI_Load_A; 1476 break; 1477 case G_Load_A_Register(0): 1478 offset = M_Offset_G0_Load_A; 1479 break; 1480 case G_Load_A_Register(1): 1481 offset = M_Offset_G1_Load_A; 1482 break; 1483 case G_Load_B_Register(0): 1484 offset = M_Offset_G0_Load_B; 1485 break; 1486 case G_Load_B_Register(1): 1487 offset = M_Offset_G1_Load_B; 1488 break; 1489 default: 1490 rt_printk("%s: bug! unhandled register=0x%x in switch.\n", 1491 __func__, reg); 1492 BUG(); 1493 return; 1494 break; 1495 } 1496 ni_writel(data, offset); 1497} 1498 1499static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg) 1500{ 1501 unsigned offset; 1502 switch (reg) { 1503 case G_HW_Save_Register(0): 1504 offset = M_Offset_G0_HW_Save; 1505 break; 1506 case G_HW_Save_Register(1): 1507 offset = M_Offset_G1_HW_Save; 1508 break; 1509 case G_Save_Register(0): 1510 offset = M_Offset_G0_Save; 1511 break; 1512 case G_Save_Register(1): 1513 offset = M_Offset_G1_Save; 1514 break; 1515 default: 1516 rt_printk("%s: bug! unhandled register=0x%x in switch.\n", 1517 __func__, reg); 1518 BUG(); 1519 return 0; 1520 break; 1521 } 1522 return ni_readl(offset); 1523} 1524 1525#define interrupt_pin(a) 0 1526#define IRQ_POLARITY 1 1527 1528#define NI_E_IRQ_FLAGS IRQF_SHARED 1529 1530#include "ni_mio_common.c" 1531 1532static int pcimio_find_device(struct comedi_device *dev, int bus, int slot); 1533static int pcimio_ai_change(struct comedi_device *dev, struct comedi_subdevice *s, 1534 unsigned long new_size); 1535static int pcimio_ao_change(struct comedi_device *dev, struct comedi_subdevice *s, 1536 unsigned long new_size); 1537static int pcimio_gpct0_change(struct comedi_device *dev, struct comedi_subdevice *s, 1538 unsigned long new_size); 1539static int pcimio_gpct1_change(struct comedi_device *dev, struct comedi_subdevice *s, 1540 unsigned long new_size); 1541static int pcimio_dio_change(struct comedi_device *dev, struct comedi_subdevice *s, 1542 unsigned long new_size); 1543 1544static void m_series_init_eeprom_buffer(struct comedi_device *dev) 1545{ 1546 static const int Start_Cal_EEPROM = 0x400; 1547 static const unsigned window_size = 10; 1548 static const int serial_number_eeprom_offset = 0x4; 1549 static const int serial_number_eeprom_length = 0x4; 1550 unsigned old_iodwbsr_bits; 1551 unsigned old_iodwbsr1_bits; 1552 unsigned old_iodwcr1_bits; 1553 int i; 1554 1555 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR); 1556 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1); 1557 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1); 1558 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR); 1559 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr), 1560 devpriv->mite->mite_io_addr + MITE_IODWBSR_1); 1561 writel(0x1 | old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1); 1562 writel(0xf, devpriv->mite->mite_io_addr + 0x30); 1563 1564 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number)); 1565 for (i = 0; i < serial_number_eeprom_length; ++i) { 1566 char *byte_ptr = (char*)&devpriv->serial_number + i; 1567 *byte_ptr = ni_readb(serial_number_eeprom_offset + i); 1568 } 1569 devpriv->serial_number = be32_to_cpu(devpriv->serial_number); 1570 1571 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) { 1572 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i); 1573 } 1574 1575 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1); 1576 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR); 1577 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1); 1578 writel(0x0, devpriv->mite->mite_io_addr + 0x30); 1579} 1580 1581static void init_6143(struct comedi_device *dev) 1582{ 1583 /* Disable interrupts */ 1584 devpriv->stc_writew(dev, 0, Interrupt_Control_Register); 1585 1586 /* Initialise 6143 AI specific bits */ 1587 ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */ 1588 ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */ 1589 ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */ 1590 1591 ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143); /* Set the FIFO half full level */ 1592 1593 /* Strobe Relay disable bit */ 1594 devpriv->ai_calib_source_enabled = 0; 1595 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, 1596 Calibration_Channel_6143); 1597 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143); 1598} 1599 1600/* cleans up allocated resources */ 1601static int pcimio_detach(struct comedi_device *dev) 1602{ 1603 mio_common_detach(dev); 1604 if (dev->irq) { 1605 comedi_free_irq(dev->irq, dev); 1606 } 1607 if (dev->private) { 1608 mite_free_ring(devpriv->ai_mite_ring); 1609 mite_free_ring(devpriv->ao_mite_ring); 1610 mite_free_ring(devpriv->cdo_mite_ring); 1611 mite_free_ring(devpriv->gpct_mite_ring[0]); 1612 mite_free_ring(devpriv->gpct_mite_ring[1]); 1613 if (devpriv->mite) 1614 mite_unsetup(devpriv->mite); 1615 } 1616 1617 return 0; 1618} 1619 1620static int pcimio_attach(struct comedi_device *dev, struct comedi_devconfig *it) 1621{ 1622 int ret; 1623 1624 printk("comedi%d: ni_pcimio:", dev->minor); 1625 1626 ret = ni_alloc_private(dev); 1627 if (ret < 0) 1628 return ret; 1629 1630 ret = pcimio_find_device(dev, it->options[0], it->options[1]); 1631 if (ret < 0) 1632 return ret; 1633 1634 printk(" %s", boardtype.name); 1635 dev->board_name = boardtype.name; 1636 1637 if (boardtype.reg_type & ni_reg_m_series_mask) { 1638 devpriv->stc_writew = &m_series_stc_writew; 1639 devpriv->stc_readw = &m_series_stc_readw; 1640 devpriv->stc_writel = &m_series_stc_writel; 1641 devpriv->stc_readl = &m_series_stc_readl; 1642 } else { 1643 devpriv->stc_writew = &e_series_win_out; 1644 devpriv->stc_readw = &e_series_win_in; 1645 devpriv->stc_writel = &win_out2; 1646 devpriv->stc_readl = &win_in2; 1647 } 1648 1649 ret = mite_setup(devpriv->mite); 1650 if (ret < 0) { 1651 printk(" error setting up mite\n"); 1652 return ret; 1653 } 1654 comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev); 1655 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite); 1656 if (devpriv->ai_mite_ring == NULL) 1657 return -ENOMEM; 1658 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite); 1659 if (devpriv->ao_mite_ring == NULL) 1660 return -ENOMEM; 1661 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite); 1662 if (devpriv->cdo_mite_ring == NULL) 1663 return -ENOMEM; 1664 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite); 1665 if (devpriv->gpct_mite_ring[0] == NULL) 1666 return -ENOMEM; 1667 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite); 1668 if (devpriv->gpct_mite_ring[1] == NULL) 1669 return -ENOMEM; 1670 1671 if (boardtype.reg_type & ni_reg_m_series_mask) 1672 m_series_init_eeprom_buffer(dev); 1673 if (boardtype.reg_type == ni_reg_6143) 1674 init_6143(dev); 1675 1676 dev->irq = mite_irq(devpriv->mite); 1677 1678 if (dev->irq == 0) { 1679 printk(" unknown irq (bad)\n"); 1680 } else { 1681 printk(" ( irq = %u )", dev->irq); 1682 if ((ret = comedi_request_irq(dev->irq, ni_E_interrupt, 1683 NI_E_IRQ_FLAGS, DRV_NAME, 1684 dev)) < 0) { 1685 printk(" irq not available\n"); 1686 dev->irq = 0; 1687 } 1688 } 1689 1690 ret = ni_E_init(dev, it); 1691 if (ret < 0) 1692 return ret; 1693 1694 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change; 1695 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change; 1696 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change; 1697 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change; 1698 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change; 1699 1700 return ret; 1701} 1702 1703static int pcimio_find_device(struct comedi_device *dev, int bus, int slot) 1704{ 1705 struct mite_struct *mite; 1706 int i; 1707 1708 for (mite = mite_devices; mite; mite = mite->next) { 1709 if (mite->used) 1710 continue; 1711 if (bus || slot) { 1712 if (bus != mite->pcidev->bus->number || 1713 slot != PCI_SLOT(mite->pcidev->devfn)) 1714 continue; 1715 } 1716 1717 for (i = 0; i < n_pcimio_boards; i++) { 1718 if (mite_device_id(mite) == ni_boards[i].device_id) { 1719 dev->board_ptr = ni_boards + i; 1720 devpriv->mite = mite; 1721 1722 return 0; 1723 } 1724 } 1725 } 1726 printk("no device found\n"); 1727 mite_list_devices(); 1728 return -EIO; 1729} 1730 1731static int pcimio_ai_change(struct comedi_device *dev, struct comedi_subdevice *s, 1732 unsigned long new_size) 1733{ 1734 int ret; 1735 1736 ret = mite_buf_change(devpriv->ai_mite_ring, s->async); 1737 if (ret < 0) 1738 return ret; 1739 1740 return 0; 1741} 1742 1743static int pcimio_ao_change(struct comedi_device *dev, struct comedi_subdevice *s, 1744 unsigned long new_size) 1745{ 1746 int ret; 1747 1748 ret = mite_buf_change(devpriv->ao_mite_ring, s->async); 1749 if (ret < 0) 1750 return ret; 1751 1752 return 0; 1753} 1754 1755static int pcimio_gpct0_change(struct comedi_device *dev, struct comedi_subdevice *s, 1756 unsigned long new_size) 1757{ 1758 int ret; 1759 1760 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async); 1761 if (ret < 0) 1762 return ret; 1763 1764 return 0; 1765} 1766 1767static int pcimio_gpct1_change(struct comedi_device *dev, struct comedi_subdevice *s, 1768 unsigned long new_size) 1769{ 1770 int ret; 1771 1772 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async); 1773 if (ret < 0) 1774 return ret; 1775 1776 return 0; 1777} 1778 1779static int pcimio_dio_change(struct comedi_device *dev, struct comedi_subdevice *s, 1780 unsigned long new_size) 1781{ 1782 int ret; 1783 1784 ret = mite_buf_change(devpriv->cdo_mite_ring, s->async); 1785 if (ret < 0) 1786 return ret; 1787 1788 return 0; 1789} 1790