13d9f073994925a2c8206e41b12a8c12282972cecDan Christian/* plx9080.h 23d9f073994925a2c8206e41b12a8c12282972cecDan Christian * 33d9f073994925a2c8206e41b12a8c12282972cecDan Christian * Copyright (C) 2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net> 43d9f073994925a2c8206e41b12a8c12282972cecDan Christian * 53d9f073994925a2c8206e41b12a8c12282972cecDan Christian * I modified this file from the plx9060.h header for the 63d9f073994925a2c8206e41b12a8c12282972cecDan Christian * wanXL device driver in the linux kernel, 73d9f073994925a2c8206e41b12a8c12282972cecDan Christian * for the register offsets and bit definitions. Made minor modifications, 83d9f073994925a2c8206e41b12a8c12282972cecDan Christian * added plx9080 registers and 93d9f073994925a2c8206e41b12a8c12282972cecDan Christian * stripped out stuff that was specifically for the wanXL driver. 103d9f073994925a2c8206e41b12a8c12282972cecDan Christian * Note: I've only made sure the definitions are correct as far 113d9f073994925a2c8206e41b12a8c12282972cecDan Christian * as I make use of them. There are still various plx9060-isms 123d9f073994925a2c8206e41b12a8c12282972cecDan Christian * left in this header file. 133d9f073994925a2c8206e41b12a8c12282972cecDan Christian * 143d9f073994925a2c8206e41b12a8c12282972cecDan Christian ******************************************************************** 153d9f073994925a2c8206e41b12a8c12282972cecDan Christian * 16631dd1a885b6d7e9f6f51b4e5b311c2bb04c323cJustin P. Mattock * Copyright (C) 1999 RG Studio s.c. 173d9f073994925a2c8206e41b12a8c12282972cecDan Christian * Written by Krzysztof Halasa <khc@rgstudio.com.pl> 183d9f073994925a2c8206e41b12a8c12282972cecDan Christian * 193d9f073994925a2c8206e41b12a8c12282972cecDan Christian * Portions (C) SBE Inc., used by permission. 203d9f073994925a2c8206e41b12a8c12282972cecDan Christian * 213d9f073994925a2c8206e41b12a8c12282972cecDan Christian * This program is free software; you can redistribute it and/or 223d9f073994925a2c8206e41b12a8c12282972cecDan Christian * modify it under the terms of the GNU General Public License 233d9f073994925a2c8206e41b12a8c12282972cecDan Christian * as published by the Free Software Foundation; either version 243d9f073994925a2c8206e41b12a8c12282972cecDan Christian * 2 of the License, or (at your option) any later version. 253d9f073994925a2c8206e41b12a8c12282972cecDan Christian */ 263d9f073994925a2c8206e41b12a8c12282972cecDan Christian 273d9f073994925a2c8206e41b12a8c12282972cecDan Christian#ifndef __COMEDI_PLX9080_H 283d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define __COMEDI_PLX9080_H 293d9f073994925a2c8206e41b12a8c12282972cecDan Christian 30b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton/* descriptor block used for chained dma transfers */ 313d9f073994925a2c8206e41b12a8c12282972cecDan Christianstruct plx_dma_desc { 323d9f073994925a2c8206e41b12a8c12282972cecDan Christian volatile uint32_t pci_start_addr; 333d9f073994925a2c8206e41b12a8c12282972cecDan Christian volatile uint32_t local_start_addr; 343d9f073994925a2c8206e41b12a8c12282972cecDan Christian /* transfer_size is in bytes, only first 23 bits of register are used */ 353d9f073994925a2c8206e41b12a8c12282972cecDan Christian volatile uint32_t transfer_size; 363d9f073994925a2c8206e41b12a8c12282972cecDan Christian /* address of next descriptor (quad word aligned), plus some 373d9f073994925a2c8206e41b12a8c12282972cecDan Christian * additional bits (see PLX_DMA0_DESCRIPTOR_REG) */ 383d9f073994925a2c8206e41b12a8c12282972cecDan Christian volatile uint32_t next; 393d9f073994925a2c8206e41b12a8c12282972cecDan Christian}; 403d9f073994925a2c8206e41b12a8c12282972cecDan Christian 413d9f073994925a2c8206e41b12a8c12282972cecDan Christian/********************************************************************** 423d9f073994925a2c8206e41b12a8c12282972cecDan Christian** Register Offsets and Bit Definitions 433d9f073994925a2c8206e41b12a8c12282972cecDan Christian** 443d9f073994925a2c8206e41b12a8c12282972cecDan Christian** Note: All offsets zero relative. IE. Some standard base address 453d9f073994925a2c8206e41b12a8c12282972cecDan Christian** must be added to the Register Number to properly access the register. 463d9f073994925a2c8206e41b12a8c12282972cecDan Christian** 473d9f073994925a2c8206e41b12a8c12282972cecDan Christian**********************************************************************/ 483d9f073994925a2c8206e41b12a8c12282972cecDan Christian 493d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_LAS0RNG_REG 0x0000 /* L, Local Addr Space 0 Range Register */ 503d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_LAS1RNG_REG 0x00f0 /* L, Local Addr Space 1 Range Register */ 513d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define LRNG_IO 0x00000001 /* Map to: 1=I/O, 0=Mem */ 523d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define LRNG_ANY32 0x00000000 /* Locate anywhere in 32 bit */ 533d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define LRNG_LT1MB 0x00000002 /* Locate in 1st meg */ 543d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define LRNG_ANY64 0x00000004 /* Locate anywhere in 64 bit */ 55b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define LRNG_MEM_MASK 0xfffffff0 /* bits that specify range for memory io */ 56b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define LRNG_IO_MASK 0xfffffffa /* bits that specify range for normal io */ 573d9f073994925a2c8206e41b12a8c12282972cecDan Christian 583d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_LAS0MAP_REG 0x0004 /* L, Local Addr Space 0 Remap Register */ 593d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_LAS1MAP_REG 0x00f4 /* L, Local Addr Space 1 Remap Register */ 603d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define LMAP_EN 0x00000001 /* Enable slave decode */ 61b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define LMAP_MEM_MASK 0xfffffff0 /* bits that specify decode for memory io */ 62b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define LMAP_IO_MASK 0xfffffffa /* bits that specify decode bits for normal io */ 633d9f073994925a2c8206e41b12a8c12282972cecDan Christian 643d9f073994925a2c8206e41b12a8c12282972cecDan Christian/* Mode/Arbitration Register. 653d9f073994925a2c8206e41b12a8c12282972cecDan Christian*/ 663d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_MARB_REG 0x8 /* L, Local Arbitration Register */ 673d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_DMAARB_REG 0xac 683d9f073994925a2c8206e41b12a8c12282972cecDan Christianenum marb_bits { 693d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_LLT_MASK = 0x000000ff, /* Local Bus Latency Timer */ 703d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_LPT_MASK = 0x0000ff00, /* Local Bus Pause Timer */ 713d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_LTEN = 0x00010000, /* Latency Timer Enable */ 723d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_LPEN = 0x00020000, /* Pause Timer Enable */ 733d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_BREQ = 0x00040000, /* Local Bus BREQ Enable */ 743d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_DMA_PRIORITY_MASK = 0x00180000, 753d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_LBDS_GIVE_UP_BUS_MODE = 0x00200000, /* local bus direct slave give up bus mode */ 763d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_DS_LLOCK_ENABLE = 0x00400000, /* direct slave LLOCKo# enable */ 773d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_PCI_REQUEST_MODE = 0x00800000, 783d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_PCIv21_MODE = 0x01000000, /* pci specification v2.1 mode */ 793d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_PCI_READ_NO_WRITE_MODE = 0x02000000, 803d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_PCI_READ_WITH_WRITE_FLUSH_MODE = 0x04000000, 813d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_GATE_TIMER_WITH_BREQ = 0x08000000, /* gate local bus latency timer with BREQ */ 823d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_PCI_READ_NO_FLUSH_MODE = 0x10000000, 833d9f073994925a2c8206e41b12a8c12282972cecDan Christian MARB_USE_SUBSYSTEM_IDS = 0x20000000, 843d9f073994925a2c8206e41b12a8c12282972cecDan Christian}; 853d9f073994925a2c8206e41b12a8c12282972cecDan Christian 863d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_BIGEND_REG 0xc 873d9f073994925a2c8206e41b12a8c12282972cecDan Christianenum bigend_bits { 883d9f073994925a2c8206e41b12a8c12282972cecDan Christian BIGEND_CONFIG = 0x1, /* use big endian ordering for configuration register accesses */ 893d9f073994925a2c8206e41b12a8c12282972cecDan Christian BIGEND_DIRECT_MASTER = 0x2, 903d9f073994925a2c8206e41b12a8c12282972cecDan Christian BIGEND_DIRECT_SLAVE_LOCAL0 = 0x4, 913d9f073994925a2c8206e41b12a8c12282972cecDan Christian BIGEND_ROM = 0x8, 923d9f073994925a2c8206e41b12a8c12282972cecDan Christian BIGEND_BYTE_LANE = 0x10, /* use byte lane consisting of most significant bits instead of least significant */ 933d9f073994925a2c8206e41b12a8c12282972cecDan Christian BIGEND_DIRECT_SLAVE_LOCAL1 = 0x20, 943d9f073994925a2c8206e41b12a8c12282972cecDan Christian BIGEND_DMA1 = 0x40, 953d9f073994925a2c8206e41b12a8c12282972cecDan Christian BIGEND_DMA0 = 0x80, 963d9f073994925a2c8206e41b12a8c12282972cecDan Christian}; 973d9f073994925a2c8206e41b12a8c12282972cecDan Christian 983d9f073994925a2c8206e41b12a8c12282972cecDan Christian/* Note: The Expansion ROM stuff is only relevant to the PC environment. 993d9f073994925a2c8206e41b12a8c12282972cecDan Christian** This expansion ROM code is executed by the host CPU at boot time. 1003d9f073994925a2c8206e41b12a8c12282972cecDan Christian** For this reason no bit definitions are provided here. 1013d9f073994925a2c8206e41b12a8c12282972cecDan Christian*/ 1023d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_ROMRNG_REG 0x0010 /* L, Expn ROM Space Range Register */ 1033d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_ROMMAP_REG 0x0014 /* L, Local Addr Space Range Register */ 1043d9f073994925a2c8206e41b12a8c12282972cecDan Christian 1053d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_REGION0_REG 0x0018 /* L, Local Bus Region 0 Descriptor */ 1063d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_WIDTH 0x00000002 /* Local bus width bits */ 1073d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_8BITS 0x00000000 /* 08 bit Local Bus */ 1083d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_16BITS 0x00000001 /* 16 bit Local Bus */ 1093d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_32BITS 0x00000002 /* 32 bit Local Bus */ 1103d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_MWS 0x0000003C /* Memory Access Wait States */ 1113d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_0MWS 0x00000000 1123d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_1MWS 0x00000004 1133d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_2MWS 0x00000008 1143d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_3MWS 0x0000000C 1153d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_4MWS 0x00000010 1163d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_6MWS 0x00000018 1173d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_8MWS 0x00000020 1183d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_MRE 0x00000040 /* Memory Space Ready Input Enable */ 1193d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_MBE 0x00000080 /* Memory Space Bterm Input Enable */ 1203d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_READ_PREFETCH_DISABLE 0x00000100 1213d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_ROM_PREFETCH_DISABLE 0x00000200 1223d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_READ_PREFETCH_COUNT_ENABLE 0x00000400 1233d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_RWS 0x003C0000 /* Expn ROM Wait States */ 1243d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_RRE 0x00400000 /* ROM Space Ready Input Enable */ 1253d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_RBE 0x00800000 /* ROM Space Bterm Input Enable */ 1263d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_MBEN 0x01000000 /* Memory Space Burst Enable */ 1273d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_RBEN 0x04000000 /* ROM Space Burst Enable */ 1283d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_THROT 0x08000000 /* De-assert TRDY when FIFO full */ 1293d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define RGN_TRD 0xF0000000 /* Target Ready Delay /8 */ 1303d9f073994925a2c8206e41b12a8c12282972cecDan Christian 1313d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_REGION1_REG 0x00f8 /* L, Local Bus Region 1 Descriptor */ 1323d9f073994925a2c8206e41b12a8c12282972cecDan Christian 1333d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_DMRNG_REG 0x001C /* L, Direct Master Range Register */ 1343d9f073994925a2c8206e41b12a8c12282972cecDan Christian 1353d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_LBAPMEM_REG 0x0020 /* L, Lcl Base Addr for PCI mem space */ 1363d9f073994925a2c8206e41b12a8c12282972cecDan Christian 1373d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_LBAPIO_REG 0x0024 /* L, Lcl Base Addr for PCI I/O space */ 1383d9f073994925a2c8206e41b12a8c12282972cecDan Christian 1393d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_DMMAP_REG 0x0028 /* L, Direct Master Remap Register */ 1403d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_MAE 0x00000001 /* Direct Mstr Memory Acc Enable */ 1413d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_IAE 0x00000002 /* Direct Mstr I/O Acc Enable */ 1423d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_LCK 0x00000004 /* LOCK Input Enable */ 1433d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_PF4 0x00000008 /* Prefetch 4 Mode Enable */ 1443d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_THROT 0x00000010 /* Assert IRDY when read FIFO full */ 1453d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_PAF0 0x00000000 /* Programmable Almost fill level */ 1463d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_PAF1 0x00000020 /* Programmable Almost fill level */ 1473d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_PAF2 0x00000040 /* Programmable Almost fill level */ 1483d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_PAF3 0x00000060 /* Programmable Almost fill level */ 1493d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_PAF4 0x00000080 /* Programmable Almost fill level */ 1503d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_PAF5 0x000000A0 /* Programmable Almost fill level */ 1513d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_PAF6 0x000000C0 /* Programmable Almost fill level */ 1523d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_PAF7 0x000000D0 /* Programmable Almost fill level */ 1533d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define DMM_MAP 0xFFFF0000 /* Remap Address Bits */ 1543d9f073994925a2c8206e41b12a8c12282972cecDan Christian 1553d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_CAR_REG 0x002C /* L, Configuration Address Register */ 1563d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CAR_CT0 0x00000000 /* Config Type 0 */ 1573d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CAR_CT1 0x00000001 /* Config Type 1 */ 1583d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CAR_REG 0x000000FC /* Register Number Bits */ 1593d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CAR_FUN 0x00000700 /* Function Number Bits */ 1603d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CAR_DEV 0x0000F800 /* Device Number Bits */ 1613d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CAR_BUS 0x00FF0000 /* Bus Number Bits */ 1623d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CAR_CFG 0x80000000 /* Config Spc Access Enable */ 1633d9f073994925a2c8206e41b12a8c12282972cecDan Christian 1643d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_DBR_IN_REG 0x0060 /* L, PCI to Local Doorbell Register */ 1653d9f073994925a2c8206e41b12a8c12282972cecDan Christian 1663d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_DBR_OUT_REG 0x0064 /* L, Local to PCI Doorbell Register */ 1673d9f073994925a2c8206e41b12a8c12282972cecDan Christian 1683d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_INTRCS_REG 0x0068 /* L, Interrupt Control/Status Reg */ 1693d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_AERR 0x00000001 /* Assert LSERR on ABORT */ 1703d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_PERR 0x00000002 /* Assert LSERR on Parity Error */ 1713d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_SERR 0x00000004 /* Generate PCI SERR# */ 172b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define ICS_MBIE 0x00000008 /* mailbox interrupt enable */ 1733d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_PIE 0x00000100 /* PCI Interrupt Enable */ 1743d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_PDIE 0x00000200 /* PCI Doorbell Interrupt Enable */ 1753d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_PAIE 0x00000400 /* PCI Abort Interrupt Enable */ 1763d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_PLIE 0x00000800 /* PCI Local Int Enable */ 1773d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_RAE 0x00001000 /* Retry Abort Enable */ 1783d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_PDIA 0x00002000 /* PCI Doorbell Interrupt Active */ 1793d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_PAIA 0x00004000 /* PCI Abort Interrupt Active */ 1803d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_LIA 0x00008000 /* Local Interrupt Active */ 1813d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_LIE 0x00010000 /* Local Interrupt Enable */ 1823d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_LDIE 0x00020000 /* Local Doorbell Int Enable */ 1833d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_DMA0_E 0x00040000 /* DMA #0 Interrupt Enable */ 1843d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_DMA1_E 0x00080000 /* DMA #1 Interrupt Enable */ 1853d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_LDIA 0x00100000 /* Local Doorbell Int Active */ 1863d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_DMA0_A 0x00200000 /* DMA #0 Interrupt Active */ 1873d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_DMA1_A 0x00400000 /* DMA #1 Interrupt Active */ 1883d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_BIA 0x00800000 /* BIST Interrupt Active */ 1893d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_TA_DM 0x01000000 /* Target Abort - Direct Master */ 1903d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_TA_DMA0 0x02000000 /* Target Abort - DMA #0 */ 1913d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_TA_DMA1 0x04000000 /* Target Abort - DMA #1 */ 1923d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define ICS_TA_RA 0x08000000 /* Target Abort - Retry Timeout */ 193b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define ICS_MBIA(x) (0x10000000 << ((x) & 0x3)) /* mailbox x is active */ 1943d9f073994925a2c8206e41b12a8c12282972cecDan Christian 1953d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_CONTROL_REG 0x006C /* L, EEPROM Cntl & PCI Cmd Codes */ 1963d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_RDMA 0x0000000E /* DMA Read Command */ 1973d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_WDMA 0x00000070 /* DMA Write Command */ 1983d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_RMEM 0x00000600 /* Memory Read Command */ 1993d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_WMEM 0x00007000 /* Memory Write Command */ 2003d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_USERO 0x00010000 /* USERO output pin control bit */ 2013d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_USERI 0x00020000 /* USERI input pin bit */ 2023d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_EE_CLK 0x01000000 /* EEPROM Clock line */ 2033d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_EE_CS 0x02000000 /* EEPROM Chip Select */ 2043d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_EE_W 0x04000000 /* EEPROM Write bit */ 2053d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_EE_R 0x08000000 /* EEPROM Read bit */ 2063d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_EECHK 0x10000000 /* EEPROM Present bit */ 2073d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_EERLD 0x20000000 /* EEPROM Reload Register */ 2083d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_RESET 0x40000000 /* !! Adapter Reset !! */ 2093d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define CTL_READY 0x80000000 /* Local Init Done */ 2103d9f073994925a2c8206e41b12a8c12282972cecDan Christian 211b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_ID_REG 0x70 /* hard-coded plx vendor and device ids */ 2123d9f073994925a2c8206e41b12a8c12282972cecDan Christian 213b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_REVISION_REG 0x74 /* silicon revision */ 2143d9f073994925a2c8206e41b12a8c12282972cecDan Christian 215b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA0_MODE_REG 0x80 /* dma channel 0 mode register */ 216b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA1_MODE_REG 0x94 /* dma channel 0 mode register */ 2173d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_LOCAL_BUS_16_WIDE_BITS 0x1 2183d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_LOCAL_BUS_32_WIDE_BITS 0x3 2193d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_LOCAL_BUS_WIDTH_MASK 0x3 220b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA_EN_READYIN_BIT 0x40 /* enable ready in input */ 221b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_EN_BTERM_BIT 0x80 /* enable BTERM# input */ 222b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA_LOCAL_BURST_EN_BIT 0x100 /* enable local burst mode */ 223b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_EN_CHAIN_BIT 0x200 /* enables chaining */ 224b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_EN_DMA_DONE_INTR_BIT 0x400 /* enables interrupt on dma done */ 225b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_LOCAL_ADDR_CONST_BIT 0x800 /* hold local address constant (don't increment) */ 226b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DEMAND_MODE_BIT 0x1000 /* enables demand-mode for dma transfer */ 2273d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_EOT_ENABLE_BIT 0x4000 2283d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_STOP_MODE_BIT 0x8000 229b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA_INTR_PCI_BIT 0x20000 /* routes dma interrupt to pci bus (instead of local bus) */ 2303d9f073994925a2c8206e41b12a8c12282972cecDan Christian 231b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA0_PCI_ADDRESS_REG 0x84 /* pci address that dma transfers start at */ 2323d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_DMA1_PCI_ADDRESS_REG 0x98 2333d9f073994925a2c8206e41b12a8c12282972cecDan Christian 234b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA0_LOCAL_ADDRESS_REG 0x88 /* local address that dma transfers start at */ 2353d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_DMA1_LOCAL_ADDRESS_REG 0x9c 2363d9f073994925a2c8206e41b12a8c12282972cecDan Christian 237b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA0_TRANSFER_SIZE_REG 0x8c /* number of bytes to transfer (first 23 bits) */ 2383d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_DMA1_TRANSFER_SIZE_REG 0xa0 2393d9f073994925a2c8206e41b12a8c12282972cecDan Christian 240b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA0_DESCRIPTOR_REG 0x90 /* descriptor pointer register */ 2413d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_DMA1_DESCRIPTOR_REG 0xa4 242b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DESC_IN_PCI_BIT 0x1 /* descriptor is located in pci space (not local space) */ 243b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_END_OF_CHAIN_BIT 0x2 /* end of chain bit */ 244b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_INTR_TERM_COUNT 0x4 /* interrupt when this descriptor's transfer is finished */ 245b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_XFER_LOCAL_TO_PCI 0x8 /* transfer from local to pci bus (not pci to local) */ 2463d9f073994925a2c8206e41b12a8c12282972cecDan Christian 247b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA0_CS_REG 0xa8 /* command status register */ 2483d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_DMA1_CS_REG 0xa9 249b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA_EN_BIT 0x1 /* enable dma channel */ 250b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA_START_BIT 0x2 /* start dma transfer */ 251b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA_ABORT_BIT 0x4 /* abort dma transfer */ 252b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_CLEAR_DMA_INTR_BIT 0x8 /* clear dma interrupt */ 253b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA_DONE_BIT 0x10 /* transfer done status bit */ 2543d9f073994925a2c8206e41b12a8c12282972cecDan Christian 255b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton#define PLX_DMA0_THRESHOLD_REG 0xb0 /* command status register */ 2563d9f073994925a2c8206e41b12a8c12282972cecDan Christian 2573d9f073994925a2c8206e41b12a8c12282972cecDan Christian/* 2583d9f073994925a2c8206e41b12a8c12282972cecDan Christian * Accesses near the end of memory can cause the PLX chip 2593d9f073994925a2c8206e41b12a8c12282972cecDan Christian * to pre-fetch data off of end-of-ram. Limit the size of 2603d9f073994925a2c8206e41b12a8c12282972cecDan Christian * memory so host-side accesses cannot occur. 2613d9f073994925a2c8206e41b12a8c12282972cecDan Christian */ 2623d9f073994925a2c8206e41b12a8c12282972cecDan Christian 2633d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define PLX_PREFETCH 32 2643d9f073994925a2c8206e41b12a8c12282972cecDan Christian 2653d9f073994925a2c8206e41b12a8c12282972cecDan Christian/* 2663d9f073994925a2c8206e41b12a8c12282972cecDan Christian * The PCI Interface, via the PCI-9060 Chip, has up to eight (8) Mailbox 2673d9f073994925a2c8206e41b12a8c12282972cecDan Christian * Registers. The PUTS (Power-Up Test Suite) handles the board-side 2683d9f073994925a2c8206e41b12a8c12282972cecDan Christian * interface/interaction using the first 4 registers. Specifications for 2693d9f073994925a2c8206e41b12a8c12282972cecDan Christian * the use of the full PUTS' command and status interface is contained 2703d9f073994925a2c8206e41b12a8c12282972cecDan Christian * within a separate SBE PUTS Manual. The Host-Side Device Driver only 2713d9f073994925a2c8206e41b12a8c12282972cecDan Christian * uses a subset of the full PUTS interface. 2723d9f073994925a2c8206e41b12a8c12282972cecDan Christian */ 2733d9f073994925a2c8206e41b12a8c12282972cecDan Christian 2743d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*****************************************/ 2753d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*** MAILBOX #(-1) - MEM ACCESS STS ***/ 2763d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*****************************************/ 2773d9f073994925a2c8206e41b12a8c12282972cecDan Christian 2783d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_STS_VALID 0x57584744 /* 'WXGD' */ 2793d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_STS_DILAV 0x44475857 /* swapped = 'DGXW' */ 2803d9f073994925a2c8206e41b12a8c12282972cecDan Christian 2813d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*****************************************/ 2823d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*** MAILBOX #0 - PUTS STATUS ***/ 2833d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*****************************************/ 2843d9f073994925a2c8206e41b12a8c12282972cecDan Christian 2853d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_STS_MASK 0x000000ff /* PUTS Status Register bits */ 2863d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_STS_TMASK 0x0000000f /* register bits for TEST number */ 2873d9f073994925a2c8206e41b12a8c12282972cecDan Christian 2883d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_STS_PCIRESET 0x00000100 /* Host issued PCI reset request */ 2893d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_STS_BUSY 0x00000080 /* PUTS is in progress */ 2903d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_STS_ERROR 0x00000040 /* PUTS has failed */ 2913d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_STS_RESERVED 0x000000c0 /* Undefined -> status in transition. 2923d9f073994925a2c8206e41b12a8c12282972cecDan Christian We are in process of changing 2933d9f073994925a2c8206e41b12a8c12282972cecDan Christian bits; we SET Error bit before 2943d9f073994925a2c8206e41b12a8c12282972cecDan Christian RESET of Busy bit */ 2953d9f073994925a2c8206e41b12a8c12282972cecDan Christian 2963d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_RESERVED_5 0x00000020 /* FYI: reserved/unused bit */ 2973d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_RESERVED_4 0x00000010 /* FYI: reserved/unused bit */ 2983d9f073994925a2c8206e41b12a8c12282972cecDan Christian 2993d9f073994925a2c8206e41b12a8c12282972cecDan Christian/******************************************/ 3003d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*** MAILBOX #1 - PUTS COMMANDS ***/ 3013d9f073994925a2c8206e41b12a8c12282972cecDan Christian/******************************************/ 3023d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3033d9f073994925a2c8206e41b12a8c12282972cecDan Christian/* 3043d9f073994925a2c8206e41b12a8c12282972cecDan Christian * Any attempt to execute an unimplement command results in the PUTS 3053d9f073994925a2c8206e41b12a8c12282972cecDan Christian * interface executing a NOOP and continuing as if the offending command 3063d9f073994925a2c8206e41b12a8c12282972cecDan Christian * completed normally. Note: this supplies a simple method to interrogate 3073d9f073994925a2c8206e41b12a8c12282972cecDan Christian * mailbox command processing functionality. 3083d9f073994925a2c8206e41b12a8c12282972cecDan Christian */ 3093d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3103d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_MASK 0xffff0000 /* PUTS Command Register bits */ 3113d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3123d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_ABORTJ 0x85000000 /* abort and jump */ 3133d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_RESETP 0x86000000 /* reset and pause at start */ 3143d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_PAUSE 0x87000000 /* pause immediately */ 3153d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_PAUSEC 0x88000000 /* pause on completion */ 3163d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_RESUME 0x89000000 /* resume operation */ 3173d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_STEP 0x8a000000 /* single step tests */ 3183d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3193d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_BSWAP 0x8c000000 /* identify byte swap scheme */ 3203d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_BSWAP_0 0x8c000000 /* use scheme 0 */ 3213d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_BSWAP_1 0x8c000001 /* use scheme 1 */ 3223d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3233d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_SETHMS 0x8d000000 /* setup host memory access window 3243d9f073994925a2c8206e41b12a8c12282972cecDan Christian size */ 3253d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_SETHBA 0x8e000000 /* setup host memory access base 3263d9f073994925a2c8206e41b12a8c12282972cecDan Christian address */ 3273d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_MGO 0x8f000000 /* perform memory setup and continue 3283d9f073994925a2c8206e41b12a8c12282972cecDan Christian (IE. Done) */ 3293d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_CMD_NOOP 0xFF000000 /* dummy, illegal command */ 3303d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3313d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*****************************************/ 3323d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*** MAILBOX #2 - MEMORY SIZE ***/ 3333d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*****************************************/ 3343d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3353d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_MEMSZ_MASK 0xffff0000 /* PUTS Memory Size Register bits */ 3363d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3373d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_MEMSZ_128KB 0x00020000 /* 128 kilobyte board */ 3383d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_MEMSZ_256KB 0x00040000 /* 256 kilobyte board */ 3393d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_MEMSZ_512KB 0x00080000 /* 512 kilobyte board */ 3403d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_MEMSZ_1MB 0x00100000 /* 1 megabyte board */ 3413d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_MEMSZ_2MB 0x00200000 /* 2 megabyte board */ 3423d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_MEMSZ_4MB 0x00400000 /* 4 megabyte board */ 3433d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_MEMSZ_8MB 0x00800000 /* 8 megabyte board */ 3443d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_MEMSZ_16MB 0x01000000 /* 16 megabyte board */ 3453d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3463d9f073994925a2c8206e41b12a8c12282972cecDan Christian/***************************************/ 3473d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*** MAILBOX #2 - BOARD TYPE ***/ 3483d9f073994925a2c8206e41b12a8c12282972cecDan Christian/***************************************/ 3493d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3503d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_BTYPE_MASK 0x0000ffff /* PUTS Board Type Register */ 3513d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_BTYPE_FAMILY_MASK 0x0000ff00 /* PUTS Board Family Register */ 3523d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_BTYPE_SUBTYPE_MASK 0x000000ff /* PUTS Board Subtype */ 3533d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3543d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_BTYPE_PLX9060 0x00000100 /* PLX family type */ 3553d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_BTYPE_PLX9080 0x00000300 /* PLX wanXL100s family type */ 3563d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3573d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_BTYPE_WANXL_4 0x00000104 /* wanXL400, 4-port */ 3583d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_BTYPE_WANXL_2 0x00000102 /* wanXL200, 2-port */ 3593d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_BTYPE_WANXL_1s 0x00000301 /* wanXL100s, 1-port */ 3603d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_BTYPE_WANXL_1t 0x00000401 /* wanXL100T1, 1-port */ 3613d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3623d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*****************************************/ 3633d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*** MAILBOX #3 - SHMQ MAILBOX ***/ 3643d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*****************************************/ 3653d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3663d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_SMBX_MASK 0x000000ff /* PUTS SHMQ Mailbox bits */ 3673d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3683d9f073994925a2c8206e41b12a8c12282972cecDan Christian/***************************************/ 3693d9f073994925a2c8206e41b12a8c12282972cecDan Christian/*** GENERIC HOST-SIDE DRIVER ***/ 3703d9f073994925a2c8206e41b12a8c12282972cecDan Christian/***************************************/ 3713d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3723d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_ERR 0 3733d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_OK 1 3743d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3753d9f073994925a2c8206e41b12a8c12282972cecDan Christian/* mailbox check routine - type of testing */ 3763d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBXCHK_STS 0x00 /* check for PUTS status */ 3773d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBXCHK_NOWAIT 0x01 /* dont care about PUTS status */ 3783d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3793d9f073994925a2c8206e41b12a8c12282972cecDan Christian/* system allocates this many bytes for address mapping mailbox space */ 3803d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_ADDR_SPACE_360 0x80 /* wanXL100s/200/400 */ 3813d9f073994925a2c8206e41b12a8c12282972cecDan Christian#define MBX_ADDR_MASK_360 (MBX_ADDR_SPACE_360-1) 3823d9f073994925a2c8206e41b12a8c12282972cecDan Christian 383b74a9670857c2af74e36ecbd31bbc55ddd8e1311Greg Kroah-Hartmanstatic inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel) 3843d9f073994925a2c8206e41b12a8c12282972cecDan Christian{ 385b74a9670857c2af74e36ecbd31bbc55ddd8e1311Greg Kroah-Hartman void __iomem *dma_cs_addr; 3863d9f073994925a2c8206e41b12a8c12282972cecDan Christian uint8_t dma_status; 3873d9f073994925a2c8206e41b12a8c12282972cecDan Christian const int timeout = 10000; 3883d9f073994925a2c8206e41b12a8c12282972cecDan Christian unsigned int i; 3893d9f073994925a2c8206e41b12a8c12282972cecDan Christian 3903d9f073994925a2c8206e41b12a8c12282972cecDan Christian if (channel) 3913d9f073994925a2c8206e41b12a8c12282972cecDan Christian dma_cs_addr = iobase + PLX_DMA1_CS_REG; 3923d9f073994925a2c8206e41b12a8c12282972cecDan Christian else 3933d9f073994925a2c8206e41b12a8c12282972cecDan Christian dma_cs_addr = iobase + PLX_DMA0_CS_REG; 3943d9f073994925a2c8206e41b12a8c12282972cecDan Christian 395b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton /* abort dma transfer if necessary */ 3963d9f073994925a2c8206e41b12a8c12282972cecDan Christian dma_status = readb(dma_cs_addr); 39782675f3547ba2a0732beabd9bb4393535f74408cBill Pemberton if ((dma_status & PLX_DMA_EN_BIT) == 0) 3983d9f073994925a2c8206e41b12a8c12282972cecDan Christian return 0; 39982675f3547ba2a0732beabd9bb4393535f74408cBill Pemberton 400b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton /* wait to make sure done bit is zero */ 4013d9f073994925a2c8206e41b12a8c12282972cecDan Christian for (i = 0; (dma_status & PLX_DMA_DONE_BIT) && i < timeout; i++) { 4025f74ea14c07fee91d3bdbaad88bff6264c6200e6Greg Kroah-Hartman udelay(1); 4033d9f073994925a2c8206e41b12a8c12282972cecDan Christian dma_status = readb(dma_cs_addr); 4043d9f073994925a2c8206e41b12a8c12282972cecDan Christian } 4053d9f073994925a2c8206e41b12a8c12282972cecDan Christian if (i == timeout) { 4065f74ea14c07fee91d3bdbaad88bff6264c6200e6Greg Kroah-Hartman printk 4070a85b6f0ab0d2edb0d41b32697111ce0e4f43496Mithlesh Thukral ("plx9080: cancel() timed out waiting for dma %i done clear\n", 4080a85b6f0ab0d2edb0d41b32697111ce0e4f43496Mithlesh Thukral channel); 4093d9f073994925a2c8206e41b12a8c12282972cecDan Christian return -ETIMEDOUT; 4103d9f073994925a2c8206e41b12a8c12282972cecDan Christian } 411b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton /* disable and abort channel */ 4123d9f073994925a2c8206e41b12a8c12282972cecDan Christian writeb(PLX_DMA_ABORT_BIT, dma_cs_addr); 413b6c777571b8d387d3add91170826f32a379e4313Bill Pemberton /* wait for dma done bit */ 4143d9f073994925a2c8206e41b12a8c12282972cecDan Christian dma_status = readb(dma_cs_addr); 4153d9f073994925a2c8206e41b12a8c12282972cecDan Christian for (i = 0; (dma_status & PLX_DMA_DONE_BIT) == 0 && i < timeout; i++) { 4165f74ea14c07fee91d3bdbaad88bff6264c6200e6Greg Kroah-Hartman udelay(1); 4173d9f073994925a2c8206e41b12a8c12282972cecDan Christian dma_status = readb(dma_cs_addr); 4183d9f073994925a2c8206e41b12a8c12282972cecDan Christian } 4193d9f073994925a2c8206e41b12a8c12282972cecDan Christian if (i == timeout) { 4205f74ea14c07fee91d3bdbaad88bff6264c6200e6Greg Kroah-Hartman printk 4210a85b6f0ab0d2edb0d41b32697111ce0e4f43496Mithlesh Thukral ("plx9080: cancel() timed out waiting for dma %i done set\n", 4220a85b6f0ab0d2edb0d41b32697111ce0e4f43496Mithlesh Thukral channel); 4233d9f073994925a2c8206e41b12a8c12282972cecDan Christian return -ETIMEDOUT; 4243d9f073994925a2c8206e41b12a8c12282972cecDan Christian } 4253d9f073994925a2c8206e41b12a8c12282972cecDan Christian 4263d9f073994925a2c8206e41b12a8c12282972cecDan Christian return 0; 4273d9f073994925a2c8206e41b12a8c12282972cecDan Christian} 4283d9f073994925a2c8206e41b12a8c12282972cecDan Christian 4293d9f073994925a2c8206e41b12a8c12282972cecDan Christian#endif /* __COMEDI_PLX9080_H */ 430