s626.c revision 0a85b6f0ab0d2edb0d41b32697111ce0e4f43496
1/* 2 comedi/drivers/s626.c 3 Sensoray s626 Comedi driver 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 2000 David A. Schleef <ds@schleef.org> 7 8 Based on Sensoray Model 626 Linux driver Version 0.2 9 Copyright (C) 2002-2004 Sensoray Co., Inc. 10 11 This program is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 2 of the License, or 14 (at your option) any later version. 15 16 This program is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 GNU General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software 23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 25*/ 26 27/* 28Driver: s626 29Description: Sensoray 626 driver 30Devices: [Sensoray] 626 (s626) 31Authors: Gianluca Palli <gpalli@deis.unibo.it>, 32Updated: Fri, 15 Feb 2008 10:28:42 +0000 33Status: experimental 34 35Configuration options: 36 [0] - PCI bus of device (optional) 37 [1] - PCI slot of device (optional) 38 If bus/slot is not specified, the first supported 39 PCI device found will be used. 40 41INSN_CONFIG instructions: 42 analog input: 43 none 44 45 analog output: 46 none 47 48 digital channel: 49 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels 50 supported configuration options: 51 INSN_CONFIG_DIO_QUERY 52 COMEDI_INPUT 53 COMEDI_OUTPUT 54 55 encoder: 56 Every channel must be configured before reading. 57 58 Example code 59 60 insn.insn=INSN_CONFIG; //configuration instruction 61 insn.n=1; //number of operation (must be 1) 62 insn.data=&initialvalue; //initial value loaded into encoder 63 //during configuration 64 insn.subdev=5; //encoder subdevice 65 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel 66 //to configure 67 68 comedi_do_insn(cf,&insn); //executing configuration 69*/ 70 71#include <linux/interrupt.h> 72#include <linux/kernel.h> 73#include <linux/types.h> 74 75#include "../comedidev.h" 76 77#include "comedi_pci.h" 78 79#include "comedi_fc.h" 80#include "s626.h" 81 82MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>"); 83MODULE_DESCRIPTION("Sensoray 626 Comedi driver module"); 84MODULE_LICENSE("GPL"); 85 86struct s626_board { 87 const char *name; 88 int ai_chans; 89 int ai_bits; 90 int ao_chans; 91 int ao_bits; 92 int dio_chans; 93 int dio_banks; 94 int enc_chans; 95}; 96 97static const struct s626_board s626_boards[] = { 98 { 99 .name = "s626", 100 .ai_chans = S626_ADC_CHANNELS, 101 .ai_bits = 14, 102 .ao_chans = S626_DAC_CHANNELS, 103 .ao_bits = 13, 104 .dio_chans = S626_DIO_CHANNELS, 105 .dio_banks = S626_DIO_BANKS, 106 .enc_chans = S626_ENCODER_CHANNELS, 107 } 108}; 109 110#define thisboard ((const struct s626_board *)dev->board_ptr) 111#define PCI_VENDOR_ID_S626 0x1131 112#define PCI_DEVICE_ID_S626 0x7146 113 114/* 115 * For devices with vendor:device id == 0x1131:0x7146 you must specify 116 * also subvendor:subdevice ids, because otherwise it will conflict with 117 * Philips SAA7146 media/dvb based cards. 118 */ 119static DEFINE_PCI_DEVICE_TABLE(s626_pci_table) = { 120 {PCI_VENDOR_ID_S626, PCI_DEVICE_ID_S626, 0x6000, 0x0272, 0, 0, 0}, 121 {0} 122}; 123 124MODULE_DEVICE_TABLE(pci, s626_pci_table); 125 126static int s626_attach(struct comedi_device *dev, struct comedi_devconfig *it); 127static int s626_detach(struct comedi_device *dev); 128 129static struct comedi_driver driver_s626 = { 130 .driver_name = "s626", 131 .module = THIS_MODULE, 132 .attach = s626_attach, 133 .detach = s626_detach, 134}; 135 136struct s626_private { 137 struct pci_dev *pdev; 138 void *base_addr; 139 int got_regions; 140 short allocatedBuf; 141 uint8_t ai_cmd_running; /* ai_cmd is running */ 142 uint8_t ai_continous; /* continous aquisition */ 143 int ai_sample_count; /* number of samples to aquire */ 144 unsigned int ai_sample_timer; 145 /* time between samples in units of the timer */ 146 int ai_convert_count; /* conversion counter */ 147 unsigned int ai_convert_timer; 148 /* time between conversion in units of the timer */ 149 uint16_t CounterIntEnabs; 150 /* Counter interrupt enable mask for MISC2 register. */ 151 uint8_t AdcItems; /* Number of items in ADC poll list. */ 152 struct bufferDMA RPSBuf; /* DMA buffer used to hold ADC (RPS1) program. */ 153 struct bufferDMA ANABuf; 154 /* DMA buffer used to receive ADC data and hold DAC data. */ 155 uint32_t *pDacWBuf; 156 /* Pointer to logical adrs of DMA buffer used to hold DAC data. */ 157 uint16_t Dacpol; /* Image of DAC polarity register. */ 158 uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */ 159 uint16_t ChargeEnabled; /* Image of MISC2 Battery */ 160 /* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */ 161 uint16_t WDInterval; /* Image of MISC2 watchdog interval control bits. */ 162 uint32_t I2CAdrs; 163 /* I2C device address for onboard EEPROM (board rev dependent). */ 164 /* short I2Cards; */ 165 unsigned int ao_readback[S626_DAC_CHANNELS]; 166}; 167 168struct dio_private { 169 uint16_t RDDIn; 170 uint16_t WRDOut; 171 uint16_t RDEdgSel; 172 uint16_t WREdgSel; 173 uint16_t RDCapSel; 174 uint16_t WRCapSel; 175 uint16_t RDCapFlg; 176 uint16_t RDIntSel; 177 uint16_t WRIntSel; 178}; 179 180static struct dio_private dio_private_A = { 181 .RDDIn = LP_RDDINA, 182 .WRDOut = LP_WRDOUTA, 183 .RDEdgSel = LP_RDEDGSELA, 184 .WREdgSel = LP_WREDGSELA, 185 .RDCapSel = LP_RDCAPSELA, 186 .WRCapSel = LP_WRCAPSELA, 187 .RDCapFlg = LP_RDCAPFLGA, 188 .RDIntSel = LP_RDINTSELA, 189 .WRIntSel = LP_WRINTSELA, 190}; 191 192static struct dio_private dio_private_B = { 193 .RDDIn = LP_RDDINB, 194 .WRDOut = LP_WRDOUTB, 195 .RDEdgSel = LP_RDEDGSELB, 196 .WREdgSel = LP_WREDGSELB, 197 .RDCapSel = LP_RDCAPSELB, 198 .WRCapSel = LP_WRCAPSELB, 199 .RDCapFlg = LP_RDCAPFLGB, 200 .RDIntSel = LP_RDINTSELB, 201 .WRIntSel = LP_WRINTSELB, 202}; 203 204static struct dio_private dio_private_C = { 205 .RDDIn = LP_RDDINC, 206 .WRDOut = LP_WRDOUTC, 207 .RDEdgSel = LP_RDEDGSELC, 208 .WREdgSel = LP_WREDGSELC, 209 .RDCapSel = LP_RDCAPSELC, 210 .WRCapSel = LP_WRCAPSELC, 211 .RDCapFlg = LP_RDCAPFLGC, 212 .RDIntSel = LP_RDINTSELC, 213 .WRIntSel = LP_WRINTSELC, 214}; 215 216/* to group dio devices (48 bits mask and data are not allowed ???) 217static struct dio_private *dio_private_word[]={ 218 &dio_private_A, 219 &dio_private_B, 220 &dio_private_C, 221}; 222*/ 223 224#define devpriv ((struct s626_private *)dev->private) 225#define diopriv ((struct dio_private *)s->private) 226 227COMEDI_PCI_INITCLEANUP_NOMODULE(driver_s626, s626_pci_table); 228 229/* ioctl routines */ 230static int s626_ai_insn_config(struct comedi_device *dev, 231 struct comedi_subdevice *s, 232 struct comedi_insn *insn, unsigned int *data); 233/* static int s626_ai_rinsn(struct comedi_device *dev,struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data); */ 234static int s626_ai_insn_read(struct comedi_device *dev, 235 struct comedi_subdevice *s, 236 struct comedi_insn *insn, unsigned int *data); 237static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 238static int s626_ai_cmdtest(struct comedi_device *dev, 239 struct comedi_subdevice *s, struct comedi_cmd *cmd); 240static int s626_ai_cancel(struct comedi_device *dev, 241 struct comedi_subdevice *s); 242static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 243 struct comedi_insn *insn, unsigned int *data); 244static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 245 struct comedi_insn *insn, unsigned int *data); 246static int s626_dio_insn_bits(struct comedi_device *dev, 247 struct comedi_subdevice *s, 248 struct comedi_insn *insn, unsigned int *data); 249static int s626_dio_insn_config(struct comedi_device *dev, 250 struct comedi_subdevice *s, 251 struct comedi_insn *insn, unsigned int *data); 252static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan); 253static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int gruop, 254 unsigned int mask); 255static int s626_dio_clear_irq(struct comedi_device *dev); 256static int s626_enc_insn_config(struct comedi_device *dev, 257 struct comedi_subdevice *s, 258 struct comedi_insn *insn, unsigned int *data); 259static int s626_enc_insn_read(struct comedi_device *dev, 260 struct comedi_subdevice *s, 261 struct comedi_insn *insn, unsigned int *data); 262static int s626_enc_insn_write(struct comedi_device *dev, 263 struct comedi_subdevice *s, 264 struct comedi_insn *insn, unsigned int *data); 265static int s626_ns_to_timer(int *nanosec, int round_mode); 266static int s626_ai_load_polllist(uint8_t * ppl, struct comedi_cmd *cmd); 267static int s626_ai_inttrig(struct comedi_device *dev, 268 struct comedi_subdevice *s, unsigned int trignum); 269static irqreturn_t s626_irq_handler(int irq, void *d); 270static unsigned int s626_ai_reg_to_uint(int data); 271/* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data); */ 272 273/* end ioctl routines */ 274 275/* internal routines */ 276static void s626_dio_init(struct comedi_device *dev); 277static void ResetADC(struct comedi_device *dev, uint8_t * ppl); 278static void LoadTrimDACs(struct comedi_device *dev); 279static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan, 280 uint8_t DacData); 281static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr); 282static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val); 283static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata); 284static void SendDAC(struct comedi_device *dev, uint32_t val); 285static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage); 286static void DEBItransfer(struct comedi_device *dev); 287static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr); 288static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata); 289static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask, 290 uint16_t wdata); 291static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma, 292 size_t bsize); 293 294/* COUNTER OBJECT ------------------------------------------------ */ 295struct enc_private { 296 /* Pointers to functions that differ for A and B counters: */ 297 uint16_t(*GetEnable) (struct comedi_device * dev, struct enc_private *); /* Return clock enable. */ 298 uint16_t(*GetIntSrc) (struct comedi_device * dev, struct enc_private *); /* Return interrupt source. */ 299 uint16_t(*GetLoadTrig) (struct comedi_device * dev, struct enc_private *); /* Return preload trigger source. */ 300 uint16_t(*GetMode) (struct comedi_device * dev, struct enc_private *); /* Return standardized operating mode. */ 301 void (*PulseIndex) (struct comedi_device * dev, struct enc_private *); /* Generate soft index strobe. */ 302 void (*SetEnable) (struct comedi_device * dev, struct enc_private *, uint16_t enab); /* Program clock enable. */ 303 void (*SetIntSrc) (struct comedi_device * dev, struct enc_private *, uint16_t IntSource); /* Program interrupt source. */ 304 void (*SetLoadTrig) (struct comedi_device * dev, struct enc_private *, uint16_t Trig); /* Program preload trigger source. */ 305 void (*SetMode) (struct comedi_device * dev, struct enc_private *, uint16_t Setup, uint16_t DisableIntSrc); /* Program standardized operating mode. */ 306 void (*ResetCapFlags) (struct comedi_device * dev, struct enc_private *); /* Reset event capture flags. */ 307 308 uint16_t MyCRA; /* Address of CRA register. */ 309 uint16_t MyCRB; /* Address of CRB register. */ 310 uint16_t MyLatchLsw; /* Address of Latch least-significant-word */ 311 /* register. */ 312 uint16_t MyEventBits[4]; /* Bit translations for IntSrc -->RDMISC2. */ 313}; 314 315#define encpriv ((struct enc_private *)(dev->subdevices+5)->private) 316 317/* counters routines */ 318static void s626_timer_load(struct comedi_device *dev, struct enc_private *k, 319 int tick); 320static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k); 321static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k); 322static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k); 323static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k); 324static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k); 325static void SetMode_A(struct comedi_device *dev, struct enc_private *k, 326 uint16_t Setup, uint16_t DisableIntSrc); 327static void SetMode_B(struct comedi_device *dev, struct enc_private *k, 328 uint16_t Setup, uint16_t DisableIntSrc); 329static void SetEnable_A(struct comedi_device *dev, struct enc_private *k, 330 uint16_t enab); 331static void SetEnable_B(struct comedi_device *dev, struct enc_private *k, 332 uint16_t enab); 333static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k); 334static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k); 335static void SetLatchSource(struct comedi_device *dev, struct enc_private *k, 336 uint16_t value); 337/* static uint16_t GetLatchSource(struct comedi_device *dev, struct enc_private *k ); */ 338static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k, 339 uint16_t Trig); 340static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k, 341 uint16_t Trig); 342static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k); 343static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k); 344static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k, 345 uint16_t IntSource); 346static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k, 347 uint16_t IntSource); 348static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k); 349static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k); 350/* static void SetClkMult(struct comedi_device *dev, struct enc_private *k, uint16_t value ) ; */ 351/* static uint16_t GetClkMult(struct comedi_device *dev, struct enc_private *k ) ; */ 352/* static void SetIndexPol(struct comedi_device *dev, struct enc_private *k, uint16_t value ); */ 353/* static uint16_t GetClkPol(struct comedi_device *dev, struct enc_private *k ) ; */ 354/* static void SetIndexSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ); */ 355/* static uint16_t GetClkSrc( struct comedi_device *dev,struct enc_private *k ); */ 356/* static void SetIndexSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ); */ 357/* static uint16_t GetIndexSrc( struct comedi_device *dev,struct enc_private *k ); */ 358static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k); 359static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k); 360static void Preload(struct comedi_device *dev, struct enc_private *k, 361 uint32_t value); 362static void CountersInit(struct comedi_device *dev); 363/* end internal routines */ 364 365/* Counter objects constructor. */ 366 367/* Counter overflow/index event flag masks for RDMISC2. */ 368#define INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4))) 369#define OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10))) 370#define EVBITS(C) { 0, OVERMASK(C), INDXMASK(C), OVERMASK(C) | INDXMASK(C) } 371 372/* Translation table to map IntSrc into equivalent RDMISC2 event flag bits. */ 373/* static const uint16_t EventBits[][4] = { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) }; */ 374 375/* struct enc_private; */ 376static struct enc_private enc_private_data[] = { 377 { 378 .GetEnable = GetEnable_A, 379 .GetIntSrc = GetIntSrc_A, 380 .GetLoadTrig = GetLoadTrig_A, 381 .GetMode = GetMode_A, 382 .PulseIndex = PulseIndex_A, 383 .SetEnable = SetEnable_A, 384 .SetIntSrc = SetIntSrc_A, 385 .SetLoadTrig = SetLoadTrig_A, 386 .SetMode = SetMode_A, 387 .ResetCapFlags = ResetCapFlags_A, 388 .MyCRA = LP_CR0A, 389 .MyCRB = LP_CR0B, 390 .MyLatchLsw = LP_CNTR0ALSW, 391 .MyEventBits = EVBITS(0), 392 }, 393 { 394 .GetEnable = GetEnable_A, 395 .GetIntSrc = GetIntSrc_A, 396 .GetLoadTrig = GetLoadTrig_A, 397 .GetMode = GetMode_A, 398 .PulseIndex = PulseIndex_A, 399 .SetEnable = SetEnable_A, 400 .SetIntSrc = SetIntSrc_A, 401 .SetLoadTrig = SetLoadTrig_A, 402 .SetMode = SetMode_A, 403 .ResetCapFlags = ResetCapFlags_A, 404 .MyCRA = LP_CR1A, 405 .MyCRB = LP_CR1B, 406 .MyLatchLsw = LP_CNTR1ALSW, 407 .MyEventBits = EVBITS(1), 408 }, 409 { 410 .GetEnable = GetEnable_A, 411 .GetIntSrc = GetIntSrc_A, 412 .GetLoadTrig = GetLoadTrig_A, 413 .GetMode = GetMode_A, 414 .PulseIndex = PulseIndex_A, 415 .SetEnable = SetEnable_A, 416 .SetIntSrc = SetIntSrc_A, 417 .SetLoadTrig = SetLoadTrig_A, 418 .SetMode = SetMode_A, 419 .ResetCapFlags = ResetCapFlags_A, 420 .MyCRA = LP_CR2A, 421 .MyCRB = LP_CR2B, 422 .MyLatchLsw = LP_CNTR2ALSW, 423 .MyEventBits = EVBITS(2), 424 }, 425 { 426 .GetEnable = GetEnable_B, 427 .GetIntSrc = GetIntSrc_B, 428 .GetLoadTrig = GetLoadTrig_B, 429 .GetMode = GetMode_B, 430 .PulseIndex = PulseIndex_B, 431 .SetEnable = SetEnable_B, 432 .SetIntSrc = SetIntSrc_B, 433 .SetLoadTrig = SetLoadTrig_B, 434 .SetMode = SetMode_B, 435 .ResetCapFlags = ResetCapFlags_B, 436 .MyCRA = LP_CR0A, 437 .MyCRB = LP_CR0B, 438 .MyLatchLsw = LP_CNTR0BLSW, 439 .MyEventBits = EVBITS(3), 440 }, 441 { 442 .GetEnable = GetEnable_B, 443 .GetIntSrc = GetIntSrc_B, 444 .GetLoadTrig = GetLoadTrig_B, 445 .GetMode = GetMode_B, 446 .PulseIndex = PulseIndex_B, 447 .SetEnable = SetEnable_B, 448 .SetIntSrc = SetIntSrc_B, 449 .SetLoadTrig = SetLoadTrig_B, 450 .SetMode = SetMode_B, 451 .ResetCapFlags = ResetCapFlags_B, 452 .MyCRA = LP_CR1A, 453 .MyCRB = LP_CR1B, 454 .MyLatchLsw = LP_CNTR1BLSW, 455 .MyEventBits = EVBITS(4), 456 }, 457 { 458 .GetEnable = GetEnable_B, 459 .GetIntSrc = GetIntSrc_B, 460 .GetLoadTrig = GetLoadTrig_B, 461 .GetMode = GetMode_B, 462 .PulseIndex = PulseIndex_B, 463 .SetEnable = SetEnable_B, 464 .SetIntSrc = SetIntSrc_B, 465 .SetLoadTrig = SetLoadTrig_B, 466 .SetMode = SetMode_B, 467 .ResetCapFlags = ResetCapFlags_B, 468 .MyCRA = LP_CR2A, 469 .MyCRB = LP_CR2B, 470 .MyLatchLsw = LP_CNTR2BLSW, 471 .MyEventBits = EVBITS(5), 472 }, 473}; 474 475/* enab/disable a function or test status bit(s) that are accessed */ 476/* through Main Control Registers 1 or 2. */ 477#define MC_ENABLE(REGADRS, CTRLWORD) writel(((uint32_t)(CTRLWORD) << 16) | (uint32_t)(CTRLWORD), devpriv->base_addr+(REGADRS)) 478 479#define MC_DISABLE(REGADRS, CTRLWORD) writel((uint32_t)(CTRLWORD) << 16 , devpriv->base_addr+(REGADRS)) 480 481#define MC_TEST(REGADRS, CTRLWORD) ((readl(devpriv->base_addr+(REGADRS)) & CTRLWORD) != 0) 482 483/* #define WR7146(REGARDS,CTRLWORD) 484 writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */ 485#define WR7146(REGARDS, CTRLWORD) writel(CTRLWORD, devpriv->base_addr+(REGARDS)) 486 487/* #define RR7146(REGARDS) 488 readl((uint32_t)(devpriv->base_addr+(REGARDS))) */ 489#define RR7146(REGARDS) readl(devpriv->base_addr+(REGARDS)) 490 491#define BUGFIX_STREG(REGADRS) (REGADRS - 4) 492 493/* Write a time slot control record to TSL2. */ 494#define VECTPORT(VECTNUM) (P_TSL2 + ((VECTNUM) << 2)) 495#define SETVECT(VECTNUM, VECTVAL) WR7146(VECTPORT(VECTNUM), (VECTVAL)) 496 497/* Code macros used for constructing I2C command bytes. */ 498#define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) 499#define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) 500#define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) 501 502static const struct comedi_lrange s626_range_table = { 2, { 503 RANGE(-5, 5), 504 RANGE(-10, 10), 505 } 506}; 507 508static int s626_attach(struct comedi_device *dev, struct comedi_devconfig *it) 509{ 510/* uint8_t PollList; */ 511/* uint16_t AdcData; */ 512/* uint16_t StartVal; */ 513/* uint16_t index; */ 514/* unsigned int data[16]; */ 515 int result; 516 int i; 517 int ret; 518 resource_size_t resourceStart; 519 dma_addr_t appdma; 520 struct comedi_subdevice *s; 521 const struct pci_device_id *ids; 522 struct pci_dev *pdev = NULL; 523 524 if (alloc_private(dev, sizeof(struct s626_private)) < 0) 525 return -ENOMEM; 526 527 for (i = 0; i < (ARRAY_SIZE(s626_pci_table) - 1) && !pdev; i++) { 528 ids = &s626_pci_table[i]; 529 do { 530 pdev = pci_get_subsys(ids->vendor, ids->device, 531 ids->subvendor, ids->subdevice, 532 pdev); 533 534 if ((it->options[0] || it->options[1]) && pdev) { 535 /* matches requested bus/slot */ 536 if (pdev->bus->number == it->options[0] && 537 PCI_SLOT(pdev->devfn) == it->options[1]) 538 break; 539 } else 540 break; 541 } while (1); 542 } 543 devpriv->pdev = pdev; 544 545 if (pdev == NULL) { 546 printk("s626_attach: Board not present!!!\n"); 547 return -ENODEV; 548 } 549 550 result = comedi_pci_enable(pdev, "s626"); 551 if (result < 0) { 552 printk("s626_attach: comedi_pci_enable fails\n"); 553 return -ENODEV; 554 } 555 devpriv->got_regions = 1; 556 557 resourceStart = pci_resource_start(devpriv->pdev, 0); 558 559 devpriv->base_addr = ioremap(resourceStart, SIZEOF_ADDRESS_SPACE); 560 if (devpriv->base_addr == NULL) { 561 printk("s626_attach: IOREMAP failed\n"); 562 return -ENODEV; 563 } 564 565 if (devpriv->base_addr) { 566 /* disable master interrupt */ 567 writel(0, devpriv->base_addr + P_IER); 568 569 /* soft reset */ 570 writel(MC1_SOFT_RESET, devpriv->base_addr + P_MC1); 571 572 /* DMA FIXME DMA// */ 573 DEBUG("s626_attach: DMA ALLOCATION\n"); 574 575 /* adc buffer allocation */ 576 devpriv->allocatedBuf = 0; 577 578 devpriv->ANABuf.LogicalBase = 579 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma); 580 581 if (devpriv->ANABuf.LogicalBase == NULL) { 582 printk("s626_attach: DMA Memory mapping error\n"); 583 return -ENOMEM; 584 } 585 586 devpriv->ANABuf.PhysicalBase = appdma; 587 588 DEBUG 589 ("s626_attach: AllocDMAB ADC Logical=%p, bsize=%d, Physical=0x%x\n", 590 devpriv->ANABuf.LogicalBase, DMABUF_SIZE, 591 (uint32_t) devpriv->ANABuf.PhysicalBase); 592 593 devpriv->allocatedBuf++; 594 595 devpriv->RPSBuf.LogicalBase = 596 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma); 597 598 if (devpriv->RPSBuf.LogicalBase == NULL) { 599 printk("s626_attach: DMA Memory mapping error\n"); 600 return -ENOMEM; 601 } 602 603 devpriv->RPSBuf.PhysicalBase = appdma; 604 605 DEBUG 606 ("s626_attach: AllocDMAB RPS Logical=%p, bsize=%d, Physical=0x%x\n", 607 devpriv->RPSBuf.LogicalBase, DMABUF_SIZE, 608 (uint32_t) devpriv->RPSBuf.PhysicalBase); 609 610 devpriv->allocatedBuf++; 611 612 } 613 614 dev->board_ptr = s626_boards; 615 dev->board_name = thisboard->name; 616 617 if (alloc_subdevices(dev, 6) < 0) 618 return -ENOMEM; 619 620 dev->iobase = (unsigned long)devpriv->base_addr; 621 dev->irq = devpriv->pdev->irq; 622 623 /* set up interrupt handler */ 624 if (dev->irq == 0) { 625 printk(" unknown irq (bad)\n"); 626 } else { 627 ret = request_irq(dev->irq, s626_irq_handler, IRQF_SHARED, 628 "s626", dev); 629 630 if (ret < 0) { 631 printk(" irq not available\n"); 632 dev->irq = 0; 633 } 634 } 635 636 DEBUG("s626_attach: -- it opts %d,%d -- \n", 637 it->options[0], it->options[1]); 638 639 s = dev->subdevices + 0; 640 /* analog input subdevice */ 641 dev->read_subdev = s; 642 /* we support single-ended (ground) and differential */ 643 s->type = COMEDI_SUBD_AI; 644 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_CMD_READ; 645 s->n_chan = thisboard->ai_chans; 646 s->maxdata = (0xffff >> 2); 647 s->range_table = &s626_range_table; 648 s->len_chanlist = thisboard->ai_chans; /* This is the maximum chanlist 649 length that the board can 650 handle */ 651 s->insn_config = s626_ai_insn_config; 652 s->insn_read = s626_ai_insn_read; 653 s->do_cmd = s626_ai_cmd; 654 s->do_cmdtest = s626_ai_cmdtest; 655 s->cancel = s626_ai_cancel; 656 657 s = dev->subdevices + 1; 658 /* analog output subdevice */ 659 s->type = COMEDI_SUBD_AO; 660 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 661 s->n_chan = thisboard->ao_chans; 662 s->maxdata = (0x3fff); 663 s->range_table = &range_bipolar10; 664 s->insn_write = s626_ao_winsn; 665 s->insn_read = s626_ao_rinsn; 666 667 s = dev->subdevices + 2; 668 /* digital I/O subdevice */ 669 s->type = COMEDI_SUBD_DIO; 670 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 671 s->n_chan = S626_DIO_CHANNELS; 672 s->maxdata = 1; 673 s->io_bits = 0xffff; 674 s->private = &dio_private_A; 675 s->range_table = &range_digital; 676 s->insn_config = s626_dio_insn_config; 677 s->insn_bits = s626_dio_insn_bits; 678 679 s = dev->subdevices + 3; 680 /* digital I/O subdevice */ 681 s->type = COMEDI_SUBD_DIO; 682 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 683 s->n_chan = 16; 684 s->maxdata = 1; 685 s->io_bits = 0xffff; 686 s->private = &dio_private_B; 687 s->range_table = &range_digital; 688 s->insn_config = s626_dio_insn_config; 689 s->insn_bits = s626_dio_insn_bits; 690 691 s = dev->subdevices + 4; 692 /* digital I/O subdevice */ 693 s->type = COMEDI_SUBD_DIO; 694 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 695 s->n_chan = 16; 696 s->maxdata = 1; 697 s->io_bits = 0xffff; 698 s->private = &dio_private_C; 699 s->range_table = &range_digital; 700 s->insn_config = s626_dio_insn_config; 701 s->insn_bits = s626_dio_insn_bits; 702 703 s = dev->subdevices + 5; 704 /* encoder (counter) subdevice */ 705 s->type = COMEDI_SUBD_COUNTER; 706 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL; 707 s->n_chan = thisboard->enc_chans; 708 s->private = enc_private_data; 709 s->insn_config = s626_enc_insn_config; 710 s->insn_read = s626_enc_insn_read; 711 s->insn_write = s626_enc_insn_write; 712 s->maxdata = 0xffffff; 713 s->range_table = &range_unknown; 714 715 /* stop ai_command */ 716 devpriv->ai_cmd_running = 0; 717 718 if (devpriv->base_addr && (devpriv->allocatedBuf == 2)) { 719 dma_addr_t pPhysBuf; 720 uint16_t chan; 721 722 /* enab DEBI and audio pins, enable I2C interface. */ 723 MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C); 724 /* Configure DEBI operating mode. */ 725 WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */ 726 /* bits wide. */ 727 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT) 728 729 /* Declare DEBI */ 730 /* transfer timeout */ 731 /* interval. */ 732 |DEBI_SWAP /* Set up byte lane */ 733 /* steering. */ 734 | DEBI_CFG_INTEL); /* Intel-compatible */ 735 /* local bus (DEBI */ 736 /* never times out). */ 737 DEBUG("s626_attach: %d debi init -- %d\n", 738 DEBI_CFG_SLAVE16 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT) | 739 DEBI_SWAP | DEBI_CFG_INTEL, 740 DEBI_CFG_INTEL | DEBI_CFG_TOQ | DEBI_CFG_INCQ | 741 DEBI_CFG_16Q); 742 743 /* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */ 744 /* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */ 745 746 /* Paging is disabled. */ 747 WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */ 748 749 /* Init GPIO so that ADC Start* is negated. */ 750 WR7146(P_GPIO, GPIO_BASE | GPIO1_HI); 751 752 /* IsBoardRevA is a boolean that indicates whether the board is RevA. 753 * 754 * VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC 755 * EEPROM ADDRESS SELECTION. Initialize the I2C interface, which 756 * is used to access the onboard serial EEPROM. The EEPROM's I2C 757 * DeviceAddress is hardwired to a value that is dependent on the 758 * 626 board revision. On all board revisions, the EEPROM stores 759 * TrimDAC calibration constants for analog I/O. On RevB and 760 * higher boards, the DeviceAddress is hardwired to 0 to enable 761 * the EEPROM to also store the PCI SubVendorID and SubDeviceID; 762 * this is the address at which the SAA7146 expects a 763 * configuration EEPROM to reside. On RevA boards, the EEPROM 764 * device address, which is hardwired to 4, prevents the SAA7146 765 * from retrieving PCI sub-IDs, so the SAA7146 uses its built-in 766 * default values, instead. 767 */ 768 769 /* devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */ 770 /* DeviceType (0xA0) */ 771 /* and DeviceAddress<<1. */ 772 773 devpriv->I2CAdrs = 0xA0; /* I2C device address for onboard */ 774 /* eeprom(revb) */ 775 776 /* Issue an I2C ABORT command to halt any I2C operation in */ 777 /* progress and reset BUSY flag. */ 778 WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT); 779 /* Write I2C control: abort any I2C activity. */ 780 MC_ENABLE(P_MC2, MC2_UPLD_IIC); 781 /* Invoke command upload */ 782 while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0) ; 783 /* and wait for upload to complete. */ 784 785 /* Per SAA7146 data sheet, write to STATUS reg twice to 786 * reset all I2C error flags. */ 787 for (i = 0; i < 2; i++) { 788 WR7146(P_I2CSTAT, I2C_CLKSEL); 789 /* Write I2C control: reset error flags. */ 790 MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */ 791 while (!MC_TEST(P_MC2, MC2_UPLD_IIC)) ; 792 /* and wait for upload to complete. */ 793 } 794 795 /* Init audio interface functional attributes: set DAC/ADC 796 * serial clock rates, invert DAC serial clock so that 797 * DAC data setup times are satisfied, enable DAC serial 798 * clock out. 799 */ 800 801 WR7146(P_ACON2, ACON2_INIT); 802 803 /* Set up TSL1 slot list, which is used to control the 804 * accumulation of ADC data: RSD1 = shift data in on SD1. 805 * SIB_A1 = store data uint8_t at next available location in 806 * FB BUFFER1 register. */ 807 WR7146(P_TSL1, RSD1 | SIB_A1); 808 /* Fetch ADC high data uint8_t. */ 809 WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS); 810 /* Fetch ADC low data uint8_t; end of TSL1. */ 811 812 /* enab TSL1 slot list so that it executes all the time. */ 813 WR7146(P_ACON1, ACON1_ADCSTART); 814 815 /* Initialize RPS registers used for ADC. */ 816 817 /* Physical start of RPS program. */ 818 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase); 819 820 WR7146(P_RPSPAGE1, 0); 821 /* RPS program performs no explicit mem writes. */ 822 WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */ 823 824 /* SAA7146 BUG WORKAROUND. Initialize SAA7146 ADC interface 825 * to a known state by invoking ADCs until FB BUFFER 1 826 * register shows that it is correctly receiving ADC data. 827 * This is necessary because the SAA7146 ADC interface does 828 * not start up in a defined state after a PCI reset. 829 */ 830 831/* PollList = EOPL; // Create a simple polling */ 832/* // list for analog input */ 833/* // channel 0. */ 834/* ResetADC( dev, &PollList ); */ 835 836/* s626_ai_rinsn(dev,dev->subdevices,NULL,data); //( &AdcData ); // */ 837/* //Get initial ADC */ 838/* //value. */ 839 840/* StartVal = data[0]; */ 841 842/* // VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED EXECUTION. */ 843/* // Invoke ADCs until the new ADC value differs from the initial */ 844/* // value or a timeout occurs. The timeout protects against the */ 845/* // possibility that the driver is restarting and the ADC data is a */ 846/* // fixed value resulting from the applied ADC analog input being */ 847/* // unusually quiet or at the rail. */ 848 849/* for ( index = 0; index < 500; index++ ) */ 850/* { */ 851/* s626_ai_rinsn(dev,dev->subdevices,NULL,data); */ 852/* AdcData = data[0]; //ReadADC( &AdcData ); */ 853/* if ( AdcData != StartVal ) */ 854/* break; */ 855/* } */ 856 857 /* end initADC */ 858 859 /* init the DAC interface */ 860 861 /* Init Audio2's output DMAC attributes: burst length = 1 862 * DWORD, threshold = 1 DWORD. 863 */ 864 WR7146(P_PCI_BT_A, 0); 865 866 /* Init Audio2's output DMA physical addresses. The protection 867 * address is set to 1 DWORD past the base address so that a 868 * single DWORD will be transferred each time a DMA transfer is 869 * enabled. */ 870 871 pPhysBuf = 872 devpriv->ANABuf.PhysicalBase + 873 (DAC_WDMABUF_OS * sizeof(uint32_t)); 874 875 WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */ 876 WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */ 877 878 /* Cache Audio2's output DMA buffer logical address. This is 879 * where DAC data is buffered for A2 output DMA transfers. */ 880 devpriv->pDacWBuf = 881 (uint32_t *) devpriv->ANABuf.LogicalBase + DAC_WDMABUF_OS; 882 883 /* Audio2's output channels does not use paging. The protection 884 * violation handling bit is set so that the DMAC will 885 * automatically halt and its PCI address pointer will be reset 886 * when the protection address is reached. */ 887 888 WR7146(P_PAGEA2_OUT, 8); 889 890 /* Initialize time slot list 2 (TSL2), which is used to control 891 * the clock generation for and serialization of data to be sent 892 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL 893 * execution; this permits other slots to be safely modified 894 * without first turning off the TSL sequencer (which is 895 * apparently impossible to do). Also, SD3 (which is driven by a 896 * pull-up resistor) is shifted in and stored to the MSB of 897 * FB_BUFFER2 to be used as evidence that the slot sequence has 898 * not yet finished executing. 899 */ 900 901 SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS); 902 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */ 903 904 /* Initialize slot 1, which is constant. Slot 1 causes a 905 * DWORD to be transferred from audio channel 2's output FIFO 906 * to the FIFO's output buffer so that it can be serialized 907 * and sent to the DAC during subsequent slots. All remaining 908 * slots are dynamically populated as required by the target 909 * DAC device. 910 */ 911 SETVECT(1, LF_A2); 912 /* Slot 1: Fetch DWORD from Audio2's output FIFO. */ 913 914 /* Start DAC's audio interface (TSL2) running. */ 915 WR7146(P_ACON1, ACON1_DACSTART); 916 917 /* end init DAC interface */ 918 919 /* Init Trim DACs to calibrated values. Do it twice because the 920 * SAA7146 audio channel does not always reset properly and 921 * sometimes causes the first few TrimDAC writes to malfunction. 922 */ 923 924 LoadTrimDACs(dev); 925 LoadTrimDACs(dev); /* Insurance. */ 926 927 /* Manually init all gate array hardware in case this is a soft 928 * reset (we have no way of determining whether this is a warm 929 * or cold start). This is necessary because the gate array will 930 * reset only in response to a PCI hard reset; there is no soft 931 * reset function. */ 932 933 /* Init all DAC outputs to 0V and init all DAC setpoint and 934 * polarity images. 935 */ 936 for (chan = 0; chan < S626_DAC_CHANNELS; chan++) 937 SetDAC(dev, chan, 0); 938 939 /* Init image of WRMISC2 Battery Charger Enabled control bit. 940 * This image is used when the state of the charger control bit, 941 * which has no direct hardware readback mechanism, is queried. 942 */ 943 devpriv->ChargeEnabled = 0; 944 945 /* Init image of watchdog timer interval in WRMISC2. This image 946 * maintains the value of the control bits of MISC2 are 947 * continuously reset to zero as long as the WD timer is disabled. 948 */ 949 devpriv->WDInterval = 0; 950 951 /* Init Counter Interrupt enab mask for RDMISC2. This mask is 952 * applied against MISC2 when testing to determine which timer 953 * events are requesting interrupt service. 954 */ 955 devpriv->CounterIntEnabs = 0; 956 957 /* Init counters. */ 958 CountersInit(dev); 959 960 /* Without modifying the state of the Battery Backup enab, disable 961 * the watchdog timer, set DIO channels 0-5 to operate in the 962 * standard DIO (vs. counter overflow) mode, disable the battery 963 * charger, and reset the watchdog interval selector to zero. 964 */ 965 WriteMISC2(dev, (uint16_t) (DEBIread(dev, 966 LP_RDMISC2) & 967 MISC2_BATT_ENABLE)); 968 969 /* Initialize the digital I/O subsystem. */ 970 s626_dio_init(dev); 971 972 /* enable interrupt test */ 973 /* writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */ 974 } 975 976 DEBUG("s626_attach: comedi%d s626 attached %04x\n", dev->minor, 977 (uint32_t) devpriv->base_addr); 978 979 return 1; 980} 981 982static unsigned int s626_ai_reg_to_uint(int data) 983{ 984 unsigned int tempdata; 985 986 tempdata = (data >> 18); 987 if (tempdata & 0x2000) 988 tempdata &= 0x1fff; 989 else 990 tempdata += (1 << 13); 991 992 return tempdata; 993} 994 995/* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data){ */ 996/* return 0; */ 997/* } */ 998 999static irqreturn_t s626_irq_handler(int irq, void *d) 1000{ 1001 struct comedi_device *dev = d; 1002 struct comedi_subdevice *s; 1003 struct comedi_cmd *cmd; 1004 struct enc_private *k; 1005 unsigned long flags; 1006 int32_t *readaddr; 1007 uint32_t irqtype, irqstatus; 1008 int i = 0; 1009 short tempdata; 1010 uint8_t group; 1011 uint16_t irqbit; 1012 1013 DEBUG("s626_irq_handler: interrupt request recieved!!!\n"); 1014 1015 if (dev->attached == 0) 1016 return IRQ_NONE; 1017 /* lock to avoid race with comedi_poll */ 1018 spin_lock_irqsave(&dev->spinlock, flags); 1019 1020 /* save interrupt enable register state */ 1021 irqstatus = readl(devpriv->base_addr + P_IER); 1022 1023 /* read interrupt type */ 1024 irqtype = readl(devpriv->base_addr + P_ISR); 1025 1026 /* disable master interrupt */ 1027 writel(0, devpriv->base_addr + P_IER); 1028 1029 /* clear interrupt */ 1030 writel(irqtype, devpriv->base_addr + P_ISR); 1031 1032 /* do somethings */ 1033 DEBUG("s626_irq_handler: interrupt type %d\n", irqtype); 1034 1035 switch (irqtype) { 1036 case IRQ_RPS1: /* end_of_scan occurs */ 1037 1038 DEBUG("s626_irq_handler: RPS1 irq detected\n"); 1039 1040 /* manage ai subdevice */ 1041 s = dev->subdevices; 1042 cmd = &(s->async->cmd); 1043 1044 /* Init ptr to DMA buffer that holds new ADC data. We skip the 1045 * first uint16_t in the buffer because it contains junk data from 1046 * the final ADC of the previous poll list scan. 1047 */ 1048 readaddr = (int32_t *) devpriv->ANABuf.LogicalBase + 1; 1049 1050 /* get the data and hand it over to comedi */ 1051 for (i = 0; i < (s->async->cmd.chanlist_len); i++) { 1052 /* Convert ADC data to 16-bit integer values and copy to application */ 1053 /* buffer. */ 1054 tempdata = s626_ai_reg_to_uint((int)*readaddr); 1055 readaddr++; 1056 1057 /* put data into read buffer */ 1058 /* comedi_buf_put(s->async, tempdata); */ 1059 if (cfc_write_to_buffer(s, tempdata) == 0) 1060 printk 1061 ("s626_irq_handler: cfc_write_to_buffer error!\n"); 1062 1063 DEBUG("s626_irq_handler: ai channel %d acquired: %d\n", 1064 i, tempdata); 1065 } 1066 1067 /* end of scan occurs */ 1068 s->async->events |= COMEDI_CB_EOS; 1069 1070 if (!(devpriv->ai_continous)) 1071 devpriv->ai_sample_count--; 1072 if (devpriv->ai_sample_count <= 0) { 1073 devpriv->ai_cmd_running = 0; 1074 1075 /* Stop RPS program. */ 1076 MC_DISABLE(P_MC1, MC1_ERPS1); 1077 1078 /* send end of acquisition */ 1079 s->async->events |= COMEDI_CB_EOA; 1080 1081 /* disable master interrupt */ 1082 irqstatus = 0; 1083 } 1084 1085 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT) { 1086 DEBUG 1087 ("s626_irq_handler: enable interrupt on dio channel %d\n", 1088 cmd->scan_begin_arg); 1089 1090 s626_dio_set_irq(dev, cmd->scan_begin_arg); 1091 1092 DEBUG("s626_irq_handler: External trigger is set!!!\n"); 1093 } 1094 /* tell comedi that data is there */ 1095 DEBUG("s626_irq_handler: events %d\n", s->async->events); 1096 comedi_event(dev, s); 1097 break; 1098 case IRQ_GPIO3: /* check dio and conter interrupt */ 1099 1100 DEBUG("s626_irq_handler: GPIO3 irq detected\n"); 1101 1102 /* manage ai subdevice */ 1103 s = dev->subdevices; 1104 cmd = &(s->async->cmd); 1105 1106 /* s626_dio_clear_irq(dev); */ 1107 1108 for (group = 0; group < S626_DIO_BANKS; group++) { 1109 irqbit = 0; 1110 /* read interrupt type */ 1111 irqbit = DEBIread(dev, 1112 ((struct dio_private *)(dev-> 1113 subdevices + 1114 2 + 1115 group)-> 1116 private)->RDCapFlg); 1117 1118 /* check if interrupt is generated from dio channels */ 1119 if (irqbit) { 1120 s626_dio_reset_irq(dev, group, irqbit); 1121 DEBUG 1122 ("s626_irq_handler: check interrupt on dio group %d %d\n", 1123 group, i); 1124 if (devpriv->ai_cmd_running) { 1125 /* check if interrupt is an ai acquisition start trigger */ 1126 if ((irqbit >> (cmd->start_arg - 1127 (16 * group))) 1128 == 1 && cmd->start_src == TRIG_EXT) { 1129 DEBUG 1130 ("s626_irq_handler: Edge capture interrupt recieved from channel %d\n", 1131 cmd->start_arg); 1132 1133 /* Start executing the RPS program. */ 1134 MC_ENABLE(P_MC1, MC1_ERPS1); 1135 1136 DEBUG 1137 ("s626_irq_handler: aquisition start triggered!!!\n"); 1138 1139 if (cmd->scan_begin_src == 1140 TRIG_EXT) { 1141 DEBUG 1142 ("s626_ai_cmd: enable interrupt on dio channel %d\n", 1143 cmd-> 1144 scan_begin_arg); 1145 1146 s626_dio_set_irq(dev, 1147 cmd->scan_begin_arg); 1148 1149 DEBUG 1150 ("s626_irq_handler: External scan trigger is set!!!\n"); 1151 } 1152 } 1153 if ((irqbit >> (cmd->scan_begin_arg - 1154 (16 * group))) 1155 == 1 1156 && cmd->scan_begin_src == 1157 TRIG_EXT) { 1158 DEBUG 1159 ("s626_irq_handler: Edge capture interrupt recieved from channel %d\n", 1160 cmd->scan_begin_arg); 1161 1162 /* Trigger ADC scan loop start by setting RPS Signal 0. */ 1163 MC_ENABLE(P_MC2, MC2_ADC_RPS); 1164 1165 DEBUG 1166 ("s626_irq_handler: scan triggered!!! %d\n", 1167 devpriv->ai_sample_count); 1168 if (cmd->convert_src == 1169 TRIG_EXT) { 1170 1171 DEBUG 1172 ("s626_ai_cmd: enable interrupt on dio channel %d group %d\n", 1173 cmd->convert_arg - 1174 (16 * group), 1175 group); 1176 1177 devpriv->ai_convert_count 1178 = cmd->chanlist_len; 1179 1180 s626_dio_set_irq(dev, 1181 cmd->convert_arg); 1182 1183 DEBUG 1184 ("s626_irq_handler: External convert trigger is set!!!\n"); 1185 } 1186 1187 if (cmd->convert_src == 1188 TRIG_TIMER) { 1189 k = &encpriv[5]; 1190 devpriv->ai_convert_count 1191 = cmd->chanlist_len; 1192 k->SetEnable(dev, k, 1193 CLKENAB_ALWAYS); 1194 } 1195 } 1196 if ((irqbit >> (cmd->convert_arg - 1197 (16 * group))) 1198 == 1 1199 && cmd->convert_src == TRIG_EXT) { 1200 DEBUG 1201 ("s626_irq_handler: Edge capture interrupt recieved from channel %d\n", 1202 cmd->convert_arg); 1203 1204 /* Trigger ADC scan loop start by setting RPS Signal 0. */ 1205 MC_ENABLE(P_MC2, MC2_ADC_RPS); 1206 1207 DEBUG 1208 ("s626_irq_handler: adc convert triggered!!!\n"); 1209 1210 devpriv->ai_convert_count--; 1211 1212 if (devpriv->ai_convert_count > 1213 0) { 1214 1215 DEBUG 1216 ("s626_ai_cmd: enable interrupt on dio channel %d group %d\n", 1217 cmd->convert_arg - 1218 (16 * group), 1219 group); 1220 1221 s626_dio_set_irq(dev, 1222 cmd->convert_arg); 1223 1224 DEBUG 1225 ("s626_irq_handler: External trigger is set!!!\n"); 1226 } 1227 } 1228 } 1229 break; 1230 } 1231 } 1232 1233 /* read interrupt type */ 1234 irqbit = DEBIread(dev, LP_RDMISC2); 1235 1236 /* check interrupt on counters */ 1237 DEBUG("s626_irq_handler: check counters interrupt %d\n", 1238 irqbit); 1239 1240 if (irqbit & IRQ_COINT1A) { 1241 DEBUG 1242 ("s626_irq_handler: interrupt on counter 1A overflow\n"); 1243 k = &encpriv[0]; 1244 1245 /* clear interrupt capture flag */ 1246 k->ResetCapFlags(dev, k); 1247 } 1248 if (irqbit & IRQ_COINT2A) { 1249 DEBUG 1250 ("s626_irq_handler: interrupt on counter 2A overflow\n"); 1251 k = &encpriv[1]; 1252 1253 /* clear interrupt capture flag */ 1254 k->ResetCapFlags(dev, k); 1255 } 1256 if (irqbit & IRQ_COINT3A) { 1257 DEBUG 1258 ("s626_irq_handler: interrupt on counter 3A overflow\n"); 1259 k = &encpriv[2]; 1260 1261 /* clear interrupt capture flag */ 1262 k->ResetCapFlags(dev, k); 1263 } 1264 if (irqbit & IRQ_COINT1B) { 1265 DEBUG 1266 ("s626_irq_handler: interrupt on counter 1B overflow\n"); 1267 k = &encpriv[3]; 1268 1269 /* clear interrupt capture flag */ 1270 k->ResetCapFlags(dev, k); 1271 } 1272 if (irqbit & IRQ_COINT2B) { 1273 DEBUG 1274 ("s626_irq_handler: interrupt on counter 2B overflow\n"); 1275 k = &encpriv[4]; 1276 1277 /* clear interrupt capture flag */ 1278 k->ResetCapFlags(dev, k); 1279 1280 if (devpriv->ai_convert_count > 0) { 1281 devpriv->ai_convert_count--; 1282 if (devpriv->ai_convert_count == 0) 1283 k->SetEnable(dev, k, CLKENAB_INDEX); 1284 1285 if (cmd->convert_src == TRIG_TIMER) { 1286 DEBUG 1287 ("s626_irq_handler: conver timer trigger!!! %d\n", 1288 devpriv->ai_convert_count); 1289 1290 /* Trigger ADC scan loop start by setting RPS Signal 0. */ 1291 MC_ENABLE(P_MC2, MC2_ADC_RPS); 1292 } 1293 } 1294 } 1295 if (irqbit & IRQ_COINT3B) { 1296 DEBUG 1297 ("s626_irq_handler: interrupt on counter 3B overflow\n"); 1298 k = &encpriv[5]; 1299 1300 /* clear interrupt capture flag */ 1301 k->ResetCapFlags(dev, k); 1302 1303 if (cmd->scan_begin_src == TRIG_TIMER) { 1304 DEBUG 1305 ("s626_irq_handler: scan timer trigger!!!\n"); 1306 1307 /* Trigger ADC scan loop start by setting RPS Signal 0. */ 1308 MC_ENABLE(P_MC2, MC2_ADC_RPS); 1309 } 1310 1311 if (cmd->convert_src == TRIG_TIMER) { 1312 DEBUG 1313 ("s626_irq_handler: convert timer trigger is set\n"); 1314 k = &encpriv[4]; 1315 devpriv->ai_convert_count = cmd->chanlist_len; 1316 k->SetEnable(dev, k, CLKENAB_ALWAYS); 1317 } 1318 } 1319 } 1320 1321 /* enable interrupt */ 1322 writel(irqstatus, devpriv->base_addr + P_IER); 1323 1324 DEBUG("s626_irq_handler: exit interrupt service routine.\n"); 1325 1326 spin_unlock_irqrestore(&dev->spinlock, flags); 1327 return IRQ_HANDLED; 1328} 1329 1330static int s626_detach(struct comedi_device *dev) 1331{ 1332 if (devpriv) { 1333 /* stop ai_command */ 1334 devpriv->ai_cmd_running = 0; 1335 1336 if (devpriv->base_addr) { 1337 /* interrupt mask */ 1338 WR7146(P_IER, 0); /* Disable master interrupt. */ 1339 WR7146(P_ISR, IRQ_GPIO3 | IRQ_RPS1); /* Clear board's IRQ status flag. */ 1340 1341 /* Disable the watchdog timer and battery charger. */ 1342 WriteMISC2(dev, 0); 1343 1344 /* Close all interfaces on 7146 device. */ 1345 WR7146(P_MC1, MC1_SHUTDOWN); 1346 WR7146(P_ACON1, ACON1_BASE); 1347 1348 CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE); 1349 CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE); 1350 } 1351 1352 if (dev->irq) 1353 free_irq(dev->irq, dev); 1354 1355 if (devpriv->base_addr) 1356 iounmap(devpriv->base_addr); 1357 1358 if (devpriv->pdev) { 1359 if (devpriv->got_regions) 1360 comedi_pci_disable(devpriv->pdev); 1361 pci_dev_put(devpriv->pdev); 1362 } 1363 } 1364 1365 DEBUG("s626_detach: S626 detached!\n"); 1366 1367 return 0; 1368} 1369 1370/* 1371 * this functions build the RPS program for hardware driven acquistion 1372 */ 1373void ResetADC(struct comedi_device *dev, uint8_t * ppl) 1374{ 1375 register uint32_t *pRPS; 1376 uint32_t JmpAdrs; 1377 uint16_t i; 1378 uint16_t n; 1379 uint32_t LocalPPL; 1380 struct comedi_cmd *cmd = &(dev->subdevices->async->cmd); 1381 1382 /* Stop RPS program in case it is currently running. */ 1383 MC_DISABLE(P_MC1, MC1_ERPS1); 1384 1385 /* Set starting logical address to write RPS commands. */ 1386 pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase; 1387 1388 /* Initialize RPS instruction pointer. */ 1389 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase); 1390 1391 /* Construct RPS program in RPSBuf DMA buffer */ 1392 1393 if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) { 1394 DEBUG("ResetADC: scan_begin pause inserted\n"); 1395 /* Wait for Start trigger. */ 1396 *pRPS++ = RPS_PAUSE | RPS_SIGADC; 1397 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC; 1398 } 1399 1400 /* SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary 1401 * because the first RPS DEBI Write following a non-RPS DEBI write 1402 * seems to always fail. If we don't do this dummy write, the ADC 1403 * gain might not be set to the value required for the first slot in 1404 * the poll list; the ADC gain would instead remain unchanged from 1405 * the previously programmed value. 1406 */ 1407 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2); 1408 /* Write DEBI Write command and address to shadow RAM. */ 1409 1410 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL; 1411 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2); 1412 /* Write DEBI immediate data to shadow RAM: */ 1413 1414 *pRPS++ = GSEL_BIPOLAR5V; 1415 /* arbitrary immediate data value. */ 1416 1417 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI; 1418 /* Reset "shadow RAM uploaded" flag. */ 1419 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */ 1420 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */ 1421 1422 /* Digitize all slots in the poll list. This is implemented as a 1423 * for loop to limit the slot count to 16 in case the application 1424 * forgot to set the EOPL flag in the final slot. 1425 */ 1426 for (devpriv->AdcItems = 0; devpriv->AdcItems < 16; devpriv->AdcItems++) { 1427 /* Convert application's poll list item to private board class 1428 * format. Each app poll list item is an uint8_t with form 1429 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 = 1430 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker. 1431 */ 1432 LocalPPL = 1433 (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V : 1434 GSEL_BIPOLAR10V); 1435 1436 /* Switch ADC analog gain. */ 1437 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2); /* Write DEBI command */ 1438 /* and address to */ 1439 /* shadow RAM. */ 1440 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL; 1441 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2); /* Write DEBI */ 1442 /* immediate data to */ 1443 /* shadow RAM. */ 1444 *pRPS++ = LocalPPL; 1445 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI; /* Reset "shadow RAM uploaded" */ 1446 /* flag. */ 1447 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */ 1448 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to */ 1449 /* finish. */ 1450 1451 /* Select ADC analog input channel. */ 1452 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2); 1453 /* Write DEBI command and address to shadow RAM. */ 1454 *pRPS++ = DEBI_CMD_WRWORD | LP_ISEL; 1455 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2); 1456 /* Write DEBI immediate data to shadow RAM. */ 1457 *pRPS++ = LocalPPL; 1458 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI; 1459 /* Reset "shadow RAM uploaded" flag. */ 1460 1461 *pRPS++ = RPS_UPLOAD | RPS_DEBI; 1462 /* Invoke shadow RAM upload. */ 1463 1464 *pRPS++ = RPS_PAUSE | RPS_DEBI; 1465 /* Wait for shadow upload to finish. */ 1466 1467 /* Delay at least 10 microseconds for analog input settling. 1468 * Instead of padding with NOPs, we use RPS_JUMP instructions 1469 * here; this allows us to produce a longer delay than is 1470 * possible with NOPs because each RPS_JUMP flushes the RPS' 1471 * instruction prefetch pipeline. 1472 */ 1473 JmpAdrs = 1474 (uint32_t) devpriv->RPSBuf.PhysicalBase + 1475 (uint32_t) ((unsigned long)pRPS - 1476 (unsigned long)devpriv->RPSBuf.LogicalBase); 1477 for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) { 1478 JmpAdrs += 8; /* Repeat to implement time delay: */ 1479 *pRPS++ = RPS_JUMP; /* Jump to next RPS instruction. */ 1480 *pRPS++ = JmpAdrs; 1481 } 1482 1483 if (cmd != NULL && cmd->convert_src != TRIG_NOW) { 1484 DEBUG("ResetADC: convert pause inserted\n"); 1485 /* Wait for Start trigger. */ 1486 *pRPS++ = RPS_PAUSE | RPS_SIGADC; 1487 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC; 1488 } 1489 /* Start ADC by pulsing GPIO1. */ 1490 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */ 1491 *pRPS++ = GPIO_BASE | GPIO1_LO; 1492 *pRPS++ = RPS_NOP; 1493 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ 1494 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */ 1495 *pRPS++ = GPIO_BASE | GPIO1_HI; 1496 1497 /* Wait for ADC to complete (GPIO2 is asserted high when ADC not 1498 * busy) and for data from previous conversion to shift into FB 1499 * BUFFER 1 register. 1500 */ 1501 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */ 1502 1503 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */ 1504 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2); 1505 *pRPS++ = 1506 (uint32_t) devpriv->ANABuf.PhysicalBase + 1507 (devpriv->AdcItems << 2); 1508 1509 /* If this slot's EndOfPollList flag is set, all channels have */ 1510 /* now been processed. */ 1511 if (*ppl++ & EOPL) { 1512 devpriv->AdcItems++; /* Adjust poll list item count. */ 1513 break; /* Exit poll list processing loop. */ 1514 } 1515 } 1516 DEBUG("ResetADC: ADC items %d \n", devpriv->AdcItems); 1517 1518 /* VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the 1519 * ADC to stabilize for 2 microseconds before starting the final 1520 * (dummy) conversion. This delay is necessary to allow sufficient 1521 * time between last conversion finished and the start of the dummy 1522 * conversion. Without this delay, the last conversion's data value 1523 * is sometimes set to the previous conversion's data value. 1524 */ 1525 for (n = 0; n < (2 * RPSCLK_PER_US); n++) 1526 *pRPS++ = RPS_NOP; 1527 1528 /* Start a dummy conversion to cause the data from the last 1529 * conversion of interest to be shifted in. 1530 */ 1531 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */ 1532 *pRPS++ = GPIO_BASE | GPIO1_LO; 1533 *pRPS++ = RPS_NOP; 1534 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ 1535 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */ 1536 *pRPS++ = GPIO_BASE | GPIO1_HI; 1537 1538 /* Wait for the data from the last conversion of interest to arrive 1539 * in FB BUFFER 1 register. 1540 */ 1541 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */ 1542 1543 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */ 1544 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2); /* */ 1545 *pRPS++ = 1546 (uint32_t) devpriv->ANABuf.PhysicalBase + (devpriv->AdcItems << 2); 1547 1548 /* Indicate ADC scan loop is finished. */ 1549 /* *pRPS++= RPS_CLRSIGNAL | RPS_SIGADC ; // Signal ReadADC() that scan is done. */ 1550 1551 /* invoke interrupt */ 1552 if (devpriv->ai_cmd_running == 1) { 1553 DEBUG("ResetADC: insert irq in ADC RPS task\n"); 1554 *pRPS++ = RPS_IRQ; 1555 } 1556 /* Restart RPS program at its beginning. */ 1557 *pRPS++ = RPS_JUMP; /* Branch to start of RPS program. */ 1558 *pRPS++ = (uint32_t) devpriv->RPSBuf.PhysicalBase; 1559 1560 /* End of RPS program build */ 1561} 1562 1563/* TO COMPLETE, IF NECESSARY */ 1564static int s626_ai_insn_config(struct comedi_device *dev, 1565 struct comedi_subdevice *s, 1566 struct comedi_insn *insn, unsigned int *data) 1567{ 1568 1569 return -EINVAL; 1570} 1571 1572/* static int s626_ai_rinsn(struct comedi_device *dev,struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data) */ 1573/* { */ 1574/* register uint8_t i; */ 1575/* register int32_t *readaddr; */ 1576 1577/* DEBUG("as626_ai_rinsn: ai_rinsn enter \n"); */ 1578 1579/* Trigger ADC scan loop start by setting RPS Signal 0. */ 1580/* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */ 1581 1582/* Wait until ADC scan loop is finished (RPS Signal 0 reset). */ 1583/* while ( MC_TEST( P_MC2, MC2_ADC_RPS ) ); */ 1584 1585/* Init ptr to DMA buffer that holds new ADC data. We skip the 1586 * first uint16_t in the buffer because it contains junk data from 1587 * the final ADC of the previous poll list scan. 1588 */ 1589/* readaddr = (uint32_t *)devpriv->ANABuf.LogicalBase + 1; */ 1590 1591/* Convert ADC data to 16-bit integer values and copy to application buffer. */ 1592/* for ( i = 0; i < devpriv->AdcItems; i++ ) { */ 1593/* *data = s626_ai_reg_to_uint( *readaddr++ ); */ 1594/* DEBUG("s626_ai_rinsn: data %d \n",*data); */ 1595/* data++; */ 1596/* } */ 1597 1598/* DEBUG("s626_ai_rinsn: ai_rinsn escape \n"); */ 1599/* return i; */ 1600/* } */ 1601 1602static int s626_ai_insn_read(struct comedi_device *dev, 1603 struct comedi_subdevice *s, 1604 struct comedi_insn *insn, unsigned int *data) 1605{ 1606 uint16_t chan = CR_CHAN(insn->chanspec); 1607 uint16_t range = CR_RANGE(insn->chanspec); 1608 uint16_t AdcSpec = 0; 1609 uint32_t GpioImage; 1610 int n; 1611 1612 /* interrupt call test */ 1613/* writel(IRQ_GPIO3,devpriv->base_addr+P_PSR); */ 1614 /* Writing a logical 1 into any of the RPS_PSR bits causes the 1615 * corresponding interrupt to be generated if enabled 1616 */ 1617 1618 DEBUG("s626_ai_insn_read: entering\n"); 1619 1620 /* Convert application's ADC specification into form 1621 * appropriate for register programming. 1622 */ 1623 if (range == 0) 1624 AdcSpec = (chan << 8) | (GSEL_BIPOLAR5V); 1625 else 1626 AdcSpec = (chan << 8) | (GSEL_BIPOLAR10V); 1627 1628 /* Switch ADC analog gain. */ 1629 DEBIwrite(dev, LP_GSEL, AdcSpec); /* Set gain. */ 1630 1631 /* Select ADC analog input channel. */ 1632 DEBIwrite(dev, LP_ISEL, AdcSpec); /* Select channel. */ 1633 1634 for (n = 0; n < insn->n; n++) { 1635 1636 /* Delay 10 microseconds for analog input settling. */ 1637 udelay(10); 1638 1639 /* Start ADC by pulsing GPIO1 low. */ 1640 GpioImage = RR7146(P_GPIO); 1641 /* Assert ADC Start command */ 1642 WR7146(P_GPIO, GpioImage & ~GPIO1_HI); 1643 /* and stretch it out. */ 1644 WR7146(P_GPIO, GpioImage & ~GPIO1_HI); 1645 WR7146(P_GPIO, GpioImage & ~GPIO1_HI); 1646 /* Negate ADC Start command. */ 1647 WR7146(P_GPIO, GpioImage | GPIO1_HI); 1648 1649 /* Wait for ADC to complete (GPIO2 is asserted high when */ 1650 /* ADC not busy) and for data from previous conversion to */ 1651 /* shift into FB BUFFER 1 register. */ 1652 1653 /* Wait for ADC done. */ 1654 while (!(RR7146(P_PSR) & PSR_GPIO2)) ; 1655 1656 /* Fetch ADC data. */ 1657 if (n != 0) 1658 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1)); 1659 1660 /* Allow the ADC to stabilize for 4 microseconds before 1661 * starting the next (final) conversion. This delay is 1662 * necessary to allow sufficient time between last 1663 * conversion finished and the start of the next 1664 * conversion. Without this delay, the last conversion's 1665 * data value is sometimes set to the previous 1666 * conversion's data value. 1667 */ 1668 udelay(4); 1669 } 1670 1671 /* Start a dummy conversion to cause the data from the 1672 * previous conversion to be shifted in. */ 1673 GpioImage = RR7146(P_GPIO); 1674 1675 /* Assert ADC Start command */ 1676 WR7146(P_GPIO, GpioImage & ~GPIO1_HI); 1677 /* and stretch it out. */ 1678 WR7146(P_GPIO, GpioImage & ~GPIO1_HI); 1679 WR7146(P_GPIO, GpioImage & ~GPIO1_HI); 1680 /* Negate ADC Start command. */ 1681 WR7146(P_GPIO, GpioImage | GPIO1_HI); 1682 1683 /* Wait for the data to arrive in FB BUFFER 1 register. */ 1684 1685 /* Wait for ADC done. */ 1686 while (!(RR7146(P_PSR) & PSR_GPIO2)) ; 1687 1688 /* Fetch ADC data from audio interface's input shift register. */ 1689 1690 /* Fetch ADC data. */ 1691 if (n != 0) 1692 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1)); 1693 1694 DEBUG("s626_ai_insn_read: samples %d, data %d\n", n, data[n - 1]); 1695 1696 return n; 1697} 1698 1699static int s626_ai_load_polllist(uint8_t * ppl, struct comedi_cmd *cmd) 1700{ 1701 1702 int n; 1703 1704 for (n = 0; n < cmd->chanlist_len; n++) { 1705 if (CR_RANGE((cmd->chanlist)[n]) == 0) 1706 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_5V); 1707 else 1708 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_10V); 1709 } 1710 ppl[n - 1] |= EOPL; 1711 1712 return n; 1713} 1714 1715static int s626_ai_inttrig(struct comedi_device *dev, 1716 struct comedi_subdevice *s, unsigned int trignum) 1717{ 1718 if (trignum != 0) 1719 return -EINVAL; 1720 1721 DEBUG("s626_ai_inttrig: trigger adc start..."); 1722 1723 /* Start executing the RPS program. */ 1724 MC_ENABLE(P_MC1, MC1_ERPS1); 1725 1726 s->async->inttrig = NULL; 1727 1728 DEBUG(" done\n"); 1729 1730 return 1; 1731} 1732 1733/* TO COMPLETE */ 1734static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 1735{ 1736 1737 uint8_t ppl[16]; 1738 struct comedi_cmd *cmd = &s->async->cmd; 1739 struct enc_private *k; 1740 int tick; 1741 1742 DEBUG("s626_ai_cmd: entering command function\n"); 1743 1744 if (devpriv->ai_cmd_running) { 1745 printk("s626_ai_cmd: Another ai_cmd is running %d\n", 1746 dev->minor); 1747 return -EBUSY; 1748 } 1749 /* disable interrupt */ 1750 writel(0, devpriv->base_addr + P_IER); 1751 1752 /* clear interrupt request */ 1753 writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->base_addr + P_ISR); 1754 1755 /* clear any pending interrupt */ 1756 s626_dio_clear_irq(dev); 1757 /* s626_enc_clear_irq(dev); */ 1758 1759 /* reset ai_cmd_running flag */ 1760 devpriv->ai_cmd_running = 0; 1761 1762 /* test if cmd is valid */ 1763 if (cmd == NULL) { 1764 DEBUG("s626_ai_cmd: NULL command\n"); 1765 return -EINVAL; 1766 } else { 1767 DEBUG("s626_ai_cmd: command recieved!!!\n"); 1768 } 1769 1770 if (dev->irq == 0) { 1771 comedi_error(dev, 1772 "s626_ai_cmd: cannot run command without an irq"); 1773 return -EIO; 1774 } 1775 1776 s626_ai_load_polllist(ppl, cmd); 1777 devpriv->ai_cmd_running = 1; 1778 devpriv->ai_convert_count = 0; 1779 1780 switch (cmd->scan_begin_src) { 1781 case TRIG_FOLLOW: 1782 break; 1783 case TRIG_TIMER: 1784 /* set a conter to generate adc trigger at scan_begin_arg interval */ 1785 k = &encpriv[5]; 1786 tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg, 1787 cmd->flags & TRIG_ROUND_MASK); 1788 1789 /* load timer value and enable interrupt */ 1790 s626_timer_load(dev, k, tick); 1791 k->SetEnable(dev, k, CLKENAB_ALWAYS); 1792 1793 DEBUG("s626_ai_cmd: scan trigger timer is set with value %d\n", 1794 tick); 1795 1796 break; 1797 case TRIG_EXT: 1798 /* set the digital line and interrupt for scan trigger */ 1799 if (cmd->start_src != TRIG_EXT) 1800 s626_dio_set_irq(dev, cmd->scan_begin_arg); 1801 1802 DEBUG("s626_ai_cmd: External scan trigger is set!!!\n"); 1803 1804 break; 1805 } 1806 1807 switch (cmd->convert_src) { 1808 case TRIG_NOW: 1809 break; 1810 case TRIG_TIMER: 1811 /* set a conter to generate adc trigger at convert_arg interval */ 1812 k = &encpriv[4]; 1813 tick = s626_ns_to_timer((int *)&cmd->convert_arg, 1814 cmd->flags & TRIG_ROUND_MASK); 1815 1816 /* load timer value and enable interrupt */ 1817 s626_timer_load(dev, k, tick); 1818 k->SetEnable(dev, k, CLKENAB_INDEX); 1819 1820 DEBUG 1821 ("s626_ai_cmd: convert trigger timer is set with value %d\n", 1822 tick); 1823 break; 1824 case TRIG_EXT: 1825 /* set the digital line and interrupt for convert trigger */ 1826 if (cmd->scan_begin_src != TRIG_EXT 1827 && cmd->start_src == TRIG_EXT) 1828 s626_dio_set_irq(dev, cmd->convert_arg); 1829 1830 DEBUG("s626_ai_cmd: External convert trigger is set!!!\n"); 1831 1832 break; 1833 } 1834 1835 switch (cmd->stop_src) { 1836 case TRIG_COUNT: 1837 /* data arrives as one packet */ 1838 devpriv->ai_sample_count = cmd->stop_arg; 1839 devpriv->ai_continous = 0; 1840 break; 1841 case TRIG_NONE: 1842 /* continous aquisition */ 1843 devpriv->ai_continous = 1; 1844 devpriv->ai_sample_count = 0; 1845 break; 1846 } 1847 1848 ResetADC(dev, ppl); 1849 1850 switch (cmd->start_src) { 1851 case TRIG_NOW: 1852 /* Trigger ADC scan loop start by setting RPS Signal 0. */ 1853 /* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */ 1854 1855 /* Start executing the RPS program. */ 1856 MC_ENABLE(P_MC1, MC1_ERPS1); 1857 1858 DEBUG("s626_ai_cmd: ADC triggered\n"); 1859 s->async->inttrig = NULL; 1860 break; 1861 case TRIG_EXT: 1862 /* configure DIO channel for acquisition trigger */ 1863 s626_dio_set_irq(dev, cmd->start_arg); 1864 1865 DEBUG("s626_ai_cmd: External start trigger is set!!!\n"); 1866 1867 s->async->inttrig = NULL; 1868 break; 1869 case TRIG_INT: 1870 s->async->inttrig = s626_ai_inttrig; 1871 break; 1872 } 1873 1874 /* enable interrupt */ 1875 writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER); 1876 1877 DEBUG("s626_ai_cmd: command function terminated\n"); 1878 1879 return 0; 1880} 1881 1882static int s626_ai_cmdtest(struct comedi_device *dev, 1883 struct comedi_subdevice *s, struct comedi_cmd *cmd) 1884{ 1885 int err = 0; 1886 int tmp; 1887 1888 /* cmdtest tests a particular command to see if it is valid. Using 1889 * the cmdtest ioctl, a user can create a valid cmd and then have it 1890 * executes by the cmd ioctl. 1891 * 1892 * cmdtest returns 1,2,3,4 or 0, depending on which tests the 1893 * command passes. */ 1894 1895 /* step 1: make sure trigger sources are trivially valid */ 1896 1897 tmp = cmd->start_src; 1898 cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT; 1899 if (!cmd->start_src || tmp != cmd->start_src) 1900 err++; 1901 1902 tmp = cmd->scan_begin_src; 1903 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW; 1904 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 1905 err++; 1906 1907 tmp = cmd->convert_src; 1908 cmd->convert_src &= TRIG_TIMER | TRIG_EXT | TRIG_NOW; 1909 if (!cmd->convert_src || tmp != cmd->convert_src) 1910 err++; 1911 1912 tmp = cmd->scan_end_src; 1913 cmd->scan_end_src &= TRIG_COUNT; 1914 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 1915 err++; 1916 1917 tmp = cmd->stop_src; 1918 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 1919 if (!cmd->stop_src || tmp != cmd->stop_src) 1920 err++; 1921 1922 if (err) 1923 return 1; 1924 1925 /* step 2: make sure trigger sources are unique and mutually 1926 compatible */ 1927 1928 /* note that mutual compatiblity is not an issue here */ 1929 if (cmd->scan_begin_src != TRIG_TIMER && 1930 cmd->scan_begin_src != TRIG_EXT 1931 && cmd->scan_begin_src != TRIG_FOLLOW) 1932 err++; 1933 if (cmd->convert_src != TRIG_TIMER && 1934 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW) 1935 err++; 1936 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 1937 err++; 1938 1939 if (err) 1940 return 2; 1941 1942 /* step 3: make sure arguments are trivially compatible */ 1943 1944 if (cmd->start_src != TRIG_EXT && cmd->start_arg != 0) { 1945 cmd->start_arg = 0; 1946 err++; 1947 } 1948 1949 if (cmd->start_src == TRIG_EXT && cmd->start_arg > 39) { 1950 cmd->start_arg = 39; 1951 err++; 1952 } 1953 1954 if (cmd->scan_begin_src == TRIG_EXT && cmd->scan_begin_arg > 39) { 1955 cmd->scan_begin_arg = 39; 1956 err++; 1957 } 1958 1959 if (cmd->convert_src == TRIG_EXT && cmd->convert_arg > 39) { 1960 cmd->convert_arg = 39; 1961 err++; 1962 } 1963#define MAX_SPEED 200000 /* in nanoseconds */ 1964#define MIN_SPEED 2000000000 /* in nanoseconds */ 1965 1966 if (cmd->scan_begin_src == TRIG_TIMER) { 1967 if (cmd->scan_begin_arg < MAX_SPEED) { 1968 cmd->scan_begin_arg = MAX_SPEED; 1969 err++; 1970 } 1971 if (cmd->scan_begin_arg > MIN_SPEED) { 1972 cmd->scan_begin_arg = MIN_SPEED; 1973 err++; 1974 } 1975 } else { 1976 /* external trigger */ 1977 /* should be level/edge, hi/lo specification here */ 1978 /* should specify multiple external triggers */ 1979/* if(cmd->scan_begin_arg>9){ */ 1980/* cmd->scan_begin_arg=9; */ 1981/* err++; */ 1982/* } */ 1983 } 1984 if (cmd->convert_src == TRIG_TIMER) { 1985 if (cmd->convert_arg < MAX_SPEED) { 1986 cmd->convert_arg = MAX_SPEED; 1987 err++; 1988 } 1989 if (cmd->convert_arg > MIN_SPEED) { 1990 cmd->convert_arg = MIN_SPEED; 1991 err++; 1992 } 1993 } else { 1994 /* external trigger */ 1995 /* see above */ 1996/* if(cmd->convert_arg>9){ */ 1997/* cmd->convert_arg=9; */ 1998/* err++; */ 1999/* } */ 2000 } 2001 2002 if (cmd->scan_end_arg != cmd->chanlist_len) { 2003 cmd->scan_end_arg = cmd->chanlist_len; 2004 err++; 2005 } 2006 if (cmd->stop_src == TRIG_COUNT) { 2007 if (cmd->stop_arg > 0x00ffffff) { 2008 cmd->stop_arg = 0x00ffffff; 2009 err++; 2010 } 2011 } else { 2012 /* TRIG_NONE */ 2013 if (cmd->stop_arg != 0) { 2014 cmd->stop_arg = 0; 2015 err++; 2016 } 2017 } 2018 2019 if (err) 2020 return 3; 2021 2022 /* step 4: fix up any arguments */ 2023 2024 if (cmd->scan_begin_src == TRIG_TIMER) { 2025 tmp = cmd->scan_begin_arg; 2026 s626_ns_to_timer((int *)&cmd->scan_begin_arg, 2027 cmd->flags & TRIG_ROUND_MASK); 2028 if (tmp != cmd->scan_begin_arg) 2029 err++; 2030 } 2031 if (cmd->convert_src == TRIG_TIMER) { 2032 tmp = cmd->convert_arg; 2033 s626_ns_to_timer((int *)&cmd->convert_arg, 2034 cmd->flags & TRIG_ROUND_MASK); 2035 if (tmp != cmd->convert_arg) 2036 err++; 2037 if (cmd->scan_begin_src == TRIG_TIMER && 2038 cmd->scan_begin_arg < 2039 cmd->convert_arg * cmd->scan_end_arg) { 2040 cmd->scan_begin_arg = 2041 cmd->convert_arg * cmd->scan_end_arg; 2042 err++; 2043 } 2044 } 2045 2046 if (err) 2047 return 4; 2048 2049 return 0; 2050} 2051 2052static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 2053{ 2054 /* Stop RPS program in case it is currently running. */ 2055 MC_DISABLE(P_MC1, MC1_ERPS1); 2056 2057 /* disable master interrupt */ 2058 writel(0, devpriv->base_addr + P_IER); 2059 2060 devpriv->ai_cmd_running = 0; 2061 2062 return 0; 2063} 2064 2065/* This function doesn't require a particular form, this is just what 2066 * happens to be used in some of the drivers. It should convert ns 2067 * nanoseconds to a counter value suitable for programming the device. 2068 * Also, it should adjust ns so that it cooresponds to the actual time 2069 * that the device will use. */ 2070static int s626_ns_to_timer(int *nanosec, int round_mode) 2071{ 2072 int divider, base; 2073 2074 base = 500; /* 2MHz internal clock */ 2075 2076 switch (round_mode) { 2077 case TRIG_ROUND_NEAREST: 2078 default: 2079 divider = (*nanosec + base / 2) / base; 2080 break; 2081 case TRIG_ROUND_DOWN: 2082 divider = (*nanosec) / base; 2083 break; 2084 case TRIG_ROUND_UP: 2085 divider = (*nanosec + base - 1) / base; 2086 break; 2087 } 2088 2089 *nanosec = base * divider; 2090 return divider - 1; 2091} 2092 2093static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 2094 struct comedi_insn *insn, unsigned int *data) 2095{ 2096 2097 int i; 2098 uint16_t chan = CR_CHAN(insn->chanspec); 2099 int16_t dacdata; 2100 2101 for (i = 0; i < insn->n; i++) { 2102 dacdata = (int16_t) data[i]; 2103 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i]; 2104 dacdata -= (0x1fff); 2105 2106 SetDAC(dev, chan, dacdata); 2107 } 2108 2109 return i; 2110} 2111 2112static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 2113 struct comedi_insn *insn, unsigned int *data) 2114{ 2115 int i; 2116 2117 for (i = 0; i < insn->n; i++) 2118 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)]; 2119 2120 return i; 2121} 2122 2123/* *************** DIGITAL I/O FUNCTIONS *************** 2124 * All DIO functions address a group of DIO channels by means of 2125 * "group" argument. group may be 0, 1 or 2, which correspond to DIO 2126 * ports A, B and C, respectively. 2127 */ 2128 2129static void s626_dio_init(struct comedi_device *dev) 2130{ 2131 uint16_t group; 2132 struct comedi_subdevice *s; 2133 2134 /* Prepare to treat writes to WRCapSel as capture disables. */ 2135 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP); 2136 2137 /* For each group of sixteen channels ... */ 2138 for (group = 0; group < S626_DIO_BANKS; group++) { 2139 s = dev->subdevices + 2 + group; 2140 DEBIwrite(dev, diopriv->WRIntSel, 0); /* Disable all interrupts. */ 2141 DEBIwrite(dev, diopriv->WRCapSel, 0xFFFF); /* Disable all event */ 2142 /* captures. */ 2143 DEBIwrite(dev, diopriv->WREdgSel, 0); /* Init all DIOs to */ 2144 /* default edge */ 2145 /* polarity. */ 2146 DEBIwrite(dev, diopriv->WRDOut, 0); /* Program all outputs */ 2147 /* to inactive state. */ 2148 } 2149 DEBUG("s626_dio_init: DIO initialized \n"); 2150} 2151 2152/* DIO devices are slightly special. Although it is possible to 2153 * implement the insn_read/insn_write interface, it is much more 2154 * useful to applications if you implement the insn_bits interface. 2155 * This allows packed reading/writing of the DIO channels. The comedi 2156 * core can convert between insn_bits and insn_read/write */ 2157 2158static int s626_dio_insn_bits(struct comedi_device *dev, 2159 struct comedi_subdevice *s, 2160 struct comedi_insn *insn, unsigned int *data) 2161{ 2162 2163 /* Length of data must be 2 (mask and new data, see below) */ 2164 if (insn->n == 0) 2165 return 0; 2166 2167 if (insn->n != 2) { 2168 printk 2169 ("comedi%d: s626: s626_dio_insn_bits(): Invalid instruction length\n", 2170 dev->minor); 2171 return -EINVAL; 2172 } 2173 2174 /* 2175 * The insn data consists of a mask in data[0] and the new data in 2176 * data[1]. The mask defines which bits we are concerning about. 2177 * The new data must be anded with the mask. Each channel 2178 * corresponds to a bit. 2179 */ 2180 if (data[0]) { 2181 /* Check if requested ports are configured for output */ 2182 if ((s->io_bits & data[0]) != data[0]) 2183 return -EIO; 2184 2185 s->state &= ~data[0]; 2186 s->state |= data[0] & data[1]; 2187 2188 /* Write out the new digital output lines */ 2189 2190 DEBIwrite(dev, diopriv->WRDOut, s->state); 2191 } 2192 data[1] = DEBIread(dev, diopriv->RDDIn); 2193 2194 return 2; 2195} 2196 2197static int s626_dio_insn_config(struct comedi_device *dev, 2198 struct comedi_subdevice *s, 2199 struct comedi_insn *insn, unsigned int *data) 2200{ 2201 2202 switch (data[0]) { 2203 case INSN_CONFIG_DIO_QUERY: 2204 data[1] = 2205 (s-> 2206 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : 2207 COMEDI_INPUT; 2208 return insn->n; 2209 break; 2210 case COMEDI_INPUT: 2211 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec)); 2212 break; 2213 case COMEDI_OUTPUT: 2214 s->io_bits |= 1 << CR_CHAN(insn->chanspec); 2215 break; 2216 default: 2217 return -EINVAL; 2218 break; 2219 } 2220 DEBIwrite(dev, diopriv->WRDOut, s->io_bits); 2221 2222 return 1; 2223} 2224 2225static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan) 2226{ 2227 unsigned int group; 2228 unsigned int bitmask; 2229 unsigned int status; 2230 2231 /* select dio bank */ 2232 group = chan / 16; 2233 bitmask = 1 << (chan - (16 * group)); 2234 DEBUG("s626_dio_set_irq: enable interrupt on dio channel %d group %d\n", 2235 chan - (16 * group), group); 2236 2237 /* set channel to capture positive edge */ 2238 status = DEBIread(dev, 2239 ((struct dio_private *)(dev->subdevices + 2 + 2240 group)->private)->RDEdgSel); 2241 DEBIwrite(dev, 2242 ((struct dio_private *)(dev->subdevices + 2 + 2243 group)->private)->WREdgSel, 2244 bitmask | status); 2245 2246 /* enable interrupt on selected channel */ 2247 status = DEBIread(dev, 2248 ((struct dio_private *)(dev->subdevices + 2 + 2249 group)->private)->RDIntSel); 2250 DEBIwrite(dev, 2251 ((struct dio_private *)(dev->subdevices + 2 + 2252 group)->private)->WRIntSel, 2253 bitmask | status); 2254 2255 /* enable edge capture write command */ 2256 DEBIwrite(dev, LP_MISC1, MISC1_EDCAP); 2257 2258 /* enable edge capture on selected channel */ 2259 status = DEBIread(dev, 2260 ((struct dio_private *)(dev->subdevices + 2 + 2261 group)->private)->RDCapSel); 2262 DEBIwrite(dev, 2263 ((struct dio_private *)(dev->subdevices + 2 + 2264 group)->private)->WRCapSel, 2265 bitmask | status); 2266 2267 return 0; 2268} 2269 2270static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group, 2271 unsigned int mask) 2272{ 2273 DEBUG 2274 ("s626_dio_reset_irq: disable interrupt on dio channel %d group %d\n", 2275 mask, group); 2276 2277 /* disable edge capture write command */ 2278 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP); 2279 2280 /* enable edge capture on selected channel */ 2281 DEBIwrite(dev, 2282 ((struct dio_private *)(dev->subdevices + 2 + 2283 group)->private)->WRCapSel, mask); 2284 2285 return 0; 2286} 2287 2288static int s626_dio_clear_irq(struct comedi_device *dev) 2289{ 2290 unsigned int group; 2291 2292 /* disable edge capture write command */ 2293 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP); 2294 2295 for (group = 0; group < S626_DIO_BANKS; group++) { 2296 /* clear pending events and interrupt */ 2297 DEBIwrite(dev, 2298 ((struct dio_private *)(dev->subdevices + 2 + 2299 group)->private)->WRCapSel, 2300 0xffff); 2301 } 2302 2303 return 0; 2304} 2305 2306/* Now this function initializes the value of the counter (data[0]) 2307 and set the subdevice. To complete with trigger and interrupt 2308 configuration */ 2309static int s626_enc_insn_config(struct comedi_device *dev, 2310 struct comedi_subdevice *s, 2311 struct comedi_insn *insn, unsigned int *data) 2312{ 2313 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */ 2314 /* index. */ 2315 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */ 2316 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is Counter. */ 2317 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */ 2318 /* ( CNTDIR_UP << BF_CLKPOL ) | // Count direction is Down. */ 2319 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */ 2320 (CLKENAB_INDEX << BF_CLKENAB); 2321 /* uint16_t DisableIntSrc=TRUE; */ 2322 /* uint32_t Preloadvalue; //Counter initial value */ 2323 uint16_t valueSrclatch = LATCHSRC_AB_READ; 2324 uint16_t enab = CLKENAB_ALWAYS; 2325 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)]; 2326 2327 DEBUG("s626_enc_insn_config: encoder config\n"); 2328 2329 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */ 2330 2331 k->SetMode(dev, k, Setup, TRUE); 2332 Preload(dev, k, *(insn->data)); 2333 k->PulseIndex(dev, k); 2334 SetLatchSource(dev, k, valueSrclatch); 2335 k->SetEnable(dev, k, (uint16_t) (enab != 0)); 2336 2337 return insn->n; 2338} 2339 2340static int s626_enc_insn_read(struct comedi_device *dev, 2341 struct comedi_subdevice *s, 2342 struct comedi_insn *insn, unsigned int *data) 2343{ 2344 2345 int n; 2346 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)]; 2347 2348 DEBUG("s626_enc_insn_read: encoder read channel %d \n", 2349 CR_CHAN(insn->chanspec)); 2350 2351 for (n = 0; n < insn->n; n++) 2352 data[n] = ReadLatch(dev, k); 2353 2354 DEBUG("s626_enc_insn_read: encoder sample %d\n", data[n]); 2355 2356 return n; 2357} 2358 2359static int s626_enc_insn_write(struct comedi_device *dev, 2360 struct comedi_subdevice *s, 2361 struct comedi_insn *insn, unsigned int *data) 2362{ 2363 2364 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)]; 2365 2366 DEBUG("s626_enc_insn_write: encoder write channel %d \n", 2367 CR_CHAN(insn->chanspec)); 2368 2369 /* Set the preload register */ 2370 Preload(dev, k, data[0]); 2371 2372 /* Software index pulse forces the preload register to load */ 2373 /* into the counter */ 2374 k->SetLoadTrig(dev, k, 0); 2375 k->PulseIndex(dev, k); 2376 k->SetLoadTrig(dev, k, 2); 2377 2378 DEBUG("s626_enc_insn_write: End encoder write\n"); 2379 2380 return 1; 2381} 2382 2383static void s626_timer_load(struct comedi_device *dev, struct enc_private *k, 2384 int tick) 2385{ 2386 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */ 2387 /* index. */ 2388 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */ 2389 (CLKSRC_TIMER << BF_CLKSRC) | /* Operating mode is Timer. */ 2390 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */ 2391 (CNTDIR_DOWN << BF_CLKPOL) | /* Count direction is Down. */ 2392 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */ 2393 (CLKENAB_INDEX << BF_CLKENAB); 2394 uint16_t valueSrclatch = LATCHSRC_A_INDXA; 2395 /* uint16_t enab=CLKENAB_ALWAYS; */ 2396 2397 k->SetMode(dev, k, Setup, FALSE); 2398 2399 /* Set the preload register */ 2400 Preload(dev, k, tick); 2401 2402 /* Software index pulse forces the preload register to load */ 2403 /* into the counter */ 2404 k->SetLoadTrig(dev, k, 0); 2405 k->PulseIndex(dev, k); 2406 2407 /* set reload on counter overflow */ 2408 k->SetLoadTrig(dev, k, 1); 2409 2410 /* set interrupt on overflow */ 2411 k->SetIntSrc(dev, k, INTSRC_OVER); 2412 2413 SetLatchSource(dev, k, valueSrclatch); 2414 /* k->SetEnable(dev,k,(uint16_t)(enab != 0)); */ 2415} 2416 2417/* *********** DAC FUNCTIONS *********** */ 2418 2419/* Slot 0 base settings. */ 2420#define VECT0 (XSD2 | RSD3 | SIB_A2) 2421/* Slot 0 always shifts in 0xFF and store it to FB_BUFFER2. */ 2422 2423/* TrimDac LogicalChan-to-PhysicalChan mapping table. */ 2424static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 }; 2425 2426/* TrimDac LogicalChan-to-EepromAdrs mapping table. */ 2427static uint8_t trimadrs[] = 2428 { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 }; 2429 2430static void LoadTrimDACs(struct comedi_device *dev) 2431{ 2432 register uint8_t i; 2433 2434 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */ 2435 for (i = 0; i < ARRAY_SIZE(trimchan); i++) 2436 WriteTrimDAC(dev, i, I2Cread(dev, trimadrs[i])); 2437} 2438 2439static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan, 2440 uint8_t DacData) 2441{ 2442 uint32_t chan; 2443 2444 /* Save the new setpoint in case the application needs to read it back later. */ 2445 devpriv->TrimSetpoint[LogicalChan] = (uint8_t) DacData; 2446 2447 /* Map logical channel number to physical channel number. */ 2448 chan = (uint32_t) trimchan[LogicalChan]; 2449 2450 /* Set up TSL2 records for TrimDac write operation. All slots shift 2451 * 0xFF in from pulled-up SD3 so that the end of the slot sequence 2452 * can be detected. 2453 */ 2454 2455 SETVECT(2, XSD2 | XFIFO_1 | WS3); 2456 /* Slot 2: Send high uint8_t to target TrimDac. */ 2457 SETVECT(3, XSD2 | XFIFO_0 | WS3); 2458 /* Slot 3: Send low uint8_t to target TrimDac. */ 2459 SETVECT(4, XSD2 | XFIFO_3 | WS1); 2460 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running. */ 2461 SETVECT(5, XSD2 | XFIFO_2 | WS1 | EOS); 2462 /* Slot 5: Send NOP low uint8_t to DAC0. */ 2463 2464 /* Construct and transmit target DAC's serial packet: 2465 * ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the 2466 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a 2467 * WORD value (that writes a channel 0 NOP command to a non-existent 2468 * main DAC channel) that serves to keep the clock running after the 2469 * packet has been sent to the target DAC. 2470 */ 2471 2472 /* Address the DAC channel within the trimdac device. */ 2473 SendDAC(dev, ((uint32_t) chan << 8) 2474 | (uint32_t) DacData); /* Include DAC setpoint data. */ 2475} 2476 2477/* ************** EEPROM ACCESS FUNCTIONS ************** */ 2478/* Read uint8_t from EEPROM. */ 2479 2480static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr) 2481{ 2482 uint8_t rtnval; 2483 2484 /* Send EEPROM target address. */ 2485 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CW) 2486 /* Byte2 = I2C command: write to I2C EEPROM device. */ 2487 | I2C_B1(I2C_ATTRSTOP, addr) 2488 /* Byte1 = EEPROM internal target address. */ 2489 | I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */ 2490 /* Abort function and declare error if handshake failed. */ 2491 DEBUG("I2Cread: error handshake I2Cread a\n"); 2492 return 0; 2493 } 2494 /* Execute EEPROM read. */ 2495 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CR) 2496 2497 /* Byte2 = I2C */ 2498 /* command: read */ 2499 /* from I2C EEPROM */ 2500 /* device. */ 2501 |I2C_B1(I2C_ATTRSTOP, 0) 2502 2503 /* Byte1 receives */ 2504 /* uint8_t from */ 2505 /* EEPROM. */ 2506 |I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */ 2507 2508 /* Abort function and declare error if handshake failed. */ 2509 DEBUG("I2Cread: error handshake I2Cread b\n"); 2510 return 0; 2511 } 2512 /* Return copy of EEPROM value. */ 2513 rtnval = (uint8_t) (RR7146(P_I2CCTRL) >> 16); 2514 return rtnval; 2515} 2516 2517static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val) 2518{ 2519 /* Write I2C command to I2C Transfer Control shadow register. */ 2520 WR7146(P_I2CCTRL, val); 2521 2522 /* Upload I2C shadow registers into working registers and wait for */ 2523 /* upload confirmation. */ 2524 2525 MC_ENABLE(P_MC2, MC2_UPLD_IIC); 2526 while (!MC_TEST(P_MC2, MC2_UPLD_IIC)) ; 2527 2528 /* Wait until I2C bus transfer is finished or an error occurs. */ 2529 while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY) ; 2530 2531 /* Return non-zero if I2C error occured. */ 2532 return RR7146(P_I2CCTRL) & I2C_ERR; 2533 2534} 2535 2536/* Private helper function: Write setpoint to an application DAC channel. */ 2537 2538static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata) 2539{ 2540 register uint16_t signmask; 2541 register uint32_t WSImage; 2542 2543 /* Adjust DAC data polarity and set up Polarity Control Register */ 2544 /* image. */ 2545 signmask = 1 << chan; 2546 if (dacdata < 0) { 2547 dacdata = -dacdata; 2548 devpriv->Dacpol |= signmask; 2549 } else 2550 devpriv->Dacpol &= ~signmask; 2551 2552 /* Limit DAC setpoint value to valid range. */ 2553 if ((uint16_t) dacdata > 0x1FFF) 2554 dacdata = 0x1FFF; 2555 2556 /* Set up TSL2 records (aka "vectors") for DAC update. Vectors V2 2557 * and V3 transmit the setpoint to the target DAC. V4 and V5 send 2558 * data to a non-existent TrimDac channel just to keep the clock 2559 * running after sending data to the target DAC. This is necessary 2560 * to eliminate the clock glitch that would otherwise occur at the 2561 * end of the target DAC's serial data stream. When the sequence 2562 * restarts at V0 (after executing V5), the gate array automatically 2563 * disables gating for the DAC clock and all DAC chip selects. 2564 */ 2565 2566 WSImage = (chan & 2) ? WS1 : WS2; 2567 /* Choose DAC chip select to be asserted. */ 2568 SETVECT(2, XSD2 | XFIFO_1 | WSImage); 2569 /* Slot 2: Transmit high data byte to target DAC. */ 2570 SETVECT(3, XSD2 | XFIFO_0 | WSImage); 2571 /* Slot 3: Transmit low data byte to target DAC. */ 2572 SETVECT(4, XSD2 | XFIFO_3 | WS3); 2573 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */ 2574 SETVECT(5, XSD2 | XFIFO_2 | WS3 | EOS); 2575 /* Slot 5: running after writing target DAC's low data byte. */ 2576 2577 /* Construct and transmit target DAC's serial packet: 2578 * ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>, 2579 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes 2580 * to a non-existent TrimDac channel) that serves to keep the clock 2581 * running after the packet has been sent to the target DAC. 2582 */ 2583 SendDAC(dev, 0x0F000000 2584 /* Continue clock after target DAC data (write to non-existent trimdac). */ 2585 | 0x00004000 2586 /* Address the two main dual-DAC devices (TSL's chip select enables 2587 * target device). */ 2588 | ((uint32_t) (chan & 1) << 15) 2589 /* Address the DAC channel within the device. */ 2590 | (uint32_t) dacdata); /* Include DAC setpoint data. */ 2591 2592} 2593 2594/* Private helper function: Transmit serial data to DAC via Audio 2595 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2) 2596 * Dacpol contains valid target image. 2597 */ 2598 2599static void SendDAC(struct comedi_device *dev, uint32_t val) 2600{ 2601 2602 /* START THE SERIAL CLOCK RUNNING ------------- */ 2603 2604 /* Assert DAC polarity control and enable gating of DAC serial clock 2605 * and audio bit stream signals. At this point in time we must be 2606 * assured of being in time slot 0. If we are not in slot 0, the 2607 * serial clock and audio stream signals will be disabled; this is 2608 * because the following DEBIwrite statement (which enables signals 2609 * to be passed through the gate array) would execute before the 2610 * trailing edge of WS1/WS3 (which turns off the signals), thus 2611 * causing the signals to be inactive during the DAC write. 2612 */ 2613 DEBIwrite(dev, LP_DACPOL, devpriv->Dacpol); 2614 2615 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */ 2616 2617 /* Copy DAC setpoint value to DAC's output DMA buffer. */ 2618 2619 /* WR7146( (uint32_t)devpriv->pDacWBuf, val ); */ 2620 *devpriv->pDacWBuf = val; 2621 2622 /* enab the output DMA transfer. This will cause the DMAC to copy 2623 * the DAC's data value to A2's output FIFO. The DMA transfer will 2624 * then immediately terminate because the protection address is 2625 * reached upon transfer of the first DWORD value. 2626 */ 2627 MC_ENABLE(P_MC1, MC1_A2OUT); 2628 2629 /* While the DMA transfer is executing ... */ 2630 2631 /* Reset Audio2 output FIFO's underflow flag (along with any other 2632 * FIFO underflow/overflow flags). When set, this flag will 2633 * indicate that we have emerged from slot 0. 2634 */ 2635 WR7146(P_ISR, ISR_AFOU); 2636 2637 /* Wait for the DMA transfer to finish so that there will be data 2638 * available in the FIFO when time slot 1 tries to transfer a DWORD 2639 * from the FIFO to the output buffer register. We test for DMA 2640 * Done by polling the DMAC enable flag; this flag is automatically 2641 * cleared when the transfer has finished. 2642 */ 2643 while ((RR7146(P_MC1) & MC1_A2OUT) != 0) ; 2644 2645 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */ 2646 2647 /* FIFO data is now available, so we enable execution of time slots 2648 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3 2649 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list 2650 * detection. 2651 */ 2652 SETVECT(0, XSD2 | RSD3 | SIB_A2); 2653 2654 /* Wait for slot 1 to execute to ensure that the Packet will be 2655 * transmitted. This is detected by polling the Audio2 output FIFO 2656 * underflow flag, which will be set when slot 1 execution has 2657 * finished transferring the DAC's data DWORD from the output FIFO 2658 * to the output buffer register. 2659 */ 2660 while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0) ; 2661 2662 /* Set up to trap execution at slot 0 when the TSL sequencer cycles 2663 * back to slot 0 after executing the EOS in slot 5. Also, 2664 * simultaneously shift out and in the 0x00 that is ALWAYS the value 2665 * stored in the last byte to be shifted out of the FIFO's DWORD 2666 * buffer register. 2667 */ 2668 SETVECT(0, XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS); 2669 2670 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */ 2671 2672 /* Wait for the TSL to finish executing all time slots before 2673 * exiting this function. We must do this so that the next DAC 2674 * write doesn't start, thereby enabling clock/chip select signals: 2675 * 2676 * 1. Before the TSL sequence cycles back to slot 0, which disables 2677 * the clock/cs signal gating and traps slot // list execution. 2678 * we have not yet finished slot 5 then the clock/cs signals are 2679 * still gated and we have not finished transmitting the stream. 2680 * 2681 * 2. While slots 2-5 are executing due to a late slot 0 trap. In 2682 * this case, the slot sequence is currently repeating, but with 2683 * clock/cs signals disabled. We must wait for slot 0 to trap 2684 * execution before setting up the next DAC setpoint DMA transfer 2685 * and enabling the clock/cs signals. To detect the end of slot 5, 2686 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If 2687 * the TSL has not yet finished executing slot 5 ... 2688 */ 2689 if ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) { 2690 /* The trap was set on time and we are still executing somewhere 2691 * in slots 2-5, so we now wait for slot 0 to execute and trap 2692 * TSL execution. This is detected when FB_BUFFER2 MSB changes 2693 * from 0xFF to 0x00, which slot 0 causes to happen by shifting 2694 * out/in on SD2 the 0x00 that is always referenced by slot 5. 2695 */ 2696 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) ; 2697 } 2698 /* Either (1) we were too late setting the slot 0 trap; the TSL 2699 * sequencer restarted slot 0 before we could set the EOS trap flag, 2700 * or (2) we were not late and execution is now trapped at slot 0. 2701 * In either case, we must now change slot 0 so that it will store 2702 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes. 2703 * In order to do this, we reprogram slot 0 so that it will shift in 2704 * SD3, which is driven only by a pull-up resistor. 2705 */ 2706 SETVECT(0, RSD3 | SIB_A2 | EOS); 2707 2708 /* Wait for slot 0 to execute, at which time the TSL is setup for 2709 * the next DAC write. This is detected when FB_BUFFER2 MSB changes 2710 * from 0x00 to 0xFF. 2711 */ 2712 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0) ; 2713} 2714 2715static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage) 2716{ 2717 DEBIwrite(dev, LP_MISC1, MISC1_WENABLE); /* enab writes to */ 2718 /* MISC2 register. */ 2719 DEBIwrite(dev, LP_WRMISC2, NewImage); /* Write new image to MISC2. */ 2720 DEBIwrite(dev, LP_MISC1, MISC1_WDISABLE); /* Disable writes to MISC2. */ 2721} 2722 2723/* Initialize the DEBI interface for all transfers. */ 2724 2725static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr) 2726{ 2727 uint16_t retval; 2728 2729 /* Set up DEBI control register value in shadow RAM. */ 2730 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr); 2731 2732 /* Execute the DEBI transfer. */ 2733 DEBItransfer(dev); 2734 2735 /* Fetch target register value. */ 2736 retval = (uint16_t) RR7146(P_DEBIAD); 2737 2738 /* Return register value. */ 2739 return retval; 2740} 2741 2742/* Execute a DEBI transfer. This must be called from within a */ 2743/* critical section. */ 2744static void DEBItransfer(struct comedi_device *dev) 2745{ 2746 /* Initiate upload of shadow RAM to DEBI control register. */ 2747 MC_ENABLE(P_MC2, MC2_UPLD_DEBI); 2748 2749 /* Wait for completion of upload from shadow RAM to DEBI control */ 2750 /* register. */ 2751 while (!MC_TEST(P_MC2, MC2_UPLD_DEBI)) ; 2752 2753 /* Wait until DEBI transfer is done. */ 2754 while (RR7146(P_PSR) & PSR_DEBI_S) ; 2755} 2756 2757/* Write a value to a gate array register. */ 2758static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata) 2759{ 2760 2761 /* Set up DEBI control register value in shadow RAM. */ 2762 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr); 2763 WR7146(P_DEBIAD, wdata); 2764 2765 /* Execute the DEBI transfer. */ 2766 DEBItransfer(dev); 2767} 2768 2769/* Replace the specified bits in a gate array register. Imports: mask 2770 * specifies bits that are to be preserved, wdata is new value to be 2771 * or'd with the masked original. 2772 */ 2773static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask, 2774 uint16_t wdata) 2775{ 2776 2777 /* Copy target gate array register into P_DEBIAD register. */ 2778 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr); 2779 /* Set up DEBI control reg value in shadow RAM. */ 2780 DEBItransfer(dev); /* Execute the DEBI Read transfer. */ 2781 2782 /* Write back the modified image. */ 2783 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr); 2784 /* Set up DEBI control reg value in shadow RAM. */ 2785 2786 WR7146(P_DEBIAD, wdata | ((uint16_t) RR7146(P_DEBIAD) & mask)); 2787 /* Modify the register image. */ 2788 DEBItransfer(dev); /* Execute the DEBI Write transfer. */ 2789} 2790 2791static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma, 2792 size_t bsize) 2793{ 2794 void *vbptr; 2795 dma_addr_t vpptr; 2796 2797 DEBUG("CloseDMAB: Entering S626DRV_CloseDMAB():\n"); 2798 if (pdma == NULL) 2799 return; 2800 /* find the matching allocation from the board struct */ 2801 2802 vbptr = pdma->LogicalBase; 2803 vpptr = pdma->PhysicalBase; 2804 if (vbptr) { 2805 pci_free_consistent(devpriv->pdev, bsize, vbptr, vpptr); 2806 pdma->LogicalBase = 0; 2807 pdma->PhysicalBase = 0; 2808 2809 DEBUG("CloseDMAB(): Logical=%p, bsize=%d, Physical=0x%x\n", 2810 vbptr, bsize, (uint32_t) vpptr); 2811 } 2812} 2813 2814/* ****** COUNTER FUNCTIONS ******* */ 2815/* All counter functions address a specific counter by means of the 2816 * "Counter" argument, which is a logical counter number. The Counter 2817 * argument may have any of the following legal values: 0=0A, 1=1A, 2818 * 2=2A, 3=0B, 4=1B, 5=2B. 2819 */ 2820 2821/* Forward declarations for functions that are common to both A and B counters: */ 2822 2823/* ****** PRIVATE COUNTER FUNCTIONS ****** */ 2824 2825/* Read a counter's output latch. */ 2826 2827static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k) 2828{ 2829 register uint32_t value; 2830 /* DEBUG FIXME DEBUG("ReadLatch: Read Latch enter\n"); */ 2831 2832 /* Latch counts and fetch LSW of latched counts value. */ 2833 value = (uint32_t) DEBIread(dev, k->MyLatchLsw); 2834 2835 /* Fetch MSW of latched counts and combine with LSW. */ 2836 value |= ((uint32_t) DEBIread(dev, k->MyLatchLsw + 2) << 16); 2837 2838 /* DEBUG FIXME DEBUG("ReadLatch: Read Latch exit\n"); */ 2839 2840 /* Return latched counts. */ 2841 return value; 2842} 2843 2844/* Reset a counter's index and overflow event capture flags. */ 2845 2846static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k) 2847{ 2848 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL), 2849 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A); 2850} 2851 2852static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k) 2853{ 2854 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL), 2855 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B); 2856} 2857 2858/* Return counter setup in a format (COUNTER_SETUP) that is consistent */ 2859/* for both A and B counters. */ 2860 2861static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k) 2862{ 2863 register uint16_t cra; 2864 register uint16_t crb; 2865 register uint16_t setup; 2866 2867 /* Fetch CRA and CRB register images. */ 2868 cra = DEBIread(dev, k->MyCRA); 2869 crb = DEBIread(dev, k->MyCRB); 2870 2871 /* Populate the standardized counter setup bit fields. Note: */ 2872 /* IndexSrc is restricted to ENC_X or IndxPol. */ 2873 setup = ((cra & STDMSK_LOADSRC) /* LoadSrc = LoadSrcA. */ 2874 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcA. */ 2875 |((cra << (STDBIT_INTSRC - CRABIT_INTSRC_A)) & STDMSK_INTSRC) /* IntSrc = IntSrcA. */ 2876 |((cra << (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1))) & STDMSK_INDXSRC) /* IndxSrc = IndxSrcA<1>. */ 2877 |((cra >> (CRABIT_INDXPOL_A - STDBIT_INDXPOL)) & STDMSK_INDXPOL) /* IndxPol = IndxPolA. */ 2878 |((crb >> (CRBBIT_CLKENAB_A - STDBIT_CLKENAB)) & STDMSK_CLKENAB)); /* ClkEnab = ClkEnabA. */ 2879 2880 /* Adjust mode-dependent parameters. */ 2881 if (cra & (2 << CRABIT_CLKSRC_A)) /* If Timer mode (ClkSrcA<1> == 1): */ 2882 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */ 2883 |((cra << (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) & STDMSK_CLKPOL) /* Set ClkPol to indicate count direction (ClkSrcA<0>). */ 2884 |(MULT_X1 << STDBIT_CLKMULT)); /* ClkMult must be 1x in Timer mode. */ 2885 2886 else /* If Counter mode (ClkSrcA<1> == 0): */ 2887 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Counter mode. */ 2888 |((cra >> (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) & STDMSK_CLKPOL) /* Pass through ClkPol. */ 2889 |(((cra & CRAMSK_CLKMULT_A) == (MULT_X0 << CRABIT_CLKMULT_A)) ? /* Force ClkMult to 1x if not legal, else pass through. */ 2890 (MULT_X1 << STDBIT_CLKMULT) : 2891 ((cra >> (CRABIT_CLKMULT_A - 2892 STDBIT_CLKMULT)) & STDMSK_CLKMULT))); 2893 2894 /* Return adjusted counter setup. */ 2895 return setup; 2896} 2897 2898static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k) 2899{ 2900 register uint16_t cra; 2901 register uint16_t crb; 2902 register uint16_t setup; 2903 2904 /* Fetch CRA and CRB register images. */ 2905 cra = DEBIread(dev, k->MyCRA); 2906 crb = DEBIread(dev, k->MyCRB); 2907 2908 /* Populate the standardized counter setup bit fields. Note: */ 2909 /* IndexSrc is restricted to ENC_X or IndxPol. */ 2910 setup = (((crb << (STDBIT_INTSRC - CRBBIT_INTSRC_B)) & STDMSK_INTSRC) /* IntSrc = IntSrcB. */ 2911 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcB. */ 2912 |((crb << (STDBIT_LOADSRC - CRBBIT_LOADSRC_B)) & STDMSK_LOADSRC) /* LoadSrc = LoadSrcB. */ 2913 |((crb << (STDBIT_INDXPOL - CRBBIT_INDXPOL_B)) & STDMSK_INDXPOL) /* IndxPol = IndxPolB. */ 2914 |((crb >> (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) & STDMSK_CLKENAB) /* ClkEnab = ClkEnabB. */ 2915 |((cra >> ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)) & STDMSK_INDXSRC)); /* IndxSrc = IndxSrcB<1>. */ 2916 2917 /* Adjust mode-dependent parameters. */ 2918 if ((crb & CRBMSK_CLKMULT_B) == (MULT_X0 << CRBBIT_CLKMULT_B)) /* If Extender mode (ClkMultB == MULT_X0): */ 2919 setup |= ((CLKSRC_EXTENDER << STDBIT_CLKSRC) /* Indicate Extender mode. */ 2920 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */ 2921 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */ 2922 2923 else if (cra & (2 << CRABIT_CLKSRC_B)) /* If Timer mode (ClkSrcB<1> == 1): */ 2924 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */ 2925 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */ 2926 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */ 2927 2928 else /* If Counter mode (ClkSrcB<1> == 0): */ 2929 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Timer mode. */ 2930 |((crb >> (CRBBIT_CLKMULT_B - STDBIT_CLKMULT)) & STDMSK_CLKMULT) /* Clock multiplier is passed through. */ 2931 |((crb << (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) & STDMSK_CLKPOL)); /* Clock polarity is passed through. */ 2932 2933 /* Return adjusted counter setup. */ 2934 return setup; 2935} 2936 2937/* 2938 * Set the operating mode for the specified counter. The setup 2939 * parameter is treated as a COUNTER_SETUP data type. The following 2940 * parameters are programmable (all other parms are ignored): ClkMult, 2941 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc. 2942 */ 2943 2944static void SetMode_A(struct comedi_device *dev, struct enc_private *k, 2945 uint16_t Setup, uint16_t DisableIntSrc) 2946{ 2947 register uint16_t cra; 2948 register uint16_t crb; 2949 register uint16_t setup = Setup; /* Cache the Standard Setup. */ 2950 2951 /* Initialize CRA and CRB images. */ 2952 cra = ((setup & CRAMSK_LOADSRC_A) /* Preload trigger is passed through. */ 2953 |((setup & STDMSK_INDXSRC) >> (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1)))); /* IndexSrc is restricted to ENC_X or IndxPol. */ 2954 2955 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A /* Reset any pending CounterA event captures. */ 2956 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB))); /* Clock enable is passed through. */ 2957 2958 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */ 2959 if (!DisableIntSrc) 2960 cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC - 2961 CRABIT_INTSRC_A)); 2962 2963 /* Populate all mode-dependent attributes of CRA & CRB images. */ 2964 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) { 2965 case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode */ 2966 /* (Extender valid only for B counters). */ 2967 2968 case CLKSRC_TIMER: /* Timer Mode: */ 2969 cra |= ((2 << CRABIT_CLKSRC_A) /* ClkSrcA<1> selects system clock */ 2970 |((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) /* with count direction (ClkSrcA<0>) obtained from ClkPol. */ 2971 |(1 << CRABIT_CLKPOL_A) /* ClkPolA behaves as always-on clock enable. */ 2972 |(MULT_X1 << CRABIT_CLKMULT_A)); /* ClkMult must be 1x. */ 2973 break; 2974 2975 default: /* Counter Mode: */ 2976 cra |= (CLKSRC_COUNTER /* Select ENC_C and ENC_D as clock/direction inputs. */ 2977 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) /* Clock polarity is passed through. */ 2978 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force multiplier to x1 if not legal, otherwise pass through. */ 2979 (MULT_X1 << CRABIT_CLKMULT_A) : 2980 ((setup & STDMSK_CLKMULT) << (CRABIT_CLKMULT_A - 2981 STDBIT_CLKMULT)))); 2982 } 2983 2984 /* Force positive index polarity if IndxSrc is software-driven only, */ 2985 /* otherwise pass it through. */ 2986 if (~setup & STDMSK_INDXSRC) 2987 cra |= ((setup & STDMSK_INDXPOL) << (CRABIT_INDXPOL_A - 2988 STDBIT_INDXPOL)); 2989 2990 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */ 2991 /* enable mask to indicate the counter interrupt is disabled. */ 2992 if (DisableIntSrc) 2993 devpriv->CounterIntEnabs &= ~k->MyEventBits[3]; 2994 2995 /* While retaining CounterB and LatchSrc configurations, program the */ 2996 /* new counter operating mode. */ 2997 DEBIreplace(dev, k->MyCRA, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, cra); 2998 DEBIreplace(dev, k->MyCRB, 2999 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)), crb); 3000} 3001 3002static void SetMode_B(struct comedi_device *dev, struct enc_private *k, 3003 uint16_t Setup, uint16_t DisableIntSrc) 3004{ 3005 register uint16_t cra; 3006 register uint16_t crb; 3007 register uint16_t setup = Setup; /* Cache the Standard Setup. */ 3008 3009 /* Initialize CRA and CRB images. */ 3010 cra = ((setup & STDMSK_INDXSRC) << ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)); /* IndexSrc field is restricted to ENC_X or IndxPol. */ 3011 3012 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B /* Reset event captures and disable interrupts. */ 3013 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) /* Clock enable is passed through. */ 3014 |((setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B))); /* Preload trigger source is passed through. */ 3015 3016 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */ 3017 if (!DisableIntSrc) 3018 crb |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC - 3019 CRBBIT_INTSRC_B)); 3020 3021 /* Populate all mode-dependent attributes of CRA & CRB images. */ 3022 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) { 3023 case CLKSRC_TIMER: /* Timer Mode: */ 3024 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB<1> selects system clock */ 3025 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction (ClkSrcB<0>) obtained from ClkPol. */ 3026 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB behaves as always-on clock enable. */ 3027 |(MULT_X1 << CRBBIT_CLKMULT_B)); /* ClkMultB must be 1x. */ 3028 break; 3029 3030 case CLKSRC_EXTENDER: /* Extender Mode: */ 3031 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB source is OverflowA (same as "timer") */ 3032 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction obtained from ClkPol. */ 3033 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB controls IndexB -- always set to active. */ 3034 |(MULT_X0 << CRBBIT_CLKMULT_B)); /* ClkMultB selects OverflowA as the clock source. */ 3035 break; 3036 3037 default: /* Counter Mode: */ 3038 cra |= (CLKSRC_COUNTER << CRABIT_CLKSRC_B); /* Select ENC_C and ENC_D as clock/direction inputs. */ 3039 crb |= (((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) /* ClkPol is passed through. */ 3040 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force ClkMult to x1 if not legal, otherwise pass through. */ 3041 (MULT_X1 << CRBBIT_CLKMULT_B) : 3042 ((setup & STDMSK_CLKMULT) << (CRBBIT_CLKMULT_B - 3043 STDBIT_CLKMULT)))); 3044 } 3045 3046 /* Force positive index polarity if IndxSrc is software-driven only, */ 3047 /* otherwise pass it through. */ 3048 if (~setup & STDMSK_INDXSRC) 3049 crb |= ((setup & STDMSK_INDXPOL) >> (STDBIT_INDXPOL - 3050 CRBBIT_INDXPOL_B)); 3051 3052 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */ 3053 /* enable mask to indicate the counter interrupt is disabled. */ 3054 if (DisableIntSrc) 3055 devpriv->CounterIntEnabs &= ~k->MyEventBits[3]; 3056 3057 /* While retaining CounterA and LatchSrc configurations, program the */ 3058 /* new counter operating mode. */ 3059 DEBIreplace(dev, k->MyCRA, 3060 (uint16_t) (~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B)), cra); 3061 DEBIreplace(dev, k->MyCRB, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, crb); 3062} 3063 3064/* Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. */ 3065 3066static void SetEnable_A(struct comedi_device *dev, struct enc_private *k, 3067 uint16_t enab) 3068{ 3069 DEBUG("SetEnable_A: SetEnable_A enter 3541\n"); 3070 DEBIreplace(dev, k->MyCRB, 3071 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)), 3072 (uint16_t) (enab << CRBBIT_CLKENAB_A)); 3073} 3074 3075static void SetEnable_B(struct comedi_device *dev, struct enc_private *k, 3076 uint16_t enab) 3077{ 3078 DEBIreplace(dev, k->MyCRB, 3079 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B)), 3080 (uint16_t) (enab << CRBBIT_CLKENAB_B)); 3081} 3082 3083static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k) 3084{ 3085 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_A) & 1; 3086} 3087 3088static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k) 3089{ 3090 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_B) & 1; 3091} 3092 3093/* Return/set a counter pair's latch trigger source. 0: On read 3094 * access, 1: A index latches A, 2: B index latches B, 3: A overflow 3095 * latches B. 3096 */ 3097 3098static void SetLatchSource(struct comedi_device *dev, struct enc_private *k, 3099 uint16_t value) 3100{ 3101 DEBUG("SetLatchSource: SetLatchSource enter 3550 \n"); 3102 DEBIreplace(dev, k->MyCRB, 3103 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_LATCHSRC)), 3104 (uint16_t) (value << CRBBIT_LATCHSRC)); 3105 3106 DEBUG("SetLatchSource: SetLatchSource exit \n"); 3107} 3108 3109/* 3110 * static uint16_t GetLatchSource(struct comedi_device *dev, struct enc_private *k ) 3111 * { 3112 * return ( DEBIread( dev, k->MyCRB) >> CRBBIT_LATCHSRC ) & 3; 3113 * } 3114 */ 3115 3116/* 3117 * Return/set the event that will trigger transfer of the preload 3118 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow, 3119 * 2=OverflowA (B counters only), 3=disabled. 3120 */ 3121 3122static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k, 3123 uint16_t Trig) 3124{ 3125 DEBIreplace(dev, k->MyCRA, (uint16_t) (~CRAMSK_LOADSRC_A), 3126 (uint16_t) (Trig << CRABIT_LOADSRC_A)); 3127} 3128 3129static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k, 3130 uint16_t Trig) 3131{ 3132 DEBIreplace(dev, k->MyCRB, 3133 (uint16_t) (~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL)), 3134 (uint16_t) (Trig << CRBBIT_LOADSRC_B)); 3135} 3136 3137static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k) 3138{ 3139 return (DEBIread(dev, k->MyCRA) >> CRABIT_LOADSRC_A) & 3; 3140} 3141 3142static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k) 3143{ 3144 return (DEBIread(dev, k->MyCRB) >> CRBBIT_LOADSRC_B) & 3; 3145} 3146 3147/* Return/set counter interrupt source and clear any captured 3148 * index/overflow events. IntSource: 0=Disabled, 1=OverflowOnly, 3149 * 2=IndexOnly, 3=IndexAndOverflow. 3150 */ 3151 3152static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k, 3153 uint16_t IntSource) 3154{ 3155 /* Reset any pending counter overflow or index captures. */ 3156 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL), 3157 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A); 3158 3159 /* Program counter interrupt source. */ 3160 DEBIreplace(dev, k->MyCRA, ~CRAMSK_INTSRC_A, 3161 (uint16_t) (IntSource << CRABIT_INTSRC_A)); 3162 3163 /* Update MISC2 interrupt enable mask. */ 3164 devpriv->CounterIntEnabs = 3165 (devpriv->CounterIntEnabs & ~k-> 3166 MyEventBits[3]) | k->MyEventBits[IntSource]; 3167} 3168 3169static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k, 3170 uint16_t IntSource) 3171{ 3172 uint16_t crb; 3173 3174 /* Cache writeable CRB register image. */ 3175 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL; 3176 3177 /* Reset any pending counter overflow or index captures. */ 3178 DEBIwrite(dev, k->MyCRB, 3179 (uint16_t) (crb | CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B)); 3180 3181 /* Program counter interrupt source. */ 3182 DEBIwrite(dev, k->MyCRB, 3183 (uint16_t) ((crb & ~CRBMSK_INTSRC_B) | (IntSource << 3184 CRBBIT_INTSRC_B))); 3185 3186 /* Update MISC2 interrupt enable mask. */ 3187 devpriv->CounterIntEnabs = 3188 (devpriv->CounterIntEnabs & ~k-> 3189 MyEventBits[3]) | k->MyEventBits[IntSource]; 3190} 3191 3192static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k) 3193{ 3194 return (DEBIread(dev, k->MyCRA) >> CRABIT_INTSRC_A) & 3; 3195} 3196 3197static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k) 3198{ 3199 return (DEBIread(dev, k->MyCRB) >> CRBBIT_INTSRC_B) & 3; 3200} 3201 3202/* Return/set the clock multiplier. */ 3203 3204/* static void SetClkMult(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */ 3205/* { */ 3206/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKMULT ) | ( value << STDBIT_CLKMULT ) ), FALSE ); */ 3207/* } */ 3208 3209/* static uint16_t GetClkMult(struct comedi_device *dev, struct enc_private *k ) */ 3210/* { */ 3211/* return ( k->GetMode(dev, k ) >> STDBIT_CLKMULT ) & 3; */ 3212/* } */ 3213 3214/* Return/set the clock polarity. */ 3215 3216/* static void SetClkPol( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */ 3217/* { */ 3218/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKPOL ) | ( value << STDBIT_CLKPOL ) ), FALSE ); */ 3219/* } */ 3220 3221/* static uint16_t GetClkPol(struct comedi_device *dev, struct enc_private *k ) */ 3222/* { */ 3223/* return ( k->GetMode(dev, k ) >> STDBIT_CLKPOL ) & 1; */ 3224/* } */ 3225 3226/* Return/set the clock source. */ 3227 3228/* static void SetClkSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */ 3229/* { */ 3230/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKSRC ) | ( value << STDBIT_CLKSRC ) ), FALSE ); */ 3231/* } */ 3232 3233/* static uint16_t GetClkSrc( struct comedi_device *dev,struct enc_private *k ) */ 3234/* { */ 3235/* return ( k->GetMode(dev, k ) >> STDBIT_CLKSRC ) & 3; */ 3236/* } */ 3237 3238/* Return/set the index polarity. */ 3239 3240/* static void SetIndexPol(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */ 3241/* { */ 3242/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXPOL ) | ( (value != 0) << STDBIT_INDXPOL ) ), FALSE ); */ 3243/* } */ 3244 3245/* static uint16_t GetIndexPol(struct comedi_device *dev, struct enc_private *k ) */ 3246/* { */ 3247/* return ( k->GetMode(dev, k ) >> STDBIT_INDXPOL ) & 1; */ 3248/* } */ 3249 3250/* Return/set the index source. */ 3251 3252/* static void SetIndexSrc(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */ 3253/* { */ 3254/* DEBUG("SetIndexSrc: set index src enter 3700\n"); */ 3255/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXSRC ) | ( (value != 0) << STDBIT_INDXSRC ) ), FALSE ); */ 3256/* } */ 3257 3258/* static uint16_t GetIndexSrc(struct comedi_device *dev, struct enc_private *k ) */ 3259/* { */ 3260/* return ( k->GetMode(dev, k ) >> STDBIT_INDXSRC ) & 1; */ 3261/* } */ 3262 3263/* Generate an index pulse. */ 3264 3265static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k) 3266{ 3267 register uint16_t cra; 3268 3269 DEBUG("PulseIndex_A: pulse index enter\n"); 3270 3271 cra = DEBIread(dev, k->MyCRA); /* Pulse index. */ 3272 DEBIwrite(dev, k->MyCRA, (uint16_t) (cra ^ CRAMSK_INDXPOL_A)); 3273 DEBUG("PulseIndex_A: pulse index step1\n"); 3274 DEBIwrite(dev, k->MyCRA, cra); 3275} 3276 3277static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k) 3278{ 3279 register uint16_t crb; 3280 3281 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL; /* Pulse index. */ 3282 DEBIwrite(dev, k->MyCRB, (uint16_t) (crb ^ CRBMSK_INDXPOL_B)); 3283 DEBIwrite(dev, k->MyCRB, crb); 3284} 3285 3286/* Write value into counter preload register. */ 3287 3288static void Preload(struct comedi_device *dev, struct enc_private *k, 3289 uint32_t value) 3290{ 3291 DEBUG("Preload: preload enter\n"); 3292 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw), (uint16_t) value); /* Write value to preload register. */ 3293 DEBUG("Preload: preload step 1\n"); 3294 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw + 2), 3295 (uint16_t) (value >> 16)); 3296} 3297 3298static void CountersInit(struct comedi_device *dev) 3299{ 3300 int chan; 3301 struct enc_private *k; 3302 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */ 3303 /* index. */ 3304 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */ 3305 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is counter. */ 3306 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */ 3307 (CNTDIR_UP << BF_CLKPOL) | /* Count direction is up. */ 3308 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */ 3309 (CLKENAB_INDEX << BF_CLKENAB); /* Enabled by index */ 3310 3311 /* Disable all counter interrupts and clear any captured counter events. */ 3312 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) { 3313 k = &encpriv[chan]; 3314 k->SetMode(dev, k, Setup, TRUE); 3315 k->SetIntSrc(dev, k, 0); 3316 k->ResetCapFlags(dev, k); 3317 k->SetEnable(dev, k, CLKENAB_ALWAYS); 3318 } 3319 DEBUG("CountersInit: counters initialized \n"); 3320 3321} 3322