1/*************************************************************************** 2 * Copyright (c) 2005-2009, Broadcom Corporation. 3 * 4 * Name: crystalhd_misc . h 5 * 6 * Description: 7 * BCM70012 Linux driver general purpose routines. 8 * Includes reg/mem read and write routines. 9 * 10 * HISTORY: 11 * 12 ********************************************************************** 13 * This file is part of the crystalhd device driver. 14 * 15 * This driver is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation, version 2 of the License. 18 * 19 * This driver is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this driver. If not, see <http://www.gnu.org/licenses/>. 26 **********************************************************************/ 27 28#ifndef _CRYSTALHD_MISC_H_ 29#define _CRYSTALHD_MISC_H_ 30 31#include "crystalhd.h" 32 33#include <linux/module.h> 34#include <linux/kernel.h> 35#include <linux/errno.h> 36#include <linux/string.h> 37#include <linux/ioctl.h> 38#include <linux/dma-mapping.h> 39#include <linux/sched.h> 40#include "bc_dts_glob_lnx.h" 41 42/* Global log level variable defined in crystal_misc.c file */ 43extern uint32_t g_linklog_level; 44 45/* Global element pool for all Queue management. 46 * TX: Active = BC_TX_LIST_CNT, Free = BC_TX_LIST_CNT. 47 * RX: Free = BC_RX_LIST_CNT, Active = 2 48 * FW-CMD: 4 49 */ 50#define BC_LINK_ELEM_POOL_SZ ((BC_TX_LIST_CNT * 2) + BC_RX_LIST_CNT + 2 + 4) 51 52/* Driver's IODATA pool count */ 53#define CHD_IODATA_POOL_SZ (BC_IOCTL_DATA_POOL_SIZE * BC_LINK_MAX_OPENS) 54 55/* Scatter Gather memory pool size for Tx and Rx */ 56#define BC_LINK_SG_POOL_SZ (BC_TX_LIST_CNT + BC_RX_LIST_CNT) 57 58enum crystalhd_dio_sig { 59 crystalhd_dio_inv = 0, 60 crystalhd_dio_locked, 61 crystalhd_dio_sg_mapped, 62}; 63 64struct crystalhd_dio_user_info { 65 void *xfr_buff; 66 uint32_t xfr_len; 67 uint32_t uv_offset; 68 bool dir_tx; 69 70 uint32_t uv_sg_ix; 71 uint32_t uv_sg_off; 72 int comp_sts; 73 int ev_sts; 74 uint32_t y_done_sz; 75 uint32_t uv_done_sz; 76 uint32_t comp_flags; 77 bool b422mode; 78}; 79 80struct crystalhd_dio_req { 81 uint32_t sig; 82 uint32_t max_pages; 83 struct page **pages; 84 struct scatterlist *sg; 85 int sg_cnt; 86 int page_cnt; 87 int direction; 88 struct crystalhd_dio_user_info uinfo; 89 void *fb_va; 90 uint32_t fb_size; 91 dma_addr_t fb_pa; 92 struct crystalhd_dio_req *next; 93}; 94 95#define BC_LINK_DIOQ_SIG (0x09223280) 96 97struct crystalhd_elem { 98 struct crystalhd_elem *flink; 99 struct crystalhd_elem *blink; 100 void *data; 101 uint32_t tag; 102}; 103 104typedef void (*crystalhd_data_free_cb)(void *context, void *data); 105 106struct crystalhd_dioq { 107 uint32_t sig; 108 struct crystalhd_adp *adp; 109 struct crystalhd_elem *head; 110 struct crystalhd_elem *tail; 111 uint32_t count; 112 spinlock_t lock; 113 wait_queue_head_t event; 114 crystalhd_data_free_cb data_rel_cb; 115 void *cb_context; 116}; 117 118typedef void (*hw_comp_callback)(struct crystalhd_dio_req *, 119 wait_queue_head_t *event, enum BC_STATUS sts); 120 121/*========= Decoder (7412) register access routines.================= */ 122uint32_t bc_dec_reg_rd(struct crystalhd_adp *, uint32_t); 123void bc_dec_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t); 124 125/*========= Link (70012) register access routines.. =================*/ 126uint32_t crystalhd_reg_rd(struct crystalhd_adp *, uint32_t); 127void crystalhd_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t); 128 129/*========= Decoder (7412) memory access routines..=================*/ 130enum BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); 131enum BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); 132 133/*==========Link (70012) PCIe Config access routines.================*/ 134enum BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); 135enum BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t); 136 137/*========= Linux Kernel Interface routines. ======================= */ 138void *bc_kern_dma_alloc(struct crystalhd_adp *, uint32_t, dma_addr_t *); 139void bc_kern_dma_free(struct crystalhd_adp *, uint32_t, 140 void *, dma_addr_t); 141#define crystalhd_create_event(_ev) init_waitqueue_head(_ev) 142#define crystalhd_set_event(_ev) wake_up_interruptible(_ev) 143#define crystalhd_wait_on_event(ev, condition, timeout, ret, nosig) \ 144do { \ 145 DECLARE_WAITQUEUE(entry, current); \ 146 unsigned long end = jiffies + ((timeout * HZ) / 1000); \ 147 ret = 0; \ 148 add_wait_queue(ev, &entry); \ 149 for (;;) { \ 150 __set_current_state(TASK_INTERRUPTIBLE); \ 151 if (condition) { \ 152 break; \ 153 } \ 154 if (time_after_eq(jiffies, end)) { \ 155 ret = -EBUSY; \ 156 break; \ 157 } \ 158 schedule_timeout((HZ / 100 > 1) ? HZ / 100 : 1); \ 159 if (!nosig && signal_pending(current)) { \ 160 ret = -EINTR; \ 161 break; \ 162 } \ 163 } \ 164 __set_current_state(TASK_RUNNING); \ 165 remove_wait_queue(ev, &entry); \ 166} while (0) 167 168/*================ Direct IO mapping routines ==================*/ 169extern int crystalhd_create_dio_pool(struct crystalhd_adp *, uint32_t); 170extern void crystalhd_destroy_dio_pool(struct crystalhd_adp *); 171extern enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *, uint32_t, 172 uint32_t, bool, bool, struct crystalhd_dio_req**); 173 174extern enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *, struct crystalhd_dio_req*); 175#define crystalhd_get_sgle_paddr(_dio, _ix) (cpu_to_le64(sg_dma_address(&_dio->sg[_ix]))) 176#define crystalhd_get_sgle_len(_dio, _ix) (cpu_to_le32(sg_dma_len(&_dio->sg[_ix]))) 177 178/*================ General Purpose Queues ==================*/ 179extern enum BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *, struct crystalhd_dioq **, crystalhd_data_free_cb , void *); 180extern void crystalhd_delete_dioq(struct crystalhd_adp *, struct crystalhd_dioq *); 181extern enum BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, void *data, bool wake, uint32_t tag); 182extern void *crystalhd_dioq_fetch(struct crystalhd_dioq *ioq); 183extern void *crystalhd_dioq_find_and_fetch(struct crystalhd_dioq *ioq, uint32_t tag); 184extern void *crystalhd_dioq_fetch_wait(struct crystalhd_dioq *ioq, uint32_t to_secs, uint32_t *sig_pend); 185 186#define crystalhd_dioq_count(_ioq) ((_ioq) ? _ioq->count : 0) 187 188extern int crystalhd_create_elem_pool(struct crystalhd_adp *, uint32_t); 189extern void crystalhd_delete_elem_pool(struct crystalhd_adp *); 190 191 192/*================ Debug routines/macros .. ================================*/ 193extern void crystalhd_show_buffer(uint32_t off, uint8_t *buff, uint32_t dwcount); 194 195enum _chd_log_levels { 196 BCMLOG_ERROR = 0x80000000, /* Don't disable this option */ 197 BCMLOG_DATA = 0x40000000, /* Data, enable by default */ 198 BCMLOG_SPINLOCK = 0x20000000, /* Spcial case for Spin locks*/ 199 200 /* Following are allowed only in debug mode */ 201 BCMLOG_INFO = 0x00000001, /* Generic informational */ 202 BCMLOG_DBG = 0x00000002, /* First level Debug info */ 203 BCMLOG_SSTEP = 0x00000004, /* Stepping information */ 204}; 205 206 207#define BCMLOG(trace, fmt, args...) \ 208do { \ 209 if (g_linklog_level & trace) \ 210 printk(fmt, ##args); \ 211} while (0) 212 213 214#define BCMLOG_ERR(fmt, args...) \ 215do { \ 216 if (g_linklog_level & BCMLOG_ERROR) \ 217 printk(KERN_ERR "*ERR*:%s:%d: "fmt, \ 218 __FILE__, __LINE__, ##args); \ 219} while (0) 220 221#endif 222