1/* 2 * AD7190 AD7192 AD7195 SPI ADC driver 3 * 4 * Copyright 2011 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2. 7 */ 8 9#include <linux/interrupt.h> 10#include <linux/device.h> 11#include <linux/kernel.h> 12#include <linux/slab.h> 13#include <linux/sysfs.h> 14#include <linux/spi/spi.h> 15#include <linux/regulator/consumer.h> 16#include <linux/err.h> 17#include <linux/sched.h> 18#include <linux/delay.h> 19 20#include "../iio.h" 21#include "../sysfs.h" 22#include "../buffer.h" 23#include "../ring_sw.h" 24#include "../trigger.h" 25#include "../trigger_consumer.h" 26 27#include "ad7192.h" 28 29/* Registers */ 30#define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ 31#define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ 32#define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ 33#define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ 34#define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ 35#define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ 36#define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ 37#define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit 38 * (AD7792)/24-bit (AD7192)) */ 39#define AD7192_REG_FULLSALE 7 /* Full-Scale Register 40 * (RW, 16-bit (AD7792)/24-bit (AD7192)) */ 41 42/* Communications Register Bit Designations (AD7192_REG_COMM) */ 43#define AD7192_COMM_WEN (1 << 7) /* Write Enable */ 44#define AD7192_COMM_WRITE (0 << 6) /* Write Operation */ 45#define AD7192_COMM_READ (1 << 6) /* Read Operation */ 46#define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ 47#define AD7192_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */ 48 49/* Status Register Bit Designations (AD7192_REG_STAT) */ 50#define AD7192_STAT_RDY (1 << 7) /* Ready */ 51#define AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */ 52#define AD7192_STAT_NOREF (1 << 5) /* Error no external reference */ 53#define AD7192_STAT_PARITY (1 << 4) /* Parity */ 54#define AD7192_STAT_CH3 (1 << 2) /* Channel 3 */ 55#define AD7192_STAT_CH2 (1 << 1) /* Channel 2 */ 56#define AD7192_STAT_CH1 (1 << 0) /* Channel 1 */ 57 58/* Mode Register Bit Designations (AD7192_REG_MODE) */ 59#define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */ 60#define AD7192_MODE_DAT_STA (1 << 20) /* Status Register transmission */ 61#define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ 62#define AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */ 63#define AD7192_MODE_ACX (1 << 14) /* AC excitation enable(AD7195 only)*/ 64#define AD7192_MODE_ENPAR (1 << 13) /* Parity Enable */ 65#define AD7192_MODE_CLKDIV (1 << 12) /* Clock divide by 2 (AD7190/2 only)*/ 66#define AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */ 67#define AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */ 68#define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */ 69 70/* Mode Register: AD7192_MODE_SEL options */ 71#define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ 72#define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */ 73#define AD7192_MODE_IDLE 2 /* Idle Mode */ 74#define AD7192_MODE_PWRDN 3 /* Power-Down Mode */ 75#define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ 76#define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ 77#define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ 78#define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ 79 80/* Mode Register: AD7192_MODE_CLKSRC options */ 81#define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected 82 * from MCLK1 to MCLK2 */ 83#define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ 84#define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not 85 * available at the MCLK2 pin */ 86#define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available 87 * at the MCLK2 pin */ 88 89 90/* Configuration Register Bit Designations (AD7192_REG_CONF) */ 91 92#define AD7192_CONF_CHOP (1 << 23) /* CHOP enable */ 93#define AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */ 94#define AD7192_CONF_CHAN(x) (((x) & 0xFF) << 8) /* Channel select */ 95#define AD7192_CONF_BURN (1 << 7) /* Burnout current enable */ 96#define AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */ 97#define AD7192_CONF_BUF (1 << 4) /* Buffered Mode Enable */ 98#define AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */ 99#define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */ 100 101#define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */ 102#define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */ 103#define AD7192_CH_TEMP 2 /* Temp Sensor */ 104#define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */ 105#define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */ 106#define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */ 107#define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */ 108#define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */ 109 110/* ID Register Bit Designations (AD7192_REG_ID) */ 111#define ID_AD7190 0x4 112#define ID_AD7192 0x0 113#define ID_AD7195 0x6 114#define AD7192_ID_MASK 0x0F 115 116/* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ 117#define AD7192_GPOCON_BPDSW (1 << 6) /* Bridge power-down switch enable */ 118#define AD7192_GPOCON_GP32EN (1 << 5) /* Digital Output P3 and P2 enable */ 119#define AD7192_GPOCON_GP10EN (1 << 4) /* Digital Output P1 and P0 enable */ 120#define AD7192_GPOCON_P3DAT (1 << 3) /* P3 state */ 121#define AD7192_GPOCON_P2DAT (1 << 2) /* P2 state */ 122#define AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */ 123#define AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */ 124 125#define AD7192_INT_FREQ_MHz 4915200 126 127/* NOTE: 128 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. 129 * In order to avoid contentions on the SPI bus, it's therefore necessary 130 * to use spi bus locking. 131 * 132 * The DOUT/RDY output must also be wired to an interrupt capable GPIO. 133 */ 134 135struct ad7192_state { 136 struct spi_device *spi; 137 struct iio_trigger *trig; 138 struct regulator *reg; 139 struct ad7192_platform_data *pdata; 140 wait_queue_head_t wq_data_avail; 141 bool done; 142 bool irq_dis; 143 u16 int_vref_mv; 144 u32 mclk; 145 u32 f_order; 146 u32 mode; 147 u32 conf; 148 u32 scale_avail[8][2]; 149 long available_scan_masks[9]; 150 u8 gpocon; 151 u8 devid; 152 /* 153 * DMA (thus cache coherency maintenance) requires the 154 * transfer buffers to live in their own cache lines. 155 */ 156 u8 data[4] ____cacheline_aligned; 157}; 158 159static int __ad7192_write_reg(struct ad7192_state *st, bool locked, 160 bool cs_change, unsigned char reg, 161 unsigned size, unsigned val) 162{ 163 u8 *data = st->data; 164 struct spi_transfer t = { 165 .tx_buf = data, 166 .len = size + 1, 167 .cs_change = cs_change, 168 }; 169 struct spi_message m; 170 171 data[0] = AD7192_COMM_WRITE | AD7192_COMM_ADDR(reg); 172 173 switch (size) { 174 case 3: 175 data[1] = val >> 16; 176 data[2] = val >> 8; 177 data[3] = val; 178 break; 179 case 2: 180 data[1] = val >> 8; 181 data[2] = val; 182 break; 183 case 1: 184 data[1] = val; 185 break; 186 default: 187 return -EINVAL; 188 } 189 190 spi_message_init(&m); 191 spi_message_add_tail(&t, &m); 192 193 if (locked) 194 return spi_sync_locked(st->spi, &m); 195 else 196 return spi_sync(st->spi, &m); 197} 198 199static int ad7192_write_reg(struct ad7192_state *st, 200 unsigned reg, unsigned size, unsigned val) 201{ 202 return __ad7192_write_reg(st, false, false, reg, size, val); 203} 204 205static int __ad7192_read_reg(struct ad7192_state *st, bool locked, 206 bool cs_change, unsigned char reg, 207 int *val, unsigned size) 208{ 209 u8 *data = st->data; 210 int ret; 211 struct spi_transfer t[] = { 212 { 213 .tx_buf = data, 214 .len = 1, 215 }, { 216 .rx_buf = data, 217 .len = size, 218 .cs_change = cs_change, 219 }, 220 }; 221 struct spi_message m; 222 223 data[0] = AD7192_COMM_READ | AD7192_COMM_ADDR(reg); 224 225 spi_message_init(&m); 226 spi_message_add_tail(&t[0], &m); 227 spi_message_add_tail(&t[1], &m); 228 229 if (locked) 230 ret = spi_sync_locked(st->spi, &m); 231 else 232 ret = spi_sync(st->spi, &m); 233 234 if (ret < 0) 235 return ret; 236 237 switch (size) { 238 case 3: 239 *val = data[0] << 16 | data[1] << 8 | data[2]; 240 break; 241 case 2: 242 *val = data[0] << 8 | data[1]; 243 break; 244 case 1: 245 *val = data[0]; 246 break; 247 default: 248 return -EINVAL; 249 } 250 251 return 0; 252} 253 254static int ad7192_read_reg(struct ad7192_state *st, 255 unsigned reg, int *val, unsigned size) 256{ 257 return __ad7192_read_reg(st, 0, 0, reg, val, size); 258} 259 260static int ad7192_read(struct ad7192_state *st, unsigned ch, 261 unsigned len, int *val) 262{ 263 int ret; 264 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) | 265 AD7192_CONF_CHAN(1 << ch); 266 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | 267 AD7192_MODE_SEL(AD7192_MODE_SINGLE); 268 269 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); 270 271 spi_bus_lock(st->spi->master); 272 st->done = false; 273 274 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode); 275 if (ret < 0) 276 goto out; 277 278 st->irq_dis = false; 279 enable_irq(st->spi->irq); 280 wait_event_interruptible(st->wq_data_avail, st->done); 281 282 ret = __ad7192_read_reg(st, 1, 0, AD7192_REG_DATA, val, len); 283out: 284 spi_bus_unlock(st->spi->master); 285 286 return ret; 287} 288 289static int ad7192_calibrate(struct ad7192_state *st, unsigned mode, unsigned ch) 290{ 291 int ret; 292 293 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) | 294 AD7192_CONF_CHAN(1 << ch); 295 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | AD7192_MODE_SEL(mode); 296 297 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); 298 299 spi_bus_lock(st->spi->master); 300 st->done = false; 301 302 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, 303 (st->devid != ID_AD7195) ? 304 st->mode | AD7192_MODE_CLKDIV : 305 st->mode); 306 if (ret < 0) 307 goto out; 308 309 st->irq_dis = false; 310 enable_irq(st->spi->irq); 311 wait_event_interruptible(st->wq_data_avail, st->done); 312 313 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | 314 AD7192_MODE_SEL(AD7192_MODE_IDLE); 315 316 ret = __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode); 317out: 318 spi_bus_unlock(st->spi->master); 319 320 return ret; 321} 322 323static const u8 ad7192_calib_arr[8][2] = { 324 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1}, 325 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1}, 326 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2}, 327 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2}, 328 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3}, 329 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3}, 330 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4}, 331 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4} 332}; 333 334static int ad7192_calibrate_all(struct ad7192_state *st) 335{ 336 int i, ret; 337 338 for (i = 0; i < ARRAY_SIZE(ad7192_calib_arr); i++) { 339 ret = ad7192_calibrate(st, ad7192_calib_arr[i][0], 340 ad7192_calib_arr[i][1]); 341 if (ret) 342 goto out; 343 } 344 345 return 0; 346out: 347 dev_err(&st->spi->dev, "Calibration failed\n"); 348 return ret; 349} 350 351static int ad7192_setup(struct ad7192_state *st) 352{ 353 struct iio_dev *indio_dev = spi_get_drvdata(st->spi); 354 struct ad7192_platform_data *pdata = st->pdata; 355 unsigned long long scale_uv; 356 int i, ret, id; 357 u8 ones[6]; 358 359 /* reset the serial interface */ 360 memset(&ones, 0xFF, 6); 361 ret = spi_write(st->spi, &ones, 6); 362 if (ret < 0) 363 goto out; 364 msleep(1); /* Wait for at least 500us */ 365 366 /* write/read test for device presence */ 367 ret = ad7192_read_reg(st, AD7192_REG_ID, &id, 1); 368 if (ret) 369 goto out; 370 371 id &= AD7192_ID_MASK; 372 373 if (id != st->devid) 374 dev_warn(&st->spi->dev, "device ID query failed (0x%X)\n", id); 375 376 switch (pdata->clock_source_sel) { 377 case AD7192_CLK_EXT_MCLK1_2: 378 case AD7192_CLK_EXT_MCLK2: 379 st->mclk = AD7192_INT_FREQ_MHz; 380 break; 381 case AD7192_CLK_INT: 382 case AD7192_CLK_INT_CO: 383 if (pdata->ext_clk_Hz) 384 st->mclk = pdata->ext_clk_Hz; 385 else 386 st->mclk = AD7192_INT_FREQ_MHz; 387 break; 388 default: 389 ret = -EINVAL; 390 goto out; 391 } 392 393 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | 394 AD7192_MODE_CLKSRC(pdata->clock_source_sel) | 395 AD7192_MODE_RATE(480); 396 397 st->conf = AD7192_CONF_GAIN(0); 398 399 if (pdata->rej60_en) 400 st->mode |= AD7192_MODE_REJ60; 401 402 if (pdata->sinc3_en) 403 st->mode |= AD7192_MODE_SINC3; 404 405 if (pdata->refin2_en && (st->devid != ID_AD7195)) 406 st->conf |= AD7192_CONF_REFSEL; 407 408 if (pdata->chop_en) { 409 st->conf |= AD7192_CONF_CHOP; 410 if (pdata->sinc3_en) 411 st->f_order = 3; /* SINC 3rd order */ 412 else 413 st->f_order = 4; /* SINC 4th order */ 414 } else { 415 st->f_order = 1; 416 } 417 418 if (pdata->buf_en) 419 st->conf |= AD7192_CONF_BUF; 420 421 if (pdata->unipolar_en) 422 st->conf |= AD7192_CONF_UNIPOLAR; 423 424 if (pdata->burnout_curr_en) 425 st->conf |= AD7192_CONF_BURN; 426 427 ret = ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode); 428 if (ret) 429 goto out; 430 431 ret = ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); 432 if (ret) 433 goto out; 434 435 ret = ad7192_calibrate_all(st); 436 if (ret) 437 goto out; 438 439 /* Populate available ADC input ranges */ 440 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 441 scale_uv = ((u64)st->int_vref_mv * 100000000) 442 >> (indio_dev->channels[0].scan_type.realbits - 443 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1)); 444 scale_uv >>= i; 445 446 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 447 st->scale_avail[i][0] = scale_uv; 448 } 449 450 return 0; 451out: 452 dev_err(&st->spi->dev, "setup failed\n"); 453 return ret; 454} 455 456static int ad7192_ring_preenable(struct iio_dev *indio_dev) 457{ 458 struct ad7192_state *st = iio_priv(indio_dev); 459 struct iio_buffer *ring = indio_dev->buffer; 460 size_t d_size; 461 unsigned channel; 462 463 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength)) 464 return -EINVAL; 465 466 channel = find_first_bit(indio_dev->active_scan_mask, 467 indio_dev->masklength); 468 469 d_size = bitmap_weight(indio_dev->active_scan_mask, 470 indio_dev->masklength) * 471 indio_dev->channels[0].scan_type.storagebits / 8; 472 473 if (ring->scan_timestamp) { 474 d_size += sizeof(s64); 475 476 if (d_size % sizeof(s64)) 477 d_size += sizeof(s64) - (d_size % sizeof(s64)); 478 } 479 480 if (indio_dev->buffer->access->set_bytes_per_datum) 481 indio_dev->buffer->access-> 482 set_bytes_per_datum(indio_dev->buffer, d_size); 483 484 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | 485 AD7192_MODE_SEL(AD7192_MODE_CONT); 486 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) | 487 AD7192_CONF_CHAN(1 << indio_dev->channels[channel].address); 488 489 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); 490 491 spi_bus_lock(st->spi->master); 492 __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode); 493 494 st->irq_dis = false; 495 enable_irq(st->spi->irq); 496 497 return 0; 498} 499 500static int ad7192_ring_postdisable(struct iio_dev *indio_dev) 501{ 502 struct ad7192_state *st = iio_priv(indio_dev); 503 504 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | 505 AD7192_MODE_SEL(AD7192_MODE_IDLE); 506 507 st->done = false; 508 wait_event_interruptible(st->wq_data_avail, st->done); 509 510 if (!st->irq_dis) 511 disable_irq_nosync(st->spi->irq); 512 513 __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode); 514 515 return spi_bus_unlock(st->spi->master); 516} 517 518/** 519 * ad7192_trigger_handler() bh of trigger launched polling to ring buffer 520 **/ 521static irqreturn_t ad7192_trigger_handler(int irq, void *p) 522{ 523 struct iio_poll_func *pf = p; 524 struct iio_dev *indio_dev = pf->indio_dev; 525 struct iio_buffer *ring = indio_dev->buffer; 526 struct ad7192_state *st = iio_priv(indio_dev); 527 s64 dat64[2]; 528 s32 *dat32 = (s32 *)dat64; 529 530 if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength)) 531 __ad7192_read_reg(st, 1, 1, AD7192_REG_DATA, 532 dat32, 533 indio_dev->channels[0].scan_type.realbits/8); 534 535 /* Guaranteed to be aligned with 8 byte boundary */ 536 if (ring->scan_timestamp) 537 dat64[1] = pf->timestamp; 538 539 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp); 540 541 iio_trigger_notify_done(indio_dev->trig); 542 st->irq_dis = false; 543 enable_irq(st->spi->irq); 544 545 return IRQ_HANDLED; 546} 547 548static const struct iio_buffer_setup_ops ad7192_ring_setup_ops = { 549 .preenable = &ad7192_ring_preenable, 550 .postenable = &iio_triggered_buffer_postenable, 551 .predisable = &iio_triggered_buffer_predisable, 552 .postdisable = &ad7192_ring_postdisable, 553}; 554 555static int ad7192_register_ring_funcs_and_init(struct iio_dev *indio_dev) 556{ 557 int ret; 558 559 indio_dev->buffer = iio_sw_rb_allocate(indio_dev); 560 if (!indio_dev->buffer) { 561 ret = -ENOMEM; 562 goto error_ret; 563 } 564 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time, 565 &ad7192_trigger_handler, 566 IRQF_ONESHOT, 567 indio_dev, 568 "ad7192_consumer%d", 569 indio_dev->id); 570 if (indio_dev->pollfunc == NULL) { 571 ret = -ENOMEM; 572 goto error_deallocate_sw_rb; 573 } 574 575 /* Ring buffer functions - here trigger setup related */ 576 indio_dev->setup_ops = &ad7192_ring_setup_ops; 577 578 /* Flag that polled ring buffering is possible */ 579 indio_dev->modes |= INDIO_BUFFER_TRIGGERED; 580 return 0; 581 582error_deallocate_sw_rb: 583 iio_sw_rb_free(indio_dev->buffer); 584error_ret: 585 return ret; 586} 587 588static void ad7192_ring_cleanup(struct iio_dev *indio_dev) 589{ 590 iio_dealloc_pollfunc(indio_dev->pollfunc); 591 iio_sw_rb_free(indio_dev->buffer); 592} 593 594/** 595 * ad7192_data_rdy_trig_poll() the event handler for the data rdy trig 596 **/ 597static irqreturn_t ad7192_data_rdy_trig_poll(int irq, void *private) 598{ 599 struct ad7192_state *st = iio_priv(private); 600 601 st->done = true; 602 wake_up_interruptible(&st->wq_data_avail); 603 disable_irq_nosync(irq); 604 st->irq_dis = true; 605 iio_trigger_poll(st->trig, iio_get_time_ns()); 606 607 return IRQ_HANDLED; 608} 609 610static struct iio_trigger_ops ad7192_trigger_ops = { 611 .owner = THIS_MODULE, 612}; 613 614static int ad7192_probe_trigger(struct iio_dev *indio_dev) 615{ 616 struct ad7192_state *st = iio_priv(indio_dev); 617 int ret; 618 619 st->trig = iio_allocate_trigger("%s-dev%d", 620 spi_get_device_id(st->spi)->name, 621 indio_dev->id); 622 if (st->trig == NULL) { 623 ret = -ENOMEM; 624 goto error_ret; 625 } 626 st->trig->ops = &ad7192_trigger_ops; 627 ret = request_irq(st->spi->irq, 628 ad7192_data_rdy_trig_poll, 629 IRQF_TRIGGER_LOW, 630 spi_get_device_id(st->spi)->name, 631 indio_dev); 632 if (ret) 633 goto error_free_trig; 634 635 disable_irq_nosync(st->spi->irq); 636 st->irq_dis = true; 637 st->trig->dev.parent = &st->spi->dev; 638 st->trig->private_data = indio_dev; 639 640 ret = iio_trigger_register(st->trig); 641 642 /* select default trigger */ 643 indio_dev->trig = st->trig; 644 if (ret) 645 goto error_free_irq; 646 647 return 0; 648 649error_free_irq: 650 free_irq(st->spi->irq, indio_dev); 651error_free_trig: 652 iio_free_trigger(st->trig); 653error_ret: 654 return ret; 655} 656 657static void ad7192_remove_trigger(struct iio_dev *indio_dev) 658{ 659 struct ad7192_state *st = iio_priv(indio_dev); 660 661 iio_trigger_unregister(st->trig); 662 free_irq(st->spi->irq, indio_dev); 663 iio_free_trigger(st->trig); 664} 665 666static ssize_t ad7192_read_frequency(struct device *dev, 667 struct device_attribute *attr, 668 char *buf) 669{ 670 struct iio_dev *indio_dev = dev_get_drvdata(dev); 671 struct ad7192_state *st = iio_priv(indio_dev); 672 673 return sprintf(buf, "%d\n", st->mclk / 674 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode))); 675} 676 677static ssize_t ad7192_write_frequency(struct device *dev, 678 struct device_attribute *attr, 679 const char *buf, 680 size_t len) 681{ 682 struct iio_dev *indio_dev = dev_get_drvdata(dev); 683 struct ad7192_state *st = iio_priv(indio_dev); 684 unsigned long lval; 685 int div, ret; 686 687 ret = strict_strtoul(buf, 10, &lval); 688 if (ret) 689 return ret; 690 691 mutex_lock(&indio_dev->mlock); 692 if (iio_buffer_enabled(indio_dev)) { 693 mutex_unlock(&indio_dev->mlock); 694 return -EBUSY; 695 } 696 697 div = st->mclk / (lval * st->f_order * 1024); 698 if (div < 1 || div > 1023) { 699 ret = -EINVAL; 700 goto out; 701 } 702 703 st->mode &= ~AD7192_MODE_RATE(-1); 704 st->mode |= AD7192_MODE_RATE(div); 705 ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode); 706 707out: 708 mutex_unlock(&indio_dev->mlock); 709 710 return ret ? ret : len; 711} 712 713static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, 714 ad7192_read_frequency, 715 ad7192_write_frequency); 716 717 718static ssize_t ad7192_show_scale_available(struct device *dev, 719 struct device_attribute *attr, char *buf) 720{ 721 struct iio_dev *indio_dev = dev_get_drvdata(dev); 722 struct ad7192_state *st = iio_priv(indio_dev); 723 int i, len = 0; 724 725 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 726 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0], 727 st->scale_avail[i][1]); 728 729 len += sprintf(buf + len, "\n"); 730 731 return len; 732} 733 734static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available, 735 in_voltage-voltage_scale_available, 736 S_IRUGO, ad7192_show_scale_available, NULL, 0); 737 738static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, 739 ad7192_show_scale_available, NULL, 0); 740 741static ssize_t ad7192_show_ac_excitation(struct device *dev, 742 struct device_attribute *attr, 743 char *buf) 744{ 745 struct iio_dev *indio_dev = dev_get_drvdata(dev); 746 struct ad7192_state *st = iio_priv(indio_dev); 747 748 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX)); 749} 750 751static ssize_t ad7192_show_bridge_switch(struct device *dev, 752 struct device_attribute *attr, 753 char *buf) 754{ 755 struct iio_dev *indio_dev = dev_get_drvdata(dev); 756 struct ad7192_state *st = iio_priv(indio_dev); 757 758 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW)); 759} 760 761static ssize_t ad7192_set(struct device *dev, 762 struct device_attribute *attr, 763 const char *buf, 764 size_t len) 765{ 766 struct iio_dev *indio_dev = dev_get_drvdata(dev); 767 struct ad7192_state *st = iio_priv(indio_dev); 768 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 769 int ret; 770 bool val; 771 772 ret = strtobool(buf, &val); 773 if (ret < 0) 774 return ret; 775 776 mutex_lock(&indio_dev->mlock); 777 if (iio_buffer_enabled(indio_dev)) { 778 mutex_unlock(&indio_dev->mlock); 779 return -EBUSY; 780 } 781 782 switch ((u32) this_attr->address) { 783 case AD7192_REG_GPOCON: 784 if (val) 785 st->gpocon |= AD7192_GPOCON_BPDSW; 786 else 787 st->gpocon &= ~AD7192_GPOCON_BPDSW; 788 789 ad7192_write_reg(st, AD7192_REG_GPOCON, 1, st->gpocon); 790 break; 791 case AD7192_REG_MODE: 792 if (val) 793 st->mode |= AD7192_MODE_ACX; 794 else 795 st->mode &= ~AD7192_MODE_ACX; 796 797 ad7192_write_reg(st, AD7192_REG_GPOCON, 3, st->mode); 798 break; 799 default: 800 ret = -EINVAL; 801 } 802 803 mutex_unlock(&indio_dev->mlock); 804 805 return ret ? ret : len; 806} 807 808static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR, 809 ad7192_show_bridge_switch, ad7192_set, 810 AD7192_REG_GPOCON); 811 812static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR, 813 ad7192_show_ac_excitation, ad7192_set, 814 AD7192_REG_MODE); 815 816static struct attribute *ad7192_attributes[] = { 817 &iio_dev_attr_sampling_frequency.dev_attr.attr, 818 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr, 819 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, 820 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 821 &iio_dev_attr_ac_excitation_en.dev_attr.attr, 822 NULL 823}; 824 825static const struct attribute_group ad7192_attribute_group = { 826 .attrs = ad7192_attributes, 827}; 828 829static struct attribute *ad7195_attributes[] = { 830 &iio_dev_attr_sampling_frequency.dev_attr.attr, 831 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr, 832 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, 833 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 834 NULL 835}; 836 837static const struct attribute_group ad7195_attribute_group = { 838 .attrs = ad7195_attributes, 839}; 840 841static int ad7192_read_raw(struct iio_dev *indio_dev, 842 struct iio_chan_spec const *chan, 843 int *val, 844 int *val2, 845 long m) 846{ 847 struct ad7192_state *st = iio_priv(indio_dev); 848 int ret, smpl = 0; 849 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR); 850 851 switch (m) { 852 case 0: 853 mutex_lock(&indio_dev->mlock); 854 if (iio_buffer_enabled(indio_dev)) 855 ret = -EBUSY; 856 else 857 ret = ad7192_read(st, chan->address, 858 chan->scan_type.realbits / 8, &smpl); 859 mutex_unlock(&indio_dev->mlock); 860 861 if (ret < 0) 862 return ret; 863 864 *val = (smpl >> chan->scan_type.shift) & 865 ((1 << (chan->scan_type.realbits)) - 1); 866 867 switch (chan->type) { 868 case IIO_VOLTAGE: 869 if (!unipolar) 870 *val -= (1 << (chan->scan_type.realbits - 1)); 871 break; 872 case IIO_TEMP: 873 *val -= 0x800000; 874 *val /= 2815; /* temp Kelvin */ 875 *val -= 273; /* temp Celsius */ 876 break; 877 default: 878 return -EINVAL; 879 } 880 return IIO_VAL_INT; 881 882 case IIO_CHAN_INFO_SCALE: 883 switch (chan->type) { 884 case IIO_VOLTAGE: 885 mutex_lock(&indio_dev->mlock); 886 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; 887 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; 888 mutex_unlock(&indio_dev->mlock); 889 return IIO_VAL_INT_PLUS_NANO; 890 case IIO_TEMP: 891 *val = 1000; 892 return IIO_VAL_INT; 893 default: 894 return -EINVAL; 895 } 896 } 897 898 return -EINVAL; 899} 900 901static int ad7192_write_raw(struct iio_dev *indio_dev, 902 struct iio_chan_spec const *chan, 903 int val, 904 int val2, 905 long mask) 906{ 907 struct ad7192_state *st = iio_priv(indio_dev); 908 int ret, i; 909 unsigned int tmp; 910 911 mutex_lock(&indio_dev->mlock); 912 if (iio_buffer_enabled(indio_dev)) { 913 mutex_unlock(&indio_dev->mlock); 914 return -EBUSY; 915 } 916 917 switch (mask) { 918 case IIO_CHAN_INFO_SCALE: 919 ret = -EINVAL; 920 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 921 if (val2 == st->scale_avail[i][1]) { 922 tmp = st->conf; 923 st->conf &= ~AD7192_CONF_GAIN(-1); 924 st->conf |= AD7192_CONF_GAIN(i); 925 926 if (tmp != st->conf) { 927 ad7192_write_reg(st, AD7192_REG_CONF, 928 3, st->conf); 929 ad7192_calibrate_all(st); 930 } 931 ret = 0; 932 } 933 934 default: 935 ret = -EINVAL; 936 } 937 938 mutex_unlock(&indio_dev->mlock); 939 940 return ret; 941} 942 943static int ad7192_validate_trigger(struct iio_dev *indio_dev, 944 struct iio_trigger *trig) 945{ 946 if (indio_dev->trig != trig) 947 return -EINVAL; 948 949 return 0; 950} 951 952static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, 953 struct iio_chan_spec const *chan, 954 long mask) 955{ 956 return IIO_VAL_INT_PLUS_NANO; 957} 958 959static const struct iio_info ad7192_info = { 960 .read_raw = &ad7192_read_raw, 961 .write_raw = &ad7192_write_raw, 962 .write_raw_get_fmt = &ad7192_write_raw_get_fmt, 963 .attrs = &ad7192_attribute_group, 964 .validate_trigger = ad7192_validate_trigger, 965 .driver_module = THIS_MODULE, 966}; 967 968static const struct iio_info ad7195_info = { 969 .read_raw = &ad7192_read_raw, 970 .write_raw = &ad7192_write_raw, 971 .write_raw_get_fmt = &ad7192_write_raw_get_fmt, 972 .attrs = &ad7195_attribute_group, 973 .validate_trigger = ad7192_validate_trigger, 974 .driver_module = THIS_MODULE, 975}; 976 977#define AD7192_CHAN_DIFF(_chan, _chan2, _name, _address, _si) \ 978 { .type = IIO_VOLTAGE, \ 979 .differential = 1, \ 980 .indexed = 1, \ 981 .extend_name = _name, \ 982 .channel = _chan, \ 983 .channel2 = _chan2, \ 984 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, \ 985 .address = _address, \ 986 .scan_index = _si, \ 987 .scan_type = IIO_ST('s', 24, 32, 0)} 988 989#define AD7192_CHAN(_chan, _address, _si) \ 990 { .type = IIO_VOLTAGE, \ 991 .indexed = 1, \ 992 .channel = _chan, \ 993 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, \ 994 .address = _address, \ 995 .scan_index = _si, \ 996 .scan_type = IIO_ST('s', 24, 32, 0)} 997 998#define AD7192_CHAN_TEMP(_chan, _address, _si) \ 999 { .type = IIO_TEMP, \ 1000 .indexed = 1, \ 1001 .channel = _chan, \ 1002 .info_mask = IIO_CHAN_INFO_SCALE_SEPARATE_BIT, \ 1003 .address = _address, \ 1004 .scan_index = _si, \ 1005 .scan_type = IIO_ST('s', 24, 32, 0)} 1006 1007static struct iio_chan_spec ad7192_channels[] = { 1008 AD7192_CHAN_DIFF(1, 2, NULL, AD7192_CH_AIN1P_AIN2M, 0), 1009 AD7192_CHAN_DIFF(3, 4, NULL, AD7192_CH_AIN3P_AIN4M, 1), 1010 AD7192_CHAN_TEMP(0, AD7192_CH_TEMP, 2), 1011 AD7192_CHAN_DIFF(2, 2, "shorted", AD7192_CH_AIN2P_AIN2M, 3), 1012 AD7192_CHAN(1, AD7192_CH_AIN1, 4), 1013 AD7192_CHAN(2, AD7192_CH_AIN2, 5), 1014 AD7192_CHAN(3, AD7192_CH_AIN3, 6), 1015 AD7192_CHAN(4, AD7192_CH_AIN4, 7), 1016 IIO_CHAN_SOFT_TIMESTAMP(8), 1017}; 1018 1019static int __devinit ad7192_probe(struct spi_device *spi) 1020{ 1021 struct ad7192_platform_data *pdata = spi->dev.platform_data; 1022 struct ad7192_state *st; 1023 struct iio_dev *indio_dev; 1024 int ret, i , voltage_uv = 0; 1025 1026 if (!pdata) { 1027 dev_err(&spi->dev, "no platform data?\n"); 1028 return -ENODEV; 1029 } 1030 1031 if (!spi->irq) { 1032 dev_err(&spi->dev, "no IRQ?\n"); 1033 return -ENODEV; 1034 } 1035 1036 indio_dev = iio_allocate_device(sizeof(*st)); 1037 if (indio_dev == NULL) 1038 return -ENOMEM; 1039 1040 st = iio_priv(indio_dev); 1041 1042 st->reg = regulator_get(&spi->dev, "vcc"); 1043 if (!IS_ERR(st->reg)) { 1044 ret = regulator_enable(st->reg); 1045 if (ret) 1046 goto error_put_reg; 1047 1048 voltage_uv = regulator_get_voltage(st->reg); 1049 } 1050 1051 st->pdata = pdata; 1052 1053 if (pdata && pdata->vref_mv) 1054 st->int_vref_mv = pdata->vref_mv; 1055 else if (voltage_uv) 1056 st->int_vref_mv = voltage_uv / 1000; 1057 else 1058 dev_warn(&spi->dev, "reference voltage undefined\n"); 1059 1060 spi_set_drvdata(spi, indio_dev); 1061 st->spi = spi; 1062 st->devid = spi_get_device_id(spi)->driver_data; 1063 indio_dev->dev.parent = &spi->dev; 1064 indio_dev->name = spi_get_device_id(spi)->name; 1065 indio_dev->modes = INDIO_DIRECT_MODE; 1066 indio_dev->channels = ad7192_channels; 1067 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels); 1068 indio_dev->available_scan_masks = st->available_scan_masks; 1069 if (st->devid == ID_AD7195) 1070 indio_dev->info = &ad7195_info; 1071 else 1072 indio_dev->info = &ad7192_info; 1073 1074 for (i = 0; i < indio_dev->num_channels; i++) 1075 st->available_scan_masks[i] = (1 << i) | (1 << 1076 indio_dev->channels[indio_dev->num_channels - 1]. 1077 scan_index); 1078 1079 init_waitqueue_head(&st->wq_data_avail); 1080 1081 ret = ad7192_register_ring_funcs_and_init(indio_dev); 1082 if (ret) 1083 goto error_disable_reg; 1084 1085 ret = ad7192_probe_trigger(indio_dev); 1086 if (ret) 1087 goto error_ring_cleanup; 1088 1089 ret = iio_buffer_register(indio_dev, 1090 indio_dev->channels, 1091 indio_dev->num_channels); 1092 if (ret) 1093 goto error_remove_trigger; 1094 1095 ret = ad7192_setup(st); 1096 if (ret) 1097 goto error_unreg_ring; 1098 1099 ret = iio_device_register(indio_dev); 1100 if (ret < 0) 1101 goto error_unreg_ring; 1102 return 0; 1103 1104error_unreg_ring: 1105 iio_buffer_unregister(indio_dev); 1106error_remove_trigger: 1107 ad7192_remove_trigger(indio_dev); 1108error_ring_cleanup: 1109 ad7192_ring_cleanup(indio_dev); 1110error_disable_reg: 1111 if (!IS_ERR(st->reg)) 1112 regulator_disable(st->reg); 1113error_put_reg: 1114 if (!IS_ERR(st->reg)) 1115 regulator_put(st->reg); 1116 1117 iio_free_device(indio_dev); 1118 1119 return ret; 1120} 1121 1122static int ad7192_remove(struct spi_device *spi) 1123{ 1124 struct iio_dev *indio_dev = spi_get_drvdata(spi); 1125 struct ad7192_state *st = iio_priv(indio_dev); 1126 1127 iio_device_unregister(indio_dev); 1128 iio_buffer_unregister(indio_dev); 1129 ad7192_remove_trigger(indio_dev); 1130 ad7192_ring_cleanup(indio_dev); 1131 1132 if (!IS_ERR(st->reg)) { 1133 regulator_disable(st->reg); 1134 regulator_put(st->reg); 1135 } 1136 1137 return 0; 1138} 1139 1140static const struct spi_device_id ad7192_id[] = { 1141 {"ad7190", ID_AD7190}, 1142 {"ad7192", ID_AD7192}, 1143 {"ad7195", ID_AD7195}, 1144 {} 1145}; 1146MODULE_DEVICE_TABLE(spi, ad7192_id); 1147 1148static struct spi_driver ad7192_driver = { 1149 .driver = { 1150 .name = "ad7192", 1151 .owner = THIS_MODULE, 1152 }, 1153 .probe = ad7192_probe, 1154 .remove = __devexit_p(ad7192_remove), 1155 .id_table = ad7192_id, 1156}; 1157module_spi_driver(ad7192_driver); 1158 1159MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); 1160MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC"); 1161MODULE_LICENSE("GPL v2"); 1162