17c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich/* 27c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich * AD7298 SPI ADC driver 37c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich * 47c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich * Copyright 2011 Analog Devices Inc. 57c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich * 67c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich * Licensed under the GPL-2. 77c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich */ 87c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich 97c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#ifndef IIO_ADC_AD7298_H_ 107c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define IIO_ADC_AD7298_H_ 117c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich 127c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define AD7298_WRITE (1 << 15) /* write to the control register */ 137c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define AD7298_REPEAT (1 << 14) /* repeated conversion enable */ 147c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define AD7298_CH(x) (1 << (13 - (x))) /* channel select */ 157c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define AD7298_TSENSE (1 << 5) /* temperature conversion enable */ 167c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define AD7298_EXTREF (1 << 2) /* external reference enable */ 177c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define AD7298_TAVG (1 << 1) /* temperature sensor averaging enable */ 187c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define AD7298_PDD (1 << 0) /* partial power down enable */ 197c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich 207c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define AD7298_MAX_CHAN 8 217c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define AD7298_BITS 12 227c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define AD7298_STORAGE_BITS 16 237c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define AD7298_INTREF_mV 2500 247c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich 2501a99e182333cc3b885028eaec9fde158dde4f16Michael Hennerich#define AD7298_CH_TEMP 9 2601a99e182333cc3b885028eaec9fde158dde4f16Michael Hennerich 277c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#define RES_MASK(bits) ((1 << (bits)) - 1) 287c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich 297c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich/* 307c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich * TODO: struct ad7298_platform_data needs to go into include/linux/iio 317c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich */ 327c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich 337c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerichstruct ad7298_platform_data { 347c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich /* External Vref voltage applied */ 357c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich u16 vref_mv; 367c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich}; 377c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich 387c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerichstruct ad7298_state { 397c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich struct spi_device *spi; 407c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich struct regulator *reg; 417c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich size_t d_size; 427c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich u16 int_vref_mv; 437c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich unsigned ext_ref; 447c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich struct spi_transfer ring_xfer[10]; 457c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich struct spi_transfer scan_single_xfer[3]; 467c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich struct spi_message ring_msg; 477c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich struct spi_message scan_single_msg; 487c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich /* 497c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich * DMA (thus cache coherency maintenance) requires the 507c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich * transfer buffers to live in their own cache lines. 517c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich */ 527c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich unsigned short rx_buf[8] ____cacheline_aligned; 537c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich unsigned short tx_buf[2]; 547c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich}; 557c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich 56f2a96245baccc07f770d5993f6a523e84e44336fJonathan Cameron#ifdef CONFIG_IIO_BUFFER 577c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerichint ad7298_register_ring_funcs_and_init(struct iio_dev *indio_dev); 587c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerichvoid ad7298_ring_cleanup(struct iio_dev *indio_dev); 59f2a96245baccc07f770d5993f6a523e84e44336fJonathan Cameron#else /* CONFIG_IIO_BUFFER */ 607c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich 617c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerichstatic inline int 627c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerichad7298_register_ring_funcs_and_init(struct iio_dev *indio_dev) 637c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich{ 647c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich return 0; 657c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich} 667c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich 677c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerichstatic inline void ad7298_ring_cleanup(struct iio_dev *indio_dev) 687c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich{ 697c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich} 70f2a96245baccc07f770d5993f6a523e84e44336fJonathan Cameron#endif /* CONFIG_IIO_BUFFER */ 717c31b984c4d119d0e32a1696fd4ca6b506a73d10Michael Hennerich#endif /* IIO_ADC_AD7298_H_ */ 72