max1363_core.c revision 6fe8135fccd66aedcc55ded70824342587fd2499
1 /* 2 * iio/adc/max1363.c 3 * Copyright (C) 2008-2010 Jonathan Cameron 4 * 5 * based on linux/drivers/i2c/chips/max123x 6 * Copyright (C) 2002-2004 Stefan Eletzhofer 7 * 8 * based on linux/drivers/acron/char/pcf8583.c 9 * Copyright (C) 2000 Russell King 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 * max1363.c 16 * 17 * Partial support for max1363 and similar chips. 18 * 19 * Not currently implemented. 20 * 21 * - Control of internal reference. 22 */ 23 24#include <linux/interrupt.h> 25#include <linux/device.h> 26#include <linux/kernel.h> 27#include <linux/sysfs.h> 28#include <linux/list.h> 29#include <linux/i2c.h> 30#include <linux/regulator/consumer.h> 31#include <linux/slab.h> 32#include <linux/err.h> 33 34#include "../iio.h" 35#include "../sysfs.h" 36 37#include "../ring_generic.h" 38#include "adc.h" 39#include "max1363.h" 40 41/* Here we claim all are 16 bits. This currently does no harm and saves 42 * us a lot of scan element listings */ 43 44static const struct max1363_mode max1363_mode_table[] = { 45 /* All of the single channel options first */ 46 MAX1363_MODE_SINGLE(0, 1 << 0), 47 MAX1363_MODE_SINGLE(1, 1 << 1), 48 MAX1363_MODE_SINGLE(2, 1 << 2), 49 MAX1363_MODE_SINGLE(3, 1 << 3), 50 MAX1363_MODE_SINGLE(4, 1 << 4), 51 MAX1363_MODE_SINGLE(5, 1 << 5), 52 MAX1363_MODE_SINGLE(6, 1 << 6), 53 MAX1363_MODE_SINGLE(7, 1 << 7), 54 MAX1363_MODE_SINGLE(8, 1 << 8), 55 MAX1363_MODE_SINGLE(9, 1 << 9), 56 MAX1363_MODE_SINGLE(10, 1 << 10), 57 MAX1363_MODE_SINGLE(11, 1 << 11), 58 59 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12), 60 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13), 61 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14), 62 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15), 63 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16), 64 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17), 65 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18), 66 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19), 67 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20), 68 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21), 69 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22), 70 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23), 71 72 /* The multichannel scans next */ 73 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003), 74 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007), 75 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C), 76 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F), 77 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F), 78 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F), 79 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F), 80 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0), 81 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF), 82 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0), 83 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF), 84 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0), 85 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF), 86 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0), 87 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF), 88 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0), 89 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF), 90 91 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000), 92 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000), 93 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000), 94 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000), 95 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000), 96 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000), 97 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000), 98 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000), 99 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000), 100 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000), 101 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000), 102 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000), 103 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000), 104 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000), 105}; 106 107const struct max1363_mode 108*max1363_match_mode(u32 mask, const struct max1363_chip_info *ci) 109{ 110 int i; 111 if (mask) 112 for (i = 0; i < ci->num_modes; i++) 113 if (!((~max1363_mode_table[ci->mode_list[i]].modemask) & 114 mask)) 115 return &max1363_mode_table[ci->mode_list[i]]; 116 return NULL; 117} 118 119static int max1363_write_basic_config(struct i2c_client *client, 120 unsigned char d1, 121 unsigned char d2) 122{ 123 int ret; 124 u8 *tx_buf = kmalloc(2, GFP_KERNEL); 125 126 if (!tx_buf) 127 return -ENOMEM; 128 tx_buf[0] = d1; 129 tx_buf[1] = d2; 130 131 ret = i2c_master_send(client, tx_buf, 2); 132 kfree(tx_buf); 133 134 return (ret > 0) ? 0 : ret; 135} 136 137int max1363_set_scan_mode(struct max1363_state *st) 138{ 139 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 140 | MAX1363_SCAN_MASK 141 | MAX1363_SE_DE_MASK); 142 st->configbyte |= st->current_mode->conf; 143 144 return max1363_write_basic_config(st->client, 145 st->setupbyte, 146 st->configbyte); 147} 148 149static int max1363_read_single_chan(struct iio_dev *indio_dev, 150 struct iio_chan_spec const *chan, 151 int *val, 152 long m) 153{ 154 int ret = 0; 155 s32 data; 156 char rxbuf[2]; 157 long mask; 158 struct max1363_state *st = iio_priv(indio_dev); 159 struct i2c_client *client = st->client; 160 161 mutex_lock(&indio_dev->mlock); 162 /* 163 * If monitor mode is enabled, the method for reading a single 164 * channel will have to be rather different and has not yet 165 * been implemented. 166 */ 167 if (st->monitor_on) { 168 ret = -EBUSY; 169 goto error_ret; 170 } 171 172 /* If ring buffer capture is occurring, query the buffer */ 173 if (iio_ring_enabled(indio_dev)) { 174 mask = max1363_mode_table[chan->address].modemask; 175 data = max1363_single_channel_from_ring(mask, st); 176 if (data < 0) { 177 ret = data; 178 goto error_ret; 179 } 180 } else { 181 /* Check to see if current scan mode is correct */ 182 if (st->current_mode != 183 &max1363_mode_table[chan->address]) { 184 /* Update scan mode if needed */ 185 st->current_mode 186 = &max1363_mode_table[chan->address]; 187 ret = max1363_set_scan_mode(st); 188 if (ret) 189 goto error_ret; 190 } 191 if (st->chip_info->bits != 8) { 192 /* Get reading */ 193 data = i2c_master_recv(client, rxbuf, 2); 194 if (data < 0) { 195 ret = data; 196 goto error_ret; 197 } 198 data = (s32)(rxbuf[1]) | ((s32)(rxbuf[0] & 0x0F)) << 8; 199 } else { 200 /* Get reading */ 201 data = i2c_master_recv(client, rxbuf, 1); 202 if (data < 0) { 203 ret = data; 204 goto error_ret; 205 } 206 data = rxbuf[0]; 207 } 208 } 209 *val = data; 210error_ret: 211 mutex_unlock(&indio_dev->mlock); 212 return ret; 213 214} 215 216static int max1363_read_raw(struct iio_dev *indio_dev, 217 struct iio_chan_spec const *chan, 218 int *val, 219 int *val2, 220 long m) 221{ 222 struct max1363_state *st = iio_priv(indio_dev); 223 int ret; 224 switch (m) { 225 case 0: 226 ret = max1363_read_single_chan(indio_dev, chan, val, m); 227 if (ret) 228 return ret; 229 return IIO_VAL_INT; 230 case (1 << IIO_CHAN_INFO_SCALE_SHARED): 231 if ((1 << (st->chip_info->bits + 1)) > 232 st->chip_info->int_vref_mv) { 233 *val = 0; 234 *val2 = 500000; 235 return IIO_VAL_INT_PLUS_MICRO; 236 } else { 237 *val = (st->chip_info->int_vref_mv) 238 >> st->chip_info->bits; 239 return IIO_VAL_INT; 240 } 241 default: 242 return -EINVAL; 243 } 244 return 0; 245} 246 247/* Applies to max1363 */ 248static const enum max1363_modes max1363_mode_list[] = { 249 _s0, _s1, _s2, _s3, 250 s0to1, s0to2, s0to3, 251 d0m1, d2m3, d1m0, d3m2, 252 d0m1to2m3, d1m0to3m2, 253}; 254 255#define MAX1363_EV_M \ 256 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \ 257 | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING)) 258#define MAX1363_INFO_MASK (1 << IIO_CHAN_INFO_SCALE_SHARED) 259 260static struct iio_chan_spec max1363_channels[] = { 261 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK, 262 _s0, 0, IIO_ST('u', 12, 16, 0), MAX1363_EV_M), 263 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK, 264 _s1, 1, IIO_ST('u', 12, 16, 0), MAX1363_EV_M), 265 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK, 266 _s2, 2, IIO_ST('u', 12, 16, 0), MAX1363_EV_M), 267 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK, 268 _s3, 3, IIO_ST('u', 12, 16, 0), MAX1363_EV_M), 269 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK, 270 d0m1, 4, IIO_ST('s', 12, 16, 0), MAX1363_EV_M), 271 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK, 272 d2m3, 5, IIO_ST('s', 12, 16, 0), MAX1363_EV_M), 273 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK, 274 d1m0, 6, IIO_ST('s', 12, 16, 0), MAX1363_EV_M), 275 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK, 276 d3m2, 7, IIO_ST('s', 12, 16, 0), MAX1363_EV_M), 277 IIO_CHAN_SOFT_TIMESTAMP(8) 278}; 279 280static struct iio_chan_spec max1361_channels[] = { 281 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK, 282 _s0, 0, IIO_ST('u', 10, 16, 0), MAX1363_EV_M), 283 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK, 284 _s1, 1, IIO_ST('u', 10, 16, 0), MAX1363_EV_M), 285 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK, 286 _s2, 2, IIO_ST('u', 10, 16, 0), MAX1363_EV_M), 287 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK, 288 _s3, 3, IIO_ST('u', 10, 16, 0), MAX1363_EV_M), 289 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK, 290 d0m1, 4, IIO_ST('s', 10, 16, 0), MAX1363_EV_M), 291 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK, 292 d2m3, 5, IIO_ST('s', 10, 16, 0), MAX1363_EV_M), 293 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK, 294 d1m0, 6, IIO_ST('s', 10, 16, 0), MAX1363_EV_M), 295 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK, 296 d3m2, 7, IIO_ST('s', 10, 16, 0), MAX1363_EV_M), 297 IIO_CHAN_SOFT_TIMESTAMP(8) 298}; 299 300#define MAX1363_CHAN_U(num, address, scan_index, bits) \ 301 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, num, 0, MAX1363_INFO_MASK, \ 302 address, scan_index, IIO_ST('u', bits, \ 303 (bits == 8) ? 8 : 16, 0), 0) 304/* bipolar channel */ 305#define MAX1363_CHAN_B(num, num2, address, scan_index, bits) \ 306 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, num, num2, MAX1363_INFO_MASK,\ 307 address, scan_index, IIO_ST('s', bits, \ 308 (bits == 8) ? 8 : 16, 0), 0) 309 310#define MAX1363_4X_CHANS(bits) { \ 311 MAX1363_CHAN_U(0, _s0, 0, bits), \ 312 MAX1363_CHAN_U(1, _s1, 1, bits), \ 313 MAX1363_CHAN_U(2, _s2, 2, bits), \ 314 MAX1363_CHAN_U(3, _s3, 3, bits), \ 315 MAX1363_CHAN_B(0, 1, d0m1, 4, bits), \ 316 MAX1363_CHAN_B(2, 3, d2m3, 5, bits), \ 317 MAX1363_CHAN_B(1, 0, d1m0, 6, bits), \ 318 MAX1363_CHAN_B(3, 2, d3m2, 7, bits), \ 319 IIO_CHAN_SOFT_TIMESTAMP(8) \ 320 } 321 322static struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8); 323static struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10); 324static struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12); 325 326/* Appies to max1236, max1237 */ 327static const enum max1363_modes max1236_mode_list[] = { 328 _s0, _s1, _s2, _s3, 329 s0to1, s0to2, s0to3, 330 d0m1, d2m3, d1m0, d3m2, 331 d0m1to2m3, d1m0to3m2, 332 s2to3, 333}; 334 335/* Applies to max1238, max1239 */ 336static const enum max1363_modes max1238_mode_list[] = { 337 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11, 338 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, 339 s0to7, s0to8, s0to9, s0to10, s0to11, 340 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11, 341 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10, 342 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11, 343 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10, 344 s6to7, s6to8, s6to9, s6to10, s6to11, 345 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10, 346}; 347 348#define MAX1363_12X_CHANS(bits) { \ 349 MAX1363_CHAN_U(0, _s0, 0, bits), \ 350 MAX1363_CHAN_U(1, _s1, 1, bits), \ 351 MAX1363_CHAN_U(2, _s2, 2, bits), \ 352 MAX1363_CHAN_U(3, _s3, 3, bits), \ 353 MAX1363_CHAN_U(4, _s4, 4, bits), \ 354 MAX1363_CHAN_U(5, _s5, 5, bits), \ 355 MAX1363_CHAN_U(6, _s6, 6, bits), \ 356 MAX1363_CHAN_U(7, _s7, 7, bits), \ 357 MAX1363_CHAN_U(8, _s8, 8, bits), \ 358 MAX1363_CHAN_U(9, _s9, 9, bits), \ 359 MAX1363_CHAN_U(10, _s10, 10, bits), \ 360 MAX1363_CHAN_U(11, _s11, 11, bits), \ 361 MAX1363_CHAN_B(0, 1, d0m1, 12, bits), \ 362 MAX1363_CHAN_B(2, 3, d2m3, 13, bits), \ 363 MAX1363_CHAN_B(4, 5, d4m5, 14, bits), \ 364 MAX1363_CHAN_B(6, 7, d6m7, 15, bits), \ 365 MAX1363_CHAN_B(8, 9, d8m9, 16, bits), \ 366 MAX1363_CHAN_B(10, 11, d10m11, 17, bits), \ 367 MAX1363_CHAN_B(1, 0, d1m0, 18, bits), \ 368 MAX1363_CHAN_B(3, 2, d3m2, 19, bits), \ 369 MAX1363_CHAN_B(5, 4, d5m4, 20, bits), \ 370 MAX1363_CHAN_B(7, 6, d7m6, 21, bits), \ 371 MAX1363_CHAN_B(9, 8, d9m8, 22, bits), \ 372 MAX1363_CHAN_B(11, 10, d11m10, 23, bits), \ 373 IIO_CHAN_SOFT_TIMESTAMP(24) \ 374 } 375static struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8); 376static struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10); 377static struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12); 378 379static const enum max1363_modes max11607_mode_list[] = { 380 _s0, _s1, _s2, _s3, 381 s0to1, s0to2, s0to3, 382 s2to3, 383 d0m1, d2m3, d1m0, d3m2, 384 d0m1to2m3, d1m0to3m2, 385}; 386 387static const enum max1363_modes max11608_mode_list[] = { 388 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, 389 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7, 390 s6to7, 391 d0m1, d2m3, d4m5, d6m7, 392 d1m0, d3m2, d5m4, d7m6, 393 d0m1to2m3, d0m1to4m5, d0m1to6m7, 394 d1m0to3m2, d1m0to5m4, d1m0to7m6, 395}; 396 397#define MAX1363_8X_CHANS(bits) { \ 398 MAX1363_CHAN_U(0, _s0, 0, bits), \ 399 MAX1363_CHAN_U(1, _s1, 1, bits), \ 400 MAX1363_CHAN_U(2, _s2, 2, bits), \ 401 MAX1363_CHAN_U(3, _s3, 3, bits), \ 402 MAX1363_CHAN_U(4, _s4, 4, bits), \ 403 MAX1363_CHAN_U(5, _s5, 5, bits), \ 404 MAX1363_CHAN_U(6, _s6, 6, bits), \ 405 MAX1363_CHAN_U(7, _s7, 7, bits), \ 406 MAX1363_CHAN_B(0, 1, d0m1, 8, bits), \ 407 MAX1363_CHAN_B(2, 3, d2m3, 9, bits), \ 408 MAX1363_CHAN_B(4, 5, d4m5, 10, bits), \ 409 MAX1363_CHAN_B(6, 7, d6m7, 11, bits), \ 410 MAX1363_CHAN_B(1, 0, d1m0, 12, bits), \ 411 MAX1363_CHAN_B(3, 2, d3m2, 13, bits), \ 412 MAX1363_CHAN_B(5, 4, d5m4, 14, bits), \ 413 MAX1363_CHAN_B(7, 6, d7m6, 15, bits), \ 414 IIO_CHAN_SOFT_TIMESTAMP(16) \ 415 } 416static struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8); 417static struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10); 418static struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12); 419 420static const enum max1363_modes max11644_mode_list[] = { 421 _s0, _s1, s0to1, d0m1, d1m0, 422}; 423 424#define MAX1363_2X_CHANS(bits) { \ 425 MAX1363_CHAN_U(0, _s0, 0, bits), \ 426 MAX1363_CHAN_U(1, _s1, 1, bits), \ 427 MAX1363_CHAN_B(0, 1, d0m1, 2, bits), \ 428 MAX1363_CHAN_B(1, 0, d1m0, 3, bits), \ 429 IIO_CHAN_SOFT_TIMESTAMP(4) \ 430 } 431 432static struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10); 433static struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12); 434 435enum { max1361, 436 max1362, 437 max1363, 438 max1364, 439 max1036, 440 max1037, 441 max1038, 442 max1039, 443 max1136, 444 max1137, 445 max1138, 446 max1139, 447 max1236, 448 max1237, 449 max1238, 450 max1239, 451 max11600, 452 max11601, 453 max11602, 454 max11603, 455 max11604, 456 max11605, 457 max11606, 458 max11607, 459 max11608, 460 max11609, 461 max11610, 462 max11611, 463 max11612, 464 max11613, 465 max11614, 466 max11615, 467 max11616, 468 max11617, 469 max11644, 470 max11645, 471 max11646, 472 max11647 473}; 474 475static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600, 476 8300, 4200, 2000, 1000 }; 477 478static ssize_t max1363_monitor_show_freq(struct device *dev, 479 struct device_attribute *attr, 480 char *buf) 481{ 482 struct max1363_state *st = iio_priv(dev_get_drvdata(dev)); 483 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]); 484} 485 486static ssize_t max1363_monitor_store_freq(struct device *dev, 487 struct device_attribute *attr, 488 const char *buf, 489 size_t len) 490{ 491 struct iio_dev *indio_dev = dev_get_drvdata(dev); 492 struct max1363_state *st = iio_priv(indio_dev); 493 int i, ret; 494 unsigned long val; 495 bool found = false; 496 497 ret = strict_strtoul(buf, 10, &val); 498 if (ret) 499 return -EINVAL; 500 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++) 501 if (val == max1363_monitor_speeds[i]) { 502 found = true; 503 break; 504 } 505 if (!found) 506 return -EINVAL; 507 508 mutex_lock(&indio_dev->mlock); 509 st->monitor_speed = i; 510 mutex_unlock(&indio_dev->mlock); 511 512 return 0; 513} 514 515static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, 516 max1363_monitor_show_freq, 517 max1363_monitor_store_freq); 518 519static IIO_CONST_ATTR(sampling_frequency_available, 520 "133000 665000 33300 16600 8300 4200 2000 1000"); 521 522static int max1363_read_thresh(struct iio_dev *indio_dev, 523 int event_code, 524 int *val) 525{ 526 struct max1363_state *st = iio_priv(indio_dev); 527 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) 528 *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)]; 529 else 530 *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)]; 531 return 0; 532} 533 534static int max1363_write_thresh(struct iio_dev *indio_dev, 535 int event_code, 536 int val) 537{ 538 struct max1363_state *st = iio_priv(indio_dev); 539 /* make it handle signed correctly as well */ 540 switch (st->chip_info->bits) { 541 case 10: 542 if (val > 0x3FF) 543 return -EINVAL; 544 break; 545 case 12: 546 if (val > 0xFFF) 547 return -EINVAL; 548 break; 549 } 550 551 switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) { 552 case IIO_EV_DIR_FALLING: 553 st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val; 554 break; 555 case IIO_EV_DIR_RISING: 556 st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val; 557 break; 558 } 559 560 return 0; 561} 562 563static irqreturn_t max1363_event_handler(int irq, void *private) 564{ 565 struct iio_dev *indio_dev = private; 566 struct max1363_state *st = iio_priv(indio_dev); 567 s64 timestamp = iio_get_time_ns(); 568 u8 rx; 569 u8 tx[2] = { st->setupbyte, 570 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 }; 571 572 i2c_master_recv(st->client, &rx, 1); 573 /* todo - begging for use of for_each_set_bit */ 574 if (rx & (1 << 0)) 575 iio_push_event(indio_dev, 0, 576 IIO_EVENT_CODE_IN_LOW_THRESH(3), 577 timestamp); 578 if (rx & (1 << 1)) 579 iio_push_event(indio_dev, 0, 580 IIO_EVENT_CODE_IN_HIGH_THRESH(3), 581 timestamp); 582 if (rx & (1 << 2)) 583 iio_push_event(indio_dev, 0, 584 IIO_EVENT_CODE_IN_LOW_THRESH(2), 585 timestamp); 586 if (rx & (1 << 3)) 587 iio_push_event(indio_dev, 0, 588 IIO_EVENT_CODE_IN_HIGH_THRESH(2), 589 timestamp); 590 if (rx & (1 << 4)) 591 iio_push_event(indio_dev, 0, 592 IIO_EVENT_CODE_IN_LOW_THRESH(1), 593 timestamp); 594 if (rx & (1 << 5)) 595 iio_push_event(indio_dev, 0, 596 IIO_EVENT_CODE_IN_HIGH_THRESH(1), 597 timestamp); 598 if (rx & (1 << 6)) 599 iio_push_event(indio_dev, 0, 600 IIO_EVENT_CODE_IN_LOW_THRESH(0), 601 timestamp); 602 if (rx & (1 << 7)) 603 iio_push_event(indio_dev, 0, 604 IIO_EVENT_CODE_IN_HIGH_THRESH(0), 605 timestamp); 606 i2c_master_send(st->client, tx, 2); 607 608 return IRQ_HANDLED; 609} 610 611static int max1363_read_event_config(struct iio_dev *indio_dev, 612 int event_code) 613{ 614 struct max1363_state *st = iio_priv(indio_dev); 615 616 int val; 617 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code); 618 mutex_lock(&indio_dev->mlock); 619 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) 620 val = (1 << number) & st->mask_low; 621 else 622 val = (1 << number) & st->mask_high; 623 mutex_unlock(&indio_dev->mlock); 624 625 return val; 626} 627 628static int max1363_monitor_mode_update(struct max1363_state *st, int enabled) 629{ 630 u8 *tx_buf; 631 int ret, i = 3, j; 632 unsigned long numelements; 633 int len; 634 long modemask; 635 636 if (!enabled) { 637 /* transition to ring capture is not currently supported */ 638 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP; 639 st->configbyte &= ~MAX1363_SCAN_MASK; 640 st->monitor_on = false; 641 return max1363_write_basic_config(st->client, 642 st->setupbyte, 643 st->configbyte); 644 } 645 646 /* Ensure we are in the relevant mode */ 647 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP; 648 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 649 | MAX1363_SCAN_MASK 650 | MAX1363_SE_DE_MASK); 651 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE; 652 if ((st->mask_low | st->mask_high) & 0x0F) { 653 st->configbyte |= max1363_mode_table[s0to3].conf; 654 modemask = max1363_mode_table[s0to3].modemask; 655 } else if ((st->mask_low | st->mask_high) & 0x30) { 656 st->configbyte |= max1363_mode_table[d0m1to2m3].conf; 657 modemask = max1363_mode_table[d0m1to2m3].modemask; 658 } else { 659 st->configbyte |= max1363_mode_table[d1m0to3m2].conf; 660 modemask = max1363_mode_table[d1m0to3m2].modemask; 661 } 662 numelements = hweight_long(modemask); 663 len = 3 * numelements + 3; 664 tx_buf = kmalloc(len, GFP_KERNEL); 665 if (!tx_buf) { 666 ret = -ENOMEM; 667 goto error_ret; 668 } 669 tx_buf[0] = st->configbyte; 670 tx_buf[1] = st->setupbyte; 671 tx_buf[2] = (st->monitor_speed << 1); 672 673 /* 674 * So we need to do yet another bit of nefarious scan mode 675 * setup to match what we need. 676 */ 677 for (j = 0; j < 8; j++) 678 if (modemask & (1 << j)) { 679 /* Establish the mode is in the scan */ 680 if (st->mask_low & (1 << j)) { 681 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF; 682 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0; 683 } else if (j < 4) { 684 tx_buf[i] = 0; 685 tx_buf[i + 1] = 0; 686 } else { 687 tx_buf[i] = 0x80; 688 tx_buf[i + 1] = 0; 689 } 690 if (st->mask_high & (1 << j)) { 691 tx_buf[i + 1] |= 692 (st->thresh_high[j] >> 8) & 0x0F; 693 tx_buf[i + 2] = st->thresh_high[j] & 0xFF; 694 } else if (j < 4) { 695 tx_buf[i + 1] |= 0x0F; 696 tx_buf[i + 2] = 0xFF; 697 } else { 698 tx_buf[i + 1] |= 0x07; 699 tx_buf[i + 2] = 0xFF; 700 } 701 i += 3; 702 } 703 704 705 ret = i2c_master_send(st->client, tx_buf, len); 706 if (ret < 0) 707 goto error_ret; 708 if (ret != len) { 709 ret = -EIO; 710 goto error_ret; 711 } 712 713 /* 714 * Now that we hopefully have sensible thresholds in place it is 715 * time to turn the interrupts on. 716 * It is unclear from the data sheet if this should be necessary 717 * (i.e. whether monitor mode setup is atomic) but it appears to 718 * be in practice. 719 */ 720 tx_buf[0] = st->setupbyte; 721 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0; 722 ret = i2c_master_send(st->client, tx_buf, 2); 723 if (ret < 0) 724 goto error_ret; 725 if (ret != 2) { 726 ret = -EIO; 727 goto error_ret; 728 } 729 ret = 0; 730 st->monitor_on = true; 731error_ret: 732 733 kfree(tx_buf); 734 735 return ret; 736} 737 738/* 739 * To keep this manageable we always use one of 3 scan modes. 740 * Scan 0...3, 0-1,2-3 and 1-0,3-2 741 */ 742 743static inline int __max1363_check_event_mask(int thismask, int checkmask) 744{ 745 int ret = 0; 746 /* Is it unipolar */ 747 if (thismask < 4) { 748 if (checkmask & ~0x0F) { 749 ret = -EBUSY; 750 goto error_ret; 751 } 752 } else if (thismask < 6) { 753 if (checkmask & ~0x30) { 754 ret = -EBUSY; 755 goto error_ret; 756 } 757 } else if (checkmask & ~0xC0) 758 ret = -EBUSY; 759error_ret: 760 return ret; 761} 762 763static int max1363_write_event_config(struct iio_dev *indio_dev, 764 int event_code, 765 int state) 766{ 767 int ret = 0; 768 struct max1363_state *st = iio_priv(indio_dev); 769 u16 unifiedmask; 770 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code); 771 772 mutex_lock(&indio_dev->mlock); 773 unifiedmask = st->mask_low | st->mask_high; 774 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) { 775 776 if (state == 0) 777 st->mask_low &= ~(1 << number); 778 else { 779 ret = __max1363_check_event_mask((1 << number), 780 unifiedmask); 781 if (ret) 782 goto error_ret; 783 st->mask_low |= (1 << number); 784 } 785 } else { 786 if (state == 0) 787 st->mask_high &= ~(1 << number); 788 else { 789 ret = __max1363_check_event_mask((1 << number), 790 unifiedmask); 791 if (ret) 792 goto error_ret; 793 st->mask_high |= (1 << number); 794 } 795 } 796 797 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low)); 798error_ret: 799 mutex_unlock(&indio_dev->mlock); 800 801 return ret; 802} 803 804/* 805 * As with scan_elements, only certain sets of these can 806 * be combined. 807 */ 808static struct attribute *max1363_event_attributes[] = { 809 &iio_dev_attr_sampling_frequency.dev_attr.attr, 810 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 811 NULL, 812}; 813 814static struct attribute_group max1363_event_attribute_group = { 815 .attrs = max1363_event_attributes, 816}; 817 818#define MAX1363_EVENT_FUNCS \ 819 820 821static const struct iio_info max1238_info = { 822 .read_raw = &max1363_read_raw, 823 .driver_module = THIS_MODULE, 824}; 825 826static const struct iio_info max1363_info = { 827 .read_event_value = &max1363_read_thresh, 828 .write_event_value = &max1363_write_thresh, 829 .read_event_config = &max1363_read_event_config, 830 .write_event_config = &max1363_write_event_config, 831 .read_raw = &max1363_read_raw, 832 .driver_module = THIS_MODULE, 833 .num_interrupt_lines = 1, 834 .event_attrs = &max1363_event_attribute_group, 835}; 836 837/* max1363 and max1368 tested - rest from data sheet */ 838static const struct max1363_chip_info max1363_chip_info_tbl[] = { 839 [max1361] = { 840 .bits = 10, 841 .int_vref_mv = 2048, 842 .mode_list = max1363_mode_list, 843 .num_modes = ARRAY_SIZE(max1363_mode_list), 844 .default_mode = s0to3, 845 .channels = max1361_channels, 846 .num_channels = ARRAY_SIZE(max1361_channels), 847 .info = &max1363_info, 848 }, 849 [max1362] = { 850 .bits = 10, 851 .int_vref_mv = 4096, 852 .mode_list = max1363_mode_list, 853 .num_modes = ARRAY_SIZE(max1363_mode_list), 854 .default_mode = s0to3, 855 .channels = max1361_channels, 856 .num_channels = ARRAY_SIZE(max1361_channels), 857 .info = &max1363_info, 858 }, 859 [max1363] = { 860 .bits = 12, 861 .int_vref_mv = 2048, 862 .mode_list = max1363_mode_list, 863 .num_modes = ARRAY_SIZE(max1363_mode_list), 864 .default_mode = s0to3, 865 .channels = max1363_channels, 866 .num_channels = ARRAY_SIZE(max1363_channels), 867 .info = &max1363_info, 868 }, 869 [max1364] = { 870 .bits = 12, 871 .int_vref_mv = 4096, 872 .mode_list = max1363_mode_list, 873 .num_modes = ARRAY_SIZE(max1363_mode_list), 874 .default_mode = s0to3, 875 .channels = max1363_channels, 876 .num_channels = ARRAY_SIZE(max1363_channels), 877 .info = &max1363_info, 878 }, 879 [max1036] = { 880 .bits = 8, 881 .int_vref_mv = 4096, 882 .mode_list = max1236_mode_list, 883 .num_modes = ARRAY_SIZE(max1236_mode_list), 884 .default_mode = s0to3, 885 .info = &max1238_info, 886 .channels = max1036_channels, 887 .num_channels = ARRAY_SIZE(max1036_channels), 888 }, 889 [max1037] = { 890 .bits = 8, 891 .int_vref_mv = 2048, 892 .mode_list = max1236_mode_list, 893 .num_modes = ARRAY_SIZE(max1236_mode_list), 894 .default_mode = s0to3, 895 .info = &max1238_info, 896 .channels = max1036_channels, 897 .num_channels = ARRAY_SIZE(max1036_channels), 898 }, 899 [max1038] = { 900 .bits = 8, 901 .int_vref_mv = 4096, 902 .mode_list = max1238_mode_list, 903 .num_modes = ARRAY_SIZE(max1238_mode_list), 904 .default_mode = s0to11, 905 .info = &max1238_info, 906 .channels = max1038_channels, 907 .num_channels = ARRAY_SIZE(max1038_channels), 908 }, 909 [max1039] = { 910 .bits = 8, 911 .int_vref_mv = 2048, 912 .mode_list = max1238_mode_list, 913 .num_modes = ARRAY_SIZE(max1238_mode_list), 914 .default_mode = s0to11, 915 .info = &max1238_info, 916 .channels = max1038_channels, 917 .num_channels = ARRAY_SIZE(max1038_channels), 918 }, 919 [max1136] = { 920 .bits = 10, 921 .int_vref_mv = 4096, 922 .mode_list = max1236_mode_list, 923 .num_modes = ARRAY_SIZE(max1236_mode_list), 924 .default_mode = s0to3, 925 .info = &max1238_info, 926 .channels = max1136_channels, 927 .num_channels = ARRAY_SIZE(max1136_channels), 928 }, 929 [max1137] = { 930 .bits = 10, 931 .int_vref_mv = 2048, 932 .mode_list = max1236_mode_list, 933 .num_modes = ARRAY_SIZE(max1236_mode_list), 934 .default_mode = s0to3, 935 .info = &max1238_info, 936 .channels = max1136_channels, 937 .num_channels = ARRAY_SIZE(max1136_channels), 938 }, 939 [max1138] = { 940 .bits = 10, 941 .int_vref_mv = 4096, 942 .mode_list = max1238_mode_list, 943 .num_modes = ARRAY_SIZE(max1238_mode_list), 944 .default_mode = s0to11, 945 .info = &max1238_info, 946 .channels = max1138_channels, 947 .num_channels = ARRAY_SIZE(max1138_channels), 948 }, 949 [max1139] = { 950 .bits = 10, 951 .int_vref_mv = 2048, 952 .mode_list = max1238_mode_list, 953 .num_modes = ARRAY_SIZE(max1238_mode_list), 954 .default_mode = s0to11, 955 .info = &max1238_info, 956 .channels = max1138_channels, 957 .num_channels = ARRAY_SIZE(max1138_channels), 958 }, 959 [max1236] = { 960 .bits = 12, 961 .int_vref_mv = 4096, 962 .mode_list = max1236_mode_list, 963 .num_modes = ARRAY_SIZE(max1236_mode_list), 964 .default_mode = s0to3, 965 .info = &max1238_info, 966 .channels = max1236_channels, 967 .num_channels = ARRAY_SIZE(max1236_channels), 968 }, 969 [max1237] = { 970 .bits = 12, 971 .int_vref_mv = 2048, 972 .mode_list = max1236_mode_list, 973 .num_modes = ARRAY_SIZE(max1236_mode_list), 974 .default_mode = s0to3, 975 .info = &max1238_info, 976 .channels = max1236_channels, 977 .num_channels = ARRAY_SIZE(max1236_channels), 978 }, 979 [max1238] = { 980 .bits = 12, 981 .int_vref_mv = 4096, 982 .mode_list = max1238_mode_list, 983 .num_modes = ARRAY_SIZE(max1238_mode_list), 984 .default_mode = s0to11, 985 .info = &max1238_info, 986 .channels = max1238_channels, 987 .num_channels = ARRAY_SIZE(max1238_channels), 988 }, 989 [max1239] = { 990 .bits = 12, 991 .int_vref_mv = 2048, 992 .mode_list = max1238_mode_list, 993 .num_modes = ARRAY_SIZE(max1238_mode_list), 994 .default_mode = s0to11, 995 .info = &max1238_info, 996 .channels = max1238_channels, 997 .num_channels = ARRAY_SIZE(max1238_channels), 998 }, 999 [max11600] = { 1000 .bits = 8, 1001 .int_vref_mv = 4096, 1002 .mode_list = max11607_mode_list, 1003 .num_modes = ARRAY_SIZE(max11607_mode_list), 1004 .default_mode = s0to3, 1005 .info = &max1238_info, 1006 .channels = max1036_channels, 1007 .num_channels = ARRAY_SIZE(max1036_channels), 1008 }, 1009 [max11601] = { 1010 .bits = 8, 1011 .int_vref_mv = 2048, 1012 .mode_list = max11607_mode_list, 1013 .num_modes = ARRAY_SIZE(max11607_mode_list), 1014 .default_mode = s0to3, 1015 .info = &max1238_info, 1016 .channels = max1036_channels, 1017 .num_channels = ARRAY_SIZE(max1036_channels), 1018 }, 1019 [max11602] = { 1020 .bits = 8, 1021 .int_vref_mv = 4096, 1022 .mode_list = max11608_mode_list, 1023 .num_modes = ARRAY_SIZE(max11608_mode_list), 1024 .default_mode = s0to7, 1025 .info = &max1238_info, 1026 .channels = max11602_channels, 1027 .num_channels = ARRAY_SIZE(max11602_channels), 1028 }, 1029 [max11603] = { 1030 .bits = 8, 1031 .int_vref_mv = 2048, 1032 .mode_list = max11608_mode_list, 1033 .num_modes = ARRAY_SIZE(max11608_mode_list), 1034 .default_mode = s0to7, 1035 .info = &max1238_info, 1036 .channels = max11602_channels, 1037 .num_channels = ARRAY_SIZE(max11602_channels), 1038 }, 1039 [max11604] = { 1040 .bits = 8, 1041 .int_vref_mv = 4098, 1042 .mode_list = max1238_mode_list, 1043 .num_modes = ARRAY_SIZE(max1238_mode_list), 1044 .default_mode = s0to11, 1045 .info = &max1238_info, 1046 .channels = max1238_channels, 1047 .num_channels = ARRAY_SIZE(max1238_channels), 1048 }, 1049 [max11605] = { 1050 .bits = 8, 1051 .int_vref_mv = 2048, 1052 .mode_list = max1238_mode_list, 1053 .num_modes = ARRAY_SIZE(max1238_mode_list), 1054 .default_mode = s0to11, 1055 .info = &max1238_info, 1056 .channels = max1238_channels, 1057 .num_channels = ARRAY_SIZE(max1238_channels), 1058 }, 1059 [max11606] = { 1060 .bits = 10, 1061 .int_vref_mv = 4096, 1062 .mode_list = max11607_mode_list, 1063 .num_modes = ARRAY_SIZE(max11607_mode_list), 1064 .default_mode = s0to3, 1065 .info = &max1238_info, 1066 .channels = max1136_channels, 1067 .num_channels = ARRAY_SIZE(max1136_channels), 1068 }, 1069 [max11607] = { 1070 .bits = 10, 1071 .int_vref_mv = 2048, 1072 .mode_list = max11607_mode_list, 1073 .num_modes = ARRAY_SIZE(max11607_mode_list), 1074 .default_mode = s0to3, 1075 .info = &max1238_info, 1076 .channels = max1136_channels, 1077 .num_channels = ARRAY_SIZE(max1136_channels), 1078 }, 1079 [max11608] = { 1080 .bits = 10, 1081 .int_vref_mv = 4096, 1082 .mode_list = max11608_mode_list, 1083 .num_modes = ARRAY_SIZE(max11608_mode_list), 1084 .default_mode = s0to7, 1085 .info = &max1238_info, 1086 .channels = max11608_channels, 1087 .num_channels = ARRAY_SIZE(max11608_channels), 1088 }, 1089 [max11609] = { 1090 .bits = 10, 1091 .int_vref_mv = 2048, 1092 .mode_list = max11608_mode_list, 1093 .num_modes = ARRAY_SIZE(max11608_mode_list), 1094 .default_mode = s0to7, 1095 .info = &max1238_info, 1096 .channels = max11608_channels, 1097 .num_channels = ARRAY_SIZE(max11608_channels), 1098 }, 1099 [max11610] = { 1100 .bits = 10, 1101 .int_vref_mv = 4098, 1102 .mode_list = max1238_mode_list, 1103 .num_modes = ARRAY_SIZE(max1238_mode_list), 1104 .default_mode = s0to11, 1105 .info = &max1238_info, 1106 .channels = max1238_channels, 1107 .num_channels = ARRAY_SIZE(max1238_channels), 1108 }, 1109 [max11611] = { 1110 .bits = 10, 1111 .int_vref_mv = 2048, 1112 .mode_list = max1238_mode_list, 1113 .num_modes = ARRAY_SIZE(max1238_mode_list), 1114 .default_mode = s0to11, 1115 .info = &max1238_info, 1116 .channels = max1238_channels, 1117 .num_channels = ARRAY_SIZE(max1238_channels), 1118 }, 1119 [max11612] = { 1120 .bits = 12, 1121 .int_vref_mv = 4096, 1122 .mode_list = max11607_mode_list, 1123 .num_modes = ARRAY_SIZE(max11607_mode_list), 1124 .default_mode = s0to3, 1125 .info = &max1238_info, 1126 .channels = max1363_channels, 1127 .num_channels = ARRAY_SIZE(max1363_channels), 1128 }, 1129 [max11613] = { 1130 .bits = 12, 1131 .int_vref_mv = 2048, 1132 .mode_list = max11607_mode_list, 1133 .num_modes = ARRAY_SIZE(max11607_mode_list), 1134 .default_mode = s0to3, 1135 .info = &max1238_info, 1136 .channels = max1363_channels, 1137 .num_channels = ARRAY_SIZE(max1363_channels), 1138 }, 1139 [max11614] = { 1140 .bits = 12, 1141 .int_vref_mv = 4096, 1142 .mode_list = max11608_mode_list, 1143 .num_modes = ARRAY_SIZE(max11608_mode_list), 1144 .default_mode = s0to7, 1145 .info = &max1238_info, 1146 .channels = max11614_channels, 1147 .num_channels = ARRAY_SIZE(max11614_channels), 1148 }, 1149 [max11615] = { 1150 .bits = 12, 1151 .int_vref_mv = 2048, 1152 .mode_list = max11608_mode_list, 1153 .num_modes = ARRAY_SIZE(max11608_mode_list), 1154 .default_mode = s0to7, 1155 .info = &max1238_info, 1156 .channels = max11614_channels, 1157 .num_channels = ARRAY_SIZE(max11614_channels), 1158 }, 1159 [max11616] = { 1160 .bits = 12, 1161 .int_vref_mv = 4098, 1162 .mode_list = max1238_mode_list, 1163 .num_modes = ARRAY_SIZE(max1238_mode_list), 1164 .default_mode = s0to11, 1165 .info = &max1238_info, 1166 .channels = max1238_channels, 1167 .num_channels = ARRAY_SIZE(max1238_channels), 1168 }, 1169 [max11617] = { 1170 .bits = 12, 1171 .int_vref_mv = 2048, 1172 .mode_list = max1238_mode_list, 1173 .num_modes = ARRAY_SIZE(max1238_mode_list), 1174 .default_mode = s0to11, 1175 .info = &max1238_info, 1176 .channels = max1238_channels, 1177 .num_channels = ARRAY_SIZE(max1238_channels), 1178 }, 1179 [max11644] = { 1180 .bits = 12, 1181 .int_vref_mv = 2048, 1182 .mode_list = max11644_mode_list, 1183 .num_modes = ARRAY_SIZE(max11644_mode_list), 1184 .default_mode = s0to1, 1185 .info = &max1238_info, 1186 .channels = max11644_channels, 1187 .num_channels = ARRAY_SIZE(max11644_channels), 1188 }, 1189 [max11645] = { 1190 .bits = 12, 1191 .int_vref_mv = 4096, 1192 .mode_list = max11644_mode_list, 1193 .num_modes = ARRAY_SIZE(max11644_mode_list), 1194 .default_mode = s0to1, 1195 .info = &max1238_info, 1196 .channels = max11644_channels, 1197 .num_channels = ARRAY_SIZE(max11644_channels), 1198 }, 1199 [max11646] = { 1200 .bits = 10, 1201 .int_vref_mv = 2048, 1202 .mode_list = max11644_mode_list, 1203 .num_modes = ARRAY_SIZE(max11644_mode_list), 1204 .default_mode = s0to1, 1205 .info = &max1238_info, 1206 .channels = max11646_channels, 1207 .num_channels = ARRAY_SIZE(max11646_channels), 1208 }, 1209 [max11647] = { 1210 .bits = 10, 1211 .int_vref_mv = 4096, 1212 .mode_list = max11644_mode_list, 1213 .num_modes = ARRAY_SIZE(max11644_mode_list), 1214 .default_mode = s0to1, 1215 .info = &max1238_info, 1216 .channels = max11646_channels, 1217 .num_channels = ARRAY_SIZE(max11646_channels), 1218 }, 1219}; 1220 1221 1222 1223static int max1363_initial_setup(struct max1363_state *st) 1224{ 1225 st->setupbyte = MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 1226 | MAX1363_SETUP_POWER_UP_INT_REF 1227 | MAX1363_SETUP_INT_CLOCK 1228 | MAX1363_SETUP_UNIPOLAR 1229 | MAX1363_SETUP_NORESET; 1230 1231 /* Set scan mode writes the config anyway so wait until then*/ 1232 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte); 1233 st->current_mode = &max1363_mode_table[st->chip_info->default_mode]; 1234 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte); 1235 1236 return max1363_set_scan_mode(st); 1237} 1238 1239static int __devinit max1363_probe(struct i2c_client *client, 1240 const struct i2c_device_id *id) 1241{ 1242 int ret, i, regdone = 0; 1243 struct max1363_state *st; 1244 struct iio_dev *indio_dev; 1245 struct regulator *reg; 1246 1247 reg = regulator_get(&client->dev, "vcc"); 1248 if (!IS_ERR(reg)) { 1249 ret = regulator_enable(reg); 1250 if (ret) 1251 goto error_put_reg; 1252 } 1253 1254 indio_dev = iio_allocate_device(sizeof(struct max1363_state)); 1255 if (indio_dev == NULL) { 1256 ret = -ENOMEM; 1257 goto error_disable_reg; 1258 } 1259 st = iio_priv(indio_dev); 1260 st->reg = reg; 1261 /* this is only used for device removal purposes */ 1262 i2c_set_clientdata(client, indio_dev); 1263 1264 st->chip_info = &max1363_chip_info_tbl[id->driver_data]; 1265 st->client = client; 1266 1267 indio_dev->available_scan_masks 1268 = kzalloc(sizeof(*indio_dev->available_scan_masks)* 1269 (st->chip_info->num_modes + 1), GFP_KERNEL); 1270 if (!indio_dev->available_scan_masks) { 1271 ret = -ENOMEM; 1272 goto error_free_device; 1273 } 1274 1275 for (i = 0; i < st->chip_info->num_modes; i++) 1276 indio_dev->available_scan_masks[i] = 1277 max1363_mode_table[st->chip_info->mode_list[i]] 1278 .modemask; 1279 /* Estabilish that the iio_dev is a child of the i2c device */ 1280 indio_dev->dev.parent = &client->dev; 1281 indio_dev->name = id->name; 1282 1283 indio_dev->info = st->chip_info->info; 1284 indio_dev->modes = INDIO_DIRECT_MODE; 1285 ret = max1363_initial_setup(st); 1286 if (ret) 1287 goto error_free_available_scan_masks; 1288 1289 ret = max1363_register_ring_funcs_and_init(indio_dev); 1290 if (ret) 1291 goto error_free_available_scan_masks; 1292 1293 ret = iio_device_register(indio_dev); 1294 if (ret) 1295 goto error_cleanup_ring; 1296 regdone = 1; 1297 ret = iio_ring_buffer_register_ex(indio_dev->ring, 0, 1298 st->chip_info->channels, 1299 st->chip_info->num_channels); 1300 if (ret) 1301 goto error_cleanup_ring; 1302 1303 if (client->irq) { 1304 ret = request_threaded_irq(st->client->irq, 1305 NULL, 1306 &max1363_event_handler, 1307 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1308 "max1363_event", 1309 indio_dev); 1310 1311 if (ret) 1312 goto error_uninit_ring; 1313 } 1314 1315 return 0; 1316error_uninit_ring: 1317 iio_ring_buffer_unregister(indio_dev->ring); 1318error_cleanup_ring: 1319 max1363_ring_cleanup(indio_dev); 1320error_free_available_scan_masks: 1321 kfree(indio_dev->available_scan_masks); 1322error_free_device: 1323 if (!regdone) 1324 iio_free_device(indio_dev); 1325 else 1326 iio_device_unregister(indio_dev); 1327error_disable_reg: 1328 if (!IS_ERR(st->reg)) 1329 regulator_disable(st->reg); 1330error_put_reg: 1331 if (!IS_ERR(st->reg)) 1332 regulator_put(st->reg); 1333 1334 return ret; 1335} 1336 1337static int max1363_remove(struct i2c_client *client) 1338{ 1339 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1340 struct max1363_state *st = iio_priv(indio_dev); 1341 struct regulator *reg = st->reg; 1342 1343 if (client->irq) 1344 free_irq(st->client->irq, indio_dev); 1345 iio_ring_buffer_unregister(indio_dev->ring); 1346 max1363_ring_cleanup(indio_dev); 1347 kfree(indio_dev->available_scan_masks); 1348 if (!IS_ERR(reg)) { 1349 regulator_disable(reg); 1350 regulator_put(reg); 1351 } 1352 iio_device_unregister(indio_dev); 1353 1354 return 0; 1355} 1356 1357static const struct i2c_device_id max1363_id[] = { 1358 { "max1361", max1361 }, 1359 { "max1362", max1362 }, 1360 { "max1363", max1363 }, 1361 { "max1364", max1364 }, 1362 { "max1036", max1036 }, 1363 { "max1037", max1037 }, 1364 { "max1038", max1038 }, 1365 { "max1039", max1039 }, 1366 { "max1136", max1136 }, 1367 { "max1137", max1137 }, 1368 { "max1138", max1138 }, 1369 { "max1139", max1139 }, 1370 { "max1236", max1236 }, 1371 { "max1237", max1237 }, 1372 { "max1238", max1238 }, 1373 { "max1239", max1239 }, 1374 { "max11600", max11600 }, 1375 { "max11601", max11601 }, 1376 { "max11602", max11602 }, 1377 { "max11603", max11603 }, 1378 { "max11604", max11604 }, 1379 { "max11605", max11605 }, 1380 { "max11606", max11606 }, 1381 { "max11607", max11607 }, 1382 { "max11608", max11608 }, 1383 { "max11609", max11609 }, 1384 { "max11610", max11610 }, 1385 { "max11611", max11611 }, 1386 { "max11612", max11612 }, 1387 { "max11613", max11613 }, 1388 { "max11614", max11614 }, 1389 { "max11615", max11615 }, 1390 { "max11616", max11616 }, 1391 { "max11617", max11617 }, 1392 {} 1393}; 1394 1395MODULE_DEVICE_TABLE(i2c, max1363_id); 1396 1397static struct i2c_driver max1363_driver = { 1398 .driver = { 1399 .name = "max1363", 1400 }, 1401 .probe = max1363_probe, 1402 .remove = max1363_remove, 1403 .id_table = max1363_id, 1404}; 1405 1406static __init int max1363_init(void) 1407{ 1408 return i2c_add_driver(&max1363_driver); 1409} 1410 1411static __exit void max1363_exit(void) 1412{ 1413 i2c_del_driver(&max1363_driver); 1414} 1415 1416MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>"); 1417MODULE_DESCRIPTION("Maxim 1363 ADC"); 1418MODULE_LICENSE("GPL v2"); 1419 1420module_init(max1363_init); 1421module_exit(max1363_exit); 1422